WO2009116698A1

WO2009116698A1 - Frequency stabilized dielectric heating apparatus using semiconductor and amplification circuit structure thereof

Info

Publication number: WO2009116698A1
Application number: PCT/KR2008/001816
Authority: WO
Inventors: Uh-Hwan Jang
Original assignee: Dong Yung Engineering Co., Ltd
Priority date: 2008-03-20
Filing date: 2008-04-01
Publication date: 2009-09-24

Abstract

A frequency stabilized dielectric heating apparatus using a semiconductor and an amplification circuit structure thereof are disclosed. The frequency stabilized dielectric heating apparatus includes a phase locked loop (PLL) 100 for stabilizing a frequency, a band pass filter (BPF) 200 connected to a voltage controlled oscillator 150 of the PLL 100, for eliminating a harmonic component, a preamplifier 300 and a power amplifier 400 for amplifying an output of the BPF 200, an impedance matching circuit 500 for matching the amplified output with an impendence of a load 600 and outputting the matched output to the load 600. Therefore, the present invention locks an output frequency irrespective of external disturbance from a peripheral device and an influence by climate and temperature by using a semiconductor device instead of a vacuum tube, easily matches with an impedance of a load, and provide an output corresponding to a resonant point of the load even though dielectric heating is being kept.

Description

[DESCRIPTION] [Invention Title]

FREQUENCY STABILIZED DIELECTRIC HEATING APPARATUS USING SEMICONDUCTOR AND AMPLIFICATION CIRCUIT STRUCTURE THEREOF [Technical Field]

<ι> The present invention relates to a frequency stabilized dielectric heating apparatus using a semiconductor and an amplification circuit structure thereof, and more particularly to a frequency stabilized dielectric heating apparatus which locks an output frequency by using a semiconductor without using a vacuum tube, sets an output of a voltage controlled oscillator using a phase locked loop to 40MHz by using a crystal oscillating frequency of 10.24MHz as a reference frequency, amplifies a previously amplified signal of IW (3OdB) to 3OW (14.8dB), and finally amplifies 3OW to 500W. [Background Art]

<2> A dielectric heating apparatus is generally applied to materials having non-conductive electrical properties. A heated material (load) is placed between two electrodes and energy of a high frequency form is transferred to the electrodes so that heat is generated at a very fast rate over the entire load.

<3> Fig. 1 is a diagram illustrating an oscillating circuit of a conventional dielectric heating apparatus. A high power vacuum tube is used as shown in Fig. 1 to form a high frequency inputted to electrodes.

<4> However, the dielectric heating apparatus using the vacuum tube is low in energy efficiency because a high frequency output varies widely due to external disturbance and thus mismatching occurs frequently in impedance of a load. To keep a high power using the vacuum tube, since the oscillating circuit should be increased in size, it may be difficult to flexibly utilize the dielectric heating apparatus.

<5> That is, in the dielectric heating apparatus using the vacuum tube, a minute jump of an output frequency is frequent due to external disturbance from a peripheral device and influence by climate and temperature. Therefore, it is difficult to perfectly match an impedance of the load and it is not possible to reach a resonant point while dielectric heating is kept, thereby lowering energy efficiency.

<6> Meanwhile, the high power vacuum tube used for the dielectric heating apparatus is greatly increased in price in proportion to its size and most of the price of the dielectric heating apparatus is occupied by the high power vacuum tube. Namely, an excessively high price of equipment relative to the efficiency thereof is a cause which makes an access to the dielectric heating apparatus difficult.

<7> Frequencies of 13.56MHz±6.78KHz, 27.12MHz±162.72KHz, and 40.68MHz ±20.34KHz are generally allocated as an industrial scientific medical (ISM) band of a high frequency dielectric heating industrial field used in a dielectric heating system. Electromagnetic radiation of the above frequency band deteriorates electromagnetic environments of an electronic device and is harmful to the human body in a work place. Accordingly, it is necessary to raise power efficiency through stable oscillation and to minimize the oscillation of a harmonic component.

<8> However, since an LC (inductor-capacitor) oscillator is used for oscillation of the vacuum tube, there is a wide variation of an output frequency caused by external circumstances and mismatching occurs frequently in an impedance of a load, thereby decreasing energy efficiency. [Disclosure] [Technical Problem]

<9> Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a frequency stabilized dielectric heating apparatus using a semiconductor and an amplification circuit structure thereof which minimize harmonic oscillation through a stable frequency oscillation and raise power efficiency by keeping a resonant frequency constant while dielectric heating is implemented. The frequency stabilized dielectric heating apparatus and the amplification circuit structure thereof of the present invention lock an output frequency irrespective of external disturbance from a peripheral device and an influence by climate and temperature by using a semiconductor device instead of a vacuum tube, easily match with an impedance of a load, and provide an output corresponding to a resonant point of the load even though dielectric heating is being kept, thereby improving resistance to price for efficiency of equipment. Moreover, a phase locked loop for a stable frequency oscillation is applied by using a high power MOSFET instead of a vacuum tube used as a high power (500W) power amplifier when designing a preamplifier preceding the power amplifier, thereby generating an output of 500W or more by applying an output of the preamplifier having 40MHz±100 Hz stability, an average power of 44.77dB (3Of) to the power amplifier having an amplification factor of 12dB or more. [Technical Solution]

<io> In accordance with an aspect of the present invention, the above and other objects can be accomplished by the provision of a frequency stabilized dielectric heating apparatus using a semiconductor. The frequency stabilized dielectric heating apparatus comprises a phase locked loop, wherein the phase locked loop includes a crystal oscillator for generating an output frequency, a primary divider for primarily dividing the output frequency of the crystal oscillator, a phase detector for receiving a frequency divided by the primary divider, a voltage controlled oscillator for receiving an output of the phase detector, and a secondary divider for receiving an output of the voltage controlled oscillator and feeding back its output to the phase detector.

<π> The primary divider of the phase locked loop divides the output frequency of 10.24MHz of the crystal oscillator by a division ratio of 1024, and the secondary divider divides an output of 40MHz of the voltage controlled oscillator by a division ratio of 4000 and feeds back its divided output to the phase detector.

<12> The primary divider of the phase locked loop divides the output frequency of 10.24MHz of the crystal oscillator by a division ratio of 1024, and the secondary divider divides an output of 40MHz of the voltage controlled oscillator by a variable division ratio and feeds back its divided output to the phase detector, thereby modulating an output frequency band.

<i3> The frequency stabilized dielectric heating apparatus further comprises a band pass filter connected to the voltage controlled oscillator of the phase locked loop 100, for eliminating a harmonic component, a preamplifier and a power amplifier for amplifying an output of the band pass filter, and an impedance matching circuit for matching the amplified output with an impedance of a load and outputting the matched output to the load.

<14> The frequency stabilized dielectric heating apparatus further comprises an interface which is a buffer circuit for measuring the impedance of the load and feeding back the impedance to a voltage input terminal of the voltage controlled oscillator, wherein if an LC (inductor-capacitor) resonant frequency of the load is shifted by a variation in the impedance of the load, the interface feeds back the shifted frequency to the voltage input terminal of the voltage controlled oscillator to shift an output frequency of the phase locked loop or cut off an output of the phase locked loop.

<i5> In accordance with another aspect of the present invention, there is provided an amplification circuit structure of a frequency stabilized dielectric heating apparatus using a semiconductor. The amplification circuit structure comprises: a phase locked loop including a phase detector for receiving a reference frequency into which a crystal oscillating frequency is divided and a comparison frequency, and a voltage controlled oscillator for receiving an output of the phase detector, wherein a phase difference between the reference frequency and the comparison frequency into which an output of the voltage controlled oscillator is divided is applied via a low pass filter to the voltage controlled oscillator as a bias voltage source and an output frequency of the voltage controlled oscillator is stabilized at 40MHz; a preamplifier connected to an output terminal of the voltage controlled oscillator and including a primary amplifier for amplifying the output of the voltage controlled oscillator to IW at an impedance of 50 and a secondary amplifier connected to an output terminal of the primary amplifier to amplify an output of the primary amplifier to 3OW by eliminating a harmonic signal by a 40 MHz tuning circuit; and a power amplifier including field-effect-transistor (FET) semiconductors for amplifying a 3OW output amplified by the preamplifier to 500W.

<i6> The phase locked loop generates an output frequency of 10.24MHz by a crystal oscillator, divides the reference frequency by a primary divider of which division ratio is 1024 to set a reference clock to 10KHz, divides the 40MHz output frequency generated from the voltage controlled oscillator by a secondary divider of which division ratio is 4000 to set an output clock to 10KHz, and compares the output clock with the reference clock.

<i7> The voltage controlled oscillator eliminates an output of a phase detector of the phase locked loop, sets a central frequency to 40MHz by using a trimmer, causes an LED to be turned off by connecting the output of the phase detector to have a 40MHz lock, applies the output of the voltage controlled oscillator to a secondary divider of the phase locked loop, and applies an output of the phase detector to a varactor diode as a control voltage via a low pass filter.

<18> The primary amplifier of the preamplifier outputs IW at an impedance of 50 by a transistor driven by a power of 30V, a pre-trimmer for impedance conversion and adjustment, and a post-trimmer for maximum resonant point adjustment .

<19> The secondary amplifier of the preamplifier outputs 3OW by a metal- oxide-semiconductor (MOS) transistor by applying the If generated from the primary amplifier to both inputs of a push-pull form of a primary troidal core and controlling trimmers of secondary and third troidal cores, and wherein a 6OpF of the third troidal core eliminates a harmonic component by a 40MHz tuning circuit. [Advantageous Effects]

<2i> A frequency stabilized dielectric heating apparatus using a semiconductor and an amplification circuit structure thereof according to the present invention minimize a harmonic oscillation through a stable frequency oscillation and raise power efficiency by keeping a resonant frequency constant while dielectric heating is implemented. The frequency stabilized dielectric heating apparatus and the amplification circuit structure thereof lock an output frequency irrespective of external disturbance from a peripheral device and an influence by climate and temperature by using a semiconductor device instead of a vacuum tube, easily match with an impedance of a load, and provide an output corresponding to a resonant point of the load even though dielectric heating is being kept, thereby improving resistance to price for efficiency of equipment. Moreover, a phase locked loop for a stable frequency oscillation is applied by using a high power MOSFET instead of a vacuum tube used as a high power (500W) power amplifier when designing a preamplifier preceding the power amplifier, thereby generating an output of 500W or more by applying an output of the preamplifier having 40MHz±100 Hz stability, an average power of 44.77dB (30W) to the power amplifier having a amplification factor of 12dB or more. [Description of Drawings]

<22> The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

<23> Fig. 1 is a diagram illustrating an oscillating circuit of a conventional dielectric heating apparatus;

<24> Fig. 2 is a block diagram of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention;

<25> Fig. 3 is an output graph of a voltage controlled oscillator (VCO) of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention;

<26> Fig. 4 illustrates a partial construction of a phase locked loop (PLL) of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention;

<27> Fig. 5 is a circuit diagram of an amplification circuit structure of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention;

<28> Fig. 6 a detailed diagram of a PLL of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention;

<29> Fig.7 is a graph illustrating a characteristic of a diode which is applicable to a VCO according to the present invention;

<30> Fig.8 is a photograph illustrating output waveforms of a primary amplifier and a secondary amplifier according to the present invention; and

<3i> Fig. 9 is a graph illustrating an output performance of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention. [Best Mode]

<32> Fig.2 is a block diagram of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention, Fig. 3 is an output graph of a voltage controlled oscillator (VCO) of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention, Fig. 4 illustrates a partial construction of a phase locked loop (PLL) of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention, Fig. 5 is a circuit diagram of an amplification circuit structure of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention, Fig. 6 is a detailed diagram of a PLL of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention, Fig.7 is a graph illustrating a characteristic of a diode which is applicable to a VCO according to the present invention, Fig.8 is a photograph illustrating output waveforms of a primary amplifier and a secondary amplifier according to the present invention, and Fig.9 is a graph illustrating an output performance of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention

<33> Hereinafter, a description of constituent elements will be made with reference to the accompanying drawings.

<34> Fig. 2 is a block diagram of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention. The frequency stabilized dielectric heating apparatus includes a phase locked loop (PLL) 100, a band pass filter (BPF) 200, a preamplifier 300, a power amplifier 400, an impedance matching circuit 500, a load 600, and an interface 700.

<35> The PLL 100 is known as a phase fixing circuit, a phase locked device, or a phase locked circuit. The PLL 100 is a device for forcedly maintaining a signal at a specific phase. Since a phase is a concept of integrating a frequency, fixing the phase is almost similar to fixing the frequency in meaning. Therefore, the PLL 100 can be called a frequency fixing circuit.

<36> The PLL 100 includes a crystal oscillator 110 for generating an output frequency, a primary divider 120 for primarily dividing the output frequency of the crystal oscillator 110, a phase detector 130 for receiving a frequency divided by the primary divider 120, a voltage controlled oscillator (VCO) 150 for receiving an output of the phase detector 130, and a secondary divider 140 for receiving an output of the VCO 150 and feeding back its output to the phase detector 130.

<37> To the VCO 150 of the PLL 100 are connected the BPF 200 for eliminating a harmonic component, the preamplifier 300 and the power amplifier 400 for amplifying an output of the BPF 200, the impedance matching circuit 500 for matching the amplified output with an impendence of the load 600 and outputting the matched output to the load 600, and the interface 700 which is a buffer circuit for measuring the impendence of the load 600 and feeding back the measured impedance to a voltage input terminal of the VCO 150.

-38> The VCO 150 is a device of which output frequency is proportional to an input voltage as illustrated in Fig.3 and varies the output frequency by controlling the input voltage. The VCO 150 is unstable because its output varies according to circumstances such as an ambient temperature.

<39> Therefore, as illustrated in Fig.4, the output frequency is fed back and an input terminal compensates for the frequency so that a stable frequency may be obtained. To this end, a comparator for comparing the feedback frequency with an original output frequency is needed and such a comparator is the phase detector 130 shown in Fig.2.

<40> The phase detector 130 requires an intended output frequency, that is, a comparison target value so that the target value may be compared with the feedback frequency value. The intended output frequency should have a stabilized frequency value which is not influenced by circumstances.

<4i> However, since a frequency in a high frequency band can not be fixed without swing, the crystal oscillator 100 and the primary divider 120 according to the present invention outputs a stable frequency of a low frequency band and this frequency is used as the intended output frequency value of the phase detector 130. The output of the VCO 150 is divided by the secondary divider 140 to have the same value as the intended output frequency to be inputted to the phase detector 130 and then fed back to the phase detector 130.

<42> Therefore, in the PLL 100 of the present invention, the output of the crystal oscillator 110 is divided by the primary divider 120 and then inputted to the phase detector 130. The output of the phase detector 130 is inputted to the VCO 150. The output of the VCO 150 is divided by the secondary divider 120 to have the same frequency as the output frequency of the primary divider 120 and then fed back to the phase detector 130.

<43> A pulse-voltage converter is connected between the phase detector 130 and the VCO 150 as shown in Fig.4. The pulse-voltage converter includes a charge pump 160 and a loop filter 170 and converts a feedback compensation value compared by the phase detector 130 into a voltage. The loop filter 170 is configured by a typical low pass filter (LPF). <44> To generate an output of 40MHz corresponding to an ISM band among frequency bands of IMHz to 200MHz which may be used for a dielectric heating apparatus, the primary divider 120 of which division ratio is 1024 divides a 10.24MHz frequency of the crystal oscillator 110 to obtain a low frequency band of 10KHz. A 40MHz output frequency of the VCO 150 is divided by the secondary divider 140 of which division ratio is 4000 to obtain a low frequency band of 10KHz and the 10KHz frequency is fed back to the phase detector 130.

<45> The PLL 100 constructed as described above outputs a stable high frequency irrespective of circumstances such as an ambient temperature because an output frequency band is fixed at 40MHz.

<46> Meanwhile, the dielectric heating apparatus of the present invention should change a used frequency value according to an impedance value of the load 600. To achieve this, the dielectric heating apparatus can modulate an output frequency by varying the division ratio of the secondary divider 140 of the PLL 100 or modulate an output voltage by varying an input voltage of the VCO 150. Then since a stable modulation frequency is fed back to the PLL 100 of the present invention, the dielectric heating apparatus can selectively use a permitted ISM band among frequency bands of IMHz to 200MHz which may be used in the dielectric heating apparatus.

<47> It is possible to control a frequency by the input voltage of the VCO 150 although the above-described example has shown modulation of the output frequency band in which the 10.24MHz frequency of the crystal oscillator 110 of the PLL 100 is divided by the primary divider 120 of which division ratio is 1024, the output of the VCO 150 which outputs a 40MHz frequency is divided by the secondary divider 140 of which division ratio is variable, and the divided output is fed back to the phase detector 130.

<48> An operation of the frequency stabilized dielectric heating apparatus having the aforementioned construction according to the present invention will now be described.

<49> A 10.24MHz frequency generated from the crystal oscillator 110 of the PLL 100 is divided by the primary divider 120 with a division ratio of 1024 and the divided frequency is inputted to the phase detector 130. The output of the phase detector 130 is inputted to the VCO 150 which generates a 40MHz frequency and the output of the VCO 150 is divided by the secondary divider 140 with a variable division ratio The output of the secondary divider 140 is fed back to the phase detector 130 to modulate an output frequency band.

<50> The output frequency band is transmitted to the load 600 via the BPF 200, the preamplifier 300, the power amplifier 400, and the impedance matching circuit 500.

<5i> The BPF 200 is connected to the VCO 150 and eliminates a harmonic component generated from the PLL 100. The output of the BPF 200 is amplified by an amplification circuit. The amplification circuit includes the preamplifier 300 and the power amplifier 400. The output of the PLL 100 is amplified to 30 Watts (W) by the preamplifier 300 and the output of the power amplifier 400 is amplified to 500W.

<52> The output of the amplification circuit is matched with an impedance of the load 600 through the impedance matching circuit 500 and then inputted to the load 600.

<53> Now, a general flat electrode as an example to an electrode supplying a high frequency to the load 600 is considered in terms of an output. Dielectric heating uses dielectric loss of a heated material (load) and a principle of an LC serial resonance is used according to the thickness of an object. If the distance between flat electrodes of an output terminal or the thickness of a dielectric material of a load varies according to heating, the impedance (variation in C) of the load 600 varies, causing deviation of a resonant point (resonant frequency),

<54> Therefore, a stable power applied originally to the load 600 varies by an impedance variation of the load 600 (including variations in the distance between the electrodes and a load impedance) and thus becomes unstable with lapse of time.

<55> The present invention provides the most appropriate frequency output demanded by the load impedance by feeding back the impedance variation of the load 600 and compensating for a frequency output.

<56> To this end, the dielectric heating apparatus further includes the interface 700 which is a buffer circuit to measure the impedance of the load 600 and feeds back the measured impedance to a voltage input terminal of the VCO 150. When the impedance of the load 600 varies and thus an LC resonant frequency of the load 600 is shifted, the interface 700 feeds back the shifted frequency to the input voltage terminal of the VCO 150 to shift an output frequency or cut off an output. The impedance value of the load 600 sensed by the buffer circuit is converted into a VCO input compensation value through a compensator 151 and changes the output frequency of the VCO 150, thereby shifting the resonant frequency or cutting off a power at an impedance in which a danger of a short circuit between electrodes may exist

<57> According to the present invention described above, a desired oscillating frequency of the dielectric heating apparatus can be stably generated irrespective of external disturbance. Furthermore, the modulation of a frequency output is easily performed to meet the demand of the load 600. Optimal energy efficiency can be obtained even though the frequency output inputted to the load 600 varies with respect to a variation in the impedance of the load 600 while dielectric heating is being implemented. Moreover, it is possible to cope with a short-circuit accident which may occur in the load 600 and it is convenient to handle the dielectric heating apparatus.

<58> An amplification circuit structure of the frequency stabilized dielectric heating apparatus using a semiconductor will now be described.

<59> Fig. 5 is a circuit diagram of an amplification circuit structure of a frequency stabilized dielectric heating apparatus using a semiconductor according to the present invention. The amplification circuit structure has a construction in which an output of the VCO 150 is 40MHz by using a crystal oscillating frequency of 10.24MHz as a reference frequency, and an amplified signal of IW (3OdB) is amplified to 3OW (14.8dB) and further to 500W. The amplification circuit structure includes a PLL 100, a preamplifier 300 and a _

power amplifier 400.

<60> In the PLL 100, a crystal oscillating frequency outputted by the crystal oscillator 110 is divided into a reference frequency by the primary divider 120 and the divided frequency is inputted to the phase detector 130. An output of the phase detector 130 is inputted to the VCO 150. The output of the VCO 150 is divided into a comparison frequency by the secondary divider 140 and then inputted to the phase detector 130 which compares the comparison frequency with the reference frequency. A phase difference between the reference frequency and the comparison frequency is inputted to the charge pump 160 and inputted to the VCO 150 through the LPF 170 as a bias voltage source, thereby stabilizing the output frequency of the VCO 150 at 40MHz.

<6i> The preamplifier circuit 300 is connected to the output terminal of the VCO 150. A primary amplifier 310 of the preamplifier 300 amplifies the output of the VCO 150 to IW at an impedance of 50? A 40MHz tuning circuit of a secondary amplifier 320 connected to the output terminal of the primary amplifier 310 eliminates a harmonic signal and amplifies the output of the primary amplifier 310 to 3OW.

<62> The primary amplifier 310 of the preamplifier 300 outputs IW at an impedance of 50?by a transistor 311 driven by a power of 30V, a pre-trimmer 312 for converting and adjusting the impedance, and a post-trimmer 313 for adjusting a maximum resonant point. The secondary amplifier 320 outputs 3OW by applying the IW output outputted from the primary amplifier 310 to both inputs of a push-pull form of a first troidal core 322 and adjusting trimmers of second and third troidal cores 323 and 324. A 6OpF of the third troidal core 324 eliminates a harmonic frequency by the 40MHz tuning circuit.

<63> The 3OW output amplified by the preamplifier 300 is inputted to the power amplifier 400 and amplified to 500W by field-effect transistor (FET) semiconductors 410 and 420 of the power amplifier 400.

Ϊ64> An operation of the amplification circuit structure of the dielectric heating apparatus using a semiconductor will now be described. <65> A detailed construction of the PLL 100 is illustrated in Fig. 6. The crystal oscillator 110 of the PLL 100 generates an output frequency of 10.24MHz. The primary divider 120 divides the 10.24MHz output frequency by a division ratio of 1024 and generates a clock source so that a reference clock REF may be lOKHz. The secondary divider 140 divides a 40MHz output frequency outputted from the VCO 150 by a division ratio of 4000 so that an output clock may be 10KHz. The phase detector 130 compares the output clock with the reference clock. The compared result is supplied to the VCO 150 through the LPF for compensating for a phase according to a frequency, thereby stabilizing the frequency.

«56> Therefore, a frequency of the crystal oscillator 110 is set to 10.24MHz, and RAO and RAl are set to have a division ratio of 1024 as indicated in the following Table 1 to generate the reference clock REF of 10KHz. A 40MHz output frequency generated from the VCO 150 is divided by a division ratio of 4000 to have an output clock of 10KHz. The output clock is compared with the reference clock. A phase detection (PD) output corresponding to a phase difference between the output clock and the reference clock is applied to the VCO 150 as a bias voltage source via the LPF and varies the capacitance of a varactor diode. Consequently, an output frequency of the VCO 150 is stabilized.

<67> [Table 1] <68> Reference Frequency Divider and Decoder <69>

The output frequency of the VCO 150 is determined by a variable capacitor 5Op, a varactor diode (MV104), and an L2(0.βd/4Φ/6~7t) at

1

²^^LC _{< A} i_{ow power} transistor (2N5109) used for VHF/UHF is utilized in the VCO 150. The transistor (2N5109) has a maximum gain of 12dB at 200MHz and is used in a 40MHz driving oscillator. <70> The VCO 150 eliminates the PD output of the PLL 100 and sets a central frequency to 40MHz by using a trimmer. If the VCO 150 connects the PD output to turn off a light emitting diode (LED), a 40MHz lock is set and the output of the VCO 150 is applied to the secondary divider 140 of the PLL 100. The PD output is applied to the varactor diode as a control voltage through the LPF and thus serves as a loop.

<7i> The varactor (MV104) diode shows a variable capacitance characteristic from 10 to lOOpF with respect to an input voltage of 0.3 to 30V as shown in Fig. 7. Therefore, the varactor is suitably applied to the VCO 150 as a feedback loop circuit of the PLL 100 to obtain a stable frequency oscillating circuit.

<72> The preamplifier 300 is comprised of the primary amplifier 310 and the secondary amplifier 320 as shown in Fig. 5. The primary amplifier 310 uses a transistor (2N3866) 311 driven by a 30V power. The transistor (2N3866) is generally used in VHF/UBF band and can obtain efficiency of about 45% at a gain of 1OdB or more with respect to an output and input of IW or more.

<73> The pre-trimmer 312 for impedance conversion and adjustment and the post-trimmer 313 for maximum resonant point adjustment are controlled to obtain a maximum output of IW at an impedance of 50Ω.

<?4> Fig. 8 is a photograph illustrating output waveforms of a primary amplifier and a secondary amplifier according to the present invention. Referring to Fig. 8, a lower graph is an output waveform of the primary amplifier 310 and an upper graph is an output waveform of the secondary amplifier 320.

<75> As shown, the output of the primary amplifier 310 is a distorted waveform including many harmonic components. Therefore, a resonant circuit is constructed at an output terminal of the primary amplifier 310, that is, at an input terminal of the secondary amplifier 320 to eliminate noise generated from the harmonic components.

<76> The secondary amplifier 320 of the preamplifier 300 amplifies IW outputted from the primary amplifier 310 to 3OW by a metal-oxide-semiconductor (MOS) transistor 321. That is, the IW output is supplied to an input of a push-pull form of the primary troidal core 322 and the trimmers of the second and third troidal cores 323 and 324 are adjusted to be amplified to 3OW. The 6OpF of the third troidal core 324 eliminates a harmonic frequency by the 40MHz tuning circuit.

<77> The following Table 2 and Fig. 9 show a performance measurement result and performance comparison analysis graph of the dielectric heating apparatus measured within the range of from 11V/7W to 28V/45W. As shown in Table 2 and Fig. 9, dissipated current is increased as an input voltage is increased and the power efficiency of the entire system is about 52% with respect to dissipated power.

<78> [Table 21 <79> Performance Measurement Result <80>

The output of 3OW amplified by the preamplifier 300 is supplied to an input terminal of the power amplifier 400 and amplified to 500W by the FET semiconductors 410 and 420.

<81> Therefore, the present invention uses a semiconductor, that is, a high power MOS FET device instead of a vacuum tube used as a high power (500W) power amplifier. When a preamplifier preceding the power amplifier is designed, a PLL for stably oscillating a frequency is applied. An output of 500W or more is generated by supplying an output of the preamplifier having stability of 40 MHz±100 Hz and an average power of 3OW (44.77dB) to the power amplifier having an amplification factor of 12dB or more. Therefore, harmonic oscillation is minimized by a stable frequency oscillation and a resonant frequency (resonant point) is kept constant during dielectric heating, thereby improving power efficiency.

<82> Although the exemplary embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

[CLAIMS] [Claim 1]

<84> A frequency stabilized dielectric heating apparatus using a semiconductor, comprising:

<85> a phase locked loop 100,

<86> wherein the phase locked loop 100 includes a crystal oscillator 110 for generating an output frequency, a primary divider 120 for primarily dividing the output frequency of the crystal oscillator 110, a phase detector 130 for receiving a frequency divided by the primary divider 120, a voltage controlled oscillator 150 for receiving an output of the phase detector 130, and a secondary divider 140 for receiving an output of the voltage controlled oscillator and feeding back its output to the phase detector 130. [Claim 2]

<87> The frequency stabilized dielectric heating apparatus according to Claim 1, wherein the primary divider 120 of the phase locked loop 100 divides the output frequency of 10.24MHz of the crystal oscillator 110 by a division ratio of 1024, and the secondary divider 140 divides an output of 40MHz of the voltage controlled oscillator 150 by a division ratio of 4000 and feeds back its divided output to the phase detector 130. [Claim 3]

<88> The frequency stabilized dielectric heating apparatus according to Claim 1, wherein the primary divider 120 of the phase locked loop 100 divides the output frequency of 10.24MHz of the crystal oscillator 110 by a division ratio of 1024, and the secondary divider 140 divides an output of 40MHz of the voltage controlled oscillator by a variable division ratio and feeds back its divided output to the phase detector 130, thereby modulating an output frequency band. [Claim 4]

<89> The frequency stabilized dielectric heating apparatus according to any one of Claims 1 to 3, further comprising:

<90> a band pass filter 200 connected to the voltage controlled oscillator 150 of the phase locked loop 100, for eliminating a harmonic component;

<9i> a preamplifier 300 and a power amplifier 400 for amplifying an output of the band pass filter 200; and

<92> an impedance matching circuit 500 for matching the amplified output with an impedance of a load 600 and outputting the matched output to the load 600. [Claim 5]

<93> The frequency stabilized dielectric heating apparatus according to Claim 4, further comprising an interface 700 which is a buffer circuit for measuring the impedance of the load 600 and feeding back the impedance to a voltage input terminal of the voltage controlled oscillator 150, wherein if an LC (inductor-capacitor) resonant frequency of the load 600 is shifted by a variation in the impedance of the load 600, the interface 700 feeds back the shifted frequency to the voltage input terminal of the voltage controlled oscillator 150 to shift an output frequency of the phase locked loop 100 or cut off an output of the phase locked loop 100. [Claim 6]

<94> An amplification circuit structure of a frequency stabilized dielectric heating apparatus using a semiconductor, comprising:

<95> a phase locked loop 100 including a phase detector 130 for receiving a reference frequency into which a crystal oscillating frequency is divided and a comparison frequency, and a voltage controlled oscillator 150 for receiving an output of the phase detector 130, wherein a phase difference between the reference frequency and the comparison frequency into which an output of the voltage controlled oscillator is divided is applied via a low pass filter to the voltage controlled oscillator 150 as a bias voltage source and an output frequency of the voltage controlled oscillator 150 is stabilized at 40MHz;

<96> a preamplifier 300 connected to an output terminal of the voltage controlled oscillator 150 and including a primary amplifier 310 for amplifying the output of the voltage controlled oscillator 150 to IW at an impedance of 50 and a secondary amplifier 320 connected to an output terminal of the primary amplifier to amplify an output of the primary amplifier 310 to 3OW by eliminating a harmonic signal by a 40 MHz tuning circuit; and

<97> a power amplifier 400 including field-effect-transistor (FET) semiconductors 410 and 420 for amplifying a 3Of output amplified by the preamplifier 300 to 500W. [Claim 7]

<98> The amplification circuit structure according to Claim 6, wherein the phase locked loop 100 generates an output frequency of 10.24MHz by a crystal oscillator 110, divides the reference frequency by a primary divider 120 of which division ratio is 1024 to set a reference clock to 10KHz, divides the 40MHz output frequency generated from the voltage controlled oscillator 150 by a secondary divider 140 of which division ratio is 4000 to set an output clock to 10KHz, and compares the output clock with the reference clock. [Claim 8]

<99> The amplification circuit structure according to Claim 6, wherein the voltage controlled oscillator 150 eliminates an output of a phase detector of the phase locked loop 100, sets a central frequency to 40MHz by using a trimmer, causes an LED to be turned off by connecting the output of the phase detector to have a 40MHz lock, applies the output of the voltage controlled oscillator 150 to a secondary divider 140 of the phase locked loop 100, and applies an output of the phase detector to a varactor diode as a control voltage via a low pass filter. [Claim 9] ioo> The amplification circuit structure according to Claim 6, wherein the primary amplifier 310 of the preamplifier 300 outputs IW at an impedance of 50 by a transistor 311 driven by a power of 30V, a pre-trimmer 312 for impedance conversion and adjustment, and a post-trimmer 313 for maximum resonant point adjustment. [Claim 10] ioι> The amplification circuit structure according to any one of Claim 6 and 9, wherein the secondary amplifier 320 of the preamplifier 300 outputs 3OW by a metal-oxide-semiconductor (MOS) transistor 321 by applying the IW generated from the primary amplifier 310 to both inputs of a push-pull form of a primary troidal core 322 and controlling trimmers of secondary and third troidal cores 323 and 324, and wherein a 6OpF of the third troidal core 324 eliminates a harmonic component by a 40MHz tuning circuit.