WO2009106915A1 - Method for reducing the amount or eliminating the crystalline defects, in a semiconductor layer of a composite structure - Google Patents

Method for reducing the amount or eliminating the crystalline defects, in a semiconductor layer of a composite structure Download PDF

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Publication number
WO2009106915A1
WO2009106915A1 PCT/IB2008/001891 IB2008001891W WO2009106915A1 WO 2009106915 A1 WO2009106915 A1 WO 2009106915A1 IB 2008001891 W IB2008001891 W IB 2008001891W WO 2009106915 A1 WO2009106915 A1 WO 2009106915A1
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Prior art keywords
semiconductor layer
silicon
thickness
handle substrate
composite structure
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PCT/IB2008/001891
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French (fr)
Inventor
Oleg Kononchuk
Konstantin Bourdelle
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S.O.I.Tec Silicon On On Insulator Technologies
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Priority to PCT/IB2008/001891 priority Critical patent/WO2009106915A1/en
Publication of WO2009106915A1 publication Critical patent/WO2009106915A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface

Definitions

  • the invention relates to the treatment of structures for electronics, in particular or optoelectronics, the structure comprising a semiconductor layer made of a semiconductor material (or bulk substrate) directly bonded to a handle substrate generally referred as DSB structures (Direct Silicon Bonding).
  • DSB structures Direct Silicon Bonding
  • electro-electronic(s) and “opto-electronic(s)” relate to any micro-electronic, nano-electronic, opto-microelectronic, opto- nanoelectronic, photovoltaic or the like, components technology.
  • the quality of superficial layer is a major parameter in semiconductor structures because it influences directly the quality of the future devices.
  • OSF oxidation induced stacking faults
  • COP crystal originated particles
  • interstitial type dislocations are considered as major defects. Similar defects could be found in other semiconductor materials.
  • a solution to avoid the production of defective layer is to use silicon single crystal wafers having semiconductor layer with a high crystallographic quality.
  • the document US2005/0263063 discloses the fabrication of such wafers, by slicing a silicon single crystal ingot grown by the Czochralski method, at an extremely low growth rate.
  • the document US 2006/0172508 describes the fabrication of a SeOI structure (Semiconductor On Insulator) having a thin silicon transferred layer as the semiconductor layer, on a handle substrate bonded together via an oxide layer.
  • the semiconductor layer is transferred from a donor substrate selected to have small size of defects that can be reduced or eliminated after a subsequent curing treatment.
  • This curing treatment that can comprise in a rapid thermal annealing is applied to the structure in a non-oxidizing atmosphere leading to the reduction of the density of the vacancy clusters (COPs) present in the thin transferred layer.
  • COPs vacancy clusters
  • This method is applied particularly on SOI (Silicon On Insulator) structures, leading to the reduction of the number of COPs but it has been observed that it could not always eliminate all the vacancy cluster defects, specially those present close to the oxide layer. Furthermore, this method requires to select a donor substrate with predetermined defects characteristics.
  • the invention is aimed to overcome these previous cited problems.
  • the goal of the invention is to eliminate or reduce the size and the amount of crystalline defects present near the interface and/or inside the semiconductor layer of a composite structure, the crystalline defects being specially vacancy clusters, COPs, interstitial type dislocations or OSF, and the composite structure being a so called "DSB structure".
  • the invention allows the fabrication of composite substrates with a semiconductor layer which could have lower quality before the application of the method of the present invention, and therefore would cost less than other composite substrates directly fabricated from high quality semiconductor substrates.
  • the invention proposes, according to a first aspect, a method for eliminating or reducing the amount and/or the size of crystalline defects in a semiconductor layer of a composite structure, comprising : - providing a handle substrate 1,
  • said semiconductor layer 2 is selected so as to have a thickness greater than a threshold value which is representative of the size of the crystalline defects
  • the method further comprises a heat treatment of said bonded composite structure 10 in an inert or reducing atmosphere, with a high temperature and a duration selected for eliminating or reducing the amount and/or the size of the crystalline defects.
  • the crystalline defects comprise vacancy clusters defects
  • the heat treatment is realized in nitrogen, argon, hydrogen or a mixture thereof atmosphere;
  • the heat treatment is realized at a temperature between 900 0 C and 1300 0 C, during 5 minutes and 5 hours ;
  • the threshold value for the thickness of the semiconductor layer is around 200 nm. and the semiconductor layer 2 contains maximum 10 6 cm "3 vacancy clusters.
  • the semiconductor layer is in silicon (1 , 0, 0), silicon (1 , 1 , 0), Ie silicon (1 , 1 , 1), germanium and its thickness around 200 nm to 1 micrometer, preferably around 500 nm to 700 nm ;
  • the bonding between the handle substrate with the semiconductor layer 2 is a molecular hydrophobic bonding ;
  • the semiconductor layer 2 is transferred from a donor substrate 4 to the handle substrate 1 and submitted to a thickness adjustment.
  • Figures 1A to 1C are a schematic illustration various successive steps according to one embodiment of the present fabrication method
  • FIGS. 2A to 2E graphically illustrate various successive steps according to another embodiment of the present fabrication method
  • FIGS 3A to 3E graphically illustrate various successive steps according to another embodiment of the present fabrication method.
  • the main purpose of this invention is to reduce or eliminate crystalline defects like vacancy clusters, OSF, interstitial type dislocations present in a semiconductor layer directly bonded to a handle substrate, the semiconductor layer having a thickness of greater than a threshold value representative of the size of the defects potentially present inside the thickness of this semiconductor layer but also at the interface between this semiconductor layer and the handle substrate.
  • a semiconductor layer 2 is bonded directly to a handle substrate 1 by molecular bonding.
  • the semiconductor layer 2 is in silicon (1 ,0,0), (1 ,1 ,0) or (1 ,1 ,0) or in germanium.
  • This semiconductor layer has a thickness of 200 nm to 1 micrometer, preferably 500 nm to 700 nm. More precisely, the thickness of the semiconductor layer 2 has a thickness greater than a threshold value which is representative of the size of the crystalline defects. For instance, the semiconductor layer 2 has a maximum density of vacancy clusters of 10 6 cm '3 and the threshold value is around 200 nm.
  • the handle substrate is a mono-layer substrate or a multilayer substrate. It is in a semiconductor material like silicon (1 , 0, 0), silicon (1 , 1 , 0), silicon (1 , 1 , 1), polycristallin silicon, poly or mono-silicon carbide.
  • the semiconductor layer 2 and the handle substrate 1 are bonded by hydrophilic or hydrophobic molecular bonding.
  • the bonding is preferably a hydrophobic bonding obtained by a hydrofluoric acid (HF) cleaning known as a "HF last" treatment applied on both surfaces to be bonded, by an UV treatment coupled with a heat treatment like it is presented in the S. L. Holl's article; « UV Activation Treatment for Hydrophobia Wafer Bonding » Journal of the Electrochemical Society, 153 (7) G613-G616 (2006) or by a cleaning under HF vapor and/ or high temperature treatment under ultra high vacuum like it is exposed in the M. J. Kim and R. W. Carpenter's article , ⁇ Heterogeneous Silicon Integration by Ultra-High Vacuum Wafer Bonding » Journal of the Electrochemical Materials, VoI 32, No 8, 2003.
  • HF hydrofluoric acid
  • An other technique for hydrophobic bonding consists in preparing at least one of the future bonding surfaces by applying a heat treatment from 800 0 C to 1200 0 C in a gaseous atmosphere comprising hydrogen and/or argon for a duration of time longer than 30 seconds.
  • one or both surfaces to be bonded can be submitted to a plasma treatment (under argon, hydrogen, and /or nitrogen) to enhance the bonding energy at the bonding interface 3.
  • a plasma treatment under argon, hydrogen, and /or nitrogen
  • the bonded composite structure 10 is obtained.
  • the term "composite” means than the structure is a multilayer structure containing at least two different layers : the semiconductor layer 2 and the handle substrate 1.
  • a heat treatment of the bonded composite structure could be applied to reinforce the energy of the bonding interface 3, from 600 0 C to 1200 0 C for 30 min to several hours.
  • the method of the invention comprises a heat treatment of the bonded composite structure 10 with a high temperature and a duration selected for reducing the amount or eliminating the crystalline defects, in particular the vacancy clusters.
  • the high temperature of the heat treatment means superior to 900 0 C. More precisely, the temperature is chosen between 900 0 C and 1300 0 C, specially around 1100 0 C and 1200 0 C and the duration of this treatment is between 5 minutes and 5 hours.
  • the atmosphere is chosen to favor the diffusion of oxygen present in the composite structure.
  • the preferred atmosphere for the heat treatment is an inert or reducing atmosphere, like hydrogen, argon, nitrogen or a mixture thereof.
  • the heat treatment of the invention leads firstly to the dissolution and the diffusion of the oxygen present in particular in the vacancy clusters, especially in the inner wall of those defects, and to the curing of the layer by crystalline rearrangement of the semiconductor layer 2.
  • the limited amount of oxygen after the dissolution steps helps and favors the curing effect of the semiconductor layer by crystalline rearrangement.
  • the thickness of the semiconductor layer 2 is a very important parameter : it has to be thick enough for reducing the number or eliminating the crystalline defects, present near the interface 3 and inside the semiconductor layer 2 itself, but thin enough to allow the diffusion of the oxide out of the bonded composite structure 10. For this reason, the thickness of the semiconductor layer 2 has a thickness of 200 nm to 1 micrometer, preferably 500 nm to 700 nm. In all cases, the semiconductor layer 2 is selected to have a thickness greater than a threshold value of 200 nm, which is representative of the size of the crystalline defects, specially the vacancy clusters.
  • the semiconductor layer 2 is a layer directly bonded to the handle substrate 1 or a layer provided by a transfer from a donor substrate 4 to the handle substrate 1 ,
  • the semiconductor layer 2 is obtained by reduction of the thickness of the donor substrate 4 which can be realized by grinding, by chemical mechanical polishing, by chemical etching, or by a one dry or wet sacrificial oxidation.
  • the reduction of the thickness of the donor substrate 4 could also be obtained by formation of a zone of weakness 5 inside the donor substrate 4.
  • the zone of weakness 5 is preferably performed by implantation or co-implantation of atomic species, like for example hydrogen and/or helium, inside the donor substrate 4 delimiting the thickness of the semiconductor layer 2 to be transferred and the detachment of the semiconductor layer 2 along the zone of weakness 5 obtained by application of a thermal, mechanical and/or chemical treatment.
  • the reduction of the thickness of the donor substrate 4 is obtained by formation of a porous layer 6 delimiting the thickness of the semiconductor layer 2 to be transferred from the donor substrate 4, the detachment of the semiconductor layer 2 along the porous layer 6 being realized by application of a thermal, mechanical and/or chemical treatment.
  • the thickness of the semiconductor layer 2 could be adjusted to a final desired thickness. This could be obtained for instance by chemical, mechanical polishing and/or by oxidation/deoxidation treatments depending on the thickness to be removed.
  • RTA rapid thermal anneal
  • an additional thermal treatment could be applied on the semiconductor layer 2 before bonding with the handle substrate 1.
  • This additional treatment is realized under pure non oxidizing atmosphere at a temperature around 1000 0 C to 1200 0 C during 20 seconds to 1 minute.
  • This additional treatment is applied before bonding to enhance the efficiency of the crystalline defects elimination, especially for the vacancy clusters present on the surface of the semiconductor layer 2 which will be in contact with the handle substrate, forming the bonding interface 3.
  • a Silicon (110) donor substrate 4 is implanted with hydrogen atoms to form a zone of weakness 5 and delimitate the semiconductor layer 2.
  • the dose and energy of hydrogen atoms are about 6x10 1 ⁇ H + /cm 2 and 50 keV to delimit a thickness of about 500 nm for the semiconductor layer 2.
  • the donor substrate 4 and the silicon (1 ,0,0) handle substrate 1 are submitted to a "HF last" treatment to provide hydrophobic surfaces.
  • the bonding could also been obtained under ultrahigh vacuum, as it is described in the Fecioru's article (Alin Mihai Fecioru, Stephan Senz, Roland Scholz, and Ulrich G ⁇ sele, Appl. Phys. Lett. 89, 192109 - 2006).
  • the composite bonded structure 10 is obtained by detachment along the zone of weakness 5 in the donor substrate 4 after application of an annealing at 600-700 0 C during 30 minutes : the semiconductor layer 2 in silicon (1 ,1 ,0) is therefore transferred onto the silicon (1 ,0,0) handle substrate 1.
  • the heat treatment conform to the invention is then applied.
  • the bonded composite structure 10 is heated in a pure argon atmosphere, at 1200 0 C during 30 minutes for eliminating vacancy clusters present at the interface and in the thickness of the semiconductor layer 2 and generally improve crystalline quality of the semiconductor layer 2.
  • a finishing step like a dry oxidation followed by a deoxidation step is then realized for removing damages due to the implantation step and reducing the thickness of the semiconductor layer 2 to the desired thickness of 300 nm.
  • the final semiconductor layer 2' is therefore obtained, after application of a RTA treatment for smoothing the final surface (Figure 2E).
  • those steps could be repeated.
  • a thin native oxide layer 6 is present at the surface of the Si (1 ,0,0) donor substrate 4.
  • the detachment of the semiconductor layer 2 is realized by a mechanical withdrawal of a part of the donor substrate 4 by a grinding and polishing step to reach the desired thickness of the semiconductor layer 2 ( Figure 3D).
  • the heat treatment of the present invention is applied by heating the bonded structure at 1000 0 C in pure nitrogen atmosphere. After 2 hours of heating for dissolving the native oxide layer but also eliminating the crystalline defects, present in the semiconductor layer 2 and/or at the bonding interface 3, the bonded composite structure 10 is obtained ( Figure 3E) with an improved crystalline quality of the semiconductor layer 2.
  • the heat treatment of the invention leads to a very smooth final surface of the bonded composite structure 10 avoiding any finishing steps.

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Abstract

The present invention relates to a method for reducing the amount or eliminating the crystalline defects in a semiconductor layer of a composite structure, said composite structure comprising said semiconductor layer bonded to a handle substrate, the method comprising providing a handle substrate, providing said semiconductor layer, bonding said handle substrate to the said semiconductor layer, in order to obtain a bonded composite structure, the method being characterized in that the semiconductor layer is selected to have a thickness greater than a threshold value which is representative of the size of the crystalline defects, and further comprises a heat treatment of said bonded composite structure with a high temperature and a duration selected for reducing the amount or eliminating the crystalline defects.

Description

Method for reducing the amount or eliminating the crystalline defects, in a semiconductor layer of a composite structure
The invention relates to the treatment of structures for electronics, in particular or optoelectronics, the structure comprising a semiconductor layer made of a semiconductor material (or bulk substrate) directly bonded to a handle substrate generally referred as DSB structures (Direct Silicon Bonding).
It is to be understood that the terms "electronic(s)" and "opto-electronic(s)" relate to any micro-electronic, nano-electronic, opto-microelectronic, opto- nanoelectronic, photovoltaic or the like, components technology.
The quality of superficial layer is a major parameter in semiconductor structures because it influences directly the quality of the future devices. For example, in silicon, micro-defects of oxygen precipitates that become nuclei of oxidation induced stacking faults (referred as OSF)1 crystal originated particles (referred to as COP) and interstitial type dislocations are considered as major defects. Similar defects could be found in other semiconductor materials.
A solution to avoid the production of defective layer is to use silicon single crystal wafers having semiconductor layer with a high crystallographic quality. The document US2005/0263063 discloses the fabrication of such wafers, by slicing a silicon single crystal ingot grown by the Czochralski method, at an extremely low growth rate.
An other technique described in the US 6 224 668 or US 6 843 847 documents consist in doping the silicon single crystal with nitrogen during its growth to reduce the size and density of crystal defects.
Alternatively, it can be sought to manufacture a semiconductor structure followed by a specific heat treatment leading to the elimination of the crystals defects.
In particular, the document US 2006/0172508 describes the fabrication of a SeOI structure (Semiconductor On Insulator) having a thin silicon transferred layer as the semiconductor layer, on a handle substrate bonded together via an oxide layer. The semiconductor layer is transferred from a donor substrate selected to have small size of defects that can be reduced or eliminated after a subsequent curing treatment. This curing treatment, that can comprise in a rapid thermal annealing is applied to the structure in a non-oxidizing atmosphere leading to the reduction of the density of the vacancy clusters (COPs) present in the thin transferred layer. This method is applied particularly on SOI (Silicon On Insulator) structures, leading to the reduction of the number of COPs but it has been observed that it could not always eliminate all the vacancy cluster defects, specially those present close to the oxide layer. Furthermore, this method requires to select a donor substrate with predetermined defects characteristics.
Therefore, it would be advantageous to find a method to fabricate SeOI structures without any constraint on the quality of the donor substrates, particularly for DSB structures, to give high quality final structure without or with only few defects inside the semiconductor layer or at the interface between the semiconductor layer and the handle substrate.
The invention is aimed to overcome these previous cited problems.
Especially, the goal of the invention is to eliminate or reduce the size and the amount of crystalline defects present near the interface and/or inside the semiconductor layer of a composite structure, the crystalline defects being specially vacancy clusters, COPs, interstitial type dislocations or OSF, and the composite structure being a so called "DSB structure".
The invention allows the fabrication of composite substrates with a semiconductor layer which could have lower quality before the application of the method of the present invention, and therefore would cost less than other composite substrates directly fabricated from high quality semiconductor substrates.
SUMMARY OF THE INVENTION
In order to reach this goal and to overcome the drawbacks of the prior art, the invention proposes, according to a first aspect, a method for eliminating or reducing the amount and/or the size of crystalline defects in a semiconductor layer of a composite structure, comprising : - providing a handle substrate 1,
- providing said semiconductor layer 2,
- bonding said handle substrate 1 directly to the said semiconductor layer 2, in order to obtain a bonded composite structure 10, the method being characterized in that :
• said semiconductor layer 2 is selected so as to have a thickness greater than a threshold value which is representative of the size of the crystalline defects,
• the method further comprises a heat treatment of said bonded composite structure 10 in an inert or reducing atmosphere, with a high temperature and a duration selected for eliminating or reducing the amount and/or the size of the crystalline defects.
Other optional characteristics of the said method are:
- the crystalline defects comprise vacancy clusters defects;
- the heat treatment is realized in nitrogen, argon, hydrogen or a mixture thereof atmosphere;
- the heat treatment is realized at a temperature between 9000C and 13000C, during 5 minutes and 5 hours ;
- the threshold value for the thickness of the semiconductor layer is around 200 nm. and the semiconductor layer 2 contains maximum 106 cm"3 vacancy clusters.;
- the semiconductor layer is in silicon (1 , 0, 0), silicon (1 , 1 , 0), Ie silicon (1 , 1 , 1), germanium and its thickness around 200 nm to 1 micrometer, preferably around 500 nm to 700 nm ;
- the bonding between the handle substrate with the semiconductor layer 2 is a molecular hydrophobic bonding ;
- the semiconductor layer 2 is transferred from a donor substrate 4 to the handle substrate 1 and submitted to a thickness adjustment.
BRIEF DECRIPTION OF THE FIGURES
Other aspects, purposes and advantages of this invention will become clearer after reading the following detailed description of the use of preferred processes of the invention, given as non-limitative examples with reference to the attached drawings in which :
Figures 1A to 1C are a schematic illustration various successive steps according to one embodiment of the present fabrication method;
Figures 2A to 2E graphically illustrate various successive steps according to another embodiment of the present fabrication method;
Figures 3A to 3E graphically illustrate various successive steps according to another embodiment of the present fabrication method.
DETAILED DESCRIPTION OF THE INVENTION
The main purpose of this invention is to reduce or eliminate crystalline defects like vacancy clusters, OSF, interstitial type dislocations present in a semiconductor layer directly bonded to a handle substrate, the semiconductor layer having a thickness of greater than a threshold value representative of the size of the defects potentially present inside the thickness of this semiconductor layer but also at the interface between this semiconductor layer and the handle substrate.
With reference to Figure 1 A to 1C, a semiconductor layer 2 is bonded directly to a handle substrate 1 by molecular bonding.
The semiconductor layer 2 is in silicon (1 ,0,0), (1 ,1 ,0) or (1 ,1 ,0) or in germanium. This semiconductor layer has a thickness of 200 nm to 1 micrometer, preferably 500 nm to 700 nm. More precisely, the thickness of the semiconductor layer 2 has a thickness greater than a threshold value which is representative of the size of the crystalline defects. For instance, the semiconductor layer 2 has a maximum density of vacancy clusters of 106 cm'3 and the threshold value is around 200 nm.
The handle substrate is a mono-layer substrate or a multilayer substrate. It is in a semiconductor material like silicon (1 , 0, 0), silicon (1 , 1 , 0), silicon (1 , 1 , 1), polycristallin silicon, poly or mono-silicon carbide.
The semiconductor layer 2 and the handle substrate 1 are bonded by hydrophilic or hydrophobic molecular bonding. The bonding is preferably a hydrophobic bonding obtained by a hydrofluoric acid (HF) cleaning known as a "HF last" treatment applied on both surfaces to be bonded, by an UV treatment coupled with a heat treatment like it is presented in the S. L. Holl's article; « UV Activation Treatment for Hydrophobia Wafer Bonding », Journal of the Electrochemical Society, 153 (7) G613-G616 (2006) or by a cleaning under HF vapor and/ or high temperature treatment under ultra high vacuum like it is exposed in the M. J. Kim and R. W. Carpenter's article , ^Heterogeneous Silicon Integration by Ultra-High Vacuum Wafer Bonding », Journal of the Electrochemical Materials, VoI 32, No 8, 2003.
An other technique for hydrophobic bonding consists in preparing at least one of the future bonding surfaces by applying a heat treatment from 8000C to 12000C in a gaseous atmosphere comprising hydrogen and/or argon for a duration of time longer than 30 seconds.
Optionally, one or both surfaces to be bonded can be submitted to a plasma treatment (under argon, hydrogen, and /or nitrogen) to enhance the bonding energy at the bonding interface 3.
After such preparation, the bonded composite structure 10 is obtained. The term "composite" means than the structure is a multilayer structure containing at least two different layers : the semiconductor layer 2 and the handle substrate 1. A heat treatment of the bonded composite structure could be applied to reinforce the energy of the bonding interface 3, from 6000C to 12000C for 30 min to several hours.
The method of the invention comprises a heat treatment of the bonded composite structure 10 with a high temperature and a duration selected for reducing the amount or eliminating the crystalline defects, in particular the vacancy clusters.
The high temperature of the heat treatment means superior to 9000C. More precisely, the temperature is chosen between 9000C and 13000C, specially around 11000C and 12000C and the duration of this treatment is between 5 minutes and 5 hours.
The atmosphere is chosen to favor the diffusion of oxygen present in the composite structure. For this reason, the preferred atmosphere for the heat treatment is an inert or reducing atmosphere, like hydrogen, argon, nitrogen or a mixture thereof. The heat treatment of the invention leads firstly to the dissolution and the diffusion of the oxygen present in particular in the vacancy clusters, especially in the inner wall of those defects, and to the curing of the layer by crystalline rearrangement of the semiconductor layer 2. The limited amount of oxygen after the dissolution steps helps and favors the curing effect of the semiconductor layer by crystalline rearrangement.
In the case of hydrophilic bonding, an other effect of the heat treatment is the dissolution of the native oxide that is present at the bonding interface 3. In this case, the heat treatment would need to be longer in comparison to structures obtained by hydrophobic bonding.
In both cases, the dissolution and the diffusion of oxygen from the semiconductor layer 2, particularly from the vacancies clusters, favor the crystalline rearrangement and lead to a better quality of the semiconductor layer 2. This can not be achievable when the bonded composite structure 10 presents an intermediate oxide layer between the semiconductor layer 2 and the handle substrate 1 , as disclosed in prior art, the intermediate oxygen layer acting as a source of oxygen and limiting crystalline rearrangement.
The thickness of the semiconductor layer 2 is a very important parameter : it has to be thick enough for reducing the number or eliminating the crystalline defects, present near the interface 3 and inside the semiconductor layer 2 itself, but thin enough to allow the diffusion of the oxide out of the bonded composite structure 10. For this reason, the thickness of the semiconductor layer 2 has a thickness of 200 nm to 1 micrometer, preferably 500 nm to 700 nm. In all cases, the semiconductor layer 2 is selected to have a thickness greater than a threshold value of 200 nm, which is representative of the size of the crystalline defects, specially the vacancy clusters.
The semiconductor layer 2 is a layer directly bonded to the handle substrate 1 or a layer provided by a transfer from a donor substrate 4 to the handle substrate 1 , The semiconductor layer 2 is obtained by reduction of the thickness of the donor substrate 4 which can be realized by grinding, by chemical mechanical polishing, by chemical etching, or by a one dry or wet sacrificial oxidation.
In reference with the figure 2B, the reduction of the thickness of the donor substrate 4 could also be obtained by formation of a zone of weakness 5 inside the donor substrate 4. In this case, the zone of weakness 5 is preferably performed by implantation or co-implantation of atomic species, like for example hydrogen and/or helium, inside the donor substrate 4 delimiting the thickness of the semiconductor layer 2 to be transferred and the detachment of the semiconductor layer 2 along the zone of weakness 5 obtained by application of a thermal, mechanical and/or chemical treatment.
In another embodiment, the reduction of the thickness of the donor substrate 4 is obtained by formation of a porous layer 6 delimiting the thickness of the semiconductor layer 2 to be transferred from the donor substrate 4, the detachment of the semiconductor layer 2 along the porous layer 6 being realized by application of a thermal, mechanical and/or chemical treatment.
Thereafter, if it is required the thickness of the semiconductor layer 2 could be adjusted to a final desired thickness. This could be obtained for instance by chemical, mechanical polishing and/or by oxidation/deoxidation treatments depending on the thickness to be removed.
Finally, a finishing step could applied on the final thin transferred layer 2' like a rapid thermal anneal (RTA). The RTA consists in an annealing from 10000C to 12000C during 30 seconds to 2 minutes, in an inert or reducing atmosphere with argon and /or nitrogen and/ or hydrogen.
Optionally, an additional thermal treatment could be applied on the semiconductor layer 2 before bonding with the handle substrate 1. This additional treatment is realized under pure non oxidizing atmosphere at a temperature around 10000C to 12000C during 20 seconds to 1 minute. This additional treatment is applied before bonding to enhance the efficiency of the crystalline defects elimination, especially for the vacancy clusters present on the surface of the semiconductor layer 2 which will be in contact with the handle substrate, forming the bonding interface 3.
The different steps of a first embodiment will be described more in detail with reference Figures 2A to 2E wherein a Silicon (110) donor substrate 4 is implanted with hydrogen atoms to form a zone of weakness 5 and delimitate the semiconductor layer 2. The dose and energy of hydrogen atoms are about 6x101δ H+/cm2 and 50 keV to delimit a thickness of about 500 nm for the semiconductor layer 2.
Before bonding, the donor substrate 4 and the silicon (1 ,0,0) handle substrate 1 are submitted to a "HF last" treatment to provide hydrophobic surfaces. Optionally, the bonding could also been obtained under ultrahigh vacuum, as it is described in the Fecioru's article (Alin Mihai Fecioru, Stephan Senz, Roland Scholz, and Ulrich Gόsele, Appl. Phys. Lett. 89, 192109 - 2006). Like presented on the figure 2D, the composite bonded structure 10 is obtained by detachment along the zone of weakness 5 in the donor substrate 4 after application of an annealing at 600-7000C during 30 minutes : the semiconductor layer 2 in silicon (1 ,1 ,0) is therefore transferred onto the silicon (1 ,0,0) handle substrate 1.
The heat treatment conform to the invention is then applied. The bonded composite structure 10 is heated in a pure argon atmosphere, at 12000C during 30 minutes for eliminating vacancy clusters present at the interface and in the thickness of the semiconductor layer 2 and generally improve crystalline quality of the semiconductor layer 2.
A finishing step, like a dry oxidation followed by a deoxidation step is then realized for removing damages due to the implantation step and reducing the thickness of the semiconductor layer 2 to the desired thickness of 300 nm. The final semiconductor layer 2' is therefore obtained, after application of a RTA treatment for smoothing the final surface (Figure 2E). Optionally, those steps could be repeated.
The different steps of a second embodiment will be described more in detail with reference Figures 3A to 3E. In this example as illustrated on Figure 3A, a thin native oxide layer 6 is present at the surface of the Si (1 ,0,0) donor substrate 4. After the bonding step with the silicon handle substrate 1 as it is illustrated on Figure 3C, the detachment of the semiconductor layer 2 is realized by a mechanical withdrawal of a part of the donor substrate 4 by a grinding and polishing step to reach the desired thickness of the semiconductor layer 2 (Figure 3D).
The heat treatment of the present invention is applied by heating the bonded structure at 10000C in pure nitrogen atmosphere. After 2 hours of heating for dissolving the native oxide layer but also eliminating the crystalline defects, present in the semiconductor layer 2 and/or at the bonding interface 3, the bonded composite structure 10 is obtained (Figure 3E) with an improved crystalline quality of the semiconductor layer 2. In this example, the heat treatment of the invention leads to a very smooth final surface of the bonded composite structure 10 avoiding any finishing steps.

Claims

1. Method for eliminating or reducing the amount and/or the size of crystalline defects in a semiconductor layer of a composite structure, comprising :
- providing a handle substrate 1 ,
- providing said semiconductor layer 2,
- bonding said handle substrate 1 directly to the said semiconductor layer 2, in order to obtain a bonded composite structure 10, the method being characterized in that :
• said semiconductor layer 2 is selected so as to have a thickness greater than a threshold value which is representative of the size of the crystalline defects,
• the method further comprises a heat treatment of said bonded composite structure 10 in an inert or reducing atmosphere, with a high temperature and a duration selected for eliminating or reducing the amount and/or the size of the crystalline defects.
2. Method according to claim 1 wherein the crystalline defects comprise vacancy cluster defects.
3. Method according to claim 1 and 2, wherein the inert or reducing atmosphere comprises nitrogen, argon, hydrogen or a mixture thereof.
4. Method according to one of claim 1 to 3 , wherein the high temperature is between 9000C and 13000C.
5. Method according to one of claim 1 to 4, wherein the duration of the heat treatment is between 5 minutes and 5 hours.
6. Method according to one of claim 1 to 5, wherein the threshold value is 200 nm.
7. Method according to one of claim 1 to 6, wherein the semiconductor layer 2 contains a maximum of 106 cm"3 vacancy clusters.
8. Method according to one of claim 1 to 7, wherein the semiconductor layer 2 is in silicon (1 , 0, O)1 silicon (1 , 1 , 0), Ie silicon (1 , 1 , 1), germanium.
9. Method according to one of claim 1 to 8, wherein the thickness of the semiconductor layer 2 is around 200 nm to 1 micrometer, preferably around 500 nm to 700 nm.
10. Method according to one of claim 1 to 9, wherein the bonding between the handle substrate 1 with the semiconductor layer 2 is hydrophobic bonding.
11. Method according to one of claim 1 to 10, wherein a native oxide layer is present at the interface 3 of the bonded composite structure 10.
12. Method according to one of claim 1 to 11 , wherein the semiconductor layer 2 is transferred from a donor substrate 4 to the handle substrate 1.
13. Method according to one of claim 1 to 12, wherein the transfer of the semiconductor layer 2 is obtained by reduction of the thickness of the donor substrate 4.
14. Method according to claim 13,
(a) wherein the reduction of the thickness donor substrate 4 is obtained by forming a zone of weakness 5 in the donor substrate 4 delimiting the thickness of the semiconductor layer 2 to be transferred,
(b) and wherein the transfer of the said semiconductor layer 2 on the handle substrate 1 is obtained by application of a thermal, mechanical and/or chemical treatment and by detachment of the semiconductor layer 2 along the zone of weakness 5.
15. Method according to claim 14, wherein the zone of weakness 5 is obtained by implantation of at least one atomic and/or ionic species and wherein the detachment is realized by application of a heat treatment between 2000C and 6000C.
16. Method according to one of claim 1 to 15, wherein the thickness of the semiconductor layer 2' around 200 nm to 1 micrometer is obtained by a thickness adjustment realized by chemical mechanical polishing and/or by oxidation/deoxidation treatments.
17. Method according to one of claim 1 to claim 16, wherein an additional thermal treatment applied on the semiconductor layer 2 before bonding it with the handle substrate 1.
18. Method according to claim 17, wherein the additional thermal treatment is realized under pure non oxidizing atmosphere at a temperature around 1000°C to 12000C during 20 seconds to 1 minute.
19. Method according to one of claimi to 18, wherein the handle substrate is silicon (1 , 0, 0), silicon (1 , 1 , 0), Ie silicon (1 , 1 , 1), polycrystalline silicon, mono or poly- silicon carbide, quartz.
PCT/IB2008/001891 2008-02-26 2008-02-26 Method for reducing the amount or eliminating the crystalline defects, in a semiconductor layer of a composite structure WO2009106915A1 (en)

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