WO2009104129A2

WO2009104129A2 - Electronic circuitry and method of controlling an electronic circuitry

Info

Publication number: WO2009104129A2
Application number: PCT/IB2009/050637
Authority: WO
Inventors: Joseph Briaire
Original assignee: Nxp B.V.
Priority date: 2008-02-18
Filing date: 2009-02-17
Publication date: 2009-08-27
Also published as: WO2009104129A3

Abstract

An electronic circuitry based on current-mode logic is provided which comprise a logic unit (LP) having a plurality of latch logic units (L1, L2, LN) each with a hold node (H1 - HN) and a sample node (S1 - SN) and a clock unit (CP) having a sample node (S0) and a hold node (H0) as well as a clock circuitry (T1, T2, I_N) for providing clock signals to the logic unit (LP) by providing clock controlled current to the latch logic units (L1 - LN). Each latch logic unit (L1, L2, LN) is coupled via their hold nodes (H1 - HN) and their sample nodes (S1 - SN) to the respective sample node (S0) and the hold node (H0) of the clock unit (CP).

Description

Electronic circuitry and method of controlling an electronic circuitry

FIELD OF THE INVENTION

The present invention relates to an electronic circuitry and to a method of controlling an electronic circuitry.

BACKGROUND OF THE INVENTION

In electronic circuitry, current-mode logic CML as well as CMOS logic are known. The power consumption of current-mode logic CML is often considered as higher as that of CMOS logic due to the fact that current-mode logic requires a constant current while in the ON state while on the other hand CMOS logic only requires power when the logic has to change its state. Accordingly, if the switching activity is low, the power efficiency of CMOS logic will be better than the power efficiency of current mode logic. However, this does not necessarily also apply for the clock circuitry or clock network required for the logic function. Due to its inherent characteristics, clock circuitries will always switch their state. This applies for current mode logic as well as CMOS logic. Accordingly, the power efficiency of current mode logic is not inferior to the power efficiency of CMOS logic for the cases of clock circuitry or a clock network.

US 2002/0003443 Al discloses a toggle flip-flop circuit with a master latch circuit with an emitter-coupled logic circuit, i.e. a current-mode logic circuit. Here, the clock of the master and slave latches are controlled simultaneously. However, the global clock signal is provided in the voltage domain.

Fig. 2 shows a circuit diagram of a current-mode logic latch according to the prior art. The latch comprises a current source I₀, two transistors Tl, T2 which receive the clock signals CLK, CLK', respectively, and transistors T3, T4 which receive the input A, A', respectively. The latch also comprises output terminals Z, Z'. In the case of Fig. 2, the input constitutes a differential input, wherein the differential bit is applied to the input terminals A, A'. The input signal is sampled and hold at the output terminals Z, Z'. The clock signals CLK, CLK' serve to define which leg is active and which is passive. The current source Io is used to bias the latch. The two transistors, T5, T6 are used to hold the sampled differential input bits. As each latch requires the clock signals CLK, CLK', the clock signals must be provided throughout the system, i.e. the clock signals need to be present for all latches within an electronic circuitry.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an electronic circuitry with an improved power-efficiency.

This object is solved by an electronic circuitry according to claim 1. Therefore, an electronic circuitry at least based on current-mode logic is provided. The electronic circuitry comprises a clock unit and a logic unit. The logic unit comprises a plurality of latch logic units each with a hold node and sample node. The clock unit comprises a clock circuitry for providing clock signals for the latch logic units. The clock unit furthermore comprises a sample node and a hold node each for providing clock controlled current to the latch logic units. The hold nodes and the sample nodes of the latch logic units are coupled to the sample node and the hold node of the clock unit, respectively. According to an aspect of the invention, each latch logic unit comprises an input for receiving an input signal and an output for holding the input signal. The clock unit comprises a current source for providing a current according to the number of latch logic units in the logic unit. Accordingly, the current source must be able to provide sufficient current to drive all the latch logic units which are supplied with clock signals from the clock unit. The sample node and hold node of the clock circuitry can be coupled to the sample and hold nodes of each latch logic unit.

The invention also relates to a method of controlling an electronic circuitry based on current-mode logic. The electronic circuitry comprises a logic unit having a plurality of latch logic units each with a hold node and a sample node and a clock unit having a sample node and a hold node as well as a clock circuitry. Each latch logic unit is coupled via their hold nodes and their sample nodes to the respective sample node and the hold node of the clock unit. Clock signals are provided by the clock circuitry to the logic unit by providing clock controlled current to the latch logic units.

The present invention relates to the realization that for a latch based on current-mode logic CML, the current will be steered to the sample V_s and hold Vh nodes. The hold Vh (Vhoid) node is present between the transistors T5 and T6. The sample V_s (V_sampie) node is provided between the transistor T3 and T4.

The present invention also relates to the idea to split a latch based on a current- mode logic into its logic part (upwards from the V_s and Vh nodes) and into a clock part which comprises the clock controlled current steering circuitry below the V_s and Vh nodes. The logic part of the latch will remain as it is but the clocked current steering circuitry will be placed centrally for several latches in an electronic circuitry. Accordingly, a plurality of logic latch cells will share common sample V_s and hold Vh nodes or rails. Therefore, the clocked current will flow through these two lines or nodes and will increase as the number of latches increases. While the conventional voltage-based clock distribution has been used in the prior art, for example as depicted in Fig. 2, the distribution of the clock signals according to the invention is based on a current switching which is distributed over the electronic circuitry instead of a distribution of the clock signals itself. Accordingly, the current via the clock lines or via the sample and hold nodes is used for a clock distribution as well as to keep the latches in their desired state. As the power of a latch can also be used for a clock distribution, the power efficiency of the clock network can be improved. One advantage of the electronic circuitry according to the invention is that a lower voltage swing is required for the clock distribution lines. Hence, a current mode logic clock network can be more power efficient than a CMOS based clock network. It should be noted that the parasitic clock wire capacitance will only increase at a slower rate. This is advantageous as the charging time for the parasitic capacitance will be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and embodiments of the invention will now be described in more detail with reference to the Figures.

Fig. 1 shows a circuit diagram of an electronic circuitry according to the invention, and

Fig. 2 shows a circuit diagram of an electronic circuitry of a current-mode logic latch according to the prior art.

DETAILED DESCRIPTION OF EMBODIMENTS

Fig. 1 shows a circuit diagram of an electronic circuitry according to the invention. The electronic circuitry according to the invention relates to a plurality of current- mode logic latches. As each latch can be divided into a logic unit and a clock unit, the electronic circuitry comprises two units, namely a clock unit CP and a logic unit LP. The clock unit CP is used for a plurality of logic units of the latches. The clock unit CP comprises a current source Io for biasing the latch logic units of the logic unit LP and a first and second transistor Tl, T2. The first transistor Tl receives the clock signal CLK and the second transistor T2 receives the clock signal CLK' at their gates, respectively. The current source Io should be able to produce the required current to supply or drive all the latches in the electronic circuitry. IfN latches, i.e. N latch logic units are present, the current source should be able to supply NxIo current. The logic unit LP may comprise the latch logic units of N latches. A first latch logic unit Ll may comprise the input terminals A₁, A'] and the output terminals Z₁, Z'] for holding the input signal or bits as well as the transistors T31, T41, T51, T61. The function of the transistors T31, T41, T51, T61 substantially correspond to the function of the transistors T3, T4, T5, T6 according to Fig. 2. A first hold node Hl is coupled between the transistors T51, T61. A first sample node Sl is coupled between the transistors T31, T41.

A second latch L2 may comprise the input terminals A₂, A'₂, the output terminals Z₂, Z'₂ and the transistors T32, T42, T52 and T62. The second latch L2 comprises a second hold node H2 coupled between the transistors T52, T62. A N-th latch LN may comprise the input terminals A_N, A'_N, the output terminals Z_N, Z'_N as well as the transistors T3N, T4N, T5N, T6N. The N-th latch LN comprises a nth hold node HN and a N-th sample node SN.

The clock unit CP comprises a first and second output terminal sample node, hold node SO, HO at which the sample voltage V_s and the hold voltage Vh is applied, respectively. The sample nodes Sl - SN are coupled to the first output terminal SO of the clock unit. The hold nodes Hl - HN are coupled to the second output terminal HO of the clock unit CP.

Accordingly, the sample and hold nodes V_s and Vh are shared between all latch parts of the electronic circuitry. Furthermore, instead of a dedicated clock unit for each latch the clock units CP are shared between a plurality of latches.

With the electronic circuitry according to the invention, the clocked current flows through the sample and hold nodes SO, HO and will increase with the number of latches present in the circuitry. On the other hand, the parasitic clock wire capacitance will increase at a slower pace such that the charging time for this parasitic capacitance will be reduced. Moreover, the voltage swing on the clock lines will be determined by the amount of overdrive voltage required to switch a logic state from active to passive or from passive to active. The overdrive voltage will correspond to V_GS-V_T for a MOS technology. Furthermore, it should be noted that the overdrive voltage is also influenced by the transconductance of the switches and by the amount of current being switched. Moreover, the overdrive voltage is also determined by the amount of leakage or bias current which is present in the passive state. Accordingly, a relative small amount of constant bias current can be added to the clock lines such that the switches do not switch off completely when switched into the passive state. With the principles of the invention, the current of the current-mode logic latch may be used to route clock signals across an electronic circuitry. The required voltage swing on these clock lines can be minimal such that less power is required for charging and discharging the clock network.

With the electronic circuitry according to the invention, a current mode logic based clock distribution is provided. Instead of a voltage based clock distribution as used in the state of the art, the clock distribution according to the present invention is based on a current switching by the clock signals CLK, CLK' . The switched current is distributed over the circuitry instead of the clock signals themselves. Therefore, the current flowing through the clock lines can be used for the clock distribution as well as to keep the latches in their desired state. Advantageously, the electronic circuitry according to the invention requires a lower voltage swing over the clock distribution lines such that a current mode logic clock network can be more power efficient than a CMOS based clock network.

However, on the other hand, the resistance in the paths towards the latches can be distributed symmetrically in order to ensure a symmetrical current distribution. Although in the above, the electronic circuitry has been described using current mode logic CML, the electronic circuitry may also use source-coupled logic SCL or emitter-coupled logic ECL if a clock signal switches a bias current to more than one latch unit.

Although in the above an electronic circuitry with latches have been described the principles of the invention can also be applied to electronic circuitry with other logic elements which require clock signal, i.e. instead of latch logic units other (logic) units can be used.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Furthermore, any reference signs in the claims shall not be constrained as limiting the scope of the claims.

Claims

CLAIMS:

1. Electronic circuitry based on current-mode logic, comprising: a logic unit (LP) having a plurality of latch logic units (Ll, L2, LN) each with a hold node (Hl - HN) and a sample node (Sl - SN); and a clock unit (CP) having a sample node (SO) and a hold node (HO) as well as a clock circuitry (Tl, T2, I_N) for providing clock signals to the logic unit (LP) by providing clock controlled current to the latch logic units (Ll - LN) wherein each latch logic unit (Ll, L2, LN) is coupled via their hold nodes (Hl

- HN) and their sample nodes (Sl - SN) to the respective sample node (SO) and the hold node (HO) of the clock unit (CP).

2. Electronic circuitry according to claim 1, wherein each latch logic unit (Ll - LN) comprises an input (Ai, A₂, A_N; A'_I, A'₂, A'_N) for receiving an input signal and an output (Zi, Z₂, Z_N; Z'_I, Z'₂, Z'_N) for holding the input signal, - wherein the clock unit (CP) comprises a current source (Io) for providing a current (Io) according to the number (N) of latch logic units (Ll - LN) in the logic unit (LP) to bias the latch logic units (Ll - LN).

3. Electronic device comprising an electronic circuitry according to claim 1 or 2.

4. Method of controlling an electronic circuitry based on current-mode logic comprising a logic unit (LP) having a plurality of latch logic units (Ll, L2, LN) each with a hold node (Hl - HN) and a sample node (Sl - SN); and a clock unit (CP) having a sample node (SO) and a hold node (HO) as well as a clock circuitry (Tl, T2, Io), wherein each latch logic unit (Ll, L2, LN) is coupled via their hold nodes (Hl - HN) and their sample nodes (Sl

- SN) to the respective sample node (SO) and the hold node (HO) of the clock unit (CP), comprising the step of: providing clock signals by the clock circuitry (Tl, T2; I₀) to the logic unit (LP) by providing clock controlled current to the latch logic units (Ll - LN).