WO2009101897A1 - Clock data reproduction circuit - Google Patents

Clock data reproduction circuit Download PDF

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Publication number
WO2009101897A1
WO2009101897A1 PCT/JP2009/052002 JP2009052002W WO2009101897A1 WO 2009101897 A1 WO2009101897 A1 WO 2009101897A1 JP 2009052002 W JP2009052002 W JP 2009052002W WO 2009101897 A1 WO2009101897 A1 WO 2009101897A1
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WO
WIPO (PCT)
Prior art keywords
phase
clock
input signal
frequency
multiplication
Prior art date
Application number
PCT/JP2009/052002
Other languages
French (fr)
Japanese (ja)
Inventor
Hidemi Noguchi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009553404A priority Critical patent/JP5423967B2/en
Publication of WO2009101897A1 publication Critical patent/WO2009101897A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to a clock 'data reproduction circuit used in general serial data communication systems.
  • clock and data recovery circuits that extract clock signal components from received data signals and identify and recover data are widely used.
  • a clock data recovery circuit using a phase interpolator is often applied because it has good compatibility with the CMOS process and can be realized with low power consumption and a small area.
  • FIG. 1 shows the clock data recovery circuit.
  • the clock / data recovery circuit 15 first multiplies the low-frequency reference clock 6 held on the receiving side by an integer ⁇ multiplication circuit 3-1 (N times) to obtain the desired input as the reference for the recovered clock. Generates double clock 7 with a frequency near the signal bit rate.
  • the double clock 7 is guided to the phase comparator 1 through the clock phase variable unit 2.
  • the clock phase shifter 2 uses a circuit that generates a clock signal from two clock signals (I CLKZQCLK) whose phases are shifted from each other by 90 degrees as shown in FIG. 3, for example.
  • Figure 3A shows the circuit diagram of the clock phase shifter
  • Figure 3B shows its waveform.
  • the clock phase shifter 2 is a circuit that generates a clock (CLK) signal having an arbitrary intermediate phase between the I CLKZQCLK signals by adding two I CLK / QCLK signals at an arbitrary ratio. Therefore, the clock phase shifter 2 is also called a phase trap. This phase switching can be digitally controlled from the outside, and phase switching with a certain resolution (phase step) is possible.
  • the position is such that I C LK (t 1) and QC LK (t 2) are trapped according to the source weight m: n. That is, if the current source weight m: n is variable, the phase of t 3 can be controlled.
  • the phase comparator 1 compares the phase of the recovered clock 8 output from the clock phase shifter 2 and the input signal 5 and indicates whether the recovered clock 8 is delayed or advanced with respect to the input signal 5. UP / DOWN signal) 1 0 is generated. Then, the phase comparison output 10 of the phase comparator 1 is signal-processed by the digital inductor 4 and the phase of the clock phase variable device 2 is controlled in accordance with the phase control signal 11. The input signal can be regenerated by applying feedback so that the phase of the recovered clock 8 is in the optimal position according to the phase fluctuation of the input signal 5.
  • Figure 2 shows the timing chart of the circuit shown in Figure 1.
  • N is an integer
  • the input signal, the multiple clock and the regenerated clock are all synchronized, and all are in the optimal phase position.
  • the identification phase position that identifies the phase of the input signal, the multiple clock, and the recovered clock is based on when the eye opening in the phase direction of the input signal is the middle point. As shown by the dotted line in Fig. 2, at the midpoint of the input signal, the multiplication clock and the rising edge phase of the recovered clock are identified. Therefore, the optimum phase position is the state where the phase of the rising edge of the double clock and the recovered clock is synchronized at the midpoint of the input signal.
  • the phase of the input signal and the multiple clock gradually shifts with each data period.
  • the phase difference Tm # between the input signal and the multiple clock and the phase difference T r # between the input signal and the recovered clock are increased by adding the period difference ⁇ between the two signals for each data period.
  • the clock phase shifter 2 is controlled as shown in FIG. By performing phase switching, the frequency difference between the input signal and the multiplying clock is absorbed.
  • Patent Document 1 discloses a digital PLL that synchronizes phases when there is a frequency difference between signals.
  • Patent Document 1 shows the digital P L L when the phase between the reference clock frequency input to the phase comparator and the internally generated clock frequency is synchronized.
  • the digital filter operation section in this digital P L L is equipped with a phase difference integrator that integrates two phase differences. First, match the phases of the two signals, and add up the phase difference from here. By switching the phase based on this accumulated phase difference and setting it as a temporary phase convergence, the phase is captured at high speed.
  • the correction value of the convergence point is updated by the phase convergence point changing unit, and the final phase convergence with the target phase difference set in advance is set. Gradually approach the point. By setting the temporary phase convergence point and repeating the operation to confirm the phase synchronization, gradually approach the final phase convergence point.
  • the digital PLL that can capture the phase at high speed by digital processing is shown. Disclosure of the invention
  • phase switching described above is a digital phase switching control with a finite resolution
  • jitter accompanying the switching operation occurs.
  • the linearity and resolution of phase switching of the clock phase shifter is also the jitter of the recovered clock. There is also a problem that it is difficult to design a clock and data recovery circuit because it greatly affects the increase.
  • An object of the present invention is to provide a clock / data recovery circuit and a clock / data recovery method capable of suppressing the occurrence of jitter, which is the problem described above.
  • a non-integer multiplier circuit that doubles a reference clock and outputs a double clock, and a recovered clock that has the multiple clock as an input and the phase of the double clock is variable.
  • An output queuing phase variable device a phase comparator for detecting a phase difference between the reproduction queuing clock and an input signal, a digital filter for processing a phase comparison output from the phase comparator,
  • the non-integer multiplication circuit adjusts the multiplication ratio of the non-integer multiplication circuit so that the data rate of the input signal and the frequency of the multiplication clock coincide with each other.
  • a clock / data recovery circuit is obtained in which the phase of the reproduction clock is varied so as to synchronize and the optimum identification phase is obtained.
  • the non-integer multiplication circuit outputs a double clock based on frequency deviation information obtained by comparing the input signal and the phase of the internally generated clock. Based on the phase difference information obtained by comparing the phase of the phase of the input signal and the recovered clock to the phase of the recovered clock so that the input signal and the phase of the recovered clock match.
  • a clock data recovery method is obtained in which the phase of the recovered clock is varied so as to synchronize with the input signal so that the optimum identification phase is obtained.
  • a non-integer multiplication circuit is used as a reference clock multiplication circuit instead of an integer multiplication circuit.
  • the frequency deviation between the input signal and the multiplication clock is reduced, and the frequency of periodic phase switching of the reproduction clock to absorb the frequency deviation can be reduced. it can. Therefore, the effect of suppressing the jitter of the recovered clock can be obtained.
  • the frequency of periodic phase switching of the recovered clock can be reduced, there is a need for the resolution and linearity of the clock phase variable circuit that constitutes the clock data recovery circuit. 2
  • FIG. 1 is a block diagram of the clock and data recovery circuit as a related technology.
  • FIG. 2 is a timing chart of the clock data recovery circuit in FIG.
  • Figure 3A is a circuit diagram of the clock phase shifter (phase interpolator).
  • Fig. 3B is a waveform diagram of the clock phase shifter (phase interpolator).
  • FIG. 4 is a block diagram showing the configuration of the clock data recovery circuit according to the first embodiment of the present invention.
  • FIG. 5 is a timing chart of the clock data recovery circuit of the present invention.
  • FIG. 6 is a block diagram showing the configuration of the clock and data recovery circuit according to the second embodiment of the present invention.
  • FIG. 7 is a block diagram of the configuration of the clock data recovery circuit according to the third embodiment of the present invention.
  • FIG. 4 shows a configuration block diagram of the clock data recovery circuit 15-1 according to the first embodiment of the present invention.
  • Figure 5 shows the timing chart.
  • the clock data recovery circuit 15-1 receives the input signal 5 and the reference clock 6, and outputs synchronized playback data 9 and playback clock 8. Based on the multiplication ratio control signal 12, the non-integer multiplication circuit 3 generates a multiplication clock 7 of a frequency near the desired data rate with a multiplication ratio (M times) of the non-integer multiple from the reference clock 6. Generate. At this time, use a non-integer multiplier circuit that can control the multiplier ratio from the outside.
  • the multiple clock 7 from the non-integer multiple circuit 3 is made variable by a clock phase variable device 2 at the next stage with a finite resolution based on the phase control signal 11 1.
  • the clock whose phase has been changed is led to the phase comparator 1 as a recovered clock 8 for identifying the input signal.
  • the phase interpolator shown in FIG. 3 can be used as the clock phase variable unit 2.
  • the phase interpolator uses two clock signals (I CLKZQCLK) that are 90 degrees out of phase with each other. By adding the two IC LK / QCLK signals in any ratio, it is possible to generate a clock signal with any intermediate phase between I CLKZQCLK.
  • phase comparator 1 identifies the input signal 5 by using the reproduction clock 8 output from the clock phase variable unit 2 and outputs the reproduction data 9.
  • a phase comparison output also called UP / D OWN signal
  • the digital filter 4 receives the UP / DOWN signal 10 from the phase comparator 1 and performs appropriate signal processing so that the phase of the reproduction clock becomes the optimum phase position for identifying the input signal.
  • the digital filter 4 processes the UP ZD OWN signal 10 and sends a phase control signal 11 to the clock phase shifter 2 and a multiplication ratio control signal 12 to the non-integer multiplication circuit 3.
  • the clock phase shifter 2 adjusts the phase of the double clock 7 based on the phase control signal 11.
  • the non-integer multiplication circuit 3 adjusts the multiplication ratio of the multiplication clock 7 based on the multiplication ratio control signal 12.
  • the phase comparator 1 outputs a large number of UP signals to advance the phase. Conversely, if the frequency is high, many DOWN signals are output to delay the phase. Therefore, the average value of the UPZD OWN signal at the output of the phase comparator is proportional to the frequency deviation between the data rate of the input signal and the multiplying clock. Therefore, by using this frequency deviation information to control the multiplication ratio of the non-integer multiplication circuit and applying feedback so that the frequency deviation becomes smaller, the optimum non-integer multiplication ratio ( ⁇ 'multiple) is selected according to the input signal. ) Automatic control to be Thus, the frequency deviation can be kept small.
  • the Kuguchik phase shifter does not need to perform periodic phase switching to absorb the frequency deviation. Only a fixed delay between the signal and the reproduction clock is adjusted. Therefore, once the phase adjustment is completed, it is not necessary to switch the phase thereafter, so the jitter associated with digital phase control can be eliminated.
  • the frequency deviation cannot be completely reduced to zero using a non-integer multiplication circuit. However, by making the frequency deviation sufficiently small, it is possible to bring the period of the periodic clock phase switching control to absorb the frequency deviation sufficiently to the low frequency side. If the period of the Kuchikku phase switching control is set to the low frequency side and taken outside the jitter standard band, it can be virtually ignored.
  • FIG. 5 shows a timing chart when the frequency of the double clock 7 is lower than the data rate of the input signal 5.
  • the identification phase position for identifying the phase of the input signal, the multiple clock, and the recovered clock is based on the middle point of the eye opening in the phase direction of the input signal. Therefore, the optimum phase position is when the rising edge of the double clock and the recovered clock reaches the middle point of the eye opening in the phase direction of the input signal.
  • the multiplication ratio M of the non-integer multiplication circuit 3 is not optimal. For this reason, there is a difference between the data rate of the input signal and the frequency of the multiplication clock multiplied by the non-integer multiplication circuit from the reference clock.
  • the period difference between the input signal and the double clock is ⁇ ⁇
  • T r # (# 1, 2, 3 ⁇ )
  • the time when the phase of the input signal, the multiple clock and the recovered clock are matched based on the information from the phase comparison output from the phase comparator is shown in FIG. 5 as the first period of the input signal.
  • the phase difference is the data ⁇ is accumulated and increased every period.
  • the average value of the delay between this input signal and the multiple clock is ⁇ . If this one-cycle difference ⁇ ⁇ is corrected, the frequency deviation is eliminated.
  • the frequency deviation information is the difference ⁇ between this input signal and the multiplication clock.
  • the digital filter 4 calculates the frequency deviation information and the optimum multiplication ratio based on the phase comparison output (UPZDOWN signal) 10 from the phase comparator, and uses the non-integer multiplication circuit as the multiplication ratio control signal 12. Send to 3.
  • the non-integer multiplier circuit 3 switches the output to a multiple clock with the optimum multiplication ratio ( ⁇ 'times) by the multiplication ratio control signal.
  • the phase comparator 1 detects the phase difference between the input signal 5 and the recovered clock 8 and outputs the UPZDOWN signal 10 corresponding to the phase delay / advance.
  • the frequency of the playback clock is lower than the data rate of the input signal, so phase comparator 1 outputs an UP signal to advance the phase.
  • the clock phase shifter 2 is controlled via the digital filter 4 to perform phase switching to advance the phase, and feedback is applied to absorb the phase shift due to the frequency deviation.
  • the frequency of the UP signal output from the phase comparator 1 is proportional to the frequency deviation between the input signal 5 and the multiple clock 7.
  • frequency deviation information can be obtained by calculating the average value of the output of the phase comparator.
  • the non-integer multiplier circuit switches to a multiple clock with the optimum multiplication ratio ( ⁇ 'times) based on the frequency deviation information.
  • the non-integer multiplier circuit 3 switches and outputs the optimum multiplier ratio ( ⁇ 'times) through the clock with the multiplication ratio control signal 12.
  • the data rate of the input signal 5 and the frequency deviation of the double clock 7 are reduced.
  • the optimum multiplication ratio ( ⁇ 'times) has been set, the frequencies are almost the same, so only the phases are matched. However, even though the multiplication ratio is a non-integer multiple, the frequency deviation is actually zero. There is a period difference ⁇ ⁇ 'between the input signal and the double clock.
  • T skw be the phase difference of the 5th round of the input signal switched to the optimal multiple ratio ( ⁇ ⁇ ⁇ ⁇ 'multiple) multiple clock.
  • Tm6 Tskw + ⁇ T
  • Tm7 Tskw + 2AT ′.
  • T r 6 T sk w + ⁇ T
  • Tm 7 T sk w + 2 ⁇ T ′.
  • This phase difference T skw is phase difference information and is sent from the digital filter 4 to the clock phase variable unit 2 as the phase control signal 11.
  • the Kuguchik phase shifter 2 adjusts the phase according to the phase control signal 1 1.
  • phase comparator is the input signal! ?
  • the phase difference from the raw clock is detected, and the UPZD OWN signal is output in response to the phase delay / advance.
  • the phase of the recovered clock is controlled at the 8th round of the input signal, and the input signal and recovered clock are synchronized.
  • Tm 9 T s kw + 4 ⁇ ⁇ '
  • Tm 10 ⁇ s k w + 5 ⁇ ⁇ '.
  • the phase switching control cycle for absorbing the frequency deviation can be lengthened.
  • the frequency of phase switching control can be reduced. Therefore, it is possible to reduce the frequency of jitter generation associated with this phase switching control and bring it to a sufficiently low frequency side.
  • the frequency deviation ⁇ ' is large, the frequency deviation ⁇ ' can be made sufficiently small by repeating the adjustment of the multiplication ratio and the adjustment of the phase difference again.
  • the multiplication ratio can be freely selected by making the multiplication circuit a non-integer multiplication circuit, so that the frequency deviation AT'O can be sufficiently reduced.
  • a jitter band is defined, and the low frequency jitter is not an operational problem and can be ignored. Therefore, by applying the present invention, it is possible to realize a clock data recovery circuit in which the jitter of the recovered clock is greatly reduced.
  • the linearity and resolution performance of the clock phase shifter can be greatly relaxed, which not only facilitates circuit design, but also increases the circuit scale. Can be reduced. As a result, the effect of improving resistance against the effects of process variations can be obtained.
  • the digital filter 4 is based on the UP ZD OWN signal 1 0 from the phase comparator 1 and the phase control signal 1 1 that is phase information and the multiplication ratio control signal 1 that is frequency deviation information. 2 is generated. Based on the multiplication ratio control signal 1 2, the multiplication ratio of the non-integer multiplier 3 is controlled, and on the basis of the phase control signal 11 1, the phase of the queuing phase shifter is controlled. By controlling the multiplication ratio and phase, it becomes possible to realize a clock and data recovery circuit that greatly reduces the jitter of the recovered clock. (Second embodiment)
  • FIG. 6 shows a block diagram of the configuration of the clock data recovery circuit 15-2 according to the second embodiment.
  • the difference between the first embodiment and this embodiment is that a phase frequency comparator 1 3 is used instead of the phase comparator 1.
  • This embodiment is an embodiment that is particularly effective when the frequency deviation between the data rate of the input signal and the multiplying clock is large.
  • Clock data recovery circuit 1 5—2 receives input signal 5 and reference clock 6, and outputs synchronized playback data 9 and playback clock 8.
  • the phase frequency comparator 13 operates as a frequency comparator when there is a phase difference of 1 cycle or more between input signals.
  • the phase frequency comparator 13 is a comparator that operates as a frequency comparator or a phase comparator depending on the magnitude of the frequency deviation (phase difference) between the input signal 5 and the recovered clock 8.
  • Phase comparison output from the phase frequency comparator 1 3 (UP signal D OWN signal) 1 0 is fed back to the non-integer multiplication circuit 3 and the clock phase shifter 2 via the digital filter 4, and the phase due to the frequency deviation is Absorb the deviation.
  • the configuration and operation of the other clock phase variable device 2, the non-integer multiplication circuit 3 and the digital filter 4 in this embodiment are the same as those in the first embodiment, and the description thereof is omitted.
  • the input signal 5 and the recovered clock 8 When the frequency deviation is large, the phase frequency comparator 13 operates more effectively than the phase comparator 1.
  • the phase comparison output 10 from the phase frequency comparator 13 includes frequency deviation information.
  • the phase comparison output 10 controls the non-integer multiplication circuit 3 based on the multiplication ratio control signal 12 through the digital filter 4 to determine the multiplication ratio.
  • the non-integer multiplier circuit 3 switches the multiplication ratio, the frequency deviation between the frequency input signal 5 and the recovered clock 8 becomes smaller and becomes almost zero. The frequency deviation decreases, and the phase control signal 1 1 controls the clock phase shifter 2 to adjust the phase.
  • the timing chart of this embodiment is the same as FIG. First, the input signal 5 is synchronized with the double clock 7 and the recovery clock 8. Next, in FIG. 5, the multiplication ratio of the multiplying clock 7 of the non-integer multiplication circuit 3 is changed in the fifth cycle of the input signal.
  • the digital filter 4 to which the phase comparison output from the phase frequency comparator 13 is input sends the multiplication ratio control signal 12 to the non-integer multiplication circuit 3.
  • the non-integer multiplication circuit 3 switches the set multiplication ratio (M times) to the multiplication ratio ( ⁇ 'times), and outputs a normal clock 7 of the set multiplication ratio ( ⁇ ' times). By switching the multiplication ratio of the non-integer multiplier circuit 3, the frequency deviation between the input signal 5 and the multiplier clock 7 is reduced.
  • the phase frequency comparator 13 operates as a phase comparator. Based on the U PZD OWN signal 1 0 from the phase frequency comparator 1 3, the digital filter 4 controls the phase switching of the clock phase shifter 2 using the phase control signal 1 1. In Fig. 5, the clock phase is changed in the 8th period of the input signal.
  • the digital filter 4 generates the phase control signal 11 and the multiplication ratio control signal 12 based on the phase comparison output from the phase frequency comparator.
  • the multiplication ratio of the non-integer multiplier 3 is controlled based on the multiplication ratio control signal 1 2 and the phase of the clock phase variable device is controlled based on the phase control signal 11.
  • a phase frequency comparator even if the frequency deviation is large, it is possible to obtain a stable frequency deviation information that does not cause cycle slip, thereby enabling a stable pull-in operation.
  • FIG. 7 shows a configuration block diagram of a clock data recovery circuit 15-3 according to the third embodiment.
  • the difference between the first embodiment and this embodiment is that a separate frequency comparator for comparing the frequency of the input signal and the multiplying clock is provided, and the multiplication ratio of the non-integer communication circuit using the frequency comparator is provided. It is a point that controls.
  • this embodiment is particularly effective when the frequency deviation between the data rate of the input signal and the multiplication clock is large.
  • the clock 'data recovery circuit 1 5-3 shown in FIG. 8 includes a phase comparator 1, a clock phase variable device 2, a non-integer multiplication circuit 3, a digital filter 4, and a frequency comparator 14.
  • the clock / data recovery circuit 1 5-3 receives the input signal 5 and the reference clock 6, and outputs synchronized playback data 9 and playback clock 8.
  • a frequency comparator 14 for comparing the frequency of the input signal and the multiplication clock is added to control the multiplication ratio of the non-integer multiplication circuit.
  • the frequency comparator 14 is a frequency comparator that receives an input signal 5 and a multiplication clock 7 generated by a non-integer multiplication circuit and detects a frequency difference between the two. According to the comparison result, the frequency comparator 14 controls the multiplication ratio of the non-integer multiplication circuit.
  • the multiplication ratio control signal 1 2 for controlling the multiplication ratio of the non-integer multiplication circuit is issued from the digital filter 4 in the first embodiment, but is issued from the frequency comparator 14 in this embodiment. It will be.
  • Other phase comparator 1 of this embodiment and variable clock phase The configuration and operation of the device 2, the non-integer multiplier 3 and the digital filter 4 are almost the same as those in the first embodiment, and the description thereof is omitted.
  • the frequency comparator 14 receives the input signal 5 and the multiplication clock 7 and outputs a multiplication ratio control signal 12 which is the comparison output to the non-integer multiplication circuit 3.
  • the non-integer multiplication circuit 3 switches the multiplication ratio based on the multiplication ratio control signal 12 and outputs the multiplication clock 7 having the designated multiplication ratio.
  • the phase comparator 1 receives the input signal 5 and the reproduction clock 8 and outputs the phase comparison output 10 to the digital filter 4.
  • the digital filter 4 outputs the phase control signal 11 to the clock phase variable unit 2.
  • the clock phase shifter 2 switches the phase based on the phase control signal 1 1 and outputs a recovered clock.
  • a frequency comparator and a phase comparator are provided, and the frequency and phase can be individually adjusted based on the comparison results.
  • a frequency comparator stable pull-in operation is possible by obtaining stable frequency deviation information that does not cause cycle slip even when the frequency deviation is large.
  • the non-integer multiplier circuit that doubles the reference clock and outputs the double clock, and the clock phase that outputs the recovered clock with the multiple clock input as the input and the phase of the double clock as variable are input.
  • the digital filter of the clock data recovery circuit of the present invention adjusts the multiplication ratio of the non-integer multiplication circuit based on the frequency deviation information obtained by signal processing the phase comparison output input from the phase comparator. be able to.
  • the frequency deviation information can be obtained from the average value of the UP / D OWN signal, which is the phase comparison output from the phase comparator. wear.
  • the phase comparator is either a phase comparator that detects a phase difference between the recovered clock and the input signal, or a phase frequency comparator that detects a phase difference and a frequency difference between the recovered clock and the input signal. Can do.
  • a frequency comparator that detects the frequency difference between the clock and the input signal is provided separately, and the output from the frequency comparator is used to adjust the multiplication ratio of the non-integer multiplier circuit. You can also.
  • the first phase adjustment in which the non-integer multiplication circuit outputs the multiple clock Based on the step and the phase difference information obtained by comparing the phase of the input signal and the recovered clock, the second phase that varies the phase of the recovered clock to match the phase of the input signal and the recovered clock
  • An adjustment step and a clock / data recovery method in which the phase of the reproduction clock is varied to synchronize with the input signal so as to obtain an optimum identification phase.
  • the phase comparator outputs a phase comparison output that detects the phase difference between the input signal and the playback clock, and is calculated from the phase comparison output.
  • the multiplication ratio of the non-integer multiplication circuit can be adjusted based on the frequency deviation information.
  • the phase frequency comparator outputs a phase comparison output in which the phase difference and the frequency difference between the input signal and the recovered clock are detected, and the non-integer multiplication circuit passes through the frequency deviation information calculated from the frequency difference of the phase comparison output. You can also adjust the multiplication ratio.
  • the frequency comparator may output frequency deviation information obtained by comparing the input signal and the multiplication clock, and the multiplication ratio of the non-integer multiplication circuit may be adjusted based on the frequency deviation information.

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The clock multiplication circuit of a clock data reproduction circuit is defined as a non-integral multiplication circuit in which the multiplication ratio of a non-integer is possible. A frequency shift can be decreased to reduce the frequency of a phase switching operation by setting the multiplication ratio according to the multiplication ratio control signal in which an input signal is compared with a clock. The clock data reproduction circuit capable of significantly reducing the jitter of a reproduction clock can be provided.

Description

クロック ·データ再生回路 技術分野  Clock and data recovery circuit Technical Field
本発明は、 シリアルデータ通信システム全般に使用されるクロック 'データ再 生回路に関する。  The present invention relates to a clock 'data reproduction circuit used in general serial data communication systems.
明  Light
背景技術 Background art
田  Rice field
高速ディジタル通信システムにおいては、 受信したデータ信号からクロック信 号成分を抽出し、 データを識別 ·再生するクロック ·データ再生回路が広く用い られている。 このクロック 'データ再生回路として、 CMOSプロセスと親和性 が良く、 低消費電力かつ小面積で実現が可能なことから、 位相補間器を用いたク ロック ·データ再生回路がしばしば適用される。  In high-speed digital communication systems, clock and data recovery circuits that extract clock signal components from received data signals and identify and recover data are widely used. As this clock data recovery circuit, a clock data recovery circuit using a phase interpolator is often applied because it has good compatibility with the CMOS process and can be realized with low power consumption and a small area.
図 1に、 クロック .データ再生回路を示す。 クロック ·データ再生回路 15で は、 まず、 受信側で持ち合わせている低周波のリファレンスクロック 6を整数遁 倍回路 3— 1で整数遞倍 （N倍） し、 再生クロックの基準となる所望の入力信号 ビットレート近傍の周波数を持つ遁倍クロック 7を生成する。  Figure 1 shows the clock data recovery circuit. The clock / data recovery circuit 15 first multiplies the low-frequency reference clock 6 held on the receiving side by an integer 倍 multiplication circuit 3-1 (N times) to obtain the desired input as the reference for the recovered clock. Generates double clock 7 with a frequency near the signal bit rate.
この遁倍クロック 7は、 クロック位相可変器 2を介して位相比較器 1へと導か れる。 一般的に、 クロック位相可変器 2は、 例えば図 3に示すような位相が互い に 90度ずれた 2つのクロック信号 （I CLKZQCLK) からクロック信号を 生成する回路が用いられる。 図 3 Aにはクロック位相可変器の回路図、 図 3Bに はその波形図を示す。 クロック位相可変器 2は、 2つの I CLK/QCLK信号 を任意の比で足し合わせることにより、 I CLKZQCLK信号間の任意の中間 位相をもったクロック （CLK) 信号を生成する回路である。 そのためクロック 位相可変器 2は、 位相捕間器とも呼ばれる。 また、 この位相切換えは外部からデ イジタル的に制御でき、 ある分解能 （位相ステップ） を有した位相切換えが可能 である。  The double clock 7 is guided to the phase comparator 1 through the clock phase variable unit 2. In general, the clock phase shifter 2 uses a circuit that generates a clock signal from two clock signals (I CLKZQCLK) whose phases are shifted from each other by 90 degrees as shown in FIG. 3, for example. Figure 3A shows the circuit diagram of the clock phase shifter, and Figure 3B shows its waveform. The clock phase shifter 2 is a circuit that generates a clock (CLK) signal having an arbitrary intermediate phase between the I CLKZQCLK signals by adding two I CLK / QCLK signals at an arbitrary ratio. Therefore, the clock phase shifter 2 is also called a phase trap. This phase switching can be digitally controlled from the outside, and phase switching with a certain resolution (phase step) is possible.
図 3 Bにおいては、 生成されるクロック （CLK) のタイミング （t 3) は電 P2009/052002 In Figure 3B, the timing (t 3) of the generated clock (CLK) is P2009 / 052002
流源の重み m： nに応じて I C LK ( t 1) と QC LK ( t 2) を捕間するよう な位置となる。 すなわち電流源の重み m： nを可変とすれば t 3の位相をコント ロールできる。 図では電流源の重み m： n= 1 ： 1の場合であり、 t 3は t 1と t 2の中間位相となる。 The position is such that I C LK (t 1) and QC LK (t 2) are trapped according to the source weight m: n. That is, if the current source weight m: n is variable, the phase of t 3 can be controlled. In the figure, the current source weight m is n = 1: 1, and t 3 is an intermediate phase between t 1 and t 2.
位相比較器 1は、 クロック位相可変器 2から出力される再生クロック 8と入力 信号 5の位相を比較し、 再生クロック 8が入力信号 5に対して遅れているか進ん でいるかを示す位相比較出力 （UP/DOWN信号） 1 0を生成する。 そして、 位相比較器 1の位相比較出力 1 0をディジタノレフイノレタ 4にて信号処理し、 その 位相制御信号 1 1に応じてクロック位相可変器 2の位相を制御する。 入力信号 5 の位相変動に応じて再生クロック 8の位相が最適な位置となるようフィードバッ クを掛けることにより入力信号の再生を可能とするものである。  The phase comparator 1 compares the phase of the recovered clock 8 output from the clock phase shifter 2 and the input signal 5 and indicates whether the recovered clock 8 is delayed or advanced with respect to the input signal 5. UP / DOWN signal) 1 0 is generated. Then, the phase comparison output 10 of the phase comparator 1 is signal-processed by the digital inductor 4 and the phase of the clock phase variable device 2 is controlled in accordance with the phase control signal 11. The input signal can be regenerated by applying feedback so that the phase of the recovered clock 8 is in the optimal position according to the phase fluctuation of the input signal 5.
図 2に図 1に示す回路のタイミングチャートを示す。 入力信号 5のデータレー ト （周波数） を fdata、 リファレンスクロック 6の周波数を fref とすると、 整 数通倍回路 3— 1によって N (Nは整数） 通倍された遁倍クロック 7の周波数は N X fref となる。 入力信号と通倍クロックの位相差を Tm# (# = 1、 2、 Figure 2 shows the timing chart of the circuit shown in Figure 1. When the data rate (frequency) of the input signal 5 is fdata and the frequency of the reference clock 6 is fref, the frequency of the double clock 7 multiplied by N (N is an integer) by the multiplier circuit 3—1 is NX fref. Set the phase difference between the input signal and the multiple clock to Tm # (# = 1, 2,
3、 ——）、 入力信号と再生クロックの位相差を T r # ( # = 1、 2、3, ——), T r # (# = 1, 2,
3、 ■···) とする。 最初の時点 （#= 1 ) では、 入力信号、 通倍クロック及び再 生クロックは全て同期し、 全てが最適な位相位置にあるとする。 ここで入力信号、 通倍クロック、 再生クロックの位相を識別する識別位相位置は、 入力信号の位相 方向のアイ開口が中点となったときを基準とする。 図 2の点線で示すように入力 信号の中点において、 通倍ク口ック及び再生クロックの立ち上がりエッジ位相を 識別する。 従って最適な位相位置は、 入力信号の中点において、 遁倍クロック及 び再生クロックの立ち上がりェッジの位相が同期した状態である。 3,)). At the first time (# = 1), the input signal, the multiple clock and the regenerated clock are all synchronized, and all are in the optimal phase position. Here, the identification phase position that identifies the phase of the input signal, the multiple clock, and the recovered clock is based on when the eye opening in the phase direction of the input signal is the middle point. As shown by the dotted line in Fig. 2, at the midpoint of the input signal, the multiplication clock and the rising edge phase of the recovered clock are identified. Therefore, the optimum phase position is the state where the phase of the rising edge of the double clock and the recovered clock is synchronized at the midpoint of the input signal.
このとき、 入力信号 5の周波数と遁倍クロック 7の周波数は正確には一致して いない。 そのため、 図 2に示すように、 入力信号と通倍クロックの位相はデータ 周期ごとに徐々にずれていく。 すなわち、 入力信号と通倍クロックの位相差 Tm #及ぴ入力信号と再生クロックの位相差 T r #は、 両信号の周期差 Δ Τがデー タ周期ごとに積算され増大する。 この位相ずれを吸収するために、 図 2に示すよ うにクロック位相可変器 2を制御して周期的に適切なクロック位相となるよう位 相切換えを行うことで、 入力信号と遁倍クロックとの周波数差を吸収している。 入力信号と再生クロックとの位相差は、 T r l = 0、 T r 2 = Δ Τ , T r 3 = 2 厶1\ T r 4 = 3 A Tとなる。 ここ 5周期目で、 再び位相を一致させ T r 5 = 0 とする。 しかし、 入力信号と遁倍クロック間で周波数差があることから、 再び T r 6 = A T、 T r 7 = 2 Δ Τ, T r 8 = 3 Δ Τと位相がずれる。 そのため周期的 に適切なクロック位相となるよう位相切換えを行うことが必要になる。 At this time, the frequency of the input signal 5 and the frequency of the multiplying clock 7 do not exactly match. Therefore, as shown in Figure 2, the phase of the input signal and the multiple clock gradually shifts with each data period. In other words, the phase difference Tm # between the input signal and the multiple clock and the phase difference T r # between the input signal and the recovered clock are increased by adding the period difference ΔΤ between the two signals for each data period. In order to absorb this phase shift, the clock phase shifter 2 is controlled as shown in FIG. By performing phase switching, the frequency difference between the input signal and the multiplying clock is absorbed. The phase difference between the input signal and the recovered clock is T rl = 0, T r 2 = Δ ,, T r 3 = 2 厶 1 \ T r 4 = 3 AT. In this fifth cycle, the phases are matched again and T r 5 = 0 is set. However, because there is a frequency difference between the input signal and the multiplying clock, the phase is again shifted to T r 6 = AT, T r 7 = 2 Δ Τ, T r 8 = 3 Δ 再 び. Therefore, it is necessary to switch the phase periodically so that the clock phase is appropriate.
さらに、 特開 2 0 0 7— 2 7 8 0 9号公報 （特許文献 1 ) には、 信号間に周波 数差がある場合の位相を同期させるディジタル P L Lが開示されている。 特許文 献 1には、 位相比較器に入力される基準ク口ック周波数と内部発生のク口ック周 波数間の位相を同期させる場合のデイジタル P L Lが示されている。 このディジ タル P L Lにおけるディジタルフィルタ演算部には、 2つの位相差を積算する位 相差積算器を備えている。 最初に 2つの信号の位相を合わせ、 ここからの位相差 を積算する。 この積算された位相差に基づいて位相を切換え、 仮の位相収束とし て設定することで、 高速に位相を取り込む。 その仮の位相収束点のもとでの周波 数同期完了を確認した後、 位相収束点変更部によつて収束点の補正値を更新し、 位相差をあらかじめ設定された目的とする最終位相収束点に徐々に近づける。 仮 の位相収束点を設定し、 位相同期を確定させる動作を繰り返すことで、 徐々に最 終位相収束点に近づける。 ディジタル処理により高速に位相を取り込むことがで きるディジタル P L Lが示されている。 発明の開示  Furthermore, Japanese Patent Application Laid-Open No. 2 07-27 8 09 (Patent Document 1) discloses a digital PLL that synchronizes phases when there is a frequency difference between signals. Patent Document 1 shows the digital P L L when the phase between the reference clock frequency input to the phase comparator and the internally generated clock frequency is synchronized. The digital filter operation section in this digital P L L is equipped with a phase difference integrator that integrates two phase differences. First, match the phases of the two signals, and add up the phase difference from here. By switching the phase based on this accumulated phase difference and setting it as a temporary phase convergence, the phase is captured at high speed. After confirming the completion of frequency synchronization under the temporary phase convergence point, the correction value of the convergence point is updated by the phase convergence point changing unit, and the final phase convergence with the target phase difference set in advance is set. Gradually approach the point. By setting the temporary phase convergence point and repeating the operation to confirm the phase synchronization, gradually approach the final phase convergence point. The digital PLL that can capture the phase at high speed by digital processing is shown. Disclosure of the invention
発明が解決しょうとする課題 Problems to be solved by the invention
しかしながら、 上記した位相切換えは有限の分解能を持つディジタル的な位相 切換え制御であるため、 切換え動作に伴うジッタが生じる。 またディジタル処理 の場合には入力信号と通倍クロックとの間に周波数偏差がある場合がある。 その ため、 入力信号と遁倍クロックとの間の周波数偏差により、 周期的に位相を切り 換える必要がある。 従って、 たとえ入力信号にジッタが無かったとしても、 この 位相切換え制御によつて再生クロックジッタの増加を招くという問題点がある。 またクロック位相可変器の位相切換えの線形性や分解能も再生クロックのジッタ 増大に大きく影響するため、 クロック ·データ再生回路の設計が困難であるとい う問題もある。 However, since the phase switching described above is a digital phase switching control with a finite resolution, jitter accompanying the switching operation occurs. In the case of digital processing, there may be a frequency deviation between the input signal and the multiple clock. For this reason, it is necessary to periodically switch the phase due to the frequency deviation between the input signal and the multiplying clock. Therefore, even if there is no jitter in the input signal, there is a problem that this phase switching control causes an increase in the recovered clock jitter. In addition, the linearity and resolution of phase switching of the clock phase shifter is also the jitter of the recovered clock. There is also a problem that it is difficult to design a clock and data recovery circuit because it greatly affects the increase.
本発明の目的は、 上述した課題であるジッタの発生を抑えることができるクロ ック ·データ再生回路及びクロック ·データ再生方法を提供することにある。 An object of the present invention is to provide a clock / data recovery circuit and a clock / data recovery method capable of suppressing the occurrence of jitter, which is the problem described above.
WMを解決するための手段 Means to solve WM
本発明の 1つの視点によれば、 リファレンスクロックを遁倍し、 遲倍クロック を出力する非整数遁倍回路と、 前記通倍クロックを入力とし、 その通倍クロック の位相を可変した再生クロックを出力するク口ック位相可変器と、 前記再生ク口 ックと入力信号との位相差を検出する位相比較器と、 該位相比較器からの位相比 較出力を信号処理するディジタルフィルタと、 を備え、 前記非整数遁倍回路は、 前記入力信号のデータレートと前記通倍クロックの周波数が一致するように、 前 記非整数通倍回路の通倍比を調整することで、 入力信号に同期するように再生ク 口ックの位相を可変して最適な識別位相とするクロック ·データ再生回路が得ら れる。  According to one aspect of the present invention, a non-integer multiplier circuit that doubles a reference clock and outputs a double clock, and a recovered clock that has the multiple clock as an input and the phase of the double clock is variable. An output queuing phase variable device, a phase comparator for detecting a phase difference between the reproduction queuing clock and an input signal, a digital filter for processing a phase comparison output from the phase comparator, The non-integer multiplication circuit adjusts the multiplication ratio of the non-integer multiplication circuit so that the data rate of the input signal and the frequency of the multiplication clock coincide with each other. A clock / data recovery circuit is obtained in which the phase of the reproduction clock is varied so as to synchronize and the optimum identification phase is obtained.
さらに、 本発明の他の視点によれば、 入力信号と内部生成したクロックの位相 とを比較することで得られた周波数偏差情報に基づいて、 非整数通倍回路が遁倍 クロックを出力する第 1の位相調整ステツプと、 前記入力信号と再生クロックの 位相とを比較することで得られた位相差情報に基づいて、 前記入力信号と再生ク ロックの位相とを一致させるように前記再生クロックの位相を可変する第 2の位 相調整ステップと、 を有することで入力信号に同期するように再生クロックの位 相を可変して最適な識別位相とするクロック ·データ再生方法が得られる。  Furthermore, according to another aspect of the present invention, the non-integer multiplication circuit outputs a double clock based on frequency deviation information obtained by comparing the input signal and the phase of the internally generated clock. Based on the phase difference information obtained by comparing the phase of the phase of the input signal and the recovered clock to the phase of the recovered clock so that the input signal and the phase of the recovered clock match. By providing a second phase adjustment step for varying the phase, a clock data recovery method is obtained in which the phase of the recovered clock is varied so as to synchronize with the input signal so that the optimum identification phase is obtained.
発明の効果 The invention's effect
以上説明したように本発明によれば、 リファレンスクロックの遁倍回路として、 整数遁倍回路ではなく、 非整数遞倍回路を用いることを特徴とする。 非整数遁倍 回路を用いることで、 入力信号と遁倍クロックとの周波数偏差が小さくなり、 周 波数偏差を吸収するための再生ク口ックの周期的な位相切換え頻度を低減するこ とができる。 そのため再生クロックのジッタを小さく抑える効果が得られる。 ま た、 再生クロックの周期的な位相切換え頻度を低減できることから、 クロック ' データ再生回路を構成するクロック位相可変器の分解能や線形性に対する要求を 2 As described above, according to the present invention, a non-integer multiplication circuit is used as a reference clock multiplication circuit instead of an integer multiplication circuit. By using a non-integer multiplication circuit, the frequency deviation between the input signal and the multiplication clock is reduced, and the frequency of periodic phase switching of the reproduction clock to absorb the frequency deviation can be reduced. it can. Therefore, the effect of suppressing the jitter of the recovered clock can be obtained. In addition, since the frequency of periodic phase switching of the recovered clock can be reduced, there is a need for the resolution and linearity of the clock phase variable circuit that constitutes the clock data recovery circuit. 2
大幅に緩和することが可能となる。 そのため、 クロック 'データ再生回路の設計 を容易にするだけでなく、 プロセスバラツキなどの影響に対しても耐カが向上す るという効果が得られる。 It becomes possible to relieve significantly. Therefore, not only the design of the clock data recovery circuit is facilitated, but also the effect of improving the resistance against the influence of process variations and the like can be obtained.
本発明によれば、 再生クロックのジッタを小さく抑えることができるクロッ ク ·データ再生回路及びクロック ·データ再生方法が得られる。 図面の簡単な説明  According to the present invention, it is possible to obtain a clock data recovery circuit and a clock data recovery method capable of suppressing the jitter of the recovered clock. Brief Description of Drawings
図 1は、 関連技術としてのクロック ·データ再生回路の構成プロック図である。 図 2は、 図 1におけるクロック ·データ再生回路のタイミングチャートである。 図 3 Aは、 クロック位相可変器 （位相補間器） の回路図である。  Figure 1 is a block diagram of the clock and data recovery circuit as a related technology. FIG. 2 is a timing chart of the clock data recovery circuit in FIG. Figure 3A is a circuit diagram of the clock phase shifter (phase interpolator).
図 3 Bは、 クロック位相可変器 （位相補間器） の波形図である。  Fig. 3B is a waveform diagram of the clock phase shifter (phase interpolator).
図 4は、 本発明の第 1の実施形態のクロック ·データ再生回路の構成ブロック 図である。  FIG. 4 is a block diagram showing the configuration of the clock data recovery circuit according to the first embodiment of the present invention.
図 5は、 本発明のクロック 'データ再生回路のタイミングチャートである。 図 6は、 本発明の第 2の実施形態のクロック ·データ再生回路の構成ブロック 図である。  FIG. 5 is a timing chart of the clock data recovery circuit of the present invention. FIG. 6 is a block diagram showing the configuration of the clock and data recovery circuit according to the second embodiment of the present invention.
図 7は、 本発明の第 3の実施形態のクロック 'データ再生回路の構成プロック 図である。 発明を実施するための最良の形態  FIG. 7 is a block diagram of the configuration of the clock data recovery circuit according to the third embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
次に、 本発明の実施形態について図面を参照しながら詳細に説明する。  Next, embodiments of the present invention will be described in detail with reference to the drawings.
(第 1の実施の形態）  (First embodiment)
本発明の第 1の実施形態として、 図 4、 5を参照して詳細に説明する。 図 4に、 本発明の第 1の実施形態に係るクロック 'データ再生回路 1 5— 1の構成プロッ ク図を示す。 図 5に、 そのタイミングチヤ一トを示す。  The first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 4 shows a configuration block diagram of the clock data recovery circuit 15-1 according to the first embodiment of the present invention. Figure 5 shows the timing chart.
図 4に示すクロック 'データ再生回路 1 5— 1は、 位相比較器 1と、 クロック 位相可変器 2と、 非整数遞倍回路 3及びディジタルフィルタ 4とを備える。 クロ ック .データ再生回路 1 5—1は、 入力信号 5と、 リファレンスクロック 6とが 入力され、 同期した再生データ 9と再生クロック 8とを出力する。 非整数通倍回路 3は、 通倍比制御信号 12に基づいて、 リファレンスクロック 6から非整数倍の通倍比（M倍）で所望のデータレート近傍の周波数の遁倍ク口ッ ク 7を生成する。 このとき、 外部から通倍比の制御が可能な非整数通倍回路を使 用する。 非整数通倍回路 3からの通倍クロック 7は、 次段のクロック位相可変器 2によって、 位相制御信号 1 1に基づいてクロックの位相を有限分解能で可変と される。 位相が可変されたク口ックは入力信号を識別する再生クロック 8として 位相比較器 1へと導かれる。 このクロック位相可変器 2には、 図 3の位相補間器 を用いることができる。 位相補間器では、 位相が互いに 90度ずれた 2つクロッ ク信号 （I CLKZQCLK) が使用される。 2つの I C LK/QCLK信号を 任意の比で足し合わせることにより、 I CLKZQCLK間の任意の中間位相を もったクロック信号を生成することが可能となる。 4 includes a phase comparator 1, a clock phase variable device 2, a non-integer multiplication circuit 3, and a digital filter 4. The clock data recovery circuit 15-1 receives the input signal 5 and the reference clock 6, and outputs synchronized playback data 9 and playback clock 8. Based on the multiplication ratio control signal 12, the non-integer multiplication circuit 3 generates a multiplication clock 7 of a frequency near the desired data rate with a multiplication ratio (M times) of the non-integer multiple from the reference clock 6. Generate. At this time, use a non-integer multiplier circuit that can control the multiplier ratio from the outside. The multiple clock 7 from the non-integer multiple circuit 3 is made variable by a clock phase variable device 2 at the next stage with a finite resolution based on the phase control signal 11 1. The clock whose phase has been changed is led to the phase comparator 1 as a recovered clock 8 for identifying the input signal. As the clock phase variable unit 2, the phase interpolator shown in FIG. 3 can be used. The phase interpolator uses two clock signals (I CLKZQCLK) that are 90 degrees out of phase with each other. By adding the two IC LK / QCLK signals in any ratio, it is possible to generate a clock signal with any intermediate phase between I CLKZQCLK.
また、 位相比較器 1は、 クロック位相可変器 2から出力される再生クロック 8 を用いて入力信号 5を識別し、 再生データ 9を出力する。 入力信号 5の識別と同 時に両者の位相比較を行い、 位相の遅れ Z進みに対して位相比較出力 （UP/D OWN信号とも言う） 10を生成し、 次段のディジタルフィルタ 4へと送る。 デ イジタルフィルタ 4は、 位相比較器 1からの UP/DOWN信号 10を受け、 再 生クロックの位相が入力信号を識別するための最適な位相位置となるよう適切な 信号処理を施す。 ディジタルフィルタ 4は、 UP ZD OWN信号 10を信号処理 し、 クロック位相可変器 2に対し位相制御信号 11、 非整数通倍回路 3に対し遁 倍比制御信号 12を送る。 ク口ック位相可変器 2は、 位相制御信号 11に基づい て遁倍クロック 7の位相を調整する。 非整数遁倍回路 3は、 通倍比制御信号 12 に基づいて遁倍クロック 7の遁倍比を調整する。  Further, the phase comparator 1 identifies the input signal 5 by using the reproduction clock 8 output from the clock phase variable unit 2 and outputs the reproduction data 9. At the same time as the identification of input signal 5, the two are compared, and a phase comparison output (also called UP / D OWN signal) 10 is generated for the phase delay Z advance and sent to digital filter 4 in the next stage. The digital filter 4 receives the UP / DOWN signal 10 from the phase comparator 1 and performs appropriate signal processing so that the phase of the reproduction clock becomes the optimum phase position for identifying the input signal. The digital filter 4 processes the UP ZD OWN signal 10 and sends a phase control signal 11 to the clock phase shifter 2 and a multiplication ratio control signal 12 to the non-integer multiplication circuit 3. The clock phase shifter 2 adjusts the phase of the double clock 7 based on the phase control signal 11. The non-integer multiplication circuit 3 adjusts the multiplication ratio of the multiplication clock 7 based on the multiplication ratio control signal 12.
このとき位相比較器 1からは、 入力信号 5のデータレートに対し再生クロック 8の周波数が低ければ、 位相を進めるべく UP信号が多く出力される。 逆に周波 数が高ければ位相を遅らせるべく DOWN信号が多く出力される。 よって位相比 較器の出力の UPZD OWN信号の平均値は入力信号のデータレートと遁倍ク口 ックとの周波数偏差に比例する。 従って、 この周波数偏差情報を用いて非整数通 倍回路の遁倍比を制御し周波数偏差が小さくなるようフィードバックをかけるこ とにより、 入力信号に応じて最適な非整数通倍比 （Μ' 倍） となるよう自動制御 され、 周波数偏差を小さく抑えることが可能となる。 At this time, if the frequency of the recovered clock 8 is lower than the data rate of the input signal 5, the phase comparator 1 outputs a large number of UP signals to advance the phase. Conversely, if the frequency is high, many DOWN signals are output to delay the phase. Therefore, the average value of the UPZD OWN signal at the output of the phase comparator is proportional to the frequency deviation between the data rate of the input signal and the multiplying clock. Therefore, by using this frequency deviation information to control the multiplication ratio of the non-integer multiplication circuit and applying feedback so that the frequency deviation becomes smaller, the optimum non-integer multiplication ratio (Μ 'multiple) is selected according to the input signal. ) Automatic control to be Thus, the frequency deviation can be kept small.
例えば、 入力信号のデータレートと通倍クロックの周波数偏差がゼ口になれば、 ク口ック位相可変器は周波数偏差を吸収するための周期的な位相切換えを行う必 要が無く、 単に入力信号と再生クロックの一定遅延分を調整するのみとなる。 よ つて、 いったん位相調整が終了すれば、 その後は位相の切換えは不必要であるた めディジタル的な位相制御に伴うジッタをなくすことができる。 実際には、 非整 数遁倍回路を用いても周波数偏差を完全にゼロにすることは出来ない。 しかし、 周波数偏差を十分に小さくすることで、 周波数偏差を吸収するための周期的なク ロック位相切換え制御の周期を、 十分に低周波側に持って行くことが可能となる。 ク口ック位相切換え制御の周期を低周波側とし、 ジッタ規格の帯域外に持って行 けば事実上無視することが可能となる。  For example, if the data rate of the input signal and the frequency deviation of the multiple clock are close to each other, the Kuguchik phase shifter does not need to perform periodic phase switching to absorb the frequency deviation. Only a fixed delay between the signal and the reproduction clock is adjusted. Therefore, once the phase adjustment is completed, it is not necessary to switch the phase thereafter, so the jitter associated with digital phase control can be eliminated. In practice, the frequency deviation cannot be completely reduced to zero using a non-integer multiplication circuit. However, by making the frequency deviation sufficiently small, it is possible to bring the period of the periodic clock phase switching control to absorb the frequency deviation sufficiently to the low frequency side. If the period of the Kuchikku phase switching control is set to the low frequency side and taken outside the jitter standard band, it can be virtually ignored.
第 1のクロック ·データ再生回路 1 5の動作を図 5に示すタイミングチャート を使って具体的に説明する。 図 5では入力信号 5のデータレートに対して遁倍ク ロック 7の周波数が低い場合のタイミングチャートを示している。 このとき入力' 信号、 通倍クロック、 再生クロックの位相を識別する識別位相位置は、 入力信号 の位相方向のアイ開口の中点となったときを基準とする。 従って遁倍クロック及 び再生クロックの立ち上がりエツジが入力信号の位相方向のアイ開口の中点とな つたときが最適な位相位置となる。  The operation of the first clock / data recovery circuit 15 will be specifically described with reference to the timing chart shown in FIG. FIG. 5 shows a timing chart when the frequency of the double clock 7 is lower than the data rate of the input signal 5. At this time, the identification phase position for identifying the phase of the input signal, the multiple clock, and the recovered clock is based on the middle point of the eye opening in the phase direction of the input signal. Therefore, the optimum phase position is when the rising edge of the double clock and the recovered clock reaches the middle point of the eye opening in the phase direction of the input signal.
電源投入時などの初期状態においては、 非整数遁倍回路 3の通倍比 Mは最適で はない。 そのため、 入力信号のデータレートと、 リファレンスクロックから非整 数遁倍回路によって通倍された遁倍クロックの周波数とは、 ずれがある。 ここで、 入力信号と遁倍クロックの一周期差を Δ Τ、 入力信号と通倍クロックの位相差 T m # ( # = 1、 2、 3 - · · )、 入力信号と再生クロックの位相差 T r # ( # = 1、 2、 3 · · · ) とする。  In the initial state such as when the power is turned on, the multiplication ratio M of the non-integer multiplication circuit 3 is not optimal. For this reason, there is a difference between the data rate of the input signal and the frequency of the multiplication clock multiplied by the non-integer multiplication circuit from the reference clock. Where the period difference between the input signal and the double clock is Δ Δ, the phase difference between the input signal and the double clock T m # (# = 1, 2, 3-...), the phase difference between the input signal and the recovered clock Let T r # (# = 1, 2, 3 ···).
最初に、 位相比較器からの位相比較出力からの情報に基づいて、 入力信号と遁 倍クロックと再生クロックの位相を合わせた時点を、 入力信号の 1周期目として 図 5に示している。 この時は、 入力信号と通倍クロックの位相差 Tm l = 0、 入 力信号と再生クロックの位相差 T r 1 = 0となる。 しかし入力信号と通倍クロッ クでは周波数がずれているため （周波数偏差があるため）、 その位相差はデータ 周期ごとに ΔΤが積算され、 増大していく。 入力信号と遁倍クロックの位相差 Tm#は、 Tml=0、 Τπι2 = ΔΤ、 Tm 3 = 2 Δ T, Tm4 = 3 ATとなる。 また入力信号と再生クロックの位相差 Τ r #は、 Tr l = 0、 T r 2-ΔΤ, T Γ 3 = 2 ΔΤ、 Tr 4 = 3厶 Τとなる。 First, the time when the phase of the input signal, the multiple clock and the recovered clock are matched based on the information from the phase comparison output from the phase comparator is shown in FIG. 5 as the first period of the input signal. At this time, the phase difference Tm l = 0 between the input signal and the multiple clock, and the phase difference T r 1 = 0 between the input signal and the recovered clock. However, since the frequency is different between the input signal and the multiple clock (because there is a frequency deviation), the phase difference is the data ΔΤ is accumulated and increased every period. The phase difference Tm # between the input signal and the multiplying clock is Tml = 0, Τπι2 = ΔΤ, Tm 3 = 2 Δ T, Tm4 = 3 AT. The phase difference Τ r # between the input signal and the recovered clock is Tr l = 0, T r 2-ΔΤ, T Γ 3 = 2 ΔΤ, and Tr 4 = 3 厶 #.
この入力信号と通倍クロックの遅れの平均値は ΔΤである。 この一周期差 厶 Τを補正すれば、 周波数偏差がなくなることになる。 この入力信号と通倍ク口ッ クの一周期差 ΔΤが周波数偏差情報である。 ディジタルフィルタ 4は、 位相比 較器からの位相比較出力 （UPZDOWN信号） 10に基づいて、 この周波数偏 差情報と最適な通倍比を算出し、 通倍比制御信号 12として非整数通倍回路 3に 送る。 非整数遁倍回路 3は遁倍比制御信号により最適な通倍比 （Μ' 倍） の遁倍 クロックに切り替え出力する。  The average value of the delay between this input signal and the multiple clock is ΔΤ. If this one-cycle difference 厶 補正 is corrected, the frequency deviation is eliminated. The frequency deviation information is the difference ΔΤ between this input signal and the multiplication clock. The digital filter 4 calculates the frequency deviation information and the optimum multiplication ratio based on the phase comparison output (UPZDOWN signal) 10 from the phase comparator, and uses the non-integer multiplication circuit as the multiplication ratio control signal 12. Send to 3. The non-integer multiplier circuit 3 switches the output to a multiple clock with the optimum multiplication ratio (Μ 'times) by the multiplication ratio control signal.
このように位相比較器 1は、 入力信号 5と再生クロック 8との位相差を検出し、 位相の遅れ ·進みに対応して UPZDOWN信号 10を出力する。 このタイミン グチャートの例では、 再生ク口ックの周波数が入力信号のデータレートに対して 低いため、 位相比較器 1は位相を進めるべく UP信号を出力する。 そしてデイジ タルフィルタ 4を介してクロック位相可変器 2を制御し位相を進めるべく位相切 換えを行い、 周波数偏差による位相のずれを吸収するようフィードバックが掛か つている。 このとき、 位相比較器 1が出力する UP信号の頻度は、 入力信号 5と 通倍クロック 7の周波数偏差に比例する。 すなわち、 遁倍クロックの周波数が入 力信号データレートに対して低ければ UP信号を多く出力し、 周波数が高ければ DOWN信号を多く出力する。 また、 その周波数偏差が大きいほど UPZDOW Nの出力頻度は多くなる。 したがって、 位相比較器の出力の平均値を求めること で、 周波数偏差情報を得ることができる。 非整数遞倍回路は、 周波数偏差情報に 基づいて、 最適な遁倍比 （Μ' 倍） の遁倍クロックに切り替え出力する。  In this way, the phase comparator 1 detects the phase difference between the input signal 5 and the recovered clock 8 and outputs the UPZDOWN signal 10 corresponding to the phase delay / advance. In this timing chart example, the frequency of the playback clock is lower than the data rate of the input signal, so phase comparator 1 outputs an UP signal to advance the phase. Then, the clock phase shifter 2 is controlled via the digital filter 4 to perform phase switching to advance the phase, and feedback is applied to absorb the phase shift due to the frequency deviation. At this time, the frequency of the UP signal output from the phase comparator 1 is proportional to the frequency deviation between the input signal 5 and the multiple clock 7. In other words, if the frequency of the double clock is lower than the input signal data rate, more UP signals are output, and if the frequency is higher, more DOWN signals are output. The larger the frequency deviation, the higher the output frequency of UPZDOW N. Therefore, frequency deviation information can be obtained by calculating the average value of the output of the phase comparator. The non-integer multiplier circuit switches to a multiple clock with the optimum multiplication ratio (Μ 'times) based on the frequency deviation information.
図 5では入力信号の 5周期目で、 非整数通倍回路 3は遁倍比制御信号 12によ り最適な遞倍比 （Μ' 倍） の通倍クロックに切り替え出力する。 これにより、 入 力信号 5のデータレートと通倍クロック 7の周波数偏差は小さくなる。 最適な通 倍比 （Μ' 倍） が設定された後は、 周波数はほぼ一致しているため、 位相を合わ せるのみとなる。 しかし、 通倍比が非整数倍とはいえ実際には周波数偏差をゼロ にすることはできないため、 入力信号と遁倍クロックの周期差 ΔΤ' がある。 ここで、 最適な遁倍比 （Μ' 倍） の遞倍クロックに切り替えられた入力信号 5 周目の位相差を T s k wとする。 このとき、 入力信号と通倍クロックの位相差 T m#は、 Tm5=T s kw、 Tm 6 = T s k w +厶 T，、 Tm 7 =T s k w+ 2 AT' となる。 また入力信号と再生クロックの位相差 T r #は、 Tr 5=T s k w、 T r 6 =T s k w+ Δ T，、 Tm 7 = T s k w+ 2厶 T ' となる。 この位相 差 T s k wが位相差情報であり、 位相制御信号 11としてディジタルフィルタ 4 からクロック位相可変器 2に送られる。 ク口ック位相可変器 2は位相制御信号 1 1に従って位相を調整する。 In Fig. 5, in the 5th cycle of the input signal, the non-integer multiplier circuit 3 switches and outputs the optimum multiplier ratio (倍 'times) through the clock with the multiplication ratio control signal 12. As a result, the data rate of the input signal 5 and the frequency deviation of the double clock 7 are reduced. After the optimum multiplication ratio (Μ 'times) has been set, the frequencies are almost the same, so only the phases are matched. However, even though the multiplication ratio is a non-integer multiple, the frequency deviation is actually zero. There is a period difference Δ 差 'between the input signal and the double clock. Here, let T skw be the phase difference of the 5th round of the input signal switched to the optimal multiple ratio (ク ロ ッ ク 'multiple) multiple clock. At this time, the phase difference T m # between the input signal and the multiple clock is Tm5 = Tskw, Tm6 = Tskw + 厶 T, and Tm7 = Tskw + 2AT ′. The phase difference T r # between the input signal and the recovered clock is Tr 5 = T skw, T r 6 = T sk w + ΔT, and Tm 7 = T sk w + 2 厶 T ′. This phase difference T skw is phase difference information and is sent from the digital filter 4 to the clock phase variable unit 2 as the phase control signal 11. The Kuguchik phase shifter 2 adjusts the phase according to the phase control signal 1 1.
さらに、 位相比較器は入力信号と！？生クロックとの位相差を検出し、 位相の遅 れ ·進みに対応して UPZD OWN信号を出力する。 図 5では入力信号の 8周目 で再生クロックの位相が制御され、 入力信号と再生クロックは同期する。 その後 入力信号と遁倍クロックの位相差 Tm#は、 Tm8 =T s k w+ 3 Δ T'、 Tm 9=T s kw+4厶 Τ'、 Tm 10 =Τ s k w+ 5厶 Τ' となる。 また入力信号 と再生クロックの位相差 T r #は、 T r 8 = 0、 T r 9 = AT'、 Tm 10 = 2 ΔΤ' となる。  In addition, the phase comparator is the input signal! ? The phase difference from the raw clock is detected, and the UPZD OWN signal is output in response to the phase delay / advance. In Fig. 5, the phase of the recovered clock is controlled at the 8th round of the input signal, and the input signal and recovered clock are synchronized. After that, the phase difference Tm # between the input signal and the multiplying clock is Tm8 = T s k w + 3 ΔT ', Tm 9 = T s kw + 4 厶 Τ', Tm 10 = Τ s k w + 5 厶 Τ '. The phase difference T r # between the input signal and the recovered clock is T r 8 = 0, T r 9 = AT ', Tm 10 = 2 ΔΤ'.
この周波数偏差 ΔΤ' を十分に小さく抑えれば （すなわち ΔΤ' =0), 周波 数偏差を吸収するための位相切換え制御の周期を長くすることができる。 位相切 換え制御の頻度を低減できる。 したがって、 この位相切換え制御に伴うジッタ発 生頻度を低減し、 十分に低周波側に持っていくことが可能となる。 また周波数偏 差 ΔΤ' が大きい場合には再度通倍比の調整と位相差の調整が繰り返さすこと で、 周波数偏差 ΔΤ' を十分に小さくできる。 本発明においては通倍回路を非 整数遁倍回路とすることで通倍比を自由に選択できることから、 この周波数偏差 AT' Oに十分に小さく抑えることができる。  If this frequency deviation ΔΤ 'is kept sufficiently small (ie ΔΤ' = 0), the phase switching control cycle for absorbing the frequency deviation can be lengthened. The frequency of phase switching control can be reduced. Therefore, it is possible to reduce the frequency of jitter generation associated with this phase switching control and bring it to a sufficiently low frequency side. If the frequency deviation ΔΤ 'is large, the frequency deviation ΔΤ' can be made sufficiently small by repeating the adjustment of the multiplication ratio and the adjustment of the phase difference again. In the present invention, the multiplication ratio can be freely selected by making the multiplication circuit a non-integer multiplication circuit, so that the frequency deviation AT'O can be sufficiently reduced.
通常、 ディジタル伝送システムにおいては、 ジッタ帯域が規定されており、 低 周波域のジッタは運用上問題にはならず、 無視することができる。 そのため、 本 発明を適用することで再生クロックのジッタを大幅に低減したクロック 'データ 再生回路を実現することが可能となる。 また、 クロック位相可変器の線形性や分 解能の性能も大きく緩和でき、 回路設計が容易になるばかりでなく、 回路規模も 低減できる。 そのため、 プロセスバラツキなどの影響に対しても耐カが向上する 効果も得られる。 Usually, in a digital transmission system, a jitter band is defined, and the low frequency jitter is not an operational problem and can be ignored. Therefore, by applying the present invention, it is possible to realize a clock data recovery circuit in which the jitter of the recovered clock is greatly reduced. In addition, the linearity and resolution performance of the clock phase shifter can be greatly relaxed, which not only facilitates circuit design, but also increases the circuit scale. Can be reduced. As a result, the effect of improving resistance against the effects of process variations can be obtained.
本実施形態例においては、 位相比較器 1からの U P ZD OWN信号 1 0に基づ いてディジタルフィルタ 4は位相情報である位相制御信号 1 1と、 周波数偏差情 報である通倍比制御信号 1 2を生成する。 遁倍比制御信号 1 2に基づいて非整数 通倍器 3の遁倍比を制御するとともに、 位相制御信号 1 1に基づいてク口ック位 相可変器の位相を制御する。 遁倍比と位相を制御することで、 再生クロックのジ ッタを大幅に低減したクロック ·データ再生回路を実現することが可能となる。 (第 2の実施形態）  In this embodiment, the digital filter 4 is based on the UP ZD OWN signal 1 0 from the phase comparator 1 and the phase control signal 1 1 that is phase information and the multiplication ratio control signal 1 that is frequency deviation information. 2 is generated. Based on the multiplication ratio control signal 1 2, the multiplication ratio of the non-integer multiplier 3 is controlled, and on the basis of the phase control signal 11 1, the phase of the queuing phase shifter is controlled. By controlling the multiplication ratio and phase, it becomes possible to realize a clock and data recovery circuit that greatly reduces the jitter of the recovered clock. (Second embodiment)
本発明の第 2の実施形態として、 図 6を参照して説明する。 図 6に第 2の実施 形態に係るクロック .データ再生回路 1 5— 2の構成プロック図を示す。 第 1の 実施例と本実施例との相違点は、 位相比較器 1の代わりに位相周波数比較器 1 3 を用いている点である。 本実施形態例は入力信号のデータレートと遲倍クロック との周波数偏差が大きい場合に特に有効である実施形態である。  A second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a block diagram of the configuration of the clock data recovery circuit 15-2 according to the second embodiment. The difference between the first embodiment and this embodiment is that a phase frequency comparator 1 3 is used instead of the phase comparator 1. This embodiment is an embodiment that is particularly effective when the frequency deviation between the data rate of the input signal and the multiplying clock is large.
図 6に示すクロック 'データ再生回路 1 5— 2は、 位相周波数比較器 1 3と、 ク口ック位相可変器 2と、 非整数通倍回路 3及びディジタルフィルタ 4とを備え る。 クロック .データ再生回路 1 5— 2は、 入力信号 5と、 リファレンスクロッ ク 6とが入力され、 同期した再生データ 9と再生クロック 8とを出力する。  6 includes a phase frequency comparator 13, a clock phase variable circuit 2, a non-integer multiplication circuit 3, and a digital filter 4. Clock data recovery circuit 1 5—2 receives input signal 5 and reference clock 6, and outputs synchronized playback data 9 and playback clock 8.
位相周波数比較器 1 3は、 入力される信号間に 1サイクル以上の位相差の場合 には周波数比較器として動作する。 一方 1サイクル以内の位相差の場合には位相 比較器として動作する位相比較器の 1つである。 従って位相周波数比較器 1 3は、 入力信号 5と再生クロック 8との周波数偏差 （位相差） の大小により周波数比較 器、 又は位相比較器として動作する比較器である。 位相周波数比較器 1 3からの 位相比較出力 （U Pノ D OWN信号） 1 0を、 ディジタルフィルタ 4を介して非 整数遁倍回路 3及びクロック位相可変器 2にフィードバックを掛け、 周波数偏差 による位相のずれを吸収する。 本実施例のその他のクロック位相可変器 2と、 非 整数遁倍回路 3及びディジタルフィルタ 4の構成及びその動作は第 1実施形態と 同様であり、 その説明は省略する。  The phase frequency comparator 13 operates as a frequency comparator when there is a phase difference of 1 cycle or more between input signals. On the other hand, in the case of a phase difference within one cycle, it is one of the phase comparators that operate as a phase comparator. Therefore, the phase frequency comparator 13 is a comparator that operates as a frequency comparator or a phase comparator depending on the magnitude of the frequency deviation (phase difference) between the input signal 5 and the recovered clock 8. Phase comparison output from the phase frequency comparator 1 3 (UP signal D OWN signal) 1 0 is fed back to the non-integer multiplication circuit 3 and the clock phase shifter 2 via the digital filter 4, and the phase due to the frequency deviation is Absorb the deviation. The configuration and operation of the other clock phase variable device 2, the non-integer multiplication circuit 3 and the digital filter 4 in this embodiment are the same as those in the first embodiment, and the description thereof is omitted.
従って第 2の実施形態においては、 入力された入力信号 5と再生クロック 8と の周波数偏差の大きい場合には、 位相周波数比較器 1 3が位相比較器 1よりも効 果的に動作することになる。 入力された入力信号 5と再生クロック 8との周波数 偏差が大きい （1サイクル以上） 場合には、 位相周波数比較器 1 3からの位相比 較出力 1 0は、 周波数偏差情報を含む。 位相比較出力 1 0は、 ディジタルフィル タ 4を介して遁倍比制御信号 1 2に基づいて非整数通倍回路 3を制御して、 通倍 比を決定する。 非整数通倍回路 3が遁倍比を切り替えることで、 周波数入力信号 5と再生クロック 8との周波数偏差が小さくなりほぼ零となる。 周波数偏差が小 さくなり、 さらに位相制御信号 1 1がクロック位相可変器 2を制御して、 位相を 調整する。 Therefore, in the second embodiment, the input signal 5 and the recovered clock 8 When the frequency deviation is large, the phase frequency comparator 13 operates more effectively than the phase comparator 1. When the frequency deviation between the input signal 5 and the recovered clock 8 is large (1 cycle or more), the phase comparison output 10 from the phase frequency comparator 13 includes frequency deviation information. The phase comparison output 10 controls the non-integer multiplication circuit 3 based on the multiplication ratio control signal 12 through the digital filter 4 to determine the multiplication ratio. When the non-integer multiplier circuit 3 switches the multiplication ratio, the frequency deviation between the frequency input signal 5 and the recovered clock 8 becomes smaller and becomes almost zero. The frequency deviation decreases, and the phase control signal 1 1 controls the clock phase shifter 2 to adjust the phase.
本実施形態のタイミングチャートは、 図 5と同じである。 最初に、 入力信号 5 と通倍クロック 7及び再生クロック 8を同期させる。 次に、 図 5においては入力 信号の 5周期目に非整数通倍回路 3の遁倍クロック 7の通倍比を変更している。 位相周波数比較器 1 3からの位相比較出力を入力されたディジタルフィルタ 4は、 遁倍比制御信号 1 2を非整数通倍回路 3に送る。 非整数遁倍回路 3は、 設定され た遁倍比 （M倍） を遁倍比 （Μ'倍） に切り替え、 設定された遁倍比 （Μ'倍） の 通倍クロック 7を出力する。 非整数通倍回路 3の遁倍比を切り替えることで、 入 力信号 5と通倍クロック 7の周波数偏差が小さくなる。  The timing chart of this embodiment is the same as FIG. First, the input signal 5 is synchronized with the double clock 7 and the recovery clock 8. Next, in FIG. 5, the multiplication ratio of the multiplying clock 7 of the non-integer multiplication circuit 3 is changed in the fifth cycle of the input signal. The digital filter 4 to which the phase comparison output from the phase frequency comparator 13 is input sends the multiplication ratio control signal 12 to the non-integer multiplication circuit 3. The non-integer multiplication circuit 3 switches the set multiplication ratio (M times) to the multiplication ratio (Μ 'times), and outputs a normal clock 7 of the set multiplication ratio (Μ' times). By switching the multiplication ratio of the non-integer multiplier circuit 3, the frequency deviation between the input signal 5 and the multiplier clock 7 is reduced.
入力される入力信号 5と再生クロック 8との周波数偏差が小さくなった段階で は、 位相周波数比較器 1 3は位相比較器として動作する。 位相周波数比較器 1 3 からの U PZD OWN信号 1 0に基づいて、 ディジタルフィルタ 4は、 位相制御 信号 1 1を使用してクロック位相可変器 2の位相切換えを制御する。 図 5におい ては、 入力信号の 8周期目にクロックの位相を変更している。  At the stage when the frequency deviation between the input signal 5 and the recovered clock 8 is reduced, the phase frequency comparator 13 operates as a phase comparator. Based on the U PZD OWN signal 1 0 from the phase frequency comparator 1 3, the digital filter 4 controls the phase switching of the clock phase shifter 2 using the phase control signal 1 1. In Fig. 5, the clock phase is changed in the 8th period of the input signal.
第 1の実施例では、 電源投入時などの初期状態において、 入力信号のデータレ 一トと遁倍クロックとの周波数偏差が大きすぎると、 クロック位相可変器の位相 切換えが追いつかず、 位相比較器がサイクルスリップを引き起こす。 このため、 安定な周波数偏差情報が得られず、 非整数通倍回路の通倍比設定が不安定となり 安定なロックが出来ない可能性がある。 本実施例では、 位相周波数比較器を用い ることで、 サイクルスリップを引き起こさない安定した周波数偏差情報を得るこ とで、 この問題を解決することができる。 JP2009/052002 In the first embodiment, if the frequency deviation between the data rate of the input signal and the multiplying clock is too large in the initial state such as when the power is turned on, the phase switching of the clock phase shifter cannot catch up and the phase comparator Causes a cycle slip. For this reason, stable frequency deviation information cannot be obtained, and the multiplication ratio setting of the non-integer multiplication circuit becomes unstable, and there is a possibility that stable locking cannot be performed. In this embodiment, this problem can be solved by using the phase frequency comparator to obtain stable frequency deviation information that does not cause cycle slip. JP2009 / 052002
本実施形態例においては、 位相周波数比較器からの位相比較出力に基づいてデ ィジタルフィルタ 4は位相制御信号 1 1と遁倍比制御信号 1 2を生成する。 遁倍 比制御信号 1 2に基づいて非整数通倍器 3の通倍比を制御するとともに、 位相制 御信号 1 1に基づいてクロック位相可変器の位相を制御する。 さらに、 位相周波 数比較器を用いることで、 周波数偏差が大きい場合にも、 サイクルスリップを引 き起こさない安定した周波数偏差情報を得ることで安定な引き込み動作が可能と なる。 本実施形態例では、 周波数の通倍比と位相を制御することで、 再生クロッ クのジッタを大幅に低減したクロック ·データ再生回路を実現することが可能と なる。 In the present embodiment, the digital filter 4 generates the phase control signal 11 and the multiplication ratio control signal 12 based on the phase comparison output from the phase frequency comparator. The multiplication ratio of the non-integer multiplier 3 is controlled based on the multiplication ratio control signal 1 2 and the phase of the clock phase variable device is controlled based on the phase control signal 11. In addition, by using a phase frequency comparator, even if the frequency deviation is large, it is possible to obtain a stable frequency deviation information that does not cause cycle slip, thereby enabling a stable pull-in operation. In this embodiment, it is possible to realize a clock / data recovery circuit in which the jitter of the recovered clock is greatly reduced by controlling the frequency multiplication ratio and phase.
(第 3の実施形態）  (Third embodiment)
本発明の第 3の実施形態として、 図 7を参照して説明する。 図 7に第 3の実施 形態に係るクロック 'データ再生回路 1 5— 3の構成ブロック図を示す。 第 1の 実施例と本実施例との相違点は、 入力信号と遁倍クロックとの周波数を比較する 周波数比較器を別途設け、 周波数比較器を使用して非整数遁信回路の通倍比を制 御している点である。 本実施形態例は、 第 2実施形態と同様に、 入力信号のデー タレートと通倍ク口ックとの周波数偏差が大きい場合に特に有効である。  A third embodiment of the present invention will be described with reference to FIG. FIG. 7 shows a configuration block diagram of a clock data recovery circuit 15-3 according to the third embodiment. The difference between the first embodiment and this embodiment is that a separate frequency comparator for comparing the frequency of the input signal and the multiplying clock is provided, and the multiplication ratio of the non-integer communication circuit using the frequency comparator is provided. It is a point that controls. As in the second embodiment, this embodiment is particularly effective when the frequency deviation between the data rate of the input signal and the multiplication clock is large.
図 Ίに示すクロック 'データ再生回路 1 5— 3は、 位相比較器 1と、 クロック 位相可変器 2と、 非整数遁倍回路 3、 ディジタルフィルタ 4及び周波数比較器 1 4とを備える。 クロック ·データ再生回路 1 5— 3は、 入力信号 5と、 リファレ ンスクロック 6とが入力され、 同期した再生データ 9と再生クロック 8とを出力 する。  The clock 'data recovery circuit 1 5-3 shown in FIG. 8 includes a phase comparator 1, a clock phase variable device 2, a non-integer multiplication circuit 3, a digital filter 4, and a frequency comparator 14. The clock / data recovery circuit 1 5-3 receives the input signal 5 and the reference clock 6, and outputs synchronized playback data 9 and playback clock 8.
第 1実施形態の構成に比較して、 非整数遁倍回路の遁倍比を制御するため入力 信号と遁倍クロックとの周波数を比較する周波数比較器 1 4が追加されている。 周波数比較器 1 4は、 入力信号 5と非整数遁倍回路によって生成された通倍ク口 ック 7とが入力され、 その 2つの周波数差を検出する周波数比較器である。 その 比較結果に応じて、 周波数比較器 1 4は非整数通倍回路の通倍比を制御する。 非 整数遁倍回路の通倍比を制御する遁倍比制御信号 1 2は、 第 1実施形態ではディ ジタルフィルタ 4から発行されていたが、 本実施形態では周波数比較器 1 4から 発行されることになる。 本実施例のその他の位相比較器 1と、 クロック位相可変 器 2と、 非整数通倍回路 3及ぴディジタルフィルタ 4の構成及ぴその動作は第 1 実施形態とほぼ同様であり、 その説明は省略する。 Compared to the configuration of the first embodiment, a frequency comparator 14 for comparing the frequency of the input signal and the multiplication clock is added to control the multiplication ratio of the non-integer multiplication circuit. The frequency comparator 14 is a frequency comparator that receives an input signal 5 and a multiplication clock 7 generated by a non-integer multiplication circuit and detects a frequency difference between the two. According to the comparison result, the frequency comparator 14 controls the multiplication ratio of the non-integer multiplication circuit. The multiplication ratio control signal 1 2 for controlling the multiplication ratio of the non-integer multiplication circuit is issued from the digital filter 4 in the first embodiment, but is issued from the frequency comparator 14 in this embodiment. It will be. Other phase comparator 1 of this embodiment and variable clock phase The configuration and operation of the device 2, the non-integer multiplier 3 and the digital filter 4 are almost the same as those in the first embodiment, and the description thereof is omitted.
本実施例においては、 周波数比較器 1 4は、 入力信号 5と遁倍クロック 7を入 力され、 その比較出力である遁倍比制御信号 1 2を非整数通倍回路 3に出力する。 非整数通倍回路 3は、 通倍比制御信号 1 2に基づいて遁倍比を切り替え、 指定さ れた通倍比の通倍クロック 7を出力する。 位相比較器 1は、 入力信号 5と再生ク ロック 8とが入力され、 その位相比較出力 1 0をディジタルフィルタ 4に出力す る。 ディジタルフィルタ 4は、 位相制御信号 1 1をクロック位相可変器 2に出力 する。 ク口ック位相可変器 2は、 位相制御信号 1 1に基づいて位相を切り替え、 再生クロックを出力する。 周波数の通倍比と位相を制御することで、 再生クロッ クのジッタを大幅に低減したクロック ·データ再生回路が得られる。  In this embodiment, the frequency comparator 14 receives the input signal 5 and the multiplication clock 7 and outputs a multiplication ratio control signal 12 which is the comparison output to the non-integer multiplication circuit 3. The non-integer multiplication circuit 3 switches the multiplication ratio based on the multiplication ratio control signal 12 and outputs the multiplication clock 7 having the designated multiplication ratio. The phase comparator 1 receives the input signal 5 and the reproduction clock 8 and outputs the phase comparison output 10 to the digital filter 4. The digital filter 4 outputs the phase control signal 11 to the clock phase variable unit 2. The clock phase shifter 2 switches the phase based on the phase control signal 1 1 and outputs a recovered clock. By controlling the frequency multiplication ratio and phase, it is possible to obtain a clock and data recovery circuit that greatly reduces the jitter of the recovered clock.
本実施形態例においては、 周波数比較器と位相比較器とを備え、 それぞれの比 較結果に基づいて周波数と位相とを個別に調整することができる。 周波数比較器 を備えることで、 周波数偏差が大きい場合にもサイクルスリップを引き起こさな い安定した周波数偏差情報を得ることで安定な引き込み動作が可能となる。 本実 施例では、 周波数の遁倍比と位相を制御することで、 再生クロックのジッタを大 幅に低減したクロック ·データ再生回路を実現することが可能となる。  In this embodiment, a frequency comparator and a phase comparator are provided, and the frequency and phase can be individually adjusted based on the comparison results. By providing a frequency comparator, stable pull-in operation is possible by obtaining stable frequency deviation information that does not cause cycle slip even when the frequency deviation is large. In this embodiment, it is possible to realize a clock / data recovery circuit in which the jitter of the recovered clock is greatly reduced by controlling the frequency multiplication ratio and phase.
本願発明によれば、 リファレンスクロックを遁倍し、 遁倍クロックを出力する 非整数遁倍回路と、 通倍クロックを入力とし、 その遞倍クロックの位相を可変し た再生クロックを出力するクロック位相可変器と、 再生クロックと入力信号との 位相差を検出する位相比較器と、 位相比較器からの位相比較出力を信号処理する ディジタルフィルタと、 を備え、 非整数遁倍回路は、 入力信号のデータレートと 遞倍クロックの周波数が一致するように、 非整数遁倍回路の遁倍比を調整するこ とで、 入力信号に同期するように再生クロックの位相を可変して最適な識別位相 とするクロック ·データ再生回路が提供できる。  According to the present invention, the non-integer multiplier circuit that doubles the reference clock and outputs the double clock, and the clock phase that outputs the recovered clock with the multiple clock input as the input and the phase of the double clock as variable are input. A variable filter, a phase comparator for detecting the phase difference between the recovered clock and the input signal, and a digital filter for signal processing the phase comparison output from the phase comparator. By adjusting the multiplication ratio of the non-integer multiplication circuit so that the data rate and the frequency of the multiplication clock match, the phase of the recovered clock can be varied to synchronize with the input signal, and the optimum identification phase can be obtained. A clock data recovery circuit can be provided.
本願発明のクロック 'データ再生回路のディジタルフィルタは、 位相比較器か ら入力された位相比較出力を信号処理して得られる周波数偏差情報に基づいて、 非整数通倍回路の遁倍比を調整することができる。 その周波数偏差情報は、 位相 比較器からの位相比較出力である U P /D OWN信号の平均値から得ることがで きる。 また位相比較器は、 前記再生クロックと入力信号との位相差を検出する位 相比較器、 又は前記再生クロックと入力信号との位相差及び周波数差を検出する 位相周波数比較器のいずれかとすることができる。 さらに、 通倍クロックと入力 信号とを入力とし、 両者の周波数差を検出する周波数比較器をさらに個別に備え、 周波数比較器からの出力を用いて非整数通倍回路の通倍比を調整することもでき る。 The digital filter of the clock data recovery circuit of the present invention adjusts the multiplication ratio of the non-integer multiplication circuit based on the frequency deviation information obtained by signal processing the phase comparison output input from the phase comparator. be able to. The frequency deviation information can be obtained from the average value of the UP / D OWN signal, which is the phase comparison output from the phase comparator. wear. The phase comparator is either a phase comparator that detects a phase difference between the recovered clock and the input signal, or a phase frequency comparator that detects a phase difference and a frequency difference between the recovered clock and the input signal. Can do. In addition, a frequency comparator that detects the frequency difference between the clock and the input signal is provided separately, and the output from the frequency comparator is used to adjust the multiplication ratio of the non-integer multiplier circuit. You can also.
さらに、 本願発明によれば、 入力信号と内部生成したクロックの位相とを比較 することで得られた周波数偏差情報に基づいて、 非整数遁倍回路が通倍クロック を出力する第 1の位相調整ステツプと、 入力信号と再生クロックの位相とを比較 することで得られた位相差情報に基づいて、 入力信号と再生クロックの位相とを 一致させるように再生クロックの位相を可変する第 2の位相調整ステップと、 を 有し、 入力信号に同期するように再生ク口ックの位相を可変して最適な識別位相 とするクロック ·データ再生方法が提供できる。  Further, according to the present invention, based on the frequency deviation information obtained by comparing the input signal and the phase of the internally generated clock, the first phase adjustment in which the non-integer multiplication circuit outputs the multiple clock Based on the step and the phase difference information obtained by comparing the phase of the input signal and the recovered clock, the second phase that varies the phase of the recovered clock to match the phase of the input signal and the recovered clock An adjustment step, and a clock / data recovery method in which the phase of the reproduction clock is varied to synchronize with the input signal so as to obtain an optimum identification phase.
本願発明のクロック ·データ再生方法の第 1の位相調整ステップにおいては、 位相比較器が入力信号と再生ク口ックとの位相差を検出した位相比較出力を出力 し、 位相比較出力から算出した周波数偏差情報に基づいて非整数遁倍回路の通倍 比を調整することができる。 また位相周波数比較器が入力信号と再生クロックと の位相差及び周波数差を検出した位相比較出力を出力し、 位相比較出力の周波数 差から算出した周波数偏差情報に基づいて非整数遁倍回路の通倍比を調整するこ ともできる。 さらに周波数比較器が入力信号と遁倍クロックとを比較した周波数 偏差情報を出力し、 周波数偏差情報に基づいて非整数遁倍回路の遞倍比を調整し てもよい。  In the first phase adjustment step of the clock and data recovery method of the present invention, the phase comparator outputs a phase comparison output that detects the phase difference between the input signal and the playback clock, and is calculated from the phase comparison output. The multiplication ratio of the non-integer multiplication circuit can be adjusted based on the frequency deviation information. The phase frequency comparator outputs a phase comparison output in which the phase difference and the frequency difference between the input signal and the recovered clock are detected, and the non-integer multiplication circuit passes through the frequency deviation information calculated from the frequency difference of the phase comparison output. You can also adjust the multiplication ratio. Further, the frequency comparator may output frequency deviation information obtained by comparing the input signal and the multiplication clock, and the multiplication ratio of the non-integer multiplication circuit may be adjusted based on the frequency deviation information.
上記したように実施形態を参照して本願発明を説明したが、 本願発明は上記の 実施形態に限定されるものではない。 本願発明の構成や詳細には、 本願発明のス コープ内で様々な変更をすることができるものである。  As described above, the present invention has been described with reference to the embodiment, but the present invention is not limited to the above-described embodiment. Various changes can be made to the configuration and details of the present invention within the scope of the present invention.
この出願は、 2 0 0 8年 2月 1 2日に出願された日本出願特願 2 0 0 8 - 0 3 0 2 8 9号を基礎とする優先権を主張し、 その開示の全てをここに取り込むもの である。  This application claims priority based on Japanese Patent Application No. 2 0 0 8-0 3 0 2 8 9 filed on February 1st, February 2008, the entire disclosure of which is here It is to be taken in.

Claims

請 求 の 範 囲 The scope of the claims
1 . 入力信号に同期するように再生クロックの位相を可変して最適な識別位相 とするクロック .データ再生回路であって、 リファレンスクロックを遁倍し、 通 倍クロックを出力する非整数遁倍回路と、 前記遁倍クロックを入力とし、 その遁 倍クロックの位相を可変した再生クロックを出力するク口ック位相可変器と、 前 記再生クロックと入力信号との位相差を検出する位相比較器と、 該位相比較器か らの位相比較出力を信号処理するディジタルフィルタと、 を備え、 前記非整数遁 倍回路は、 前記入力信号のデータレートと前記通倍クロックの周波数が一致する ように、 前記非整数遲倍回路の通倍比を調整することを特徴とするクロック -デ ータ再生回路。 1. A clock that changes the phase of the recovered clock to synchronize with the input signal to obtain the optimum identification phase.Data recovery circuit that doubles the reference clock and outputs a common clock A clock phase variable unit that outputs the recovered clock in which the phase of the multiplied clock is changed, and a phase comparator that detects a phase difference between the reproduced clock and the input signal. And a digital filter that performs signal processing on the phase comparison output from the phase comparator, and the non-integer multiplication circuit is configured such that the data rate of the input signal and the frequency of the multiple clock coincide with each other. A clock-data recovery circuit which adjusts a multiplication ratio of the non-integer multiplication circuit.
2 . 前記ディジタルフィルタは、 前記位相比較器から入力された位相比較出力 を信号処理して得られる周波数偏差情報に基づいて、 前記非整数通倍回路の遁倍 比を調整することを特徴とする請求項 1に記載のクロック ·データ再生回路。 2. The digital filter adjusts a multiplication ratio of the non-integer multiplication circuit based on frequency deviation information obtained by performing signal processing on the phase comparison output input from the phase comparator. The clock data recovery circuit according to claim 1.
3 . 前記周波数偏差情報は、 前記位相比較器からの位相比較出力である U P Z D OWN信号の平均値から得られることを特徴とする請求項 2に記載のクロッ ク ·データ再生回路。 3. The clock data reproduction circuit according to claim 2, wherein the frequency deviation information is obtained from an average value of the UP Z D OWN signal which is a phase comparison output from the phase comparator.
4 . 前記位相比較器は、 前記再生クロックと入力信号との位相差を検出する位 相比較器、 又は前記再生ク口ックと入力信号との位相差及び周波数差を検出する 位相周波数比較器のいずれかであることを特徴とする請求項 1乃至 3のいずれか に記載のクロック 'データ再生回路。 4. The phase comparator detects a phase difference between the reproduction clock and the input signal, or detects a phase difference and a frequency difference between the reproduction clock and the input signal. 4. The clock data recovery circuit according to claim 1, wherein the clock data recovery circuit is any one of the above.
5 . 前記通倍クロックと入力信号とを入力とし、 両者の周波数差を検出する周 波数比較器をさらに備え、 前記周波数比較器からの出力を用いて非整数遁倍回路 の遞倍比を調整することを特徴とする請求項 1に記載のクロック 'データ再生回 路。 5. A frequency comparator for detecting the frequency difference between the double clock and the input signal is further provided, and the multiplication ratio of the non-integer multiplication circuit is adjusted using the output from the frequency comparator. 2. The clock data recovery circuit according to claim 1, wherein:
6 . 入力信号に同期するように再生ク口ックの位相を可変して最適な識別位相 とするクロック 'データ再生方法であって、 前記入力信号と内部生成したクロッ クの位相とを比較することで得られた周波数偏差情報に基づいて、 非整数遁倍回 路が遁倍クロックを出力する第 1の位相調整ステツプと、 前記入力信号と再生ク ロックの位相とを比較することで得られた位相差情報に基づいて、 前記入力信号 と再生クロックの位相とを一致させるように前記再生クロックの位相を可変する 第 2の位相調整ステップと、 を有することを特徴とするクロック ·データ再生方 法。 6. Clock that changes the phase of the playback clock to synchronize with the input signal so as to obtain the optimum identification phase. This is a data recovery method that compares the phase of the input signal with the internally generated clock. Based on the obtained frequency deviation information, the first integer phase adjustment step in which the non-integer multiplication circuit outputs a multiplication clock is compared with the phase of the input signal and the reproduction clock. And a second phase adjustment step of varying the phase of the recovered clock so that the phase of the input signal and the recovered clock are matched based on the phase difference information. Law.
7 . 前記第 1の位相調整ステップにおいて、 位相比較器が前記入力信号と再生 クロックとの位相差を検出した位相比較出力を出力し、 前記位相比較出力から算 出した周波数偏差情報に基づいて前記非整数通倍回路の通倍比を調整することを 特徴とする請求項 6に記載のクロック ·データ再生方法。 7. In the first phase adjustment step, a phase comparator outputs a phase comparison output in which a phase difference between the input signal and the reproduction clock is detected, and based on the frequency deviation information calculated from the phase comparison output 7. The clock data recovery method according to claim 6, wherein a multiplication ratio of the non-integer multiplication circuit is adjusted.
8 . 前記第 1の位相調整ステップにおいて、 位相周波数比較器が前記入力信号 と再生クロックとの位相差及び周波数差を検出した位相比較出力を出力し、 前記 位相比較出力の周波数差から算出した周波数偏差情報に基づいて前記非整数通倍 回路の遁倍比を調整することを特徴とする請求項 6に記載のクロック ·データ再 生方法。 8. In the first phase adjustment step, a phase frequency comparator outputs a phase comparison output in which a phase difference and a frequency difference between the input signal and the recovered clock are detected, and a frequency calculated from the frequency difference of the phase comparison output 7. The clock data reproduction method according to claim 6, wherein a multiplication ratio of the non-integer multiplication circuit is adjusted based on deviation information.
9 . 前記第 1の位相調整ステップにおいて、 周波数比較器が前記入力信号と遁 倍クロックとを比較した周波数偏差情報を出力し、 前記周波数偏差情報に基づい て前記非整数通倍回路の遁倍比を調整することを特徴とする請求項 6に記载のク ロック ，データ再生方法。 9. In the first phase adjustment step, a frequency comparator outputs frequency deviation information comparing the input signal and the multiplication clock, and based on the frequency deviation information, the multiplication ratio of the non-integer multiplication circuit The clock and data reproduction method according to claim 6, wherein the clock is adjusted.
PCT/JP2009/052002 2008-02-12 2009-01-30 Clock data reproduction circuit WO2009101897A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425809B2 (en) 2015-01-08 2016-08-23 Kabushiki Kaisha Toshiba Local oscillator

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