WO2009093154A1

WO2009093154A1 - Automatic gain control in a radio receiver circuit, and related interface

Info

Publication number: WO2009093154A1
Application number: PCT/IB2009/050140
Authority: WO
Inventors: Andreas Bury
Original assignee: Nxp B.V.
Priority date: 2008-01-22
Filing date: 2009-01-15
Publication date: 2009-07-30

Abstract

A demodulator for reception of radio signals consists of an analog radio receiver and a digital demodulator. Due to limited dynamic range of signals, automatic gain control is provided in the analog radio receiver that may however result in a degradation of reception quality due to inappropriately timed gain changes. The invention contemplates to assign the task of defining an optimized gain to the analog radio receiver and to assign the task of selecting the point in time when a gain update is initiated to the digital demodulator to mitigate degradation of reception quality due to gain changes, which are particularly present under mobile reception conditions. Thus, an essentially self-contained automatic gain control in a radio receiver circuit and an associated control interface between analog radio receiver and digital demodulator is provided which allows stand-alone testing of these circuits.

Description

AUTOMATIC GAIN CONTROL IN A RADIO RECEIVER CIRCUIT, AND RELATED INTERFACE

FIELD OF THE INVENTION

The present invention relates to radio receiver circuits and methods for performing automatic gain control in such receivers. The invention further relates to automatic gain control in a receiver circuit interfaced to a digital decoder circuit. More specifically, the invention relates to circuits arrangements and methods of automatic gain control in an Orthogonal Frequency Division Multiplexing (OFDM) receiver/demodulator.

BACKGROUND OF THE INVENTION

There is a recent trend in the mobile telephone market towards the mobile phone becoming 'the' mobile device per se, as more and more functionality is put on the application processor. The complexity of the digital functionality in a mobile phone increases tremendously, calling for larger and larger integration scale. New technology nodes of very large scale integrated CMOS allow to squeeze the same digital functionality onto an even smaller silicon area, or to increase the amount of digital functionality on the same area. In contrast, analog functionality like in radio transmitters and receivers does not scale in the same way, since it is dominated by the space needed for passive components rather than the transistors of digital standard cells. Production mask costs increase roughly inversely proportional to the silicon feature size, which imposes a high financial risk on producing a set of masks if the production volume turns out to become significantly smaller than forecasted. Test costs for analog and mixed-signal testing increase as compared to plain digital testing.

The above considerations suggest a system partitioning such that all analog functionality of a radio transceiver on one hand and all digital functionality of the application processor on the other hand are implemented on separate silicon dies. The application processor is manufactured in a technology with the smallest state-of the art feature size (e.g., CMOS 045) for lowest silicon costs at a very high volume production, and the radio transceiver is implemented in a mature technology offering a good ratio of mask cost versus production cost of silicon dies (e.g., CMOS 12). With this partitioning of functionality split to a radio transceiver' s analog and mixed- signal functionality on one silicon die and plain digital functionality of the application processor on another silicon die, the interface between those two silicon circuits is plain digital. In order to minimize pin count, a high speed serial interface becomes a likely choice, and industry effort is spent to standardize high speed digital interfaces for radio transceivers. Examples are the DigRF interface standard or the MIPI standard, for more details see http://www.mipi.org/. To minimize power consumption a further goal is to minimize the amount of information exchanged over this interface. Putting all analog functionality onto one silicon die offers the opportunity to factory-calibrate single dies without dependencies of external circuitry. This suggests building a self-contained circuit that allows simple integration with the digital demodulator. Thus, this system partitioning also provides for independent development of analog and digital circuitry on multiple sites of a company. Orthogonal frequency division multiplexing (OFDM) is a radio transmission scheme which is gaining more and more popularity. Due to its potential for low complexity receiver implementation, it has been adopted for many transmission standards supporting high data rates above 5 Mbps. In OFDM, the transmitted signal has a block structure, and the receiver periodically discards unused signal portions between such blocks. This may be exploited to optimize the demodulator performance in a continuous reception where the receive conditions change over time.

A receiver for radio signals consists of an analog radio frequency receiver circuit and a digital demodulator. Due to limited dynamic range of signals, means for gain control are provided in the analog radio receiver. A typical example of a prior art autonomous automatic gain control (AGC) for radio signals in an analog radio receiver is shown in Fig. 1.

An analog radio receiver 100 comprises a free-running AGC control loop, including a receive signal strength indicator (RSSI) unit 120 which measures the level of a received signal at one of several possible nodes in a down conversion chain 110. The RSSI level is compared with a target level by a target comparison unit 130, and depending on the current situation the gain is either increased or decreased or kept constant by a gain selection unit 140, with the aim of reaching the AGC target level at the measurement node. Multiple independent control loops are possible. However, the architecture described above has several disadvantages. If an analog radio receiver running a fully autonomous automatic gain control is interfaced with a digital demodulator 150, e.g. an OFDM demodulator, the reception quality may be degraded due to

- transients caused by gain jumps, which distort the received signal;

- a discontinuity of the gain between antenna and demodulated signal, which may affect any kind of algorithm exploiting signal portions extended in time.

These problems become particularly severe in a mobile environment, e.g., with a mobile phone receiver.

To overcome the above problems there has already been proposed a circuit arrangement wherein automatic gain control (AGC) is incorporated in the digital demodulator. An exemplary implementation of such architecture is shown in Fig. 2. Components similar or equivalent to those of Fig. 1 are designated with equivalent reference numerals, the last two digits thereof being the same as that of Fig. 1. Here digital demodulator 250 reads the output of receive signal strength indicator unit 220 as a basis for gain selection. Digital demodulator 250 has full control over the point in time when the gain is set, and there is a large degree of freedom in the algorithm selected for gain control. In a modification to the diagram of Fig. 2 RSSI unit 220 may be part of digital demodulator 250. However, the architecture of Fig. 2 has the following drawbacks. Digital demodulator 250 may require a gain table associated with the gain codes that select certain gains. Values in this table may require calibration. Production testing of the automatic gain control loop requires the combined systems of analog radio receiver and digital demodulator; it cannot be easily performed on a stand-alone basis for each of the silicon dies of the radio receiver and of digital demodulator, respectively.

Another problem in receiver circuits may arise when RSSI measurement is performed within a period when signal strength is down due to a momentary interruption of transmission which may lead to an erroneous signal strength indication entailing an inappropriate gain setting. Therefore, a general object of the invention is to provide a RF receiver/Baseband demodulator circuitry wherein degradation of reception quality due to gain changes, particularly under mobile reception conditions, is reduced. A particular object of the invention is to provide automatic gain control in an analog radio receiver that is not susceptible to gain jumps and gain discontinuity, while maintaining a self-contained architecture for both analog radio receiver and digital demodulator circuits that allows standalone testing of these circuits. A further more particular object of the invention is to prevent erroneous signal strength indications that could entail inappropriate gain settings in performing automatic gain control in an analog radio receiver.

SUMMARY OF THE INVENTION

According to an aspect of the present invention there is provided a radio receiver circuit arrangement with automatic gain control according to claim 1. According to another aspect of the present invention there is provided an analogue radio transceiver in accordance with claim 15. According to a further aspect of the present invention there is provided an OFDM receiver as claimed in claim 16. According to a still further aspect of the present invention there is provided a method for performing automatic gain control in a radio receiver circuit arrangement according to claim 24. According to another aspect of the present invention there is provided a method for performing automatic gain control in a radio receiver circuit of an OFDM receiver claimed in claim 31.

By assigning the task of defining an optimized gain to the analog radio receiver and assigning the task of selecting the point in time when a gain update is initiated to the digital demodulator, and communicating a set gain value from the analog radio receiver to the digital demodulator, as contemplated by the inventive receiver and method, degradation of reception quality due to gain changes is mitigated significantly.

The invention is particularly applicable in conjunction with high performance OFDM demodulators, but also in other modulation schemes.

BRIEF DESCRIPTION OF THE DRAWINGS Additional features and advantages of the present invention will be apparent from the following detailed description of specific embodiments which are given by way of example and in which reference will be made to the accompanying drawings, wherein:

Fig. 1 is a schematic block diagram of a known implementation of an RF receiver/baseband demodulator circuit; Fig. 2 is a schematic block diagram of another known RF receiver/baseband demodulator circuit;

Fig. 3 is a schematic block diagram of a RF receiver/baseband demodulator circuit incorporating automatic gain control according to an embodiment of the present invention; Fig. 4 is a schematic block diagram of a RF receiver/baseband demodulator circuit incorporating automatic gain control according to another embodiment of the present invention;

Fig. 5 is a schematic block diagram of a RF receiver/baseband demodulator circuit similar to Fig. 4 illustrating a specific embodiment of the demodulator in greater detail;

Fig. 6 is a schematic diagram illustrating the principle of gain switching in accordance with the invention;

Fig. 7 is a schematic diagram illustrating the effect of automatic gain control according to an aspect of the present invention;

Fig. 8 is a schematic block diagram of a RF receiver/baseband demodulator circuit according to the invention illustrating in greater detail an embodiment including an analog interface between analog radio receiver and digital demodulator;

Fig. 9 is a schematic block diagram of a RF receiver/baseband demodulator circuit according to the invention illustrating in greater detail an embodiment including a digital analog interface between analog radio receiver and digital demodulator;

Fig. 10 illustrates the RF receiver/baseband demodulator circuit with digital interface of Fig. 9 embedded in a complete analog radio transceiver/digital modem circuit with full digital interface; and Fig. 11 shows communication sequences between the analog radio receiver and the digital demodulator according to an implementation example of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Specific exemplary embodiments of the invention are illustrated in Figs. 3 to 5 and 8 to 10 which may be employed separately or in combination to implement the different aspects of the invention. Throughout the accompanying drawings the same or equivalent components are designated with equivalent reference numerals, the last two digits thereof being the same for similar or equivalent elements. To illustrate a general aspect of the present invention Fig. 3 shows a simplified schematic block diagram of a RF receiver/baseband demodulator circuit incorporating automatic gain control according to the invention. An analog radio receiver 300 comprises a receive signal strength indicator (RSSI) unit 320 for measuring the current signal level, and means to derive a more appropriate gain setting based upon the determined RSSI level. This is handled in a target comparison unit 330 and a gain selection unit 340. Target comparison unit 330 compares the determined RSSI level with a target level and supplies an up/down indication to gain selection unit 340 which sets a new gain in down conversion chain 310.

In a modified implementation, as illustrated in Fig. 4, target comparison unit is omitted and a new optimized gain value is directly computed by gain selection unit 440.

To the extend so far described analog radio receivers 300 and 400 are similar to receiver 100 of Fig. 1. However, in contrary to Fig. 1 automatic gain control is not performed autonomously but is triggered by an entity external to analog radio receiver circuit, e.g. digital demodulators 350 and 450 in Figs. 3 and 4, respectively. In a production test environment the external entity could be an auxiliary test circuit, e.g., allowing to test analog radio receiver circuit independently from digital demodulator circuit. As can be seen in Figs. 3 and 4, analog radio receiver circuits 300 and 400 additionally comprise two interfaces adapted to receive trigger signals from and supply computed gain values to the external entity, respectively. Interfaces 344, 444 of analog radio receivers 300 and 400, respectively, receive a control signal from a respective digital demodulator 350, 450 initiating a new gain setting based upon an RSSI value. Alternatively, not the point in time when gain is set may be controlled, but rather the point in time when the computation of the new gain setting is started. Interfaces 342, 442 of analog radio receiver 300 and 400, respectively, comprise means to provide the current gain value to digital baseband demodulators 350 and 450, respectively. Gain values may be provided in form of a gain code unambiguously representing the respective gain values. By assigning the task of defining an optimized gain to the analog radio receiver and assigning the task of selecting the point in time when a gain update is initiated to the digital demodulator, and communicating a set gain value from the analog radio receiver to the digital demodulator, as contemplated by the inventive receiver and method, degradation of reception quality due to gain changes can be mitigated significantly. Digital demodulators 350, 450 employ the supplied gain values for example in the time interpolation part of channel estimation algorithm which will be explained in further detail with reference to Fig. 5.

Shortly stated, according to the proposed embodiments of the invention, described above, digital baseband demodulators 350, 450 control the points in time when the gain is set, and analog radio receivers control selection of an appropriate gain value, which may be made available to the digital baseband demodulators. For this arrangement we coin the term 'Assisted autonomous AGC, or shortly 'Assisted AGC, in contrast to the 'autonomous AGC of Fig. 1.

To permit a thorough understanding of the invention a particular implementation of assisted AGC in accordance with the invention will be discussed in conjunction with an exemplary embodiment of a receiver for OFDM (orthogonal frequency division multiplexing) modulated signals. As shown in Fig. 5, OFDM receiver comprises an analog radio receiver 500 and a digital demodulator 550. Radio receiver 500 receives a RF signal, down-converts the signal and supplies a baseband receive signal to digital demodulator 550. In OFDM transmission the demodulator typically discards a fraction of each time-domain OFDM symbol, wherein the length of the discarded portion corresponds to the duration of the cyclic repetition which had been inserted at the modulator. This is performed in guard interval removal unit 562 of Fig. 5. The signal fractions discarded by the digital demodulator, i.e., the guard intervals, of a receive signal are illustrated in Fig. 6 by II, 12, 13. Then, a Discrete Fourier Transform (DFT) is performed on each remainder of the signal blocks. DFT is typically implemented as a Fast Fourier Transform (FFT) in a FFT unit 564. The signal portions used by the digital demodulator, i.e. the FFT input blocks, are illustrated in Fig. 6 and designated Sl, ..., S4.

As stated above, signal sections between FFT blocks are discarded as guard intervals. If the analog radio front-end gain is switched directly after an FFT block has been extracted, a possible switching transient falls into the discarded signal portion and does not affect demodulation of the next FFT block. This is illustrated in Fig. 6. Digital demodulator 550 sends gain set control signals to analog radio receiver 500 which are aligned in time such that gain changes are performed only at the beginning of a discarded signal portion. This allows any gain switching transient to be decayed before the next used signal portion, i.e., the next FFT input vector.

Each time, digital demodulator 550 initiates a gain adaptation by means of assisted AGC the analog radio receiver supplies the most recent gain value to a gain compensation unit 566 in digital demodulator 550. This enables the digital demodulator to compensate for respective gain values of corresponding signal portions, allowing to implement algorithms operating across multiple OFDM symbols in the time direction, when the relative amplitude of respective OFDM symbols is important for the algorithm to function. An example for such an algorithm is channel estimation performed in channel estimation unit 567 of Fig. 5, employing filtering in time direction across multiple OFDM symbols. In Fig. 5, gain compensation is performed directly after FFT. Alternatively, gain compensation may be performed before the FFT, or in channel estimation unit 567 and/or equalization unit 568.

Furthermore, if the digital demodulator knows the radio front-end gain setting associated with an FFT block, exact time interpolation of, e.g., the channel estimate can be computed across multiple successive FFT blocks, even if the gain has been changed between successive blocks. Fig. 7 illustrates the operation of AGC and gain compensation in a case where the compensation is implemented before FFT. In this example the signal level at the antenna is continuously increasing. Discarded signal portions and used parts (FFT input blocks) are shown. The used signal portions are designated Sn, ..., Sn+3. Gain switching occurs during unused signal portions, as explained above with reference to Fig. 6. Due to the effect of assisted automatic gain control the signal level after the AGC, i.e. the baseband receive signal in Fig. 5, changes significantly less compared to the antenna input. Respective gain values are used in the digital demodulator to compute the compensated signal. This compensation is only performed for the used signal portions. The compensated signal has the same amplitude shape as the signal at the antenna input.

To provide the functionality explained above, interfaces as discussed in relation to Figs. 3 and 4 are provided in similar manner in the embodiments of analog radio receivers detailed in Figs. 5 and 8-10, as will be described below. Those interfaces may be implemented as dedicated interfaces similar to interfaces 344, 444 and 342, 442 in Figs. 3 and 4, respectively, or via connections merged within a common control interface of the analog radio receiver. In Figs. 5 and 8 - 10 such interfaces are not explicitly shown, rather, the signal flow between analog radio receiver and digital demodulator is illustrated by arrow between those components, for the sake of simplicity of the illustration. Fig. 8 shows a RF receiver/baseband demodulator circuit illustrating in greater detail a receiver chain with assisted autonomous AGC according to the invention. This embodiment includes an analog interface between analog radio receiver and digital demodulator, i.e. analog radio receiver 800 feeds an analog I/Q baseband signal to digital demodulator 850. In another embodiment, analog radio receiver 800 may feed an analog intermediate frequency (IF) signal to digital demodulator 850. Analog radio receiver 800 comprises an input band-pass filter 811 at radio frequency followed by a low noise amplifier (LNA) 812 with adjustable gain, a subsequent mixer 813 which operates using a local oscillator (LO) 814 output signal, an analog low-pass filter 815, which is, on a silicon circuit, typically realized as an active filter, and a variable gain amplifier (VGA) 816. It should be noted, that in case of an I/Q interface between analog radio receiver 800 and digital demodulator 850, since the output signal from the analog radio receiver 800 represents a complex signal composed of a real and an imaginary part, each of components 813 to 816 of the down converter chain, illustrated in Fig. 8, are intended to represent a pair of such components for processing the real and the imaginary parts, respectively. Two receive signal strength indicators (RSSI), one, 822, measuring the LNA output signal, and the other, 824, measuring the VGA output signal, supply their signal strengths measurements to a gain selection unit 840. Gain selection is triggered by digital demodulator 850 via a dedicated control signal or control command. As stated above, this signal may be received by gain selection unit 840 via a dedicated interface similar to interfaces 344, 444 as exemplified in Figs. 3 and 4, or via an interface merged in a common control interface of the analog radio receiver. Gain selection unit 840 sets the gain of both the LNA and the VGA. Gain selection unit 840 also communicates the selected gain value to the digital demodulator via a dedicated interface. Gain selection unit 840 may me implemented in hard-wired logic or in a dedicated microcontroller or a combination thereof. Modifications of the embodiment shown in Fig. 8 will readily suggest themselves to persons skilled in the art. For example, RSSI measurements may be taken at one or more additional points of down conversion chain 811- 816. Gain may be set at one stage or distributed across multiple gain stages. Further, each AGC step may be computed differentially or as an absolute value. In Fig. 8, this control signal is designated "gain-set timing". Alternatively, not the point in time when gain is set may be controlled, but rather the point in time when computation of a new optimized gain is initiated.

Fig. 9 is similar to Fig. 8, except that A/D conversion and subsequent digital filtering and digital gain control form part of analog radio receiver 900, as illustrated by components 917 - 919, and analog radio receiver 900 feeds a digital signal to digital demodulator 950. As already set forth in relation to Fig. 8, in case of an I/Q interface between analog radio receiver 900 and digital demodulator 950, devices 913 to 919 actually consist of a pair of such devices for processing the real and the imaginary parts, respectively, of the complex signal. A further RSSI unit 926 has been added, which measures the level of the digital output signal. Implementation alternatives similar to those discussed above in conjunction with Fig. 8 may be employed, i.e. RSSI measurements may be taken at one or more additional points of down conversion chain 911-919; gain may be set at one stage or distributed across multiple gain stages; and each AGC step may be computed differentially or as an absolute value. As in Fig. 8, gain selection is triggered by digital demodulator 950 via a dedicated control signal that may be received by gain selection unit 940 via a dedicated interface similar to interfaces 344, 444 as exemplified in Figs. 3 and 4, or via an interface merged in a common control interface which in this case would be a full digital interface. As stated above, this signal controls the point in time when gain is set or computation of a new optimized gain is initiated.

In a further modification of the embodiments explained above, the time of RSSI measurement in components 320, 420, 520, 822, 824, 922, 924, and 926 optionally may be controlled by an additional timing signal from the digital demodulator, as exemplified in the drawings by arrows "RSSI timing" in Figs. 5, 8 and 9. In this way, erroneous signal strength indications resulting from RSSI measurements being taken within a period when signal strength is down due to a momentary interruption of transmission may be prevented from entailing inappropriate gain settings.

Fig. 10 shows how such an analog radio receiver 900 with all-digital interface may be embedded into a complete analog radio transceiver with digital interface. All data communication between analog radio transceiver 1000 and digital modem 1050 is exchanged via a single digital interface 1040, which is typically implemented as a high speed bidirectional serial interface. All communication between analog radio receiver 900 and digital demodulator 950 as described above with reference to Fig. 9 is handled via this common interface, multiplexed with the communication between digital modulator and analog radio transmitter. In addition to the receive signal and AGC related control signals further control information may be sent via this interface. Such a high speed digital serial interface has been developed by the DigRF working group of the MIPI Alliance.

Fig. 11 shows six different communication exchange sequences between a digital demodulator and an analog radio receiver which could be implemented to support an assisted autonomous AGC in accordance with the invention. This set of messages is based on the assumption that the analog radio receiver supports two modes, a free-running autonomous AGC as exemplified in Fig. 1 and the assisted autonomous AGC according the invention as illustrated in Figs. 3 - 5 and 8 - 10. Messages 1 and 3 in this list allow to switch back and forth between these two modes, message 2 allows to read the current gain value, message 4 is provided to initiate a RSSI measurement, message 5 is defined to initiate an autonomous gain adaptation step, and message 6 combines messages 2 and 5 to initiate an autonomous gain adaptation step and afterwards read the updated gain value.

Claims

CLAIMS:

1. A radio receiver circuit arrangement with automatic gain control, comprising a down conversion chain (310; 410; 510; 811-816; 911-919), means (320; 420; 520; 822, 824; 922, 924, 926) for identifying a signal strength of a receive signal, means (330, 340; 440; 540; 840; 940) for selecting an optimized gain value based on the determined signal strength, and means for setting a gain (812, 816; 912, 916, 919) in said down conversion chain of the receiver circuit, the circuit arrangement being characterized in that it further comprises means (342, 344) adapted to receive a time control signal from an entity (350; 450; 550: 562; 850; 950) external to the radio receiver circuit, wherein said gain selection means are responsive to said signal for initiating a gain updating process employed in automatic gain control of the receiver circuit.

2. The circuit arrangement according to claim 1, wherein said external entity comprises a digital demodulator circuit (350; 450; 550; 850; 950).

3. The circuit arrangement according to claim 1, wherein said external entity comprises an auxiliary test circuit for testing the radio receiver circuit arrangement.

4. The circuit arrangement according to any of claims 1 to 3, further comprising means (342; 442) adapted to provide an indication for a most recent gain value derived from said gain selection means to said entity (350; 450; 550: 566; 850; 950) external to the radio receiver circuit.

5. The circuit arrangement according to claim 4, wherein said gain value indication is provided by means of a unique one-to-one mapping of gain values to code values.

6. The circuit arrangement according to any of claims 1 to 5, further comprising means in said signal strength identifying means responsive to a timing signal received from said external entity, for initiating a signal strength identifying process employed in automatic gain control of the receiver circuit.

7. The circuit arrangement according to any of the preceding claims, wherein said means (342, 344) for receiving a time control signal for initiating a gain update comprises a dedicated digital interface connectable to said external entity, and wherein gain updating is initiated by a change in logic level of the signal.

8. The circuit arrangement according to any of the preceding claims, further comprising means for analog-to-digital conversion (917) of the down-converted signal.

9. The circuit arrangement according to claim 8, further comprising means (918) for digitally filtering the output signal of the analog-to-digital conversion.

10. The circuit arrangement according to claims 8 and 9, further comprising means (919) for digital gain control.

11. The circuit arrangement according to claims 8 to 10, further comprising means

(926) for identifying signal strength of the digital receive signal.

12. The circuit arrangement according to any of the preceding claims, wherein signal strength is identified at one or more points (822, 824; 922, 924, 926) in the analog and/or digital down conversion chain, and each determined signal strength value is fed to said gain selecting means (330, 340; 440; 540; 840; 940).

13. The circuit arrangement according to any of the preceding claims, wherein said means for gain setting are distributed within down conversion chain (310; 410; 510; 811 -816; 911 -919), comprising a plurality of amplifiers with adjustable gain, and each of said amplifiers is controlled by said gain selecting means (330, 340; 440; 540; 840; 940).

14. The circuit arrangement according to any of claims 8 to 13, comprising a single digital interface (1040) connectable to an external entity, for communicating both signal and AGC related control information from and to said external entity.

15. An analog radio transceiver, comprising a radio receiver circuit arrangement according to any of claims 8 to 14, further comprising an analog radio transmitter circuit, and a single digital interface (1040) connectable to a digital modulator/demodulator (1050), over which said AGC related control signals are communicated.

16. An OFDM receiver, comprising a radio receiver circuit arrangement according to any of the preceding claims, and a digital demodulator (350; 450; 550; 850; 950) receiving a baseband receive signal from said radio receiver circuit arrangement for processing the same to output demodulated data, said digital demodulator comprising: means (562) for removing a guard interval from the baseband receive signal, means (564) for performing a Fast Fourier Transform (FFT) on the remainder of the baseband receive signal, gain compensation means (566), channel estimation means (567) and equalization means (568); wherein said guard interval removing means (562) are adapted to supply, in function of the timing of the discarded guard intervals, a gain update control signal to analog radio receiver, for initiating gain updating to be employed in automatic gain control in analog radio receiver.

17. The OFDM receiver according to claim 16, wherein said gain selection means (562) of digital demodulator further are adapted to supply, in function of the timing of the discarded guard intervals, a RSSI timing signal to analog radio receiver, for initiating signal strength identification that is to be employed in automatic gain control in analog radio receiver.

18. The OFDM receiver according to claim 16 or claim 17, wherein said gain selecting means (330, 340; 440; 540; 840; 940) of analog radio receiver are adapted to provide an indication representing a most recently updated optimized gain value to said gain compensation means (566) of digital modulator.

19. The OFDM receiver according to claim 18, wherein said gain compensation means (566) are provided upstream FFT means (564).

20. The OFDM receiver according to claim 18, wherein said gain compensation means (566) are provided downstream FFT means (564).

21. The OFDM receiver according to claim 18, wherein said gain compensation means (566) are incorporated in channel estimation means (567).

22. The OFDM receiver according to claim 18, wherein said gain compensation means (566) are incorporated in equalization means (568).

23. An OFDM transceiver comprising an OFDM receiver according to any of claims 16 to 22.

24. A method for performing automatic gain control in a radio receiver circuit arrangement (300; 400; 500; 800; 900) comprising the steps of identifying a signal strength of a receive signal, selecting an optimized gain value based on the determined signal strength, and setting a gain in a down conversion chain of said receiver circuit, the method being characterized in that it further comprises the steps of receiving a time control signal from an entity external to the radio receiver circuit, and initiating, in response to said time control signal, gain updating in the automatic gain control process of the receiver circuit.

25. The method according to claim 24, wherein said external entity comprises a digital demodulator circuit (350; 450; 550; 850; 950).

26. The method according to claim 24, wherein said external entity comprises an auxiliary test circuit for testing the radio receiver circuit arrangement.

27. The method according to any of claims 24 to 26, wherein said time control signal for initiating a gain update initiates recalculation of an optimized gain value.

28. The method according to any of claims 24 to 26, wherein said time control signal for initiating a gain update initiates setting a currently optimized gain value in said down converter chain of the receiver circuit.

29. The method according to any of claims 24 to 28, further comprising the step of providing an indication for a most recently updated gain value to said entity (350; 450; 550: 566; 850; 950) external to the radio receiver circuit.

30. The method according to claim 24 to 29, further comprising the steps of receiving a timing signal from said external entity, and initiating, in response to said time control signal, a signal strength identifying process to be used for automatic gain control of the receiver circuit.

31. The method according to any of claims 24 to 30, wherein said time control signal for initiating a gain update is received over a dedicated digital interface connectable to said external entity, and wherein gain updating is initiated by a change in the logic level of the signal.

32. The method according to any of claims 24 to 30, wherein said AGC related control signals are communicated to and from radio receiver circuit arrangement via a single digital interface together with a data signal.

33. A method for performing automatic gain control in a radio receiver circuit arrangement of an OFDM receiver which comprises said radio receiver circuit arrangement for down converting a RF receive signal and supplying it to a digital demodulator for demodulating the signal to output demodulated data, the method comprising the steps of identifying a signal strength of a receive signal, selecting an optimized gain value based on the determined signal strength, and setting a gain in a down conversion chain of said receiver circuit, the method being characterized in that it further comprises the step of initiating a gain update to be employed in automatic gain control in said radio receiver circuit in function of the timing of guard intervals of the baseband receive signal that are discarded in digital demodulator, said initiation being triggered by means of a gain update control signal that is provided by the digital demodulator to the analog radio receiver.

34. The method according to claim 33, further comprising the step of initiating signal strength identification to be employed in automatic gain control in analog radio receiver by supplying, in function of the timing of the discarded guard intervals, a RSSI timing control signal from digital demodulator to analog radio receiver.

35. The method according to claim 33 or claim 34, further comprising the step of providing an indication representing a most recently updated optimized gain value from analog radio receiver to digital demodulator, for gain compensation within digital demodulator.