WO2009086778A1 - Rate adapting method and apparatus, exchange board and line card - Google Patents

Rate adapting method and apparatus, exchange board and line card Download PDF

Info

Publication number
WO2009086778A1
WO2009086778A1 PCT/CN2008/073804 CN2008073804W WO2009086778A1 WO 2009086778 A1 WO2009086778 A1 WO 2009086778A1 CN 2008073804 W CN2008073804 W CN 2008073804W WO 2009086778 A1 WO2009086778 A1 WO 2009086778A1
Authority
WO
WIPO (PCT)
Prior art keywords
multiplexed signal
multiplexing
parallel data
module
cell
Prior art date
Application number
PCT/CN2008/073804
Other languages
French (fr)
Chinese (zh)
Inventor
Xiaodong Li
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2009086778A1 publication Critical patent/WO2009086778A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction

Definitions

  • Rate adaptation method and device, switch board and line card The application is submitted to the Chinese Patent Office on December 29, 2007, and the application number is 200710306070.x, and the invention name is "rate adaptation method and device, switch board and The priority of the Chinese Patent Application for Line Cards, the entire contents of which is incorporated herein by reference.
  • the present invention relates to the field of packet switching, and in particular, to a method and device for rate adaptation, a switch board and a line card.
  • Circuit switching refers to the fact that when a computer terminal communicates, one party initiates a call and monopolizes a physical line. When the switch completes the connection, the other party receives the signal from the initiator, and the two parties can communicate.
  • the circuit is occupied by both parties throughout the communication process. It is characterized by strong real-time performance, low latency, and low switching equipment costs. However, it also has the disadvantages of low line utilization, long circuit connection time, low communication efficiency, and inability to communicate between different types of end users. Circuit switching is more suitable for communication between fixed users who use large amounts of information, long messages, and frequently used. Packet switching is essentially based on "storage one-to-one forwarding".
  • Packet switching uses dynamic multiplexing techniques on the line to transmit data that is divided into a number of small segments by a certain length. After each packet is identified, a dynamic multiplexing technique is employed on one physical line to simultaneously transmit multiple data packets. The data from the user's origin is temporarily stored in the memory of the switch, and then forwarded in the network. After reaching the receiving end, the packet header is removed, and the data fields are reassembled into complete messages in order. Packet switching is more efficient than circuit switched circuits.
  • the fixed-length packet cell switching network mainly adopts the MCM architecture, the intermediate level is a Switching Crossbar chip (SC), and the two sides are a shared switching chip (SM), which needs to be
  • SC Switching Crossbar chip
  • SM shared switching chip
  • multiple inputs may compete for one output at the same time, that is, there is competition between the input and output, and an arbitration algorithm is required to schedule the cells.
  • the SC After being scheduled by the arbitration algorithm, the SC returns a grant signal to the SM. After receiving the grant signal, the SM, after receiving the grant signal, sends the cell to the SC, and the SC exchanges it.
  • the SC After receiving the grant signal, the SM, after receiving the grant signal, sends the cell to the SC, and the SC exchanges it.
  • the SM in the existing packet switching device, the SM is placed on a circuit board (also referred to as a line card), and the SC is placed on the switch board, and the switch board completes the exchange of cells on each circuit board. .
  • the signals on the left board 0 to 15 are the signals to be sent. After switching through the switch boards 0 to 3, they are output to the right board 0 to 15, and are output accordingly. Out to other communication devices.
  • the bus in the packet switching device is globally set, and the entire device is unified to a rate, such as 3.125 Gb/s or
  • the embodiment of the invention provides a method and device for rate adaptation, a switch board and a line card.
  • the technical solution is as follows:
  • an embodiment of the present invention provides a method for rate adaptation, where the method includes:
  • the embodiment of the present invention further provides a switchboard, where the switchboard includes:
  • a receiving module configured to receive a multiplexed signal of a to-be-transmitted cell from the line card, where the plurality of cell headers carry a multiplexing sequence identifier;
  • a conversion module configured to perform serial-to-parallel conversion on the multiplexed signal received by the receiving module according to the pre-stored multiplexing sequence identifier to obtain parallel data
  • a switching module configured to exchange and output parallel data obtained by the conversion module.
  • the embodiment of the present invention further provides a line card, where the line card includes:
  • a multiplexing module configured to multiplex a plurality of to-be-transmitted cells to obtain a multiplexed signal, and add a multiplexing sequence identifier to the plurality of cell headers in the multiplexed signal according to a multiplexing sequence;
  • a sending module configured to send the multiplexed signal obtained by the multiplexing module.
  • an embodiment of the present invention further provides a rate adaptation device, where the device includes:
  • a line card configured to send a multiplexed signal of a cell to be transmitted, where a plurality of cell headers of the multiplexed signal carry a multiplexing sequence identifier
  • a switching board configured to receive a multiplexed signal sent by the line card, and according to the pre-stored multiplexing sequence identifier, to be shifted
  • the method performs serial-to-parallel conversion on the multiplexed signals to obtain parallel data, and then separately exchanges and outputs the parallel data.
  • the received multiplexed signals are serial-to-parallel converted in a shifting manner to obtain parallel data with accurate position, thereby realizing the docking of the low-speed bus line card and the high-speed bus switching board, and improving the line card and the switching board.
  • the compatibility enables existing lower-rate bus line cards to be applied to systems with higher-rate buses, effectively utilizing existing resources, and saving the cost of subsequent development.
  • FIG. 1 is a schematic structural diagram of a packet switching device in the prior art
  • FIG. 3 is a schematic diagram of multiplexing multiple signals to be transmitted according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of serial-to-parallel conversion of a multiplexed signal in a shift mode according to Embodiment 1 of the present invention
  • FIG. 5 is a serial-to-parallel conversion and exchange of a plurality of multiplexed signals by a switch board according to Embodiment 1 of the present invention
  • Figure 6 is a structural diagram of a switchboard according to Embodiment 2 of the present invention
  • FIG. 7 is a structural diagram of a line card according to Embodiment 3 of the present invention.
  • FIG. 8 is a structural diagram of a device for rate adaptation according to Embodiment 4 of the present invention. detailed description
  • the method for rate adaptation specifically includes: receiving a multiplexed signal from a line card, where a plurality of cell headers of the multiplexed signal carry a multiplexing sequence identifier; according to the multiplexing sequence identifier, The multiplexed signal is serial-to-parallel converted to obtain parallel data; the parallel data is separately exchanged and output.
  • an embodiment of the present invention provides a method for rate adaptation, which specifically includes:
  • Step 101 The line card multiplexes a plurality of cells to be transmitted, such as interpolating and multiplexing, to obtain a multiplexed signal. Since each cell to be transmitted includes a cell header, the multiplexed signal is included. Contains multiple cell headers. After the low-speed signal is multiplexed, a high-speed signal can be obtained. For example, four low-speed signals of 3.125 Gb/s are multiplexed to obtain a high-speed multiplexing signal of 12.5 Gb/s.
  • Step 102 The line card adds a multiplexing sequence identifier to the plurality of cell headers in the obtained multiplexed signal according to the multiplexing sequence.
  • the adding the multiplexing sequence identifier may be specifically: if multiple cell headers are respectively set to different values, the order of multiplexing may be identified according to the value of any one of the cell headers and the location thereof; or multiple letters may be The element headers are set to the same value, and the order of multiplexing can be identified based on the values of the plurality of cell headers. For example, referring to FIG. 3, there are four cells to be transmitted, each having a length of N bytes, and the cell headers are all H.
  • the multiplexed signal After multiplexing and multiplexing the four cells, a multiplexed signal is obtained. Then the multiplexed signal contains four identical cell headers, which are represented by 3 ⁇ 4, 3 ⁇ 4, 3 ⁇ 4 and respectively in the figure, and their values are set to 1, 2, 3 and 4, respectively, in the order of multiplexing, or set to A, B, C, D, etc., are used to identify the multiplexing order of 4 cell headers; they can also be set to the same value, for example, all 3, then 4 consecutive 3s represent complex The order used.
  • the multiplexed signal contains four identical cell headers, which are represented by 3 ⁇ 4, 3 ⁇ 4, 3 ⁇ 4 and respectively in the figure, and their values are set to 1, 2, 3 and 4, respectively, in the order of multiplexing, or set to A, B, C, D, etc., are used to identify the multiplexing order of 4 cell headers; they can also be set to the same value, for example, all 3, then 4 consecutive 3s represent complex The order used.
  • Step 103 The switch board receives the multiplexed signal sent by the line card.
  • Step 104 The switch board performs the serial-to-parallel conversion of the received multiplexed signal according to the pre-stored multiplexing sequence to obtain parallel data with accurate position, and the multiplexing sequence of multiple cell headers in the multiplexed signal.
  • the positionally accurate parallel data refers to the parallel data comprising any one of the plurality of cell headers in the multiplexed signal, and the location of the cell header in the parallel data and the cell header The positions in the plurality of cell headers are the same; when the multiplexing order identifiers of the plurality of cell headers in the multiplexed signal are all the same, the positionally accurate parallel data means that the parallel data is identical to the plurality of cell headers.
  • the pre-stored multiplexing order identifier is the multiplexing order identifier of the line card setting.
  • the process of performing serial-to-parallel conversion on the received multiplexed signal by the switch board includes:
  • the multiplexed signal contains four cell headers whose values are respectively B, C, and D; when it is judged that the value of one data in the parallel data is "B" and the data is the second in the parallel data.
  • the process of performing serial-to-parallel conversion on the received multiplexed signal by the switch board includes: Performing serial-to-parallel conversion on the multiplexed signal according to the specified length to obtain intermediate parallel data, and specifying a product whose length is equal to the length of the cell header of the to-be-transmitted cell and the number of multiplexed signals; according to the pre-stored multiplexing order identifier, determining the Whether the intermediate parallel data is the same as the plurality of cell headers; if so, the multiplexed signal is not shifted, that is, the obtained intermediate parallel data is parallel data with accurate position; otherwise, the multiplex is performed according to a preset direction Each time the signal is shifted by one bit, a serial-to-parallel conversion is performed until the obtained parallel data is identical to the plurality of cell headers, and the obtained parallel data is positionally accurate parallel data.
  • the multiplexed signal contains two cell headers, each of which has a value of 6; when it is judged that the values of the two data in the parallel data are both 6, the parallel data with accurate position is obtained.
  • the direction of the shift of the switch board string when converting and converting may be forward moving or backward moving, as long as it is ensured to shift in the same direction during the shifting process, if the cell length to be transmitted All of them are N bytes, and the corresponding transmission time period is ⁇ . Then, in the time of multiplexing the number of times XT, the positionally accurate parallel data can be obtained by shifting.
  • the length L of the cell in the cell to be transmitted is 1 byte
  • the number of multiplexing is 4
  • the cell headers in the multiplexed signal of 12.5 Gb/s are Hi, H 2 , H 3 , respectively.
  • the obtained parallel data includes the plurality of cells Any one of the cell headers, and the position of the included cell header in the parallel data is the same as the position of the cell header in the plurality of cell headers, and the parallel data is positionally accurate parallel data. , output corresponding parallel data to the switching unit for exchange.
  • Step 105 The switch board exchanges and outputs the parallel data separately, and then ends.
  • the above method is described by taking a line card to multiplex a low-speed signal to obtain a high-speed signal, and the line card is a low-speed bus line card.
  • the packet switching device can simultaneously use a low-speed bus line card and a high-speed bus line card, that is, in a packet switching device, some line cards can multiplex cells to be transmitted, and some line cards can be omitted.
  • the number of line card multiplexing to be multiplexed may also be different.
  • the switch board receives three signals from three line cards: a 12.5Gb/s multiplexed signal, a 6.25Gb/s multiplexed signal, and a 3.125Gb/s unmultiplexed signal.
  • the serial-to-parallel conversion unit performs serial-to-parallel conversion in the manner of the above-described shift control serial-to-parallel conversion, that is, converting the 12.5 Gb/s multiplexed signal at the interface 1
  • Four parallel data of 3.125Gb/s are respectively sent to the switching units 1, 2, 3 and 4 for exchange, and then output; at the interface 2, the 6.25Gb/s multiplexed signal is converted into two 3.125Gb/s
  • the parallel data is respectively sent to the switching units 1 and 2 for exchange, and then output; at the interface 3, the 3.125 Gb/s unmultiplexed signal is directly sent to the switching unit 1 for exchange, and then output.
  • the transmission period of each cell is also fixed. After the switching unit receives the parallel data, when the current cell's period arrives, the letter is received. Meta exchange.
  • the received multiplexed signal is serial-to-parallel converted according to the multiplexing sequence identifier, and the parallel data with accurate position is obtained, thereby realizing the docking of the low-speed bus line card and the high-speed bus exchange board, and improving the line card.
  • the compatibility with the switchboard enables the existing lower rate bus line cards to be applied to systems with higher rate buses, effectively utilizing existing resources, and saving the cost of subsequent development.
  • an embodiment of the present invention further provides a switch board, which specifically includes:
  • the receiving module 201 is configured to receive, by the line card, a multiplexed signal of the to-be-transmitted cell, where the multiple cell headers in the multiplexed signal carry a multiplexing sequence identifier;
  • the converting module 202 is configured to perform serial-to-parallel conversion on the multiplexed signal received by the receiving module 201 to obtain parallel data according to the pre-stored multiplexing sequence identifier;
  • the switching module 203 is configured to exchange and output the parallel data obtained by the conversion module 202.
  • the converting module 202 specifically includes: a shift converting unit, configured to receive the receiving module 201 according to a preset direction according to the pre-stored multiplexing sequence identifier Each time the multiplexed signal is moved by one bit, a serial-to-parallel conversion of the specified length is performed until the parallel data is obtained, and the parallel data includes any one of the plurality of cell headers in the multiplexed signal, and the The position of the cell header in the parallel data is the same as the position of the cell header in the plurality of cell headers.
  • the converting module 202 specifically includes: a shift converting unit, configured to receive, according to the pre-stored multiplexing sequence identifier, the receiving module according to a preset direction. Each time the multiplexed signal is shifted by one bit, a serial-to-parallel conversion of a specified length is performed until the same parallel data as that of the plurality of cell headers in the multiplexed signal is obtained.
  • the specified length is equal to the product of the length of the cell header of the cell to be transmitted and the number of multiplexing of the multiplexed signal.
  • the received multiplexed signal is serial-to-parallel converted according to the multiplexing sequence identifier, and the parallel data with accurate position is obtained, thereby realizing the docking of the low-speed bus line card and the high-speed bus exchange board, and improving the line card.
  • Compatibility with switch boards enables existing lower rate bus line cards to be used in systems with higher rate buses, effectively utilizing existing resources, Saves on the cost of subsequent development.
  • an embodiment of the present invention further provides a line card, including:
  • the multiplexing module 301 is configured to multiplex a plurality of cells to be transmitted, such as interpolating and multiplexing, to obtain a multiplexed signal, and add a plurality of cell headers in the multiplexed signal according to a multiplexing sequence.
  • the sequence identifier is used; wherein the same multiplexing sequence identifier can be added to multiple cell headers, for example, the values of the four cell headers are all set to A, and different multiplexing order identifiers can also be added to multiple cell headers. For example, the values of the two cell headers are 1 and 2, and so on.
  • the sending module 302 is configured to send the multiplexed signal obtained by the multiplexing module 301.
  • the low-speed bus line card can transmit high-speed signals to the switch board, thereby realizing the connection between the low-speed bus line card and the high-speed bus switch board, and improving the compatibility between the line card and the switch board.
  • an embodiment of the present invention further provides a rate adaptation device, which specifically includes:
  • a line card 401 configured to send a multiplexed signal of the to-be-transmitted cell, where the plurality of cell headers in the multiplexed signal carry a multiplexing sequence identifier;
  • the switch board 402 is configured to receive the multiplexed signal sent by the line card 401, perform serial-to-parallel conversion on the multiplexed signal according to the pre-stored multiplexing order identifier, and then convert the parallel data into parallel data. Output.
  • the line card specifically includes:
  • a multiplexing module configured to multiplex a plurality of to-be-transmitted cells to obtain a multiplexed signal, and add a multiplexing sequence identifier to the plurality of cell headers in the multiplexed signal according to the multiplexed sequence;
  • the sending module is configured to send the multiplexed signal obtained by the multiplexing module.
  • the switch board specifically includes:
  • a receiving module configured to receive a multiplexed signal sent by the line card, where the multiplexing sequence identifiers carried by the multiple cell headers in the multiplexed signal are different;
  • a conversion module configured to perform, according to the pre-stored multiplexing sequence identifier, a bit of a specified length of the multiplexed signal received by the receiving module according to a preset direction, and perform a serial-to-parallel conversion of the specified length until the parallel data is obtained.
  • the parallel data includes any one of a plurality of cell headers in the multiplexed signal, and the location of the cell header in the parallel data and the cell header are in the plurality of The position in the cell header is the same;
  • the switching module is configured to exchange and output parallel data obtained by the conversion module.
  • the switch board specifically includes:
  • a receiving module configured to receive a multiplexed signal sent by a line card, and a multiplexing sequence identifier carried by multiple cell headers in the multiplexed signal All the same;
  • a conversion module configured to perform, according to the pre-stored multiplexing sequence identifier, a bit of a specified length of the multiplexed signal received by the receiving module according to a preset direction, and perform a serial-to-parallel conversion of the specified length until the Decoding the same parallel data of multiple cell headers in the signal;
  • the switching module is configured to exchange and output parallel data obtained by the conversion module.
  • the specified length is equal to the product of the length of the cell header of the cell to be transmitted and the number of multiplexing of the multiplexed signal.
  • the received multiplexed signal is serial-to-parallel converted according to the multiplexing sequence identifier, and the parallel data with accurate position is obtained, thereby realizing the docking of the low-speed bus line card and the high-speed bus exchange board, and improving the line card.
  • the compatibility with the switchboard enables the existing lower rate bus line cards to be applied to systems with higher rate buses, effectively utilizing existing resources, and saving the cost of subsequent development.
  • the embodiments of the present invention can be implemented by a combination of software and hardware, and the corresponding software can be stored in a readable storage medium, such as a hard disk or an optical disk of a computer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Looms (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

A rate adapting method and apparatus, exchange board and line card are provided which relate to the group exchange field. The method includes: receiving the multiplex signal of the cell waiting to be transmitted from the line card, a number of cell headers of the multiplex signal carry multiplex sequence identifiers; performing the serial-to-parallel converting to the multiplex signal by shifting according to the multiplex sequence identifier to obtain the parallel data; exchanging the parallel data respectively and outputting it. The exchange board includes: a receiving module, a converting module and an exchanging module. The line card includes: a multiplexing module and a transmitting module. The apparatus includes: a line card and an exchange board.

Description

速率适配的方法和设备、 交换板与线卡 本申请要求于 2007年 12月 29日提交中国专利局、 申请号为 200710306070.x、发明名称 为 "速率适配的方法和设备、 交换板与线卡"的中国专利申请的优先权， 其全部内容通过引 用结合在本申请中。  Rate adaptation method and device, switch board and line card The application is submitted to the Chinese Patent Office on December 29, 2007, and the application number is 200710306070.x, and the invention name is "rate adaptation method and device, switch board and The priority of the Chinese Patent Application for Line Cards, the entire contents of which is incorporated herein by reference.
说  Say
技术领域 Technical field
本发明涉及分组交换领域， 特别涉及一种速率适配的方法和设备、 交换板与线卡。 背景技术 书  The present invention relates to the field of packet switching, and in particular, to a method and device for rate adaptation, a switch board and a line card. BACKGROUND OF THE INVENTION
现有的交换技术主要有两种： 电路交换和分组交换。 电路交换是指计算机终端之间进行 通信时， 一方发起呼叫， 独占一条物理线路， 当交换机完成接续， 对方收到发起端的信号， 双方即可进行通信。在整个通信过程中双方一直占用该电路。 它的特点是实时性强， 时延小， 交换设备成本较低。 但同时也带来线路利用率低， 电路接续时间长， 通信效率低， 不同类型 终端用户之间不能通信等缺点。 电路交换比较适用于信息量大、 长报文， 经常使用的固定用 户之间的通信。 分组交换实质上是在 "存储一一转发"基础上发展起来的。 分组交换在线路 上采用动态复用技术传送按一定长度分割为许多小段的数据一一分组。 每个分组标识后， 在 一条物理线路上采用动态复用的技术， 同时传送多个数据分组。 把来自用户发端的数据暂存 在交换机的存储器内， 接着在网内转发。 到达接收端后， 再去掉分组头， 将各数据字段按顺 序重新装配成完整的报文。 分组交换比电路交换的电路利用率高。  There are two main types of existing switching technologies: circuit switching and packet switching. Circuit switching refers to the fact that when a computer terminal communicates, one party initiates a call and monopolizes a physical line. When the switch completes the connection, the other party receives the signal from the initiator, and the two parties can communicate. The circuit is occupied by both parties throughout the communication process. It is characterized by strong real-time performance, low latency, and low switching equipment costs. However, it also has the disadvantages of low line utilization, long circuit connection time, low communication efficiency, and inability to communicate between different types of end users. Circuit switching is more suitable for communication between fixed users who use large amounts of information, long messages, and frequently used. Packet switching is essentially based on "storage one-to-one forwarding". Packet switching uses dynamic multiplexing techniques on the line to transmit data that is divided into a number of small segments by a certain length. After each packet is identified, a dynamic multiplexing technique is employed on one physical line to simultaneously transmit multiple data packets. The data from the user's origin is temporarily stored in the memory of the switch, and then forwarded in the network. After reaching the receiving end, the packet header is removed, and the data fields are reassembled into complete messages in order. Packet switching is more efficient than circuit switched circuits.
现有技术中定长分组信元交换网主要采用的是 M-C-M的架构，中间级是纵横交叉交换芯 片（Switching Crossbar chip, SC), 两边是共享缓存交换芯片（ Switching Memory chip， SM), 需要被交换的信元在 SM缓存下来， 向 SC提交换请求， 在 SC交换网中， 多个输入可能同时 竞争一个输出， 即输入输出之间存在竞争， 需要仲裁算法对信元进行调度。 经过仲裁算法调 度后， SC向 SM返回准许信号， SM收到准许信号后， 将信元调出来后， 送给 SC， SC对其 进行交换。例如， 参见图 1， 在现有的分组交换设备中， SM被放在线路板（又称为线卡）上， SC被放在交换板上， 交换板完成各个线路板上的信元的交换。 左边的线路板 0至 15上的信 号为待发送的信号， 经过交换板 0至 3进行交换后， 输出给右边的线路板 0至 15， 相应地输 出给其他通信设备。 In the prior art, the fixed-length packet cell switching network mainly adopts the MCM architecture, the intermediate level is a Switching Crossbar chip (SC), and the two sides are a shared switching chip (SM), which needs to be The exchanged cells are buffered in the SM and exchange requests with the SC. In the SC switching network, multiple inputs may compete for one output at the same time, that is, there is competition between the input and output, and an arbitration algorithm is required to schedule the cells. After being scheduled by the arbitration algorithm, the SC returns a grant signal to the SM. After receiving the grant signal, the SM, after receiving the grant signal, sends the cell to the SC, and the SC exchanges it. For example, referring to FIG. 1, in the existing packet switching device, the SM is placed on a circuit board (also referred to as a line card), and the SC is placed on the switch board, and the switch board completes the exchange of cells on each circuit board. . The signals on the left board 0 to 15 are the signals to be sent. After switching through the switch boards 0 to 3, they are output to the right board 0 to 15, and are output accordingly. Out to other communication devices.
在实现本发明的过程中， 发明人发现上述现有技术至少具有以下问题：  In carrying out the process of the present invention, the inventors have found that the above prior art has at least the following problems:
分组交换设备中的总线是全局设置， 整个设备统一为一个速率， 如 3.125Gb/s 或者 The bus in the packet switching device is globally set, and the entire device is unified to a rate, such as 3.125 Gb/s or
6.25Gb/s， 不存在部分总线是 3.125Gb/s的速率， 部分总线是 6.25Gb/s的速率。 当前设计的线 路板， 由于技术局限性， 通常采用速率较低的总线， 比如 3.125G总线， 而后续设计的线路板 和交换板， 由于技术的进步， 可以采用较高速率的总线， 比如 6.25G, 因此当采用高速总线 ***时， 上述现有技术无法实现低速总线线路板与高速总线交换板的对接。 发明内容 6.25Gb/s, there is no part of the bus is 3.125Gb / s, part of the bus is 6.25Gb / s. Currently designed circuit boards, due to technical limitations, usually use lower speed buses, such as 3.125G bus, and subsequent design of circuit boards and switch boards, due to advances in technology, can use higher speed buses, such as 6.25G Therefore, when the high-speed bus system is adopted, the above prior art cannot realize the docking of the low-speed bus circuit board and the high-speed bus switch board. Summary of the invention
为了实现低速总线线路板与高速总线交换板的对接， 本发明实施例提供了一种速率适配 的方法和设备、 交换板与线卡。 所述技术方案如下：  In order to achieve the connection between the low-speed bus circuit board and the high-speed bus switch board, the embodiment of the invention provides a method and device for rate adaptation, a switch board and a line card. The technical solution is as follows:
一方面， 本发明实施例提供了一种速率适配的方法， 所述方法包括：  In one aspect, an embodiment of the present invention provides a method for rate adaptation, where the method includes:
接收从线卡来的待发送信元的复用信号， 所述复用信号中的多个信元头携带复用顺序标 识；  Receiving, by the line card, a multiplexed signal of the to-be-transmitted cell, where the plurality of cell headers of the multiplexed signal carry a multiplexing sequence identifier;
根据所述复用顺序标识， 以移位的方式对所述复用信号进行串并转换得到并行数据； 对所述并行数据分别进行交换并输出。  And performing, according to the multiplexing order identifier, performing serial-to-parallel conversion on the multiplexed signal to obtain parallel data; and exchanging and outputting the parallel data respectively.
另一方面， 本发明实施例还提供了一种交换板， 所述交换板包括：  On the other hand, the embodiment of the present invention further provides a switchboard, where the switchboard includes:
接收模块， 用于接收从线卡来的待发送信元的复用信号， 所述复用信号中的多个信元头 携带复用顺序标识；  a receiving module, configured to receive a multiplexed signal of a to-be-transmitted cell from the line card, where the plurality of cell headers carry a multiplexing sequence identifier;
转换模块， 用于根据预存的所述复用顺序标识， 以移位的方式对所述接收模块收到的复 用信号进行串并转换得到并行数据；  a conversion module, configured to perform serial-to-parallel conversion on the multiplexed signal received by the receiving module according to the pre-stored multiplexing sequence identifier to obtain parallel data;
交换模块， 用于对所述转换模块得到的并行数据分别进行交换并输出。  And a switching module, configured to exchange and output parallel data obtained by the conversion module.
另一方面， 本发明实施例还提供了一种线卡， 所述线卡包括：  In another aspect, the embodiment of the present invention further provides a line card, where the line card includes:
复用模块， 用于对多个待发送信元进行复用， 得到复用信号， 并按照复用的顺序， 给所 述复用信号中的多个信元头添加复用顺序标识；  a multiplexing module, configured to multiplex a plurality of to-be-transmitted cells to obtain a multiplexed signal, and add a multiplexing sequence identifier to the plurality of cell headers in the multiplexed signal according to a multiplexing sequence;
发送模块， 用于发送所述复用模块得到的复用信号。  And a sending module, configured to send the multiplexed signal obtained by the multiplexing module.
另一方面， 本发明实施例还提供了一种速率适配的设备， 所述设备包括：  On the other hand, an embodiment of the present invention further provides a rate adaptation device, where the device includes:
线卡， 用于发送待发送信元的复用信号， 所述复用信号中的多个信元头携带复用顺序标 识；  a line card, configured to send a multiplexed signal of a cell to be transmitted, where a plurality of cell headers of the multiplexed signal carry a multiplexing sequence identifier;
交换板， 用于接收所述线卡发来的复用信号， 根据预存的所述复用顺序标识， 以移位的 方式对所述复用信号进行串并转换得到并行数据，然后对所述并行数据分别进行交换并输出。 本发明实施例提供的技术方案的有益效果是： a switching board, configured to receive a multiplexed signal sent by the line card, and according to the pre-stored multiplexing sequence identifier, to be shifted The method performs serial-to-parallel conversion on the multiplexed signals to obtain parallel data, and then separately exchanges and outputs the parallel data. The beneficial effects of the technical solutions provided by the embodiments of the present invention are:
根据复用顺序标识以移位的方式对收到的复用信号进行串并转换， 得到位置准确的并行 数据， 实现了低速总线线卡与高速总线交换板的对接， 提高了线卡与交换板的兼容性， 使已 有的较低速率总线线卡能够适用于较高速率总线的***中， 有效地利用现有的资源， 节省了 后续开发的成本。 附图说明  According to the multiplexing sequence identification, the received multiplexed signals are serial-to-parallel converted in a shifting manner to obtain parallel data with accurate position, thereby realizing the docking of the low-speed bus line card and the high-speed bus switching board, and improving the line card and the switching board. The compatibility enables existing lower-rate bus line cards to be applied to systems with higher-rate buses, effectively utilizing existing resources, and saving the cost of subsequent development. DRAWINGS
图 1是现有技术中分组交换设备结构示意图；  1 is a schematic structural diagram of a packet switching device in the prior art;
图 2是本发明实施例 1提供的速率适配的方法流程图；  2 is a flowchart of a method for rate adaptation according to Embodiment 1 of the present invention;
图 3是本发明实施例 1提供的对多个待发送信号进行复用的示意图；  3 is a schematic diagram of multiplexing multiple signals to be transmitted according to Embodiment 1 of the present invention;
图 4是本发明实施例 1提供的以移位方式对复用信号进行串并转换的示意图； 图 5是本发明实施例 1提供的交换板对多个复用信号进行串并转换及交换的示意图； 图 6是本发明实施例 2提供的交换板结构图；  4 is a schematic diagram of serial-to-parallel conversion of a multiplexed signal in a shift mode according to Embodiment 1 of the present invention; FIG. 5 is a serial-to-parallel conversion and exchange of a plurality of multiplexed signals by a switch board according to Embodiment 1 of the present invention; Figure 6 is a structural diagram of a switchboard according to Embodiment 2 of the present invention;
图 7是本发明实施例 3提供的线卡结构图；  7 is a structural diagram of a line card according to Embodiment 3 of the present invention;
图 8是本发明实施例 4提供的速率适配的设备结构图。 具体实施方式  FIG. 8 is a structural diagram of a device for rate adaptation according to Embodiment 4 of the present invention. detailed description
为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本发明实施方式作进 一步地详细描述。  In order to make the objects, the technical solutions and the advantages of the present invention more apparent, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
本发明实施例提供的速率适配的方法， 具体包括： 接收从线卡来的复用信号， 该复用信 号中的多个信元头携带复用顺序标识； 根据该复用顺序标识， 以移位的方式对该复用信号进 行串并转换得到并行数据； 然后对该并行数据分别进行交换并输出。  The method for rate adaptation according to the embodiment of the present invention specifically includes: receiving a multiplexed signal from a line card, where a plurality of cell headers of the multiplexed signal carry a multiplexing sequence identifier; according to the multiplexing sequence identifier, The multiplexed signal is serial-to-parallel converted to obtain parallel data; the parallel data is separately exchanged and output.
实施例 1  Example 1
参见图 2， 本发明实施例提供了一种速率适配的方法， 具体包括：  Referring to FIG. 2, an embodiment of the present invention provides a method for rate adaptation, which specifically includes:
步骤 101 : 线卡对多个待发送的信元进行复用， 如间插复用等， 得到复用信号， 由于待 发送的每个信元中都包含一个信元头， 则复用信号中包含多个信元头。 低速信号经过复用后 可以得到高速信号， 如对 4个 3.125Gb/s的低速信号进行复用， 得到一个 12.5Gb/s的高速复 用信号。  Step 101: The line card multiplexes a plurality of cells to be transmitted, such as interpolating and multiplexing, to obtain a multiplexed signal. Since each cell to be transmitted includes a cell header, the multiplexed signal is included. Contains multiple cell headers. After the low-speed signal is multiplexed, a high-speed signal can be obtained. For example, four low-speed signals of 3.125 Gb/s are multiplexed to obtain a high-speed multiplexing signal of 12.5 Gb/s.
步骤 102: 线卡按照复用的顺序， 给得到的复用信号中的多个信元头添加复用顺序标识。 其中， 添加复用顺序标识可以具体为： 将多个信元头分别设置成不同的值， 则根据其中 任一个信元头的值及其位置就能识别复用的顺序； 或者将多个信元头设置成相同的值， 则根 据所述多个信元头的值可以识别出复用的顺序。 例如， 参见图 3， 有 4个待发送的信元， 长 度均为 N个字节， 信元头均为 H， 对该 4个信元进行字节间插复用后， 得到复用信号， 则复 用信号中包含 4个相同的信元头， 在图中分别用 ¾、 ¾、 ¾和 表示， 按照复用的顺序将 它们的值分别设置为 1、 2、 3和 4， 或者设置为 A、 B、 C和 D等等， 用来标识 4个信元头的 复用顺序； 另外也可以将它们的值设置成相同的值， 如均为 3， 则 4个连续的 3代表了复用 的顺序。 Step 102: The line card adds a multiplexing sequence identifier to the plurality of cell headers in the obtained multiplexed signal according to the multiplexing sequence. The adding the multiplexing sequence identifier may be specifically: if multiple cell headers are respectively set to different values, the order of multiplexing may be identified according to the value of any one of the cell headers and the location thereof; or multiple letters may be The element headers are set to the same value, and the order of multiplexing can be identified based on the values of the plurality of cell headers. For example, referring to FIG. 3, there are four cells to be transmitted, each having a length of N bytes, and the cell headers are all H. After multiplexing and multiplexing the four cells, a multiplexed signal is obtained. Then the multiplexed signal contains four identical cell headers, which are represented by 3⁄4, 3⁄4, 3⁄4 and respectively in the figure, and their values are set to 1, 2, 3 and 4, respectively, in the order of multiplexing, or set to A, B, C, D, etc., are used to identify the multiplexing order of 4 cell headers; they can also be set to the same value, for example, all 3, then 4 consecutive 3s represent complex The order used.
步骤 103 : 交换板接收线卡发来的复用信号。  Step 103: The switch board receives the multiplexed signal sent by the line card.
步骤 104: 交换板根据预存的复用顺序标识， 以移位的方式对收到的复用信号进行串并 转换得到位置准确的并行数据， 当复用信号中多个信元头的复用顺序标识均不同时， 位置准 确的并行数据是指并行数据中包含复用信号中的多个信元头中的任一个信元头， 且该信元头 在并行数据中的位置与该信元头在该多个信元头中的位置相同； 当复用信号中多个信元头的 复用顺序标识均相同时， 位置准确的并行数据是指并行数据与所述多个信元头相同。 预存的 复用顺序标识即线卡设置的复用顺序标识。  Step 104: The switch board performs the serial-to-parallel conversion of the received multiplexed signal according to the pre-stored multiplexing sequence to obtain parallel data with accurate position, and the multiplexing sequence of multiple cell headers in the multiplexed signal. When the identifiers are different, the positionally accurate parallel data refers to the parallel data comprising any one of the plurality of cell headers in the multiplexed signal, and the location of the cell header in the parallel data and the cell header The positions in the plurality of cell headers are the same; when the multiplexing order identifiers of the plurality of cell headers in the multiplexed signal are all the same, the positionally accurate parallel data means that the parallel data is identical to the plurality of cell headers. The pre-stored multiplexing order identifier is the multiplexing order identifier of the line card setting.
当复用信号中多个信元头的复用顺序标识均不同时， 交换板对收到的复用信号进行串并 转换的过程具体包括：  When the multiplexing sequence identifiers of the plurality of cell headers in the multiplexed signal are different, the process of performing serial-to-parallel conversion on the received multiplexed signal by the switch board includes:
按指定长度对复用信号进行串并转换得到中间并行数据， 指定长度等于待发送信元的信 元头的长度与复用信号的复用数目的乘积； 根据预存的复用顺序标识， 判断该中间并行数据 中是否包含所述多个信元头中的任一个信元头， 且所包含的信元头在并行数据中的位置与该 信元头在所述多个信元头中的位置相同； 如果是， 则不对复用信号进行移位， 即得到的中间 并行数据即为位置准确的并行数据； 否则， 按照预设的方向对复用信号每移动一个比特位进 行一次串并转换， 直到得到的并行数据中包含所述多个信元头中的任一个信元头， 且该信元 头在并行数据中的位置与该信元头在所述多个信元头中的位置相同为止， 则得到的并行数据 为位置准确的并行数据。  Performing serial-to-parallel conversion on the multiplexed signal according to the specified length to obtain intermediate parallel data, and specifying a product whose length is equal to the length of the cell header of the to-be-transmitted cell and the number of multiplexed signals; according to the pre-stored multiplexing order identifier, determining the Whether the intermediate parallel data includes any one of the plurality of cell headers, and the location of the included cell header in the parallel data and the location of the cell header in the plurality of cell headers If yes, the multiplexed signal is not shifted, that is, the obtained intermediate parallel data is parallel data with accurate position; otherwise, the multiplexed signal is shifted by one bit for each bit shifted according to a preset direction, Until the obtained parallel data includes any one of the plurality of cell headers, and the location of the cell header in the parallel data is the same as the location of the cell header in the plurality of cell headers So far, the parallel data obtained is parallel data with accurate position.
例如， 复用信号中包含 4个信元头， 它们的值分别为 、 B、 C和 D; 当判断出并行数据 中有一个数据的值为 "B "且该数据为并行数据中的第 2 个数据， 则此时得到的并行数据即 位置准确的并行数据， 不用再进行移位。  For example, the multiplexed signal contains four cell headers whose values are respectively B, C, and D; when it is judged that the value of one data in the parallel data is "B" and the data is the second in the parallel data. The data, then the parallel data obtained at this time, that is, the positionally accurate parallel data, does not need to be shifted.
当复用信号中多个信元头的复用顺序标识均相同时， 交换板对收到的复用信号进行串并 转换的过程具体包括： 按指定长度对复用信号进行串并转换得到中间并行数据， 指定长度等于待发送信元的信 元头的长度与复用信号的复用数目的乘积； 根据预存的复用顺序标识， 判断该中间并行数据 是否与所述多个信元头相同； 如果是， 则不对复用信号进行移位， 即得到的中间并行数据即 为位置准确的并行数据； 否则， 按照预设的方向对复用信号每移动一个比特位进行一次串并 转换， 直到得到的并行数据与所述多个信元头相同为止， 则得到的并行数据为位置准确的并 行数据。 When the multiplexing sequence identifiers of the plurality of cell headers in the multiplexed signal are the same, the process of performing serial-to-parallel conversion on the received multiplexed signal by the switch board includes: Performing serial-to-parallel conversion on the multiplexed signal according to the specified length to obtain intermediate parallel data, and specifying a product whose length is equal to the length of the cell header of the to-be-transmitted cell and the number of multiplexed signals; according to the pre-stored multiplexing order identifier, determining the Whether the intermediate parallel data is the same as the plurality of cell headers; if so, the multiplexed signal is not shifted, that is, the obtained intermediate parallel data is parallel data with accurate position; otherwise, the multiplex is performed according to a preset direction Each time the signal is shifted by one bit, a serial-to-parallel conversion is performed until the obtained parallel data is identical to the plurality of cell headers, and the obtained parallel data is positionally accurate parallel data.
例如， 复用信号中包含 2个信元头， 它们的值均为 6; 当判断出并行数据中的两个数据 的值均为 6时， 则得到位置准确的并行数据。  For example, the multiplexed signal contains two cell headers, each of which has a value of 6; when it is judged that the values of the two data in the parallel data are both 6, the parallel data with accurate position is obtained.
其中， 交换板串并转换时移位的方向可以为向前移动， 也可以为向后移动， 只要保证在 移位的过程中按照相同的方向进行移位即可， 如果待发送的信元长度均为 N个字节， 对应的 传输时间周期为 τ， 则在复用数目 X T 的时间内， 通过移位的方式， 可以得到位置准确的并 行数据。  Wherein, the direction of the shift of the switch board string when converting and converting may be forward moving or backward moving, as long as it is ensured to shift in the same direction during the shifting process, if the cell length to be transmitted All of them are N bytes, and the corresponding transmission time period is τ. Then, in the time of multiplexing the number of times XT, the positionally accurate parallel data can be obtained by shifting.
例如， 参见图 4， 待发送的信元中信元的长度 L为 1个字节， 复用数目为 4， 12.5Gb/s 的复用信号中的信元头分别为 Hi、 H2、 H3和 H4， 对该复用信号进行串并转换， 则并行数据 有 4 X L = 4个字节， 共 32个比特位， 如果待发送信元的长度 N字节对应的一个传输时间周 期为 T， 则在复用数目 4 Χ Τ的时间内， 对首次串并转换得到的中间并行数据进行检测， 判断 是否该中间并行数据中包含预存的多个信元头 H2、 H3和 H4中的任一个信元头， 且所包 含的信元头在该中间并行数据中的位置与该信元头在所述多个信元头中的位置相同，如果是， 则不对复用信号进行移位， 该中间并行数据即为位置准确的并行数据； 否则， 对复用信号进 行向后移位， 每向后移动一个比特位， 都进行一次串并转换， 并实时检测， 直到检测到移位 后得到的并行数据中包含所述多个信元头中的任一个信元头， 且所包含的信元头在该并行数 据中的位置与该信元头在所述多个信元头中的位置相同， 则该并行数据为位置准确的并行数 据， 输出相应的并行数据给交换单元进行交换。 For example, referring to FIG. 4, the length L of the cell in the cell to be transmitted is 1 byte, the number of multiplexing is 4, and the cell headers in the multiplexed signal of 12.5 Gb/s are Hi, H 2 , H 3 , respectively. And H 4 , the serial-to-parallel conversion of the multiplexed signal, the parallel data has 4 XL = 4 bytes, a total of 32 bits, if the length of the to-be-sent cell is N bytes, a transmission time period is T And detecting, in the time of multiplexing 4 Χ , the intermediate parallel data obtained by the first serial-to-parallel conversion, and determining whether the intermediate parallel data includes the pre-stored plurality of cell headers H 2 , H 3 , and H 4 Any one of the cell headers, and the location of the included cell header in the intermediate parallel data is the same as the location of the cell header in the plurality of cell headers, and if so, the multiplexed signal is not shifted Bit, the intermediate parallel data is the parallel data with accurate position; otherwise, the multiplexed signal is shifted backward, and each bit is shifted backward, and a serial-to-parallel conversion is performed, and the detection is performed in real time until the shift is detected. The obtained parallel data includes the plurality of cells Any one of the cell headers, and the position of the included cell header in the parallel data is the same as the position of the cell header in the plurality of cell headers, and the parallel data is positionally accurate parallel data. , output corresponding parallel data to the switching unit for exchange.
步骤 105 : 交换板对并行数据分别进行交换并输出， 然后结束。  Step 105: The switch board exchanges and outputs the parallel data separately, and then ends.
上述方法是以线卡对低速信号进行复用得到高速信号为例进行说明的， 该线卡为低速总 线线卡。 在实际应用中， 分组交换设备可以同时使用低速总线线卡和高速总线线卡， 即在一 个分组交换设备中， 有的线卡可以对待发送的信元进行复用， 有的线卡可以不进行复用， 进 行复用的线卡复用的数目也可以不同。 例如， 参见图 5， 交换板收到 3个线卡发来的 3个信 号： 12.5Gb/s的复用信号、 6.25Gb/s的复用信号， 3.125Gb/s未复用的信号， 由串并转换单元 按照上述移位控制串并转换的方式进行串并转换， 即在接口 1处将 12.5Gb/s的复用信号转换 为 4个 3.125Gb/s的并行数据， 分别送给交换单元 1、 2、 3和 4进行交换， 然后输出； 在接口 2处将 6.25Gb/s的复用信号转换为 2个 3.125Gb/s的并行数据，分别送给交换单元 1和 2进行 交换， 然后输出； 在接口 3处直接将 3.125Gb/s未复用的信号送给交换单元 1进行交换， 然后 输出。 其中， 由于待发送的信元的长度都是等长的， 相应的， 每个信元的传输周期也是固定 的， 交换单元收到并行数据后， 在当前信元的周期到达时， 对该信元进行交换。 The above method is described by taking a line card to multiplex a low-speed signal to obtain a high-speed signal, and the line card is a low-speed bus line card. In practical applications, the packet switching device can simultaneously use a low-speed bus line card and a high-speed bus line card, that is, in a packet switching device, some line cards can multiplex cells to be transmitted, and some line cards can be omitted. The number of line card multiplexing to be multiplexed may also be different. For example, referring to Figure 5, the switch board receives three signals from three line cards: a 12.5Gb/s multiplexed signal, a 6.25Gb/s multiplexed signal, and a 3.125Gb/s unmultiplexed signal. The serial-to-parallel conversion unit performs serial-to-parallel conversion in the manner of the above-described shift control serial-to-parallel conversion, that is, converting the 12.5 Gb/s multiplexed signal at the interface 1 Four parallel data of 3.125Gb/s are respectively sent to the switching units 1, 2, 3 and 4 for exchange, and then output; at the interface 2, the 6.25Gb/s multiplexed signal is converted into two 3.125Gb/s The parallel data is respectively sent to the switching units 1 and 2 for exchange, and then output; at the interface 3, the 3.125 Gb/s unmultiplexed signal is directly sent to the switching unit 1 for exchange, and then output. Wherein, since the lengths of the cells to be transmitted are equal in length, correspondingly, the transmission period of each cell is also fixed. After the switching unit receives the parallel data, when the current cell's period arrives, the letter is received. Meta exchange.
本实施例根据复用顺序标识以移位的方式对收到的复用信号进行串并转换， 得到位置准 确的并行数据， 实现了低速总线线卡与高速总线交换板的对接， 提高了线卡与交换板的兼容 性， 使已有的较低速率总线线卡能够适用于较高速率总线的***中， 有效地利用现有的资源， 节省了后续开发的成本。  In this embodiment, the received multiplexed signal is serial-to-parallel converted according to the multiplexing sequence identifier, and the parallel data with accurate position is obtained, thereby realizing the docking of the low-speed bus line card and the high-speed bus exchange board, and improving the line card. The compatibility with the switchboard enables the existing lower rate bus line cards to be applied to systems with higher rate buses, effectively utilizing existing resources, and saving the cost of subsequent development.
实施例 2  Example 2
参见图 6， 本发明实施例还提供了一种交换板， 具体包括：  Referring to FIG. 6, an embodiment of the present invention further provides a switch board, which specifically includes:
接收模块 201， 用于接收线卡发来的待发送信元的复用信号， 该复用信号中的多个信元 头携带复用顺序标识；  The receiving module 201 is configured to receive, by the line card, a multiplexed signal of the to-be-transmitted cell, where the multiple cell headers in the multiplexed signal carry a multiplexing sequence identifier;
转换模块 202， 用于根据预存的复用顺序标识， 以移位的方式对接收模块 201收到的复 用信号进行串并转换得到并行数据；  The converting module 202 is configured to perform serial-to-parallel conversion on the multiplexed signal received by the receiving module 201 to obtain parallel data according to the pre-stored multiplexing sequence identifier;
交换模块 203， 用于对转换模块 202得到的并行数据分别进行交换并输出。  The switching module 203 is configured to exchange and output the parallel data obtained by the conversion module 202.
当复用信号中多个信元头的复用顺序标识均不同时， 转换模块 202具体包括： 移位转换单元， 用于根据预存的复用顺序标识， 按照预设的方向对接收模块 201收到的 复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到并行数据， 该并行数 据中包含复用信号中的多个信元头中的任一个信元头， 且该信元头在并行数据中的位置与该 信元头在多个信元头中的位置相同为止。  When the multiplexing sequence identifiers of the plurality of cell headers in the multiplexed signal are different, the converting module 202 specifically includes: a shift converting unit, configured to receive the receiving module 201 according to a preset direction according to the pre-stored multiplexing sequence identifier Each time the multiplexed signal is moved by one bit, a serial-to-parallel conversion of the specified length is performed until the parallel data is obtained, and the parallel data includes any one of the plurality of cell headers in the multiplexed signal, and the The position of the cell header in the parallel data is the same as the position of the cell header in the plurality of cell headers.
当复用信号中多个信元头的复用顺序标识均相同时， 转换模块 202具体包括： 移位转换单元， 用于根据预存的复用顺序标识， 按照预设的方向对接收模块收到的复用 信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到与复用信号中的多个信元 头相同的并行数据为止。  When the multiplexing sequence identifiers of the multiple cell headers in the multiplexed signal are all the same, the converting module 202 specifically includes: a shift converting unit, configured to receive, according to the pre-stored multiplexing sequence identifier, the receiving module according to a preset direction. Each time the multiplexed signal is shifted by one bit, a serial-to-parallel conversion of a specified length is performed until the same parallel data as that of the plurality of cell headers in the multiplexed signal is obtained.
在本发明实施例中， 指定长度等于待发送信元的信元头的长度与复用信号的复用数目的 乘积。  In the embodiment of the present invention, the specified length is equal to the product of the length of the cell header of the cell to be transmitted and the number of multiplexing of the multiplexed signal.
本实施例根据复用顺序标识以移位的方式对收到的复用信号进行串并转换， 得到位置准 确的并行数据， 实现了低速总线线卡与高速总线交换板的对接， 提高了线卡与交换板的兼容 性， 使已有的较低速率总线线卡能够适用于较高速率总线的***中， 有效地利用现有的资源， 节省了后续开发的成本。 In this embodiment, the received multiplexed signal is serial-to-parallel converted according to the multiplexing sequence identifier, and the parallel data with accurate position is obtained, thereby realizing the docking of the low-speed bus line card and the high-speed bus exchange board, and improving the line card. Compatibility with switch boards enables existing lower rate bus line cards to be used in systems with higher rate buses, effectively utilizing existing resources, Saves on the cost of subsequent development.
实施例 3  Example 3
参见图 7， 本发明实施例还提供了一种线卡， 具体包括：  Referring to FIG. 7, an embodiment of the present invention further provides a line card, including:
复用模块 301， 用于对多个待发送的信元进行复用， 如间插复用， 得到复用信号， 并按 照复用的顺序， 给复用信号中的多个信元头添加复用顺序标识； 其中， 可以给多个信元头添 加相同的复用顺序标识， 如 4个信元头的值均设置为 A， 也可以给多个信元头添加不同的复 用顺序标识， 如 2个信元头的值分别为 1和 2等等。  The multiplexing module 301 is configured to multiplex a plurality of cells to be transmitted, such as interpolating and multiplexing, to obtain a multiplexed signal, and add a plurality of cell headers in the multiplexed signal according to a multiplexing sequence. The sequence identifier is used; wherein the same multiplexing sequence identifier can be added to multiple cell headers, for example, the values of the four cell headers are all set to A, and different multiplexing order identifiers can also be added to multiple cell headers. For example, the values of the two cell headers are 1 and 2, and so on.
发送模块 302， 用于发送复用模块 301得到的复用信号。  The sending module 302 is configured to send the multiplexed signal obtained by the multiplexing module 301.
本实施例通过复用及添加复用顺序标识， 使低速总线线卡能够传输高速信号给交换板， 实现了低速总线线卡与高速总线交换板的对接， 提高了线卡与交换板的兼容性。  In this embodiment, by multiplexing and adding the multiplexing sequence identifier, the low-speed bus line card can transmit high-speed signals to the switch board, thereby realizing the connection between the low-speed bus line card and the high-speed bus switch board, and improving the compatibility between the line card and the switch board. .
实施例 4  Example 4
参见图 8， 本发明实施例还提供了一种速率适配的设备， 具体包括：  Referring to FIG. 8, an embodiment of the present invention further provides a rate adaptation device, which specifically includes:
线卡 401， 用于发送待发送信元的复用信号， 复用信号中的多个信元头携带复用顺序标 识；  a line card 401, configured to send a multiplexed signal of the to-be-transmitted cell, where the plurality of cell headers in the multiplexed signal carry a multiplexing sequence identifier;
交换板 402， 用于接收线卡 401发来的复用信号， 根据预存的复用顺序标识， 以移位的 方式对复用信号进行串并转换得到并行数据， 然后对并行数据分别进行交换并输出。  The switch board 402 is configured to receive the multiplexed signal sent by the line card 401, perform serial-to-parallel conversion on the multiplexed signal according to the pre-stored multiplexing order identifier, and then convert the parallel data into parallel data. Output.
其中， 线卡具体包括：  Among them, the line card specifically includes:
复用模块， 用于对多个待发送信元进行复用， 得到复用信号， 并按照复用的顺序， 给复 用信号中的多个信元头添加复用顺序标识；  a multiplexing module, configured to multiplex a plurality of to-be-transmitted cells to obtain a multiplexed signal, and add a multiplexing sequence identifier to the plurality of cell headers in the multiplexed signal according to the multiplexed sequence;
发送模块， 用于发送复用模块得到的复用信号。  The sending module is configured to send the multiplexed signal obtained by the multiplexing module.
其中， 交换板具体包括：  The switch board specifically includes:
接收模块， 用于接收线卡发来的复用信号， 复用信号中多个信元头携带的复用顺序标识 均不同；  a receiving module, configured to receive a multiplexed signal sent by the line card, where the multiplexing sequence identifiers carried by the multiple cell headers in the multiplexed signal are different;
转换模块， 用于根据预存的所述复用顺序标识， 按照预设的方向对所述接收模块收到的 复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到并行数据， 所述并行 数据中包含所述复用信号中的多个信元头中的任一个信元头， 且该信元头在所述并行数据中 的位置与该信元头在所述多个信元头中的位置相同；  a conversion module, configured to perform, according to the pre-stored multiplexing sequence identifier, a bit of a specified length of the multiplexed signal received by the receiving module according to a preset direction, and perform a serial-to-parallel conversion of the specified length until the parallel data is obtained. And the parallel data includes any one of a plurality of cell headers in the multiplexed signal, and the location of the cell header in the parallel data and the cell header are in the plurality of The position in the cell header is the same;
交换模块， 用于对转换模块得到的并行数据分别进行交换并输出。  The switching module is configured to exchange and output parallel data obtained by the conversion module.
另外， 交换板具体包括：  In addition, the switch board specifically includes:
接收模块， 用于接收线卡发来的复用信号， 复用信号中多个信元头携带的复用顺序标识 均相同； a receiving module, configured to receive a multiplexed signal sent by a line card, and a multiplexing sequence identifier carried by multiple cell headers in the multiplexed signal All the same;
转换模块， 用于根据预存的所述复用顺序标识， 按照预设的方向对所述接收模块收到的 复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到与所述复用信号中的 多个信元头相同的并行数据为止；  a conversion module, configured to perform, according to the pre-stored multiplexing sequence identifier, a bit of a specified length of the multiplexed signal received by the receiving module according to a preset direction, and perform a serial-to-parallel conversion of the specified length until the Decoding the same parallel data of multiple cell headers in the signal;
交换模块， 用于对转换模块得到的并行数据分别进行交换并输出。  The switching module is configured to exchange and output parallel data obtained by the conversion module.
在本发明实施例中， 指定长度等于待发送信元的信元头的长度与复用信号的复用数目的 乘积。  In the embodiment of the present invention, the specified length is equal to the product of the length of the cell header of the cell to be transmitted and the number of multiplexing of the multiplexed signal.
本实施例根据复用顺序标识以移位的方式对收到的复用信号进行串并转换， 得到位置准 确的并行数据， 实现了低速总线线卡与高速总线交换板的对接， 提高了线卡与交换板的兼容 性， 使已有的较低速率总线线卡能够适用于较高速率总线的***中， 有效地利用现有的资源， 节省了后续开发的成本。  In this embodiment, the received multiplexed signal is serial-to-parallel converted according to the multiplexing sequence identifier, and the parallel data with accurate position is obtained, thereby realizing the docking of the low-speed bus line card and the high-speed bus exchange board, and improving the line card. The compatibility with the switchboard enables the existing lower rate bus line cards to be applied to systems with higher rate buses, effectively utilizing existing resources, and saving the cost of subsequent development.
本发明实施例可以利用软硬件相结合的方式实现， 相应的软件可以存储在可读取的存储 介质中， 如计算机的硬盘或光盘中。  The embodiments of the present invention can be implemented by a combination of software and hardware, and the corresponding software can be stored in a readable storage medium, such as a hard disk or an optical disk of a computer.
以上所述仅为本发明的具体实施例， 并不用以限制本发明， 凡在本发明的原则之内， 所 作的任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。  The above is only the specific embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., which are within the scope of the present invention, should be included in the scope of the present invention. .

Claims

权 利 要 求 书 Claim
1 . 一种速率适配的方法， 其特征在于， 所述方法包括：  A method of rate adaptation, the method comprising:
接收待发送信元组成的复用信号， 所述复用信号中的多个信元头携带复用顺序标识； 根据所述复用顺序标识， 以移位的方式对所述复用信号进行串并转换得到并行数据； 对所述并行数据分别进行交换并输出。  And receiving, by the multiplexed signal, a multiplexed signal, where the plurality of cell headers in the multiplexed signal carry a multiplexed sequence identifier; and arranging the multiplexed signal in a shifted manner according to the multiplexing sequence identifier And converting to obtain parallel data; respectively, the parallel data is exchanged and output.
2. 根据权利要求 1所述的速率适配的方法， 其特征在于， 所述接收待发送信元组成的复 用信号之前， 还包括： The method for rate adaptation according to claim 1, wherein before the receiving the multiplexing signal composed of the to-be-sent cells, the method further includes:
线卡对多个待发送信元进行复用， 得到复用信号；  The line card multiplexes a plurality of to-be-sent cells to obtain a multiplexed signal;
按照复用的顺序， 给所述复用信号中的多个信元头添加复用顺序标识。  A multiplexing order identifier is added to a plurality of cell headers in the multiplexed signal in a multiplexed order.
3. 根据权利要求 1所述的速率适配的方法， 其特征在于， 所述多个信元头的复用顺序标 识均不同， 所述根据所述复用顺序标识， 以移位的方式对所述复用信号进行串并转换得到并 行数据， 具体包括： The method for rate adaptation according to claim 1, wherein the multiplexing sequence identifiers of the plurality of cell headers are different, and the multiplexing is performed according to the multiplexing sequence identifier The multiplexed signal is subjected to serial-to-parallel conversion to obtain parallel data, and specifically includes:
根据所述复用顺序标识， 按照预设的方向对所述复用信号每移动一个比特位， 进行一次 指定长度的串并转换， 直到得到并行数据， 所述并行数据中包含所述多个信元头中的任一个 信元头， 且该信元头在所述并行数据中的位置与该信元头在所述多个信元头中的位置相同。  Determining, according to the multiplexing order identifier, a bit-by-bit conversion of a specified length for each bit of the multiplexed signal according to a preset direction, until parallel data is obtained, where the parallel data includes the plurality of letters Any one of the cell headers, and the location of the cell header in the parallel data is the same as the location of the cell header in the plurality of cell headers.
4. 根据权利要求 1所述的速率适配的方法， 其特征在于， 所述多个信元头的复用顺序标 识均相同， 所述根据所述复用顺序标识， 以移位的方式对所述复用信号进行串并转换得到并 行数据， 具体包括： The method for rate adaptation according to claim 1, wherein the multiplexing sequence identifiers of the plurality of cell headers are the same, and the multiplexing is performed according to the multiplexing sequence identifier The multiplexed signal is subjected to serial-to-parallel conversion to obtain parallel data, and specifically includes:
根据所述复用顺序标识， 按照预设的方向对所述复用信号每移动一个比特位， 进行一次 指定长度的串并转换， 直到得到与所述多个信元头相同的并行数据为止。  And performing, according to the multiplexing order identifier, a bit-by-bit conversion of the specified length for each bit of the multiplexed signal in a preset direction until the same parallel data as the plurality of cell headers is obtained.
5. 一种交换板， 其特征在于， 所述交换板包括： A switch board, wherein the switch board includes:
接收模块， 用于接收从线卡来的待发送信元组成的复用信号， 所述复用信号中的多个信 元头携带复用顺序标识；  a receiving module, configured to receive a multiplexed signal consisting of a to-be-transmitted cell from the line card, where the multiple cell headers of the multiplexed signal carry a multiplexing sequence identifier;
转换模块， 用于根据预存的所述复用顺序标识， 以移位的方式对所述接收模块收到的复 用信号进行串并转换得到并行数据； 交换模块， 用于对所述转换模块得到的并行数据分别进行交换并输出。 a conversion module, configured to perform serial-to-parallel conversion on the multiplexed signal received by the receiving module according to the pre-stored multiplexing sequence identifier to obtain parallel data; And a switching module, configured to exchange and output parallel data obtained by the conversion module.
6.根据权利要求 5所述的交换板，其特征在于，所述多个信元头的复用顺序标识均不同， 所述转换模块具体包括： The switch board according to claim 5, wherein the multiplexing sequence identifiers of the plurality of cell headers are different, and the converting module specifically includes:
移位转换单元， 用于根据预存的所述复用顺序标识， 按照预设的方向对所述接收模块收 到的复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到并行数据， 所述 并行数据中包含所述复用信号中的多个信元头中的任一个信元头， 且该信元头在所述并行数 据中的位置与该信元头在所述多个信元头中的位置相同。  a shift conversion unit, configured to perform a serial-to-parallel conversion of a specified length for each multiplexed signal received by the receiving module according to a preset direction, according to the pre-stored multiplexing sequence identifier, until obtained Parallel data, wherein the parallel data includes any one of a plurality of cell headers in the multiplexed signal, and a location of the cell header in the parallel data and the cell header are in the The locations in multiple cell headers are the same.
7.根据权利要求 5所述的交换板，其特征在于，所述多个信元头的复用顺序标识均相同， 所述转换模块具体包括： The switch board according to claim 5, wherein the multiplexing order identifiers of the plurality of cell headers are the same, and the converting module specifically includes:
移位转换单元， 用于根据预存的所述复用顺序标识， 按照预设的方向对所述接收模块收 到的复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到与所述复用信号 中的多个信元头相同的并行数据为止。  a shift conversion unit, configured to perform a serial-to-parallel conversion of a specified length for each multiplexed signal received by the receiving module according to a preset direction, according to the pre-stored multiplexing sequence identifier, until obtained Up to the same parallel data as the plurality of cell headers in the multiplexed signal.
8. 一种线卡， 其特征在于， 所述线卡包括： A line card, wherein the line card comprises:
复用模块， 用于对多个待发送信元进行复用， 得到复用信号， 并按照复用的顺序， 给所 述复用信号中的多个信元头添加复用顺序标识；  a multiplexing module, configured to multiplex a plurality of to-be-transmitted cells to obtain a multiplexed signal, and add a multiplexing sequence identifier to the plurality of cell headers in the multiplexed signal according to a multiplexing sequence;
发送模块， 用于发送所述复用模块得到的复用信号。  And a sending module, configured to send the multiplexed signal obtained by the multiplexing module.
9. 一种速率适配的设备， 其特征在于， 所述设备包括： A rate-adaptable device, the device comprising:
线卡， 用于发送由待发送信元组成的复用信号， 所述复用信号中的多个信元头携带复用 顺序标识；  a line card, configured to send a multiplexed signal composed of cells to be sent, where multiple cell headers in the multiplexed signal carry a multiplexed sequence identifier;
交换板， 用于接收所述线卡发来的复用信号， 根据预存的所述复用顺序标识， 以移位的 方式对所述复用信号进行串并转换得到并行数据，然后对所述并行数据分别进行交换并输出。  a switching board, configured to receive a multiplexed signal sent by the line card, perform serial-to-parallel conversion on the multiplexed signal to obtain parallel data according to the pre-stored multiplexing sequence identifier, and then perform the Parallel data is exchanged and output separately.
10. 根据权利要求 9所述的速率适配的设备， 其特征在于， 所述线卡具体包括： 复用模块， 用于对多个待发送信元进行复用， 得到复用信号， 并按照复用的顺序， 给所 述复用信号中的多个信元头添加复用顺序标识； The rate-adaptive device according to claim 9, wherein the line card specifically includes: a multiplexing module, configured to multiplex a plurality of to-be-transmitted cells, obtain a multiplexed signal, and follow a sequence of multiplexing, adding a multiplexing order identifier to a plurality of cell headers in the multiplexed signal;
发送模块， 用于发送所述复用模块得到的复用信号。 And a sending module, configured to send the multiplexed signal obtained by the multiplexing module.
11 . 根据权利要求 9所述的速率适配的设备， 其特征在于， 所述交换板具体包括： 接收模块， 用于接收所述线卡发来的复用信号， 所述复用信号中多个信元头携带的复用 顺序标识均不同； The rate-adaptive device according to claim 9, wherein the switch board specifically includes: a receiving module, configured to receive a multiplexed signal sent by the line card, where the multiplexed signal is multiple The multiplexing order identifiers carried by the cell headers are different;
转换模块， 用于根据预存的所述复用顺序标识， 按照预设的方向对所述接收模块收到的 复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到并行数据， 所述并行 数据中包含所述复用信号中的多个信元头中的任一个信元头， 且该信元头在所述并行数据中 的位置与该信元头在所述多个信元头中的位置相同；  a conversion module, configured to perform, according to the pre-stored multiplexing sequence identifier, a bit of a specified length of the multiplexed signal received by the receiving module according to a preset direction, and perform a serial-to-parallel conversion of the specified length until the parallel data is obtained. And the parallel data includes any one of a plurality of cell headers in the multiplexed signal, and the location of the cell header in the parallel data and the cell header are in the plurality of The position in the cell header is the same;
交换模块， 用于对所述转换模块得到的并行数据分别进行交换并输出。  And a switching module, configured to exchange and output parallel data obtained by the conversion module.
12. 根据权利要求 9所述的速率适配的设备， 其特征在于， 所述交换板具体包括： 接收模块， 用于接收所述线卡发来的复用信号， 所述复用信号中多个信元头携带的复用 顺序标识均相同； The rate-adaptive device according to claim 9, wherein the switch board specifically includes: a receiving module, configured to receive a multiplexed signal sent by the line card, where the multiplexed signal is multiple The multiplexing order identifiers carried by the cell headers are the same;
转换模块， 用于根据预存的所述复用顺序标识， 按照预设的方向对所述接收模块收到的 复用信号每移动一个比特位， 进行一次指定长度的串并转换， 直到得到与所述复用信号中的 多个信元头相同的并行数据为止；  a conversion module, configured to perform, according to the pre-stored multiplexing sequence identifier, a bit of a specified length of the multiplexed signal received by the receiving module according to a preset direction, and perform a serial-to-parallel conversion of the specified length until the Decoding the same parallel data of multiple cell headers in the signal;
交换模块， 用于对所述转换模块得到的并行数据分别进行交换并输出。  And a switching module, configured to exchange and output parallel data obtained by the conversion module.
PCT/CN2008/073804 2007-12-29 2008-12-29 Rate adapting method and apparatus, exchange board and line card WO2009086778A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200710306070.X 2007-12-29
CN200710306070XA CN101471793B (en) 2007-12-29 2007-12-29 Method and equipment for adapting velocity, exchange plate and cable fastener

Publications (1)

Publication Number Publication Date
WO2009086778A1 true WO2009086778A1 (en) 2009-07-16

Family

ID=40828936

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2008/073804 WO2009086778A1 (en) 2007-12-29 2008-12-29 Rate adapting method and apparatus, exchange board and line card

Country Status (2)

Country Link
CN (1) CN101471793B (en)
WO (1) WO2009086778A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103580786B (en) * 2012-07-27 2018-01-19 中兴通讯股份有限公司 Reduce the method and system of TDM service delay variation
CN106921436B (en) * 2015-12-26 2019-11-05 华为技术有限公司 The method and device handled for the data to a variety of rates

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5553302A (en) * 1993-12-30 1996-09-03 Unisys Corporation Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data
CN1115838C (en) * 1998-09-04 2003-07-23 三星电子株式会社 Method for interfacing rate-adapting processing unit (RAPU) with board messenger processing unit (BMPU)
CN1812315A (en) * 2005-01-25 2006-08-02 华为技术有限公司 Multi-channel data signal processing method and apparatus
CN1983917A (en) * 2005-12-14 2007-06-20 中兴通讯股份有限公司 Method and structure for realizing progrmmable logic device data exchange

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5553302A (en) * 1993-12-30 1996-09-03 Unisys Corporation Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data
CN1115838C (en) * 1998-09-04 2003-07-23 三星电子株式会社 Method for interfacing rate-adapting processing unit (RAPU) with board messenger processing unit (BMPU)
CN1812315A (en) * 2005-01-25 2006-08-02 华为技术有限公司 Multi-channel data signal processing method and apparatus
CN1983917A (en) * 2005-12-14 2007-06-20 中兴通讯股份有限公司 Method and structure for realizing progrmmable logic device data exchange

Also Published As

Publication number Publication date
CN101471793B (en) 2011-05-18
CN101471793A (en) 2009-07-01

Similar Documents

Publication Publication Date Title
US6862293B2 (en) Method and apparatus for providing optimized high speed link utilization
KR100750880B1 (en) Switching system and its mechanism which enables data-switching of variable-length packets and heterogeneous network packets
US5502719A (en) Path allocation system and method having double link list queues implemented with a digital signal processor (DSP) for a high performance fiber optic switch
CN101277196B (en) Communication system, communication method and cable fastener plate based on PCIE switching network
EP2963874A1 (en) Data scheduling and switching method, apparatus, and system
JP2001524727A (en) Low latency shared memory switch structure
WO2017092394A1 (en) Data transmission method and apparatus
CN101242284B (en) Communication method and network device based on SPI bus
JPH10126412A (en) Method and system for transmitting atm cell through atm link
CN101202634B (en) Single board improving data utilization ratio and system and method of data transmission
CN108614792B (en) 1394 transaction layer data packet storage management method and circuit
WO2009086778A1 (en) Rate adapting method and apparatus, exchange board and line card
JP3097921B2 (en) Signal receiving and transmitting unit
CN108650160B (en) Bus bridge based on chain type port and working method thereof
WO2013159501A1 (en) Data transmission system, data interface device and data transmission method used among multiple servers
WO2011057447A1 (en) Router and cluster router
Obara et al. High speed transport processor for broad-band burst transport system
WO2014198156A1 (en) Method, device and system for sharing optical module
CN103401739A (en) Node device for supporting sensing access and light packet transmission
JPS5846099B2 (en) Common line access control method
Luo et al. A low power and delay multi-protocol switch with IO and network virtualization
CN117596309A (en) Message conversion system for multiple high-speed interface protocols
KR970049474A (en) Data exchange apparatus and method for providing group communication
CN114867067A (en) Device and method for multi-level message caching of distributed communication equipment
CN113746752A (en) Method and system for quick communication of series modules

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08870120

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08870120

Country of ref document: EP

Kind code of ref document: A1