WO2009081450A1 - Plasma display unit - Google Patents

Plasma display unit Download PDF

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Publication number
WO2009081450A1
WO2009081450A1 PCT/JP2007/001454 JP2007001454W WO2009081450A1 WO 2009081450 A1 WO2009081450 A1 WO 2009081450A1 JP 2007001454 W JP2007001454 W JP 2007001454W WO 2009081450 A1 WO2009081450 A1 WO 2009081450A1
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WO
WIPO (PCT)
Prior art keywords
reset
electrode
period
display
vertical synchronization
Prior art date
Application number
PCT/JP2007/001454
Other languages
French (fr)
Japanese (ja)
Inventor
Kazuya Yamaguchi
Yoshikazu Kanazawa
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP2007/001454 priority Critical patent/WO2009081450A1/en
Publication of WO2009081450A1 publication Critical patent/WO2009081450A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present invention relates to a plasma display device, and more particularly to a plasma display device with reduced black display luminance.
  • Plasma display devices are widely used as large-screen thin TVs.
  • the panel drive control of the plasma display device is composed of an address period in which a display image is written in the cell, a sustain period in which the cell written in the address period is brightened, and a reset period in which the state of the wall charge of the cell is reset.
  • the One frame image is displayed in gray scale by a plurality of subfields including a reset period, an address period, and a sustain period. By changing the number of times of light emission in the sustain period of each subfield and combining the subfields to be lit, multi-gradation display becomes possible.
  • the plasma display panel has a plurality of pairs of X and Y electrodes extending in the horizontal direction and a plurality of address electrodes extending in the vertical direction.
  • the X and Y electrodes are display electrodes, and a display line is formed by a pair of display electrodes composed of X and Y electrodes.
  • reset discharge is generated between the X and Y electrodes and between the Y electrode and the address electrode in the reset period to adjust the wall charge amount on the display electrode and the address electrode, and write data is written to the address electrode in the address period.
  • a scan pulse is applied to the Y electrode to generate an address discharge to form a wall charge in the cell
  • a sustain pulse is alternately applied between the X and Y electrodes in the sustain period to sustain the written cell. Generate a discharge. As a result, luminance display according to the number of sustain pulses is made possible.
  • the emission luminance of the phosphor accompanying the discharge is directly related to the image display.
  • the reset discharge in the reset period is a discharge for adjusting the wall charge amount and is not related to image display, and is therefore referred to as background light emission. This background light emission occurs even in black display in which all subfields are not lit, so that the luminance of black display is increased and the contrast, which is the luminance ratio of white display and black display, is deteriorated.
  • Patent Documents 1 and 2 A driving method for reducing background light emission is described in Patent Documents 1 and 2.
  • the background light emission is reduced by reducing the reset discharge scale in the reset period, and a high voltage pulse is generated just before the sustain period so that a discharge occurs in the lighting cell even with the wall charge at the time of reset.
  • a charge forming period to be applied is provided.
  • Patent Document 2 in order to suppress the luminance of black display as much as possible, a reset discharge is executed for a display cell in which display data exists, and a reset is performed for a cell in black display in which no display data exists. It is described that no discharge is performed.
  • an object of the present invention is to provide a plasma display device capable of reducing background light emission in black display.
  • a plasma display device includes a display panel having a plurality of display electrodes and a plurality of address electrodes crossing the display electrodes, and the display electrodes and the address electrodes. And a drive unit for driving.
  • the drive unit In the normal display state where the input video data does not correspond to black display, the drive unit has a reset period for generating a first reset discharge and a second reset discharge in the display electrode in a continuous vertical synchronization period.
  • the subfield having an address period for selecting a cell corresponding to display data based on the input video data and a sustain period for generating a sustain discharge in the selected cell is driven at least once in a predetermined number of vertical synchronization periods.
  • the drive unit generates the first reset discharge in at least one subfield in the first vertical synchronization period when the input video data is in a black display state corresponding to black display, and the first reset discharge is generated in the first vertical synchronization period.
  • the second reset release is performed in at least one subfield.
  • the luminance of the background light emission due to the reset discharge can be reduced.
  • the drive unit generates a first reset discharge by applying a positive blunt wave reset pulse to the first display electrode in the reset period, A negative blunt wave reset pulse is applied to the first display electrode to generate the second reset discharge.
  • the drive unit does not apply a pulse for selecting a cell in the address period to the display electrode and the address electrode in the black display state, and the drive unit in the sustain period.
  • a pulse for generating a sustain discharge is not applied to the display electrode.
  • the first and second vertical synchronization periods occur alternately, or the first and second vertical synchronization periods are between them. Are alternately generated with the third vertical synchronization period interposed therebetween.
  • the drive unit generates the first reset discharge in a single subfield in the first vertical synchronization period in the black display state, In the second vertical synchronization period, the second reset discharge is generated in a single subfield.
  • the second reset discharge is caused by applying a negative obtuse wave reset pulse twice and the reset discharge between the display electrode and the address electrode. And a reset discharge between the display electrodes.
  • the present invention it is possible to reduce the luminance of background light emission while generating a reset discharge for charge adjustment in a black display operation.
  • Display panel 30 Display panel 30, 33, 34: Display electrode drive circuit 35: Address electrode drive circuit 36: Control unit 42: Display data processing unit Video: Input video data A-DATA: Display data
  • FIG. 1 is a panel configuration diagram of the plasma display device according to the present embodiment.
  • a front substrate 11 and a rear substrate 16 are arranged with a discharge space interposed therebetween.
  • a plurality of pairs of an X electrode composed of a transparent electrode 12 and a metal bus electrode 13 superimposed thereon, and a Y electrode composed of a transparent electrode 14 and a metal bus electrode 15 superimposed thereon are arranged.
  • These X and Y electrodes are covered with a dielectric layer IFa.
  • the X and Y electrodes constitute display electrodes, and the X and Y electrodes are arranged for each display line.
  • the rear substrate 16 has a plurality of address electrodes 17, partition walls 18 disposed between the address electrodes 17, and phosphor layers 19R, 19G, and 19B provided on the address electrodes 17 and the partition walls 18. .
  • the phosphor layers 19R, 19G, and 19B are excited by ultraviolet rays that are generated when a discharge occurs in the discharge space, and emit red, green, and blue light, respectively.
  • the emitted light passes through the transparent electrodes 12 and 14 of the front substrate 11 and is emitted to the front side.
  • the barrier ribs 18 have a stripe shape along the address electrodes 17. However, the barrier ribs 18 may have a lattice shape surrounding the periphery of the cell.
  • FIG. 2 is a cross-sectional view of the panel of FIG.
  • FIG. 2 is a cross-sectional view taken along the address electrode 17 of FIG. 1 and is given the same reference numbers as FIG. That is, on the front substrate 11, an X electrode composed of the transparent electrode 12 and the metal bus electrode 13, a Y electrode composed of the transparent electrode 14 and the metal bus electrode 15, and a dielectric layer IFa covering them are formed. Further, a protective film 21 made of MgO and single crystal MgO particles 22 are disposed on the dielectric layer IFa.
  • the MgO of the protective film 21 is a polycrystal formed by vapor deposition or sputtering, whereas the MgO particles 22 are single crystal.
  • address electrodes 17, a dielectric layer IFb covering the address electrodes 17, and a phosphor 19 are formed on the rear substrate 16.
  • the partition wall 18 is not shown.
  • FIG. 3 is a configuration diagram of the drive unit of the plasma display device in the present embodiment.
  • the panel 10 is shown in a state where the front substrate 11 and the rear substrate 16 overlap each other.
  • the X electrodes X and Y electrodes Y extending in the horizontal direction are alternately arranged, and the address electrodes ADD extending in the vertical direction are provided.
  • a cell CELL is formed at the intersection of the X and Y electrode pair and the address electrode ADD.
  • the drive unit is controlled by the X electrode drive circuit 30 that drives the X electrode, the Y electrode drive circuit 32 that drives the Y electrode, the address electrode drive circuit 35 that drives the address electrode, and the drive circuits 30, 32, and 35. And a control circuit 36 for supplying signals S30, S32, and S35 to control the driving operation of the driving circuit.
  • the control circuit 36 is constituted by a microcomputer, for example.
  • the X electrode drive circuit 30 and the Y electrode drive circuit 32 constitute a display electrode drive circuit.
  • the X electrode drive circuit 30 applies a common drive pulse to all the X electrodes, applies a reset pulse and an address voltage to the X electrodes, and applies a sustain pulse to the X electrodes.
  • a sustain driving circuit X-SUS a sustain driving circuit X-SUS.
  • the Y electrode drive circuit 32 includes a scan drive circuit Y-SCAN that sequentially applies a scan pulse to the Y electrode, a reset address drive circuit YR / A that applies a reset pulse and an address voltage to the Y electrode, And a sustain drive circuit Y-SUS for applying a sustain pulse to the electrodes.
  • the control circuit 36 receives the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the synchronization clock CLK, and the RGB video data signals R, G, Bdata, and the drive control signals 30S, 32S, necessary for driving the panel 10.
  • 35S is supplied to each drive circuit 30, 32, 35.
  • the control signal 35S to the address electrode drive circuit 35 includes display data generated for each subfield based on the video data signal in addition to the drive control signal.
  • a gain adjustment circuit GAIN for adjusting the gradation values of the input RGB video data signals Rdata, Gdata, and Bdata is provided in the previous stage of the control circuit 36.
  • the gain adjustment circuit GAIN adjusts the gradation values of the R, G, and B data signals in accordance with the color temperature adjustment signal CT and the hue adjustment signal C-CON to obtain the requested color temperature or hue.
  • the video data signals Rdata, Gdata, and Bdata may be analog signals or digital signals.
  • the control circuit 36 has a sustain pulse table 37. Based on the automatic power control signal APC-CON and the contrast control signal CONT-CON, the control circuit 36 sets the optimum number of sustain pulses for a plurality of subfields in one vertical synchronization period. Select a combination.
  • the automatic power control signal APC-CON is a signal for reducing the number of sustain pulses in the sub-field when the video load factor is high and the drive circuit power is expected to increase, so that the drive circuit power exceeds the reference value. Do not.
  • the contrast control signal CONT-CON further reduces the number of sustain pulses for dark images and increases the number of sustain pulses for bright images in order to increase contrast.
  • FIG. 4 is a diagram showing panel driving of the plasma display device according to the present embodiment.
  • one vertical synchronization period VT defined by one cycle of the vertical synchronization signal Vsync corresponds to one field FL
  • the one vertical synchronization period VT has a plurality of subfields SF1 to SFn.
  • Each subfield SF1 to SFn has a reset period Reset, an address period Tadd, and a sustain period Tsus.
  • the vertical synchronization period VT (field FL) and the frame are the same.
  • two vertical synchronization periods (2 fields FL) correspond to one frame.
  • the vertical synchronization period VT shown in FIG. 4 is continuously repeated in synchronization with the vertical synchronization signal Vsync.
  • FIG. 5 is a driving waveform diagram of panel driving in the normal display state of the present embodiment.
  • FIG. 5 shows a driving waveform of one subfield SF.
  • the example of FIG. 5 is an example in which the sustain pulse Psus has positive and negative sustain voltages + Vs and ⁇ Vs.
  • the Y electrode driving circuit 32 rises from the voltage Ve with a predetermined gradient to the positive ultimate voltage + Vw (> Vs).
  • a positive blunt wave pulse Presp is applied to the Y electrode.
  • a weak reset discharge is continuously generated between the X and Y electrodes, and a positive charge on the X electrode and a negative charge on the Y electrode as wall charges, respectively. It is formed.
  • the X electrode drive circuit 30 applies a positive voltage + Vx (+ Vs) to the X electrode, and the Y electrode drive circuit 32 temporarily lowers the Y electrode from the voltage + Vw, and further with a predetermined slope.
  • a negative blunt wave pulse Presn that decreases in potential and reaches a negative ultimate voltage ⁇ Vy + ⁇ is applied to the Y electrode.
  • a weak discharge is generated between X and Y, and the wall charges on the X and Y electrodes accumulated by the reset discharge by the positive blunt wave pulse Presp are reduced.
  • the wall charge amount is adjusted to be optimal for discharge.
  • a weak discharge is generated between the address electrode ADD and the Y electrode, and the wall charge on the address electrode is adjusted.
  • the X electrode drive circuit 30 maintains the X electrode at the positive voltage + Vx, and the reset address drive circuit YR / A in the Y electrode drive circuit 32 sets all the Y electrodes to be negative. While maintaining the voltage Vsc, the scan driving circuit Y-SCAN sequentially applies the scan pulse Psc of the negative voltage ⁇ Vy to the Y electrode. In synchronization with the application of the scan pulse Psc to the Y electrode, the address electrode drive circuit 35 applies the address pulse Padd having the address voltage Va to the address electrode ADD corresponding to the display data.
  • the sustain drive circuits X-SUS and Y-SUS of the X and Y electrode drive circuits 30 and 32 are generated between the positive sustain voltage + Vs and the negative sustain voltage -Vs.
  • the pulse Psus is applied alternately to the Y electrode and the X electrode.
  • the sustain pulse Psus is applied, the voltage applied between the X and Y electrodes is superimposed with the voltage due to the negative charge and the positive charge accumulated in the address period, and a sustain discharge is generated in the cell written in the address period.
  • the number of sustain pulses is set to a number corresponding to the luminance weight given to each subfield, and a sustain discharge occurs in the lighted cell in which the address discharge has occurred, and the luminance corresponding to each subfield is output. .
  • the luminance in the field or frame period can be made to correspond to the gradation value of the input video signal.
  • FIG. 6 is a driving waveform diagram of panel driving in the normal display state of the present embodiment.
  • FIG. 6 shows a driving waveform of one subfield SF.
  • the example of FIG. 6 is an example in which the sustain pulse Psus has the ground GND and the positive sustain voltage +2 Vs around the voltage + Vs.
  • the sustain drive circuits X-SUS and Y-SUS only need to have positive power supply voltages + Vs and +2 Vs in addition to the ground GND, the circuit configuration is simple compared to the case of FIG. It becomes.
  • the drive waveform of the X electrode has the ground GND, the address voltage 2Vx, and the sustain voltage + 2Vs around the voltage Vs, and the drive waveform of the X electrode of FIG. 5 is increased by the voltage Vs.
  • the waveform is shifted. That is, the sustain pulse Psus is a pulse between the ground GND and + 2Vs.
  • the power supply of the X electrode drive circuit 30 is only the positive power supply voltages + Vs, + 2Vx, + 2Vs.
  • the drive waveform of the Y electrode is the same as that in FIG. 5 in the reset period Reset and the address period Tadd, and the sustain pulse Psus in the sustain period Tsus is a pulse between the ground GND and +2 Vs.
  • the drive waveforms shown in FIGS. 5 and 6 are drive waveforms in the first subfield SF1 among the plurality of subfields SF in the vertical synchronization period VT shown in FIG.
  • the other subfields SF2 to SFn there is no first reset waveform in the first half in the reset period Treset of the drive waveforms in FIGS. 5 and 6, and the second reset waveform in the second half, that is, while applying ⁇ Vx to the X electrode. Only a reset waveform for applying a negative blunt wave pulse Presn to the Y electrode is formed.
  • the sustain discharge using the Y electrode as the anode and the X electrode as the cathode becomes the last discharge, and the state before the reset period of the subfields SF2 to SFn starts.
  • positive charges and negative charges are accumulated as wall charges on the X electrode of the cell that is lit in the sustain period of the immediately preceding subfield.
  • the amount of wall charges of the cell lit in the immediately preceding subfield is adjusted by the reset discharge by the negative blunt wave pulse Presn.
  • the drive waveforms in the address period and the sustain period of the subfields SF2 to SFn are the same as those in FIGS.
  • the first reset discharge by the positive blunt wave pulse and the second reset discharge by the negative blunt wave pulse are performed, and in the remaining subfields Only the second reset discharge by the negative obtuse wave pulse is performed. Furthermore, the subfield having the first and second reset discharges may be performed only once in a plurality of vertical synchronization periods VT. Thereby, the background light emission luminance in the normal display state can be reduced.
  • FIG. 7 is a diagram showing continuous vertical synchronization periods in the present embodiment. As shown in FIG. 7, the vertical synchronization period VT defined in synchronization with the vertical synchronization signal Vsync is continuously generated. However, FIG. 7 shows only two vertical synchronization periods 1VT and 2VT.
  • the vertical synchronization signal Vsyc has a frequency of 60 Hz, and the vertical synchronization period VT is 1/60 sec.
  • the control circuit 36 shown in FIG. 3 controls the drive circuits 30, 32, and 35 in the normal display state when detecting that all the RGB gradation values of the video data signal input from the gain adjustment circuit GAIN are not zero. . Further, when the control circuit 36 detects that all the gradation values of RGB of the video data signal are zero, it controls the drive circuits 30, 32, and 35 in the black display state.
  • the control circuit 36 repeats the subfield based on the drive waveform shown in FIGS. 5 and 6 and the subfield based on the drive waveform excluding the reset waveform due to the positive obtuse wave pulse Presp from FIGS. Then, drive control is performed in the vertical synchronization period VT. As a result, an image corresponding to the video data signal is displayed.
  • the control circuit 36 causes the X and Y electrode drive circuit and the address electrode drive circuit to generate a drive waveform for the reset period (both the first and second reset pulses), and for the address period and the sustain period. The scan pulse, address pulse, and sustain pulse are not generated.
  • the reset period shown in FIGS. Driving is performed to stop driving in the address period and the sustain period.
  • the second black display operation only the first reset discharge by the first reset pulse Presp in the reset period is performed in the first vertical synchronization period 1VT.
  • the second vertical synchronization period 2VT that occurs after the vertical synchronization period 1VT, only the second reset discharge by the second reset pulse Presn in the reset period is performed.
  • the driving in the address period and the sustain period is not performed in each subfield. Therefore, even if the first reset discharge and the second reset discharge are performed in the different vertical synchronization periods 1VT and 2VT, as described in FIG.
  • the panel can be operated in the reset period.
  • the first and second vertical synchronization periods 1VT and 2VT may be generated alternately or alternately with one or a plurality of third vertical synchronization periods interposed therebetween. May occur.
  • both the first and second reset operations shown in FIGS. 5 and 6 are performed intermittently in successive vertical synchronization periods, that is, every other or every second vertical synchronization period. Can also be considered. However, in that case, the luminance of background light emission by one reset including the first and second reset operations is not reduced, and the frequency of background light emission is reduced. Therefore, there is a possibility that background light emission is recognized as flicker by human eyes, which is not preferable as compared with the second black display operation.
  • FIG. 8 is a diagram showing a drive waveform in the first black display operation in the present embodiment.
  • FIG. 8 shows the drive waveform of the first subfield in the vertical synchronization period, and corresponds to the drive waveform centered on the ground GND of FIG.
  • the Y electrode drive circuit 30 applies the first obtuse wave reset pulse Presp that gradually increases from the voltage Ve to Vw while the X electrode drive circuit 30 applies ⁇ Vx to the X electrode. Apply to.
  • the Y electrode drive circuit 32 temporarily reduces the potential of the Y electrode from Vw and then gradually decreases to the voltage ⁇ Vy + ⁇ .
  • a second blunt wave reset pulse Presn is applied to the Y electrode.
  • the Y electrode drive circuit 32 does not apply the scan pulse to the Y electrode, and the address electrode drive circuit 35 does not apply the address pulse to the address electrode. Therefore, address discharge does not occur. Further, in the sustain period Tsus, the X and Y electrode drive circuits 30 and 32 maintain the X and Y electrodes at the ground GND and do not apply a sustain pulse to the X and Y electrodes.
  • FIG. 9 is a diagram showing a drive waveform in the first black display operation in the present embodiment.
  • the drive waveform of the first one subfield in the vertical synchronization period is shown and corresponds to the drive waveform centered on the voltage Vs in FIG. Therefore, also in FIG. 9, the positive blunt wave reset pulse Presp and the negative blunt wave reset pulse Presn are applied to the Y electrode in the reset period Treset, and a pulse that drops from the voltage Vs to the ground GND is applied to the X electrode. .
  • the drive waveform of the X electrode is a voltage centered on Vs.
  • the drive waveforms of the address electrode and the Y electrode are the same as in FIG.
  • FIGS. 10 and 11 are diagrams showing drive waveforms in the second black display operation in the present embodiment.
  • FIGS. 10 and 11 also show driving waveforms of one subfield, and correspond to driving waveforms using + Vs and ⁇ Vs power sources with the ground GND in FIGS. 5 and 8 as the center.
  • a positive blunt wave reset pulse Presp is applied by the drive waveform shown in FIG. 10 in the first vertical synchronization period to generate the first reset discharge, and the first vertical synchronization period.
  • a negative blunt wave reset pulse Presn is applied by the drive waveform shown in FIG. 11 to generate a second reset discharge.
  • FIG. 10 shows a drive waveform in one subfield, for example, the first subfield in the first vertical synchronization period 1VT.
  • the Y electrode drive circuit 32 applies the voltage Ve to the Y electrode
  • the X electrode drive circuit 30 applies a voltage that gradually decreases from the ground GND to ⁇ Vx to the X electrode. This generates a weak reset discharge between the X and Y electrodes.
  • the X electrode driving circuit 30 keeps the X electrode at ⁇ Vx
  • the Y electrode driving circuit 32 applies the obtuse wave pulse Presp that gradually increases from the voltage Ve to Vw. This generates a weak reset discharge between the X and Y electrodes.
  • both the X and Y electrodes are maintained at the ground GND. Further, all the electrodes are maintained at the ground GND even in the address period Tadd and the sustain period Tsus. No scan pulse or sustain pulse is applied. In other words, in the first vertical synchronization period 1VT, only the first reset discharge is generated by the positive reset pulse Presp.
  • FIG. 11 shows driving waveforms in one subfield, for example, the first subfield, in the second vertical synchronization period 2VT after the first vertical synchronization period 1VT.
  • the X electrode drive circuit 30 applies a voltage + Vx to the X electrode
  • the Y electrode drive circuit 32 applies a negative blunt wave reset pulse Presn that gradually decreases from the ground to the voltage ⁇ Vy + ⁇ to the Y electrode. .
  • the amount of charge formed on the X and Y electrodes is reduced and adjusted to an appropriate amount.
  • the X, Y electrodes and address electrodes are kept at ground.
  • the scan pulse and the sustain pulse are not applied in the address period Tadd and the sustain period Tsus. In other words, in the second vertical synchronization period 2VT, only the second reset discharge is generated by the negative reset pulse Presn.
  • FIGS. 12 and 13 are diagrams showing drive waveforms in the second black display operation in the present embodiment.
  • FIGS. 12 and 13 also show driving waveforms of one subfield, and correspond to driving waveforms using +2 Vs, GND power supply with Vs in FIGS. 6 and 9 as the center. The rest is the same as FIG. 10 and FIG.
  • FIG. 12 shows a drive waveform of one subfield within the first vertical synchronization period 1VT.
  • the drive waveform of the X electrode is the ground GND and the voltage Vs.
  • the drive waveforms of the address electrode and the Y electrode are the same as in FIG. As shown in FIG. 12, only the first reset discharge is generated by the positive reset pulse Presp in the first vertical synchronization period 1VT.
  • FIG. 13 shows a drive waveform of one subfield in the second vertical synchronization period 2VT.
  • the drive waveform of the X electrode is the voltage Vs, + 2Vx.
  • the drive waveforms of the address electrode and the Y electrode are the same as in FIG. In the second vertical synchronization period 2VT, only the second reset discharge is generated by the negative reset pulse Presn.
  • the wall charges on the X and Y electrodes are erased by the positive blunt wave reset pulse Presp in the first vertical synchronization period. Generates wall charges of opposite polarity. Then, the amount of wall charges on the X and Y electrodes is adjusted by the negative blunt wave reset pulse Presn in the second vertical synchronization period. Since electrode driving is not performed in the address period and the sustain period, even if the first reset discharge and the second reset discharge are performed in different vertical synchronization periods, the same wall charge reset action as the reset operation in the normal display operation Can be obtained.
  • the two reset discharges are performed in different vertical synchronization periods, the luminance of the background light emission due to each reset discharge can be lowered, and the occurrence of flicker can be suppressed.
  • FIGS. 14 and 15 are diagrams showing modified examples of drive waveforms in the second black display operation in the present embodiment. 14 corresponds to the drive waveform centered on the ground GND in FIGS. 5 and 8, and FIG. 15 corresponds to the drive waveform centered on + Vs in FIGS.
  • the second reset discharge includes a reset discharge generated between the Y electrode and the address electrode by applying a negative blunt wave reset pulse Presn to the Y electrode while maintaining the X electrode at the ground GND, and the X electrode. Is maintained at the voltage + Vx, and a negative discharge wave reset pulse Presn is applied to the Y electrode to generate a reset discharge generated between the Y electrode and the X electrode.
  • the wall charge amount can be more accurately determined. Adjustments can be made.
  • the second reset discharge includes a reset discharge generated between the Y electrode and the address electrode by maintaining the X electrode at the voltage Vs and applying a negative blunt wave reset pulse Presn to the Y electrode,
  • a reset discharge is generated between the Y electrode and the X electrode by maintaining the electrode at the voltage + 2Vx and applying a negative blunt wave reset pulse Presn to the Y electrode.
  • a first vertical synchronization period in which a first reset discharge is generated by a positive obtuse wave pulse and a second reset discharge is generated by a negative obtuse wave pulse.
  • the luminance value of the screen in black display can be further lowered by gradually increasing the period between the vertical synchronization periods, that is, by intermittently generating the first and second vertical synchronization periods.
  • the first reset discharge by the positive obtuse wave reset pulse and the second reset by the negative obtuse wave reset pulse are performed. Since the reset discharge is executed separately, the luminance of the background light emission due to the reset discharge can be reduced, and the contrast which is the luminance ratio between the white display and the black display can be improved.
  • the first black display operation by combining the first black display operation and the second black display operation, it is possible to reduce the change in the luminance value of the screen when the normal display operation is shifted to the black display operation without any sense of incongruity.
  • the present invention can obtain useful results when applied to a plasma display device.

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

A plasma display unit has a display panel having a plurality of display electrodes and a plurality of address electrodes intersecting with the display electrodes, and a drive unit for driving the display electrodes and the address electrodes. During a continuous vertical synchronization period in a normal display state where the input video data never corresponds to the black-color display, the drive unit repeats several times a drive of the subfield having a reset period for generating a first reset discharge and a second reset discharge on the display electrodes, an addressing period for lighting cells corresponding to the display data generated in accordance with the input video data, and a sustain period for generating the sustain discharge on the lighting cells. Further, in a black-color display state where the input video data corresponds to the black-color display, the drive unit performs the black-color display driving operation to generate the first reset discharge during a first vertical synchronization period and to generate the second reset discharge during a second vertical synchronization period following the first vertical synchronization period.

Description

プラズマディスプレイ装置Plasma display device
　本発明は，プラズマディスプレイ装置に関し，特に，黒表示の輝度を低減したプラズマディスプレイ装置に関する。 The present invention relates to a plasma display device, and more particularly to a plasma display device with reduced black display luminance.
　プラズマディスプレイ装置は，大画面の薄型テレビとして普及している。プラズマディスプレイ装置のパネル駆動制御は，表示画像をセルに書き込むアドレス期間と，アドレス期間で書き込まれたセルを高輝度化するサステイン期間と，セルの壁電荷の状態をリセットするリセット期間とで構成される。そして，１つのフレーム画像は，リセット期間とアドレス期間とサステイン期間とからなる複数のサブフィールドによりその階調表示が行われる。各サブフィールドのサステイン期間での発光回数を異ならせ，点灯するサブフィールドを組み合わせることで，多階調表示を可能にする。 Plasma display devices are widely used as large-screen thin TVs. The panel drive control of the plasma display device is composed of an address period in which a display image is written in the cell, a sustain period in which the cell written in the address period is brightened, and a reset period in which the state of the wall charge of the cell is reset. The One frame image is displayed in gray scale by a plurality of subfields including a reset period, an address period, and a sustain period. By changing the number of times of light emission in the sustain period of each subfield and combining the subfields to be lit, multi-gradation display becomes possible.
　プラズマディスプレイパネルは，水平方向に延びる複数対のＸ，Ｙ電極と，垂直方向に延びる複数のアドレス電極を有する。Ｘ，Ｙ電極は表示電極であり，Ｘ，Ｙ電極からなる１対の表示電極で表示ラインを形成する。そして，パネル駆動では，リセット期間でＸ，Ｙ電極間およびＹ電極とアドレス電極間でリセット放電を発生させて表示電極とアドレス電極上の壁電荷量を調整し，アドレス期間でアドレス電極に書き込みデータを印加しＹ電極に走査パルスを印加してアドレス放電を発生させてセルに壁電荷を形成し，サステイン期間でＸ，Ｙ電極間に交互にサステインパルスを印加して，書き込まれたセルにサステイン放電を発生させる。これによりサステインパルス数に応じた輝度表示を可能にする。 The plasma display panel has a plurality of pairs of X and Y electrodes extending in the horizontal direction and a plurality of address electrodes extending in the vertical direction. The X and Y electrodes are display electrodes, and a display line is formed by a pair of display electrodes composed of X and Y electrodes. In the panel drive, reset discharge is generated between the X and Y electrodes and between the Y electrode and the address electrode in the reset period to adjust the wall charge amount on the display electrode and the address electrode, and write data is written to the address electrode in the address period. And a scan pulse is applied to the Y electrode to generate an address discharge to form a wall charge in the cell, and a sustain pulse is alternately applied between the X and Y electrodes in the sustain period to sustain the written cell. Generate a discharge. As a result, luminance display according to the number of sustain pulses is made possible.
　上記のアドレス期間およびサステイン期間での放電は，表示すべき画像データに対応して行われるので，その放電に伴う蛍光体の発光輝度は画像表示に直接関係する。しかしながら，リセット期間でのリセット放電は，壁電荷量調整のための放電であり，画像表示とは関係がないため，背景発光と称されている。この背景発光は全てのサブフィールドが非点灯になる黒表示においても発生するため，黒表示の輝度を高めてしまい，白表示と黒表示の輝度比であるコントラストを悪化させる。 Since the discharge in the address period and the sustain period is performed corresponding to the image data to be displayed, the emission luminance of the phosphor accompanying the discharge is directly related to the image display. However, the reset discharge in the reset period is a discharge for adjusting the wall charge amount and is not related to image display, and is therefore referred to as background light emission. This background light emission occurs even in black display in which all subfields are not lit, so that the luminance of black display is increased and the contrast, which is the luminance ratio of white display and black display, is deteriorated.
　背景発光を低減する駆動方法が，特許文献１，２に記載されている。特許文献１によれば，リセット期間でのリセット放電規模を低下させて背景発光を低減し，サステイン期間の直前に，リセット時の壁電荷でも点灯セルに放電が発生する程度の高電圧のパルスを印加する電荷形成期間を設けている。 A driving method for reducing background light emission is described in Patent Documents 1 and 2. According to Patent Document 1, the background light emission is reduced by reducing the reset discharge scale in the reset period, and a high voltage pulse is generated just before the sustain period so that a discharge occurs in the lighting cell even with the wall charge at the time of reset. A charge forming period to be applied is provided.
　また，特許文献２には，黒表示の輝度を可能な限り抑えるために，表示データが存在する表示セルに対してはリセット放電を実行し，表示データが存在しない黒表示となるセルにはリセット放電を実行しないことが記載されている。
特開２００４－４５１３号公報 特開２００２－７２９６１号公報 Further, in Patent Document 2, in order to suppress the luminance of black display as much as possible, a reset discharge is executed for a display cell in which display data exists, and a reset is performed for a cell in black display in which no display data exists. It is described that no discharge is performed.
JP 2004-4513 A JP 2002-72961 A
　しかしながら，特許文献１の駆動方法では，黒表示においてもリセット放電を発生させているので，背景発光の輝度を十分に低減させることはできない。また，サステイン期間の直前に電荷形成期間を設ける必要があり，また電荷形成期間ではサステインパルスよりも高電圧のパルスを印加する必要があり，駆動回路のコストアップになる。 However, in the driving method disclosed in Patent Document 1, since the reset discharge is generated even in the black display, the luminance of the background light emission cannot be sufficiently reduced. In addition, it is necessary to provide a charge formation period immediately before the sustain period, and in the charge formation period, it is necessary to apply a pulse having a higher voltage than the sustain pulse, which increases the cost of the drive circuit.
　また，特許文献２の駆動方法では，黒表示の間にリセット放電が生じないため，背景発光の輝度を低減することはできる。しかし，黒表示の間にリセット放電による壁電荷調整が行われないため，パネルのセルにおける壁電荷状態が変化し，黒表示後の通常の画像表示において最初の表示画像が乱れるという問題がある。 Further, in the driving method of Patent Document 2, since reset discharge does not occur during black display, the luminance of background light emission can be reduced. However, since wall charge adjustment by reset discharge is not performed during black display, the wall charge state in the panel cells changes, and there is a problem that the initial display image is disturbed in normal image display after black display.
　そこで，本発明の目的は，黒表示における背景発光を低減することができるプラズマディスプレイ装置を提供することにある。 Therefore, an object of the present invention is to provide a plasma display device capable of reducing background light emission in black display.
　上記の目的を達成するために，本発明の側面によれば，プラズマディスプレイ装置は，複数の表示電極と前記表示電極に交差する複数のアドレス電極とを有する表示パネルと，前記表示電極およびアドレス電極を駆動する駆動ユニットとを有する。そして，前記駆動ユニットは，入力映像データが黒表示に対応しない通常表示状態では，連続する垂直同期期間において，前記表示電極に第１のリセット放電と第２のリセット放電とを発生させるリセット期間と，前記入力映像データに基づく表示データに対応してセルを選択させるアドレス期間と，選択セルに維持放電を発生させるサステイン期間とを有するサブフィールドの駆動を所定数の垂直同期期間に少なくとも１回行い，さらに，前記駆動ユニットは，前記入力映像データが黒表示に対応する黒表示状態では，第１の垂直同期期間において少なくとも１つのサブフィールドで前記第１のリセット放電を発生させ，前記第１の垂直同期期間の後の第２の垂直同期期間において少なくとも１つのサブフィールドで前記第２のリセット放電を発生させる黒表示駆動を行う。 In order to achieve the above object, according to an aspect of the present invention, a plasma display device includes a display panel having a plurality of display electrodes and a plurality of address electrodes crossing the display electrodes, and the display electrodes and the address electrodes. And a drive unit for driving. In the normal display state where the input video data does not correspond to black display, the drive unit has a reset period for generating a first reset discharge and a second reset discharge in the display electrode in a continuous vertical synchronization period. The subfield having an address period for selecting a cell corresponding to display data based on the input video data and a sustain period for generating a sustain discharge in the selected cell is driven at least once in a predetermined number of vertical synchronization periods. Further, the drive unit generates the first reset discharge in at least one subfield in the first vertical synchronization period when the input video data is in a black display state corresponding to black display, and the first reset discharge is generated in the first vertical synchronization period. In a second vertical synchronization period after the vertical synchronization period, the second reset release is performed in at least one subfield. A black display drive that generates.
　本発明によれば，黒表示駆動で第１，第２のリセット放電を異なる垂直同期期間で行うので，リセット放電による背景発光の輝度を低減することができる。 According to the present invention, since the first and second reset discharges are performed in different vertical synchronization periods in black display driving, the luminance of the background light emission due to the reset discharge can be reduced.
　上記の本発明の側面において好ましい態様によれば，前記駆動ユニットは，前記リセット期間において，第１の表示電極に正極性の鈍波リセットパルスを印加して前記第１のリセット放電を発生させ，前記第１の表示電極に負極性の鈍波リセットパルスを印加して前記第２のリセット放電を発生させる。 According to a preferred embodiment of the above aspect of the present invention, the drive unit generates a first reset discharge by applying a positive blunt wave reset pulse to the first display electrode in the reset period, A negative blunt wave reset pulse is applied to the first display electrode to generate the second reset discharge.
　上記の本発明の側面において好ましい態様によれば，前記駆動ユニットは，前記黒表示状態では，前記アドレス期間においてセルを選択するパルスを前記表示電極及びアドレス電極に印加せず，前記サステイン期間において前記維持放電を発生させるパルスを前記表示電極に印加させない。 According to a preferred aspect of the above aspect of the present invention, the drive unit does not apply a pulse for selecting a cell in the address period to the display electrode and the address electrode in the black display state, and the drive unit in the sustain period. A pulse for generating a sustain discharge is not applied to the display electrode.
　上記の本発明の第１の側面において好ましい態様によれば，前記第１，第２の垂直同期期間は，交互に発生する，または，前記第１，第２の垂直同期期間は，それらの間に第３の垂直同期期間を挟んで交互に発生する。 According to a preferred aspect of the first aspect of the present invention, the first and second vertical synchronization periods occur alternately, or the first and second vertical synchronization periods are between them. Are alternately generated with the third vertical synchronization period interposed therebetween.
　上記の本発明の側面において好ましい態様によれば，前記駆動ユニットは，前記黒表示状態では，前記第１の垂直同期期間内において，単一のサブフィールドで前記第１のリセット放電を発生させ，前記第２の垂直同期期間内において，単一のサブフィールドで前記第２のリセット放電を発生させる。 According to a preferred aspect of the above aspect of the present invention, the drive unit generates the first reset discharge in a single subfield in the first vertical synchronization period in the black display state, In the second vertical synchronization period, the second reset discharge is generated in a single subfield.
　上記の本発明の側面において好ましい態様によれば，前記黒表示駆動において，前記第２のリセット放電が，２回の負極性の鈍波リセットパルスの印加による，表示電極とアドレス電極間のリセット放電と，表示電極間のリセット放電とを有する。 According to a preferable aspect of the above aspect of the present invention, in the black display driving, the second reset discharge is caused by applying a negative obtuse wave reset pulse twice and the reset discharge between the display electrode and the address electrode. And a reset discharge between the display electrodes.
　本発明によれば，黒表示動作において電荷調整のためのリセット放電を発生しつつそれによる背景発光の輝度を低減することができる。 According to the present invention, it is possible to reduce the luminance of background light emission while generating a reset discharge for charge adjustment in a black display operation.
本実施の形態におけるプラズマディスプレイ装置のパネル構成図である。It is a panel block diagram of the plasma display apparatus in this Embodiment. 図１のパネルの断面図である。It is sectional drawing of the panel of FIG. 本実施の形態におけるプラズマディスプレイ装置の駆動ユニットの構成図である。It is a block diagram of the drive unit of the plasma display apparatus in this Embodiment. 本実施の形態におけるプラズマディスプレイ装置のパネル駆動を示す図である。It is a figure which shows the panel drive of the plasma display apparatus in this Embodiment. 本実施の形態の通常表示状態におけるパネル駆動の駆動波形図である。It is a drive waveform diagram of the panel drive in the normal display state of the present embodiment. 本実施の形態の通常表示状態におけるパネル駆動の駆動波形図である。It is a drive waveform diagram of the panel drive in the normal display state of the present embodiment. 本実施の形態における連続する垂直同期期間を示す図である。It is a figure which shows the continuous vertical-synchronization period in this Embodiment. 本実施の形態における第１の黒表示動作での駆動波形を示す図である。It is a figure which shows the drive waveform in the 1st black display operation | movement in this Embodiment. 本実施の形態における第１の黒表示動作での駆動波形を示す図である。It is a figure which shows the drive waveform in the 1st black display operation | movement in this Embodiment. 本実施の形態における第２の黒表示動作での駆動波形を示す図である。It is a figure which shows the drive waveform in the 2nd black display operation | movement in this Embodiment. 本実施の形態における第２の黒表示動作での駆動波形を示す図である。It is a figure which shows the drive waveform in the 2nd black display operation | movement in this Embodiment. 本実施の形態における第２の黒表示動作での駆動波形を示す図である。It is a figure which shows the drive waveform in the 2nd black display operation | movement in this Embodiment. 本実施の形態における第２の黒表示動作での駆動波形を示す図である。It is a figure which shows the drive waveform in the 2nd black display operation | movement in this Embodiment. 本実施の形態における第２の黒表示動作での駆動波形の変型例を示す図である。It is a figure which shows the modification example of the drive waveform in the 2nd black display operation | movement in this Embodiment. 本実施の形態における第２の黒表示動作での駆動波形の変型例を示す図である。It is a figure which shows the modification example of the drive waveform in the 2nd black display operation | movement in this Embodiment.
符号の説明Explanation of symbols
１０：表示パネル　　　　　　　３０，３３，３４：表示電極駆動回路
３５：アドレス電極駆動回路　　３６：制御部
４２：表示データ処理部
Ｖｉｄｅｏ：入力映像データ　　Ａ－ＤＡＴＡ：表示データ
  10: Display panel 30, 33, 34: Display electrode drive circuit 35: Address electrode drive circuit 36: Control unit 42: Display data processing unit Video: Input video data A-DATA: Display data
　以下，図面にしたがって本発明の実施の形態について説明する。但し，本発明の技術的範囲はこれらの実施の形態に限定されず，特許請求の範囲に記載された事項とその均等物まで及ぶものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.
　図１は，本実施の形態におけるプラズマディスプレイ装置のパネル構成図である。プラズマディスプレイパネル１０は，前面基板１１と背面基板１６とが放電空間を挟んで配置される。前面基板１１には，透明電極１２とその上に重ねた金属バス電極１３からなるＸ電極と，透明電極１４とその上に重ねた金属バス電極１５からなるＹ電極とが，複数対配置され，それらＸ，Ｙ電極は誘電体層ＩＦａで被覆されている。Ｘ，Ｙ電極が表示電極を構成し，表示ライン毎にＸ，Ｙ電極が配置される。また，背面基板１６には，複数のアドレス電極１７と，アドレス電極１７の間に配置された隔壁１８と，アドレス電極１７及び隔壁１８上に設けられた蛍光体層１９Ｒ，１９Ｇ，１９Ｂとを有する。蛍光体層１９Ｒ，１９Ｇ，１９Ｂは，放電空間で放電が発生した時に生成される紫外線により励起されそれぞれ赤，緑，青の光を発光する。それらの発光は前面基板１１の透明電極１２，１４を通過して前面側に出射する。図１の例では，隔壁１８はアドレス電極１７に沿ったストライプ形状であるが，セルの周囲を囲む格子形状にしてもよい。 FIG. 1 is a panel configuration diagram of the plasma display device according to the present embodiment. In the plasma display panel 10, a front substrate 11 and a rear substrate 16 are arranged with a discharge space interposed therebetween. On the front substrate 11, a plurality of pairs of an X electrode composed of a transparent electrode 12 and a metal bus electrode 13 superimposed thereon, and a Y electrode composed of a transparent electrode 14 and a metal bus electrode 15 superimposed thereon are arranged. These X and Y electrodes are covered with a dielectric layer IFa. The X and Y electrodes constitute display electrodes, and the X and Y electrodes are arranged for each display line. Further, the rear substrate 16 has a plurality of address electrodes 17, partition walls 18 disposed between the address electrodes 17, and phosphor layers 19R, 19G, and 19B provided on the address electrodes 17 and the partition walls 18. . The phosphor layers 19R, 19G, and 19B are excited by ultraviolet rays that are generated when a discharge occurs in the discharge space, and emit red, green, and blue light, respectively. The emitted light passes through the transparent electrodes 12 and 14 of the front substrate 11 and is emitted to the front side. In the example of FIG. 1, the barrier ribs 18 have a stripe shape along the address electrodes 17. However, the barrier ribs 18 may have a lattice shape surrounding the periphery of the cell.
　図２は，図１のパネルの断面図である。図１のアドレス電極１７に沿った断面図であり，図１と同じ引用番号が与えられている。つまり，前面基板１１上には，透明電極１２と金属バス電極１３からなるＸ電極と，透明電極１４と金属バス電極１５からなるＹ電極と，それらを被覆する誘電体層ＩＦａとが形成され，さらに，誘電体層ＩＦａの上にはＭｇＯからなる保護膜２１と，単結晶のＭｇＯ粒子２２とが配置される。保護膜２１のＭｇＯは蒸着法やスパッタリング法で形成される多結晶体であるのに対して，ＭｇＯ粒子２２は単結晶体である。 FIG. 2 is a cross-sectional view of the panel of FIG. FIG. 2 is a cross-sectional view taken along the address electrode 17 of FIG. 1 and is given the same reference numbers as FIG. That is, on the front substrate 11, an X electrode composed of the transparent electrode 12 and the metal bus electrode 13, a Y electrode composed of the transparent electrode 14 and the metal bus electrode 15, and a dielectric layer IFa covering them are formed. Further, a protective film 21 made of MgO and single crystal MgO particles 22 are disposed on the dielectric layer IFa. The MgO of the protective film 21 is a polycrystal formed by vapor deposition or sputtering, whereas the MgO particles 22 are single crystal.
　背面基板１６上には，アドレス電極１７と，それを被覆する誘電体層ＩＦｂと，蛍光体１９とが形成されている。図２には隔壁１８は示されていない。 On the rear substrate 16, address electrodes 17, a dielectric layer IFb covering the address electrodes 17, and a phosphor 19 are formed. In FIG. 2, the partition wall 18 is not shown.
　図３は，本実施の形態におけるプラズマディスプレイ装置の駆動ユニットの構成図である。図中，パネル１０は前面基板１１と背面基板１６とが重なった状態で示されていて，水平方向に延びるＸ電極ＸとＹ電極Ｙとが交互に配置され，垂直方向に延びるアドレス電極ＡＤＤが配置されている。Ｘ，Ｙ電極対とアドレス電極ＡＤＤとの交差位置にセルＣＥＬＬが形成される。 FIG. 3 is a configuration diagram of the drive unit of the plasma display device in the present embodiment. In the figure, the panel 10 is shown in a state where the front substrate 11 and the rear substrate 16 overlap each other. The X electrodes X and Y electrodes Y extending in the horizontal direction are alternately arranged, and the address electrodes ADD extending in the vertical direction are provided. Has been placed. A cell CELL is formed at the intersection of the X and Y electrode pair and the address electrode ADD.
　駆動ユニットは，Ｘ電極を駆動するＸ電極駆動回路３０と，Ｙ電極を駆動するＹ電極駆動回路３２と，アドレス電極を駆動するアドレス電極駆動回路３５と，それら駆動回路３０，３２，３５に制御信号Ｓ３０，Ｓ３２，Ｓ３５を供給して駆動回路の駆動動作を制御する制御回路３６とを有する。制御回路３６は，例えばマイクロコンピュータにより構成される。Ｘ電極駆動回路３０とＹ電極駆動回路３２とで表示電極駆動回路を構成する。Ｘ電極駆動回路３０は，全てのＸ電極に共通の駆動パルスを印加し，リセットパルスおよびアドレス電圧をＸ電極に印加するリセット・アドレス駆動回路Ｘ－Ｒ／Ａと，サステインパルスをＸ電極に印加するサステイン駆動回路Ｘ－ＳＵＳとを有する。また，Ｙ電極駆動回路３２は，Ｙ電極に順次走査パルスを印加する走査駆動回路Ｙ－ＳＣＡＮと，Ｙ電極にリセットパルスとアドレス電圧を印加するリセット・アドレス駆動回路Ｙ－Ｒ／Ａと，Ｙ電極にサステインパルスを印加するサステイン駆動回路Ｙ－ＳＵＳとを有する。 The drive unit is controlled by the X electrode drive circuit 30 that drives the X electrode, the Y electrode drive circuit 32 that drives the Y electrode, the address electrode drive circuit 35 that drives the address electrode, and the drive circuits 30, 32, and 35. And a control circuit 36 for supplying signals S30, S32, and S35 to control the driving operation of the driving circuit. The control circuit 36 is constituted by a microcomputer, for example. The X electrode drive circuit 30 and the Y electrode drive circuit 32 constitute a display electrode drive circuit. The X electrode drive circuit 30 applies a common drive pulse to all the X electrodes, applies a reset pulse and an address voltage to the X electrodes, and applies a sustain pulse to the X electrodes. And a sustain driving circuit X-SUS. The Y electrode drive circuit 32 includes a scan drive circuit Y-SCAN that sequentially applies a scan pulse to the Y electrode, a reset address drive circuit YR / A that applies a reset pulse and an address voltage to the Y electrode, And a sustain drive circuit Y-SUS for applying a sustain pulse to the electrodes.
　制御回路３６は，水平同期信号Ｈｓｙｎｃと垂直同期信号Ｖｓｙｎｃと同期クロックＣＬＫとＲＧＢの映像データ信号Ｒ，Ｇ，Ｂｄａｔａとを入力し，パネル１０を駆動するために必要な駆動制御信号３０Ｓ，３２Ｓ，３５Ｓをそれぞれの駆動回路３０，３２，３５に供給する。アドレス電極駆動回路３５への制御信号３５Ｓは，駆動制御信号に加えて，映像データ信号に基づいてサブフィールド毎に生成された表示データも含む。 The control circuit 36 receives the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the synchronization clock CLK, and the RGB video data signals R, G, Bdata, and the drive control signals 30S, 32S, necessary for driving the panel 10. 35S is supplied to each drive circuit 30, 32, 35. The control signal 35S to the address electrode drive circuit 35 includes display data generated for each subfield based on the video data signal in addition to the drive control signal.
　制御回路３６の前段には，入力されたＲＧＢの映像データ信号Ｒｄａｔａ，Ｇｄａｔａ，Ｂｄａｔａの階調値を調整するゲイン調整回路ＧＡＩＮが設けられている。ゲイン調整回路ＧＡＩＮは，色温度調整信号ＣＴ，色合い調整信号Ｃ－ＣＯＮに応じて，Ｒ，Ｇ，Ｂのデータ信号の階調値を調整して，映像を要求された色温度または色合いにする。映像データ信号Ｒｄａｔａ，Ｇｄａｔａ，Ｂｄａｔａは，アナログ信号またはデジタル信号のいずれでもよい。 A gain adjustment circuit GAIN for adjusting the gradation values of the input RGB video data signals Rdata, Gdata, and Bdata is provided in the previous stage of the control circuit 36. The gain adjustment circuit GAIN adjusts the gradation values of the R, G, and B data signals in accordance with the color temperature adjustment signal CT and the hue adjustment signal C-CON to obtain the requested color temperature or hue. . The video data signals Rdata, Gdata, and Bdata may be analog signals or digital signals.
　制御回路３６は，サステインパルステーブル３７を有し，自動電力制御信号ＡＰＣ－ＣＯＮおよびコントラスト制御信号ＣＯＮＴ－ＣＯＮに基づいて，一つの垂直同期期間内にある複数のサブフィールドに対する最適なサステインパルス数の組み合わせを選択する。自動電力制御信号ＡＰＣ－ＣＯＮは，映像負荷率が高くなり駆動回路の電力増加が見込まれる場合に，サブフィールドのサステインパルス数を低減する信号であり，それにより駆動回路の電力が基準値を越えないようにする。また，コントラスト制御信号ＣＯＮＴ－ＣＯＮは，コントラストを高めるために暗い映像のサステインパルス数をより低減し明るい映像のサステインパルス数をより上昇させる。 The control circuit 36 has a sustain pulse table 37. Based on the automatic power control signal APC-CON and the contrast control signal CONT-CON, the control circuit 36 sets the optimum number of sustain pulses for a plurality of subfields in one vertical synchronization period. Select a combination. The automatic power control signal APC-CON is a signal for reducing the number of sustain pulses in the sub-field when the video load factor is high and the drive circuit power is expected to increase, so that the drive circuit power exceeds the reference value. Do not. Further, the contrast control signal CONT-CON further reduces the number of sustain pulses for dark images and increases the number of sustain pulses for bright images in order to increase contrast.
　図４は，本実施の形態におけるプラズマディスプレイ装置のパネル駆動を示す図である。パネル駆動において，垂直同期信号Ｖｓｙｎｃの１周期で画定される１つの垂直同期期間ＶＴが１フィールドＦＬに対応し，その１つの垂直同期期間ＶＴが複数のサブフィールドＳＦ１～ＳＦｎを有する。各サブフィールドＳＦ１～ＳＦｎは，リセット期間Ｔｒｅｓｅｔとアドレス期間Ｔａｄｄとサステイン期間Ｔｓｕｓとをそれぞれ有する。１つのフレーム画像が１回の垂直走査で表示されるプログレッシブ駆動の場合は，垂直同期期間ＶＴ（フィールドＦＬ）とフレームとは同じである。一方，１つのフレーム画像が２回の垂直走査で表示されるインターレス駆動の場合は，２回の垂直同期期間（２フィールドＦＬ）が１つのフレームに対応する。図４に示された垂直同期期間ＶＴが垂直同期信号Ｖｓｙｎｃに同期して連続して繰り返される。 FIG. 4 is a diagram showing panel driving of the plasma display device according to the present embodiment. In panel driving, one vertical synchronization period VT defined by one cycle of the vertical synchronization signal Vsync corresponds to one field FL, and the one vertical synchronization period VT has a plurality of subfields SF1 to SFn. Each subfield SF1 to SFn has a reset period Reset, an address period Tadd, and a sustain period Tsus. In the case of progressive driving in which one frame image is displayed by one vertical scan, the vertical synchronization period VT (field FL) and the frame are the same. On the other hand, in the case of interlaced driving in which one frame image is displayed by two vertical scans, two vertical synchronization periods (2 fields FL) correspond to one frame. The vertical synchronization period VT shown in FIG. 4 is continuously repeated in synchronization with the vertical synchronization signal Vsync.
　図５は，本実施の形態の通常表示状態におけるパネル駆動の駆動波形図である。図５には，１つのサブフィールドＳＦの駆動波形が示されている。また，図５の例は，サステインパルスＰｓｕｓが正負のサステイン電圧＋Ｖｓ，－Ｖｓを有する例である。 FIG. 5 is a driving waveform diagram of panel driving in the normal display state of the present embodiment. FIG. 5 shows a driving waveform of one subfield SF. Further, the example of FIG. 5 is an example in which the sustain pulse Psus has positive and negative sustain voltages + Vs and −Vs.
　最初のリセット期間Ｔｒｅｓｅｔが開始する前の状態では，その直前のサブフィールドのサステイン期間Ｔｓｕｓで点灯したセルのＸ電極上に負電荷がＹ電極上に正電荷がそれぞれ壁電荷として蓄積されている。そして，リセット期間Ｔｒｅｓｅｔの前半では，アドレス電極駆動回路３５がアドレス電極ＡＤＤを０Ｖに保ちながら，Ｙ電極駆動回路３２がＹ電極に電圧Ｖｅ（＞Ｖｓ）を印加しＸ電極駆動回路３０がＸ電極の電位を負電圧側に所定の傾きで電圧－Ｖｘまで引き下げる。これにより，直前のサステイン期間で点灯したセルのＸ，Ｙ電極間に微弱なリセット放電が発生しＸ，Ｙ電極上の負，正電荷が消去される。 In the state before the start of the first reset period Treset, negative charges and positive charges are accumulated as wall charges on the X electrode of the cell lit in the sustain period Tsus of the immediately preceding subfield. In the first half of the reset period Treset, the Y electrode drive circuit 32 applies the voltage Ve (> Vs) to the Y electrode while the address electrode drive circuit 35 keeps the address electrode ADD at 0 V, and the X electrode drive circuit 30 Is reduced to the voltage −Vx with a predetermined slope toward the negative voltage side. As a result, a weak reset discharge is generated between the X and Y electrodes of the cell lit in the immediately preceding sustain period, and the negative and positive charges on the X and Y electrodes are erased.
　さらに，Ｘ電極駆動回路３０がＸ電極の電位を負電圧－Ｖｘに維持しながら，Ｙ電極駆動回路３２が電圧Ｖｅから所定の傾きで電位が上昇して正の到達電圧＋Ｖｗ（＞Ｖｓ）に達する正の鈍波パルスＰｒｅｓｐをＹ電極に印加する。この正極性の鈍波パルスＰｒｅｓｐの印加により，さらにＸ，Ｙ電極間に微弱なリセット放電が継続して発生し，Ｘ電極上には正電荷がＹ電極上には負電荷がそれぞれ壁電荷として形成される。 Further, while the X electrode driving circuit 30 maintains the potential of the X electrode at the negative voltage −Vx, the Y electrode driving circuit 32 rises from the voltage Ve with a predetermined gradient to the positive ultimate voltage + Vw (> Vs). A positive blunt wave pulse Presp is applied to the Y electrode. By applying the positive obtuse wave pulse Presp, a weak reset discharge is continuously generated between the X and Y electrodes, and a positive charge on the X electrode and a negative charge on the Y electrode as wall charges, respectively. It is formed.
　次に，リセット期間Ｔｒｅｓｅｔの後半では，Ｘ電極駆動回路３０が正電圧＋Ｖｘ（＋Ｖｓ）をＸ電極に印加すると共に，Ｙ電極駆動回路３２がＹ電極を電圧＋Ｖｗから一旦引き下げ，さらに所定の傾きで電位が減少して負の到達電圧－Ｖｙ＋αに達する負の鈍波パルスＰｒｅｓｎをＹ電極に印加する。この負の鈍波パルスＰｒｅｓｎにより，Ｘ，Ｙ間に微弱放電が発生し正の鈍波パルスＰｒｅｓｐによるリセット放電で蓄積されたＸ，Ｙ電極上の壁電荷が減少し，後続するアドレス期間での放電に最適な壁電荷量に調整される。さらに，負の鈍波パルスＰｒｅｓｎの印加により，アドレス電極ＡＤＤとＹ電極との間でも微弱放電が発生しアドレス電極上の壁電荷も調整される。 Next, in the second half of the reset period Treset, the X electrode drive circuit 30 applies a positive voltage + Vx (+ Vs) to the X electrode, and the Y electrode drive circuit 32 temporarily lowers the Y electrode from the voltage + Vw, and further with a predetermined slope. A negative blunt wave pulse Presn that decreases in potential and reaches a negative ultimate voltage −Vy + α is applied to the Y electrode. By this negative blunt wave pulse Presn, a weak discharge is generated between X and Y, and the wall charges on the X and Y electrodes accumulated by the reset discharge by the positive blunt wave pulse Presp are reduced. The wall charge amount is adjusted to be optimal for discharge. Further, by applying the negative blunt wave pulse Presn, a weak discharge is generated between the address electrode ADD and the Y electrode, and the wall charge on the address electrode is adjusted.
　リセット期間Ｔｒｅｓｅｔに続くアドレス期間Ｔａｄｄでは，Ｘ電極駆動回路３０がＸ電極を正電圧＋Ｖｘに維持し，Ｙ電極駆動回路３２内のリセット・アドレス駆動回路Ｙ－Ｒ／Ａが全てのＹ電極を負電圧Ｖｓｃに維持しつつ，走査駆動回路Ｙ－ＳＣＡＮがＹ電極に負電圧－Ｖｙの走査パルスＰｓｃを順番に印加する。また，Ｙ電極への走査パルスＰｓｃの印加に同期して，アドレス電極駆動回路３５は，アドレス電極ＡＤＤにアドレス電圧Ｖａを有するアドレスパルスＰａｄｄを表示データに対応して印加する。その結果，走査パルスＰｓｃが印加されたＹ電極とアドレスパルスＰａｄｄが印加されたアドレス電極との間のセルでアドレス放電が発生し，さらに，そのセルにおいて走査パルスＰｓｃが印加されたＹ電極とＸ電極との間でもアドレス放電が発生する。これにより，アドレス放電が発生したセルのＸ，Ｙ電極の誘電体層上にはそれぞれ負電荷と正電荷が壁電荷として蓄積される。これがアドレス期間での書き込み動作である。アドレスパルスＰａｄｄが印加されなかったセルにはアドレス放電が発生せずリセット状態のままである。 In the address period Tadd following the reset period Treset, the X electrode drive circuit 30 maintains the X electrode at the positive voltage + Vx, and the reset address drive circuit YR / A in the Y electrode drive circuit 32 sets all the Y electrodes to be negative. While maintaining the voltage Vsc, the scan driving circuit Y-SCAN sequentially applies the scan pulse Psc of the negative voltage −Vy to the Y electrode. In synchronization with the application of the scan pulse Psc to the Y electrode, the address electrode drive circuit 35 applies the address pulse Padd having the address voltage Va to the address electrode ADD corresponding to the display data. As a result, an address discharge is generated in the cell between the Y electrode to which the scan pulse Psc is applied and the address electrode to which the address pulse Padd is applied, and the Y electrode to which the scan pulse Psc is applied and X Address discharge also occurs between the electrodes. As a result, negative charges and positive charges are accumulated as wall charges on the dielectric layers of the X and Y electrodes of the cell in which the address discharge has occurred. This is a write operation in the address period. A cell to which no address pulse Padd is applied does not generate an address discharge and remains in a reset state.
　最後に，サステイン期間Ｔｓｕｓでは，Ｘ，Ｙ電極駆動回路３０，３２のサステイン駆動回路Ｘ－ＳＵＳ，Ｙ－ＳＵＳが，正のサステイン電圧＋Ｖｓと負のサステイン電圧－Ｖｓとの間で生成されるサステインパルスＰｓｕｓをＹ電極とＸ電極とに交互に印加する。このサステインパルスＰｓｕｓが印加されたときのＸ，Ｙ電極間の印加電圧に，アドレス期間で蓄積された負電荷と正電荷による電圧が重畳されて，アドレス期間に書き込まれたセルにサステイン放電が発生する。サステインパルスの数は，各サブフィールドに与えられた輝度の重みに対応した数に設定されていて，アドレス放電が発生した点灯セルにサステイン放電が生じて，各サブフィールドに対応した輝度を出力する。 Finally, in the sustain period Tsus, the sustain drive circuits X-SUS and Y-SUS of the X and Y electrode drive circuits 30 and 32 are generated between the positive sustain voltage + Vs and the negative sustain voltage -Vs. The pulse Psus is applied alternately to the Y electrode and the X electrode. When the sustain pulse Psus is applied, the voltage applied between the X and Y electrodes is superimposed with the voltage due to the negative charge and the positive charge accumulated in the address period, and a sustain discharge is generated in the cell written in the address period. To do. The number of sustain pulses is set to a number corresponding to the luminance weight given to each subfield, and a sustain discharge occurs in the lighted cell in which the address discharge has occurred, and the luminance corresponding to each subfield is output. .
　複数のサブフィールドの点灯と非点灯とを適宜組み合わせることにより，フィールドまたはフレーム期間での輝度を入力映像信号の階調値に対応させることができる。 ¡By appropriately combining lighting and non-lighting of a plurality of subfields, the luminance in the field or frame period can be made to correspond to the gradation value of the input video signal.
　図６は，本実施の形態の通常表示状態におけるパネル駆動の駆動波形図である。図６には，１つのサブフィールドＳＦの駆動波形が示されている。また，図６の例は，サステインパルスＰｓｕｓが電圧＋Ｖｓを中心にしてグランドＧＮＤと正のサステイン電圧＋２Ｖｓを有する例である。この例によれば，サステイン駆動回路Ｘ－ＳＵＳ，Ｙ－ＳＵＳが，グランドＧＮＤに加えて正の電源電圧＋Ｖｓ，＋２Ｖｓを有していればよいので，図５の場合に比較すると回路構成が簡素化される。 FIG. 6 is a driving waveform diagram of panel driving in the normal display state of the present embodiment. FIG. 6 shows a driving waveform of one subfield SF. Further, the example of FIG. 6 is an example in which the sustain pulse Psus has the ground GND and the positive sustain voltage +2 Vs around the voltage + Vs. According to this example, since the sustain drive circuits X-SUS and Y-SUS only need to have positive power supply voltages + Vs and +2 Vs in addition to the ground GND, the circuit configuration is simple compared to the case of FIG. It becomes.
　図６の駆動波形では，Ｘ電極の駆動波形が，電圧Ｖｓを中心にグランドＧＮＤ，アドレス電圧２Ｖｘ，サステイン電圧＋２Ｖｓの電圧を有していて，図５のＸ電極の駆動波形を電圧Ｖｓだけ高くシフトした波形になっている。つまり，サステインパルスＰｓｕｓはグランドＧＮＤと＋２Ｖｓとの間のパルスになる。これにより，Ｘ電極駆動回路３０の電源は正電源電圧＋Ｖｓ，＋２Ｖｘ，＋２Ｖｓのみとなる。 In the drive waveform of FIG. 6, the drive waveform of the X electrode has the ground GND, the address voltage 2Vx, and the sustain voltage + 2Vs around the voltage Vs, and the drive waveform of the X electrode of FIG. 5 is increased by the voltage Vs. The waveform is shifted. That is, the sustain pulse Psus is a pulse between the ground GND and + 2Vs. As a result, the power supply of the X electrode drive circuit 30 is only the positive power supply voltages + Vs, + 2Vx, + 2Vs.
　一方，Ｙ電極の駆動波形は，リセット期間Ｔｒｅｓｅｔとアドレス期間Ｔａｄｄは図５と同じであり，サステイン期間ＴｓｕｓにおけるサステインパルスＰｓｕｓがグランドＧＮＤと＋２Ｖｓとの間のパルスになっている。 On the other hand, the drive waveform of the Y electrode is the same as that in FIG. 5 in the reset period Reset and the address period Tadd, and the sustain pulse Psus in the sustain period Tsus is a pulse between the ground GND and +2 Vs.
　図６の駆動波形に対するパネルの放電動作は，図５と同じである。 The panel discharge operation for the drive waveform in FIG. 6 is the same as in FIG.
　図５，６に示した駆動波形は，図４に示した垂直同期期間ＶＴ内の複数のサブフィールドＳＦのうち最初のサブフィールドＳＦ１での駆動波形である。それ以外のサブフィールドＳＦ２～ＳＦｎでは，図５，６の駆動波形のリセット期間Ｔｒｅｓｅｔにおいて前半の第１のリセット波形がなく，後半の第２のリセット波形，すなわちＸ電極に－Ｖｘを印加しながらＹ電極に負極性の鈍波パルスＰｒｅｓｎを印加するリセット波形のみが形成される。それに伴って，サブフィールドＳＦ１～ＳＦn-1でのサステイン期間では，Ｙ電極を陽極としＸ電極を陰極とするサステイン放電が最後の放電となり，サブフィールドＳＦ２～ＳＦｎのリセット期間が開始する前の状態では，直前のサブフィールドのサステイン期間で点灯したセルのＸ電極上に正電荷がＹ電極上に負電荷がそれぞれ壁電荷として蓄積されている。そして，負極性の鈍波パルスＰｒｅｓｎによるリセット放電で直前のサブフィールドで点灯したセルの壁電荷量を調整する。サブフィールドＳＦ２～ＳＦｎのアドレス期間とサステイン期間の駆動波形は，図５，６と同じである。 The drive waveforms shown in FIGS. 5 and 6 are drive waveforms in the first subfield SF1 among the plurality of subfields SF in the vertical synchronization period VT shown in FIG. In the other subfields SF2 to SFn, there is no first reset waveform in the first half in the reset period Treset of the drive waveforms in FIGS. 5 and 6, and the second reset waveform in the second half, that is, while applying −Vx to the X electrode. Only a reset waveform for applying a negative blunt wave pulse Presn to the Y electrode is formed. Accordingly, in the sustain period in the subfields SF1 to SFn-1, the sustain discharge using the Y electrode as the anode and the X electrode as the cathode becomes the last discharge, and the state before the reset period of the subfields SF2 to SFn starts. In this case, positive charges and negative charges are accumulated as wall charges on the X electrode of the cell that is lit in the sustain period of the immediately preceding subfield. Then, the amount of wall charges of the cell lit in the immediately preceding subfield is adjusted by the reset discharge by the negative blunt wave pulse Presn. The drive waveforms in the address period and the sustain period of the subfields SF2 to SFn are the same as those in FIGS.
　以上の通り，垂直同期期間ＶＴ内の最初のサブフィールドでは正極性の鈍波パルスによる第１のリセット放電と負極性の鈍波パルスによる第２のリセット放電とが行われ，残りのサブフィールドでは負極性の鈍波パルスによる第２のリセット放電のみが行われる。さらに，第１，第２のリセット放電を有するサブフィールドが複数の垂直同期期間ＶＴに１回だけ行われるようにしてもよい。それにより通常表示状態における背景発光輝度を低減できる。 As described above, in the first subfield in the vertical synchronization period VT, the first reset discharge by the positive blunt wave pulse and the second reset discharge by the negative blunt wave pulse are performed, and in the remaining subfields Only the second reset discharge by the negative obtuse wave pulse is performed. Furthermore, the subfield having the first and second reset discharges may be performed only once in a plurality of vertical synchronization periods VT. Thereby, the background light emission luminance in the normal display state can be reduced.
　図７は，本実施の形態における連続する垂直同期期間を示す図である。図７に示されるとおり，垂直同期信号Ｖｓｙｎｃに同期して画定される垂直同期期間ＶＴは連続して発生する。ただし，図７には２つの垂直同期期間１ＶＴ，２ＶＴのみが示されている。垂直同期信号Ｖｓｙｃは周波数が６０Ｈｚであり，垂直同期期間ＶＴは１／６０ｓｅｃである。 FIG. 7 is a diagram showing continuous vertical synchronization periods in the present embodiment. As shown in FIG. 7, the vertical synchronization period VT defined in synchronization with the vertical synchronization signal Vsync is continuously generated. However, FIG. 7 shows only two vertical synchronization periods 1VT and 2VT. The vertical synchronization signal Vsyc has a frequency of 60 Hz, and the vertical synchronization period VT is 1/60 sec.
　図３に示した制御回路３６は，ゲイン調整回路ＧＡＩＮから入力される映像データ信号のＲＧＢ全ての階調値がゼロでないことを検出すると，通常表示状態で駆動回路３０，３２，３５を制御する。また，制御回路３６は，上記の映像データ信号のＲＧＢ全ての階調値がゼロであることを検出すると，黒表示状態で駆動回路３０，３２，３５を制御する。 The control circuit 36 shown in FIG. 3 controls the drive circuits 30, 32, and 35 in the normal display state when detecting that all the RGB gradation values of the video data signal input from the gain adjustment circuit GAIN are not zero. . Further, when the control circuit 36 detects that all the gradation values of RGB of the video data signal are zero, it controls the drive circuits 30, 32, and 35 in the black display state.
　通常表示状態では，制御回路３６は，図５，６に示された駆動波形によるサブフィールドと図５，６から正極性の鈍波パルスＰｒｅｓｐによるリセット波形を除いた駆動波形によるサブフィールドとを繰り返して垂直同期期間ＶＴの駆動制御を行う。これにより，映像データ信号に対応した画像が表示される。黒表示状態では，制御回路３６は，Ｘ，Ｙ電極駆動回路とアドレス電極駆動回路とにリセット期間の駆動波形（第１と第２のリセットパルスの両方）を生成させ，アドレス期間とサステイン期間のスキャンパルスとアドレスパルスとサステインパルスは生成させない。黒表示状態では，映像データ信号のＲＧＢの階調値が全てゼロであるので，表示のための駆動は不要だからである。ただし，黒表示状態であっても，リセット駆動を繰り返し実行して，パネル内の全てのセルの壁電荷状態をリセット状態に保っている。隔壁構造にもよるが，セルの壁電荷状態は電荷の移動により変動するので，黒表示状態でも後続の通常表示に備えてリセット駆動を繰り返すことが望ましいからである。黒表示状態ではサステイン放電は行われないので，リセット期間では第１と第２のリセットパルスを印加する必要がある。 In the normal display state, the control circuit 36 repeats the subfield based on the drive waveform shown in FIGS. 5 and 6 and the subfield based on the drive waveform excluding the reset waveform due to the positive obtuse wave pulse Presp from FIGS. Then, drive control is performed in the vertical synchronization period VT. As a result, an image corresponding to the video data signal is displayed. In the black display state, the control circuit 36 causes the X and Y electrode drive circuit and the address electrode drive circuit to generate a drive waveform for the reset period (both the first and second reset pulses), and for the address period and the sustain period. The scan pulse, address pulse, and sustain pulse are not generated. This is because in the black display state, the RGB gradation values of the video data signal are all zero, so that driving for display is unnecessary. However, even in the black display state, reset driving is repeatedly executed to keep the wall charge states of all cells in the panel in the reset state. Although depending on the barrier rib structure, the wall charge state of the cell fluctuates due to the movement of the charge. Therefore, it is desirable to repeat the reset driving for the subsequent normal display even in the black display state. Since the sustain discharge is not performed in the black display state, it is necessary to apply the first and second reset pulses in the reset period.
　本実施の形態では，通常表示状態から黒表示状態に遷移したときは，まず第１の黒表示動作として，各垂直同期期間ＶＴ内の最初のサブフィールドＳＦにおいて，図５，６のリセット期間の駆動を行いアドレス期間とサステイン期間の駆動を停止する。 In the present embodiment, when the normal display state transitions to the black display state, first, as the first black display operation, in the first subfield SF in each vertical synchronization period VT, the reset period shown in FIGS. Driving is performed to stop driving in the address period and the sustain period.
　さらに，第１の黒表示動作後は，第２の黒表示動作として，第１の垂直同期期間１ＶＴでは，リセット期間の第１のリセットパルスＰｒｅｓｐによる第１のリセット放電だけを行い，第１の垂直同期期間１ＶＴの後に発生する第２の垂直同期期間２ＶＴでは，リセット期間の第２のリセットパルスＰｒｅｓｎによる第２のリセット放電だけを行う。黒表示状態では，各サブフィールドでアドレス期間とサステイン期間の駆動を行わないので，異なる垂直同期期間１ＶＴ，２ＶＴで第１のリセット放電と第２のリセット放電を行っても，図５で説明したリセット期間におけるパネルの動作を行うことができる。この第２の黒表示動作のように，異なる垂直同期期間で第１，第２のリセット動作を行わせることで，各垂直同期期間でのリセット放電の規模を低減することができ，背景発光の輝度をさらに低減させることができる。 Further, after the first black display operation, as the second black display operation, only the first reset discharge by the first reset pulse Presp in the reset period is performed in the first vertical synchronization period 1VT. In the second vertical synchronization period 2VT that occurs after the vertical synchronization period 1VT, only the second reset discharge by the second reset pulse Presn in the reset period is performed. In the black display state, the driving in the address period and the sustain period is not performed in each subfield. Therefore, even if the first reset discharge and the second reset discharge are performed in the different vertical synchronization periods 1VT and 2VT, as described in FIG. The panel can be operated in the reset period. By performing the first and second reset operations in different vertical synchronization periods as in the second black display operation, the scale of reset discharge in each vertical synchronization period can be reduced, and background light emission can be reduced. The luminance can be further reduced.
　上記の第２の黒表示動作において，第１，第２の垂直同期期間１ＶＴ，２ＶＴは，交互に発生してもよいし，１回のまたは複数回の第３の垂直同期期間を挟んで交互に発生しても良い。 In the second black display operation described above, the first and second vertical synchronization periods 1VT and 2VT may be generated alternately or alternately with one or a plurality of third vertical synchronization periods interposed therebetween. May occur.
　なお，連続する垂直同期期間において，間欠的に，つまり，１つおきのまたは２つおきの単一の垂直同期期間で，図５，図６に示した第１，第２のリセット動作の両方を行うことも考えられる。しかし，その場合は，第１及び第２のリセット動作を含む１回のリセットによる背景発光の輝度は低減されず，且つ背景発光の周波数が低減する。よって，人間の目には背景発光がフリッカとして認識されるおそれがあり，上記の第２の黒表示動作と比較すると好ましくない。 It should be noted that both the first and second reset operations shown in FIGS. 5 and 6 are performed intermittently in successive vertical synchronization periods, that is, every other or every second vertical synchronization period. Can also be considered. However, in that case, the luminance of background light emission by one reset including the first and second reset operations is not reduced, and the frequency of background light emission is reduced. Therefore, there is a possibility that background light emission is recognized as flicker by human eyes, which is not preferable as compared with the second black display operation.
　図８は，本実施の形態における第１の黒表示動作での駆動波形を示す図である。図８では，垂直同期期間内の最初の１つのサブフィールドの駆動波形が示され，図５のグランドＧＮＤを中心にする駆動波形に対応する。図８のサブフィールドの駆動波形によれば，リセット期間Ｔｒｅｓｅｔにおいて，Ｙ電極駆動回路３２が＋ＶｅをＹ電極に印加した状態で，Ｘ電極駆動回路３０がグランドから－Ｖｘに徐々に低下する電位をＸ電極に印加する。さらに，リセット期間Ｔｒｅｓｅｔにおいて，Ｘ電極駆動回路３０が－ＶｘをＸ電極に印加した状態で，Ｙ電極駆動回路３２が電圧ＶｅからＶｗに徐々に上昇する第１の鈍波リセットパルスＰｒｅｓｐをＹ電極に印加する。そして，リセット期間Ｔｒｅｓｅｔの最後に，Ｘ電極駆動回路３０が電圧＋ＶｘをＸ電極に印加した状態で，Ｙ電極駆動回路３２がＹ電極の電位をＶｗから一旦低下させさらに電圧－Ｖｙ＋αまで徐々に低下する第２の鈍波リセットパルスＰｒｅｓｎをＹ電極に印加する。 FIG. 8 is a diagram showing a drive waveform in the first black display operation in the present embodiment. FIG. 8 shows the drive waveform of the first subfield in the vertical synchronization period, and corresponds to the drive waveform centered on the ground GND of FIG. According to the drive waveform in the subfield of FIG. 8, in the reset period Reset, the potential at which the X electrode drive circuit 30 gradually decreases from ground to −Vx in the state where the Y electrode drive circuit 32 applies + Ve to the Y electrode. Apply to X electrode. Further, in the reset period Reset, the Y electrode drive circuit 30 applies the first obtuse wave reset pulse Presp that gradually increases from the voltage Ve to Vw while the X electrode drive circuit 30 applies −Vx to the X electrode. Apply to. Then, at the end of the reset period Treset, with the X electrode drive circuit 30 applying the voltage + Vx to the X electrode, the Y electrode drive circuit 32 temporarily reduces the potential of the Y electrode from Vw and then gradually decreases to the voltage −Vy + α. A second blunt wave reset pulse Presn is applied to the Y electrode.
　つまり，図５に示したリセット期間ＴｒｅｓｅｔのＸ，Ｙ電極の駆動波形と同じである。これにより，Ｘ，Ｙ電極とアドレス電極の上の壁電荷が適切な極性と量に調整される。 That is, it is the same as the drive waveforms of the X and Y electrodes in the reset period Reset shown in FIG. As a result, the wall charges on the X and Y electrodes and the address electrodes are adjusted to an appropriate polarity and amount.
　そして，アドレス期間Ｔａｄｄでは，Ｙ電極駆動回路３２はＹ電極へのスキャンパルスの印加を行わず，アドレス電極駆動回路３５はアドレス電極へのアドレスパルスの印加を行わない。よって，アドレス放電は発生しない。さらに，サステイン期間Ｔｓｕｓでは，Ｘ，Ｙ電極駆動回路３０，３２は，Ｘ，Ｙ電極をグランドＧＮＤに維持しＸ，Ｙ電極にサステインパルスの印加は行わない。 In the address period Tadd, the Y electrode drive circuit 32 does not apply the scan pulse to the Y electrode, and the address electrode drive circuit 35 does not apply the address pulse to the address electrode. Therefore, address discharge does not occur. Further, in the sustain period Tsus, the X and Y electrode drive circuits 30 and 32 maintain the X and Y electrodes at the ground GND and do not apply a sustain pulse to the X and Y electrodes.
　図９は，本実施の形態における第１の黒表示動作での駆動波形を示す図である。図９では，垂直同期期間内の最初の１つのサブフィールドの駆動波形が示され，図６の電圧Ｖｓを中心にする駆動波形に対応する。よって，図９においても，リセット期間Ｔｒｅｓｅｔで正の鈍波リセットパルスＰｒｅｓｐと負の鈍波リセットパルスＰｒｅｓｎとがＹ電極に印加され，電圧ＶｓからグランドＧＮＤに低下するパルスがＸ電極に印加される。そして，図８と異なり，Ｘ電極の駆動波形がＶｓを中心にした電圧になっている。アドレス電極とＹ電極の駆動波形は図８と同じである。 FIG. 9 is a diagram showing a drive waveform in the first black display operation in the present embodiment. In FIG. 9, the drive waveform of the first one subfield in the vertical synchronization period is shown and corresponds to the drive waveform centered on the voltage Vs in FIG. Therefore, also in FIG. 9, the positive blunt wave reset pulse Presp and the negative blunt wave reset pulse Presn are applied to the Y electrode in the reset period Treset, and a pulse that drops from the voltage Vs to the ground GND is applied to the X electrode. . Unlike FIG. 8, the drive waveform of the X electrode is a voltage centered on Vs. The drive waveforms of the address electrode and the Y electrode are the same as in FIG.
　本実施の形態では，通常表示状態から黒表示状態に遷移するときに，第１の黒表示動作では，図８または図９の駆動波形で各サブフィールドの駆動制御が行われる。 In this embodiment, when the transition from the normal display state to the black display state is performed, in the first black display operation, drive control of each subfield is performed with the drive waveform of FIG. 8 or FIG.
　図１０，図１１は，本実施の形態における第２の黒表示動作での駆動波形を示す図である。図１０，図１１も，１つのサブフィールドの駆動波形を示し，図５，図８のグランドＧＮＤを中心として＋Ｖｓ，－Ｖｓ電源を使用する駆動波形に対応する。 FIGS. 10 and 11 are diagrams showing drive waveforms in the second black display operation in the present embodiment. FIGS. 10 and 11 also show driving waveforms of one subfield, and correspond to driving waveforms using + Vs and −Vs power sources with the ground GND in FIGS. 5 and 8 as the center.
　第２の黒表示動作では，第１の垂直同期期間において図１０に示した駆動波形により正極性の鈍波リセットパルスＰｒｅｓｐを印加して第１のリセット放電を発生させ，第１の垂直同期期間の後の第２の垂直同期期間において図１１に示した駆動波形により負極性の鈍波リセットパルスＰｒｅｓｎを印加して第２のリセット放電を発生させる。 In the second black display operation, a positive blunt wave reset pulse Presp is applied by the drive waveform shown in FIG. 10 in the first vertical synchronization period to generate the first reset discharge, and the first vertical synchronization period. In the subsequent second vertical synchronization period, a negative blunt wave reset pulse Presn is applied by the drive waveform shown in FIG. 11 to generate a second reset discharge.
　図１０は，第１の垂直同期期間１ＶＴ内の一つのサブフィールド，例えば最初のサブフィールドにおける駆動波形である。リセット期間Ｔｒｅｓｅｔでは，Ｙ電極駆動回路３２がＹ電極に電圧Ｖｅを印加し，Ｘ電極駆動回路３０がグランドＧＮＤから－Ｖｘに徐々に低下する電圧をＸ電極に印加する。これによりＸ，Ｙ電極間に微弱なリセット放電が発生する。さらに，リセット期間Ｔｒｅｓｅｔでは，Ｘ電極駆動回路３０がＸ電極を－Ｖｘに保ち，Ｙ電極駆動回路３２が電圧ＶｅからＶｗに徐々に上昇する鈍波パルスＰｒｅｓｐを印加する。これにより，Ｘ，Ｙ電極間に微弱なリセット放電が発生する。その後のリセット期間Ｔｒｅｓｅｔでは，Ｘ，Ｙ電極共にグランドＧＮＤに維持される。さらに，アドレス期間Ｔａｄｄ，サステイン期間Ｔｓｕｓでも，全ての電極がグランドＧＮＤに維持される。走査パルスやサステインパルスの印加は行われない。すなわち，第１の垂直同期期間１ＶＴでは，正極性のリセットパルスＰｒｅｓｐによる第１のリセット放電のみが発生する。 FIG. 10 shows a drive waveform in one subfield, for example, the first subfield in the first vertical synchronization period 1VT. In the reset period Treset, the Y electrode drive circuit 32 applies the voltage Ve to the Y electrode, and the X electrode drive circuit 30 applies a voltage that gradually decreases from the ground GND to −Vx to the X electrode. This generates a weak reset discharge between the X and Y electrodes. Further, in the reset period Treset, the X electrode driving circuit 30 keeps the X electrode at −Vx, and the Y electrode driving circuit 32 applies the obtuse wave pulse Presp that gradually increases from the voltage Ve to Vw. This generates a weak reset discharge between the X and Y electrodes. In the subsequent reset period Treset, both the X and Y electrodes are maintained at the ground GND. Further, all the electrodes are maintained at the ground GND even in the address period Tadd and the sustain period Tsus. No scan pulse or sustain pulse is applied. In other words, in the first vertical synchronization period 1VT, only the first reset discharge is generated by the positive reset pulse Presp.
　図１１は，第１の垂直同期期間１ＶＴの後の第２の垂直同期期間２ＶＴ内の一つのサブフィールド，例えば最初のサブフィールドにおける駆動波形である。リセット期間Ｔｒｅｓｅｔでは，Ｘ電極駆動回路３０がＸ電極に電圧＋Ｖｘを印加し，Ｙ電極駆動回路３２がＹ電極にグランドから電圧－Ｖｙ＋αまで徐々に低下する負極性の鈍波リセットパルスＰｒｅｓｎを印加する。これにより，Ｘ，Ｙ電極上に形成された電荷量が減らされ適切な量に調整される。その後は，Ｘ，Ｙ電極およびアドレス電極はグランドに保たれる。アドレス期間Ｔａｄｄ，サステイン期間Ｔｓｕｓでの走査パルス，サステインパルスの印加は行われない。すなわち，第２の垂直同期期間２ＶＴでは，負極性のリセットパルスＰｒｅｓｎによる第２のリセット放電のみが発生する。 FIG. 11 shows driving waveforms in one subfield, for example, the first subfield, in the second vertical synchronization period 2VT after the first vertical synchronization period 1VT. In the reset period Treset, the X electrode drive circuit 30 applies a voltage + Vx to the X electrode, and the Y electrode drive circuit 32 applies a negative blunt wave reset pulse Presn that gradually decreases from the ground to the voltage −Vy + α to the Y electrode. . As a result, the amount of charge formed on the X and Y electrodes is reduced and adjusted to an appropriate amount. Thereafter, the X, Y electrodes and address electrodes are kept at ground. The scan pulse and the sustain pulse are not applied in the address period Tadd and the sustain period Tsus. In other words, in the second vertical synchronization period 2VT, only the second reset discharge is generated by the negative reset pulse Presn.
　図１２，図１３は，本実施の形態における第２の黒表示動作での駆動波形を示す図である。図１２，図１３も，１つのサブフィールドの駆動波形を示し，図６，図９のＶｓを中心として＋２Ｖｓ，ＧＮＤ電源を使用する駆動波形に対応する。それ以外は，図１０，図１１と同じである。 FIGS. 12 and 13 are diagrams showing drive waveforms in the second black display operation in the present embodiment. FIGS. 12 and 13 also show driving waveforms of one subfield, and correspond to driving waveforms using +2 Vs, GND power supply with Vs in FIGS. 6 and 9 as the center. The rest is the same as FIG. 10 and FIG.
　図１２は，第１の垂直同期期間１ＶＴ内の１つのサブフィールドの駆動波形であり，図１０と異なり，Ｘ電極の駆動波形がグランドＧＮＤと電圧Ｖｓになっている。アドレス電極とＹ電極の駆動波形は図１０と同じである。図１２に示されるとおり，第１の垂直同期期間１ＶＴでは，正極性のリセットパルスＰｒｅｓｐによる第１のリセット放電のみが発生する。 FIG. 12 shows a drive waveform of one subfield within the first vertical synchronization period 1VT. Unlike FIG. 10, the drive waveform of the X electrode is the ground GND and the voltage Vs. The drive waveforms of the address electrode and the Y electrode are the same as in FIG. As shown in FIG. 12, only the first reset discharge is generated by the positive reset pulse Presp in the first vertical synchronization period 1VT.
　図１３は，第２の垂直同期期間２ＶＴ内の１つのサブフィールドの駆動波形であり，図１１と異なり，Ｘ電極の駆動波形が電圧Ｖｓ，＋２Ｖｘになっている。アドレス電極とＹ電極の駆動波形は図１１と同じである。第２の垂直同期期間２ＶＴでは，負極性のリセットパルスＰｒｅｓｎによる第２のリセット放電のみが発生する。 FIG. 13 shows a drive waveform of one subfield in the second vertical synchronization period 2VT. Unlike FIG. 11, the drive waveform of the X electrode is the voltage Vs, + 2Vx. The drive waveforms of the address electrode and the Y electrode are the same as in FIG. In the second vertical synchronization period 2VT, only the second reset discharge is generated by the negative reset pulse Presn.
　図１０，１１または図１２，１３に示されるとおり，第２の黒表示動作では，第１の垂直同期期間で正極性の鈍波リセットパルスＰｒｅｓｐによりＸ，Ｙ電極上の壁電荷を消去しさらに逆極性の壁電荷を発生する。そして，第２の垂直同期期間で負極性の鈍波リセットパルスＰｒｅｓｎによりＸ，Ｙ電極上の壁電荷量を調整する。アドレス期間とサステイン期間では電極駆動が行われないので，第１のリセット放電と第２のリセット放電とを異なる垂直同期期間で実施しても，通常表示動作でのリセット動作と同じ壁電荷リセット作用を得ることができる。 As shown in FIGS. 10, 11 or 12, 13, in the second black display operation, the wall charges on the X and Y electrodes are erased by the positive blunt wave reset pulse Presp in the first vertical synchronization period. Generates wall charges of opposite polarity. Then, the amount of wall charges on the X and Y electrodes is adjusted by the negative blunt wave reset pulse Presn in the second vertical synchronization period. Since electrode driving is not performed in the address period and the sustain period, even if the first reset discharge and the second reset discharge are performed in different vertical synchronization periods, the same wall charge reset action as the reset operation in the normal display operation Can be obtained.
　しかも，２つのリセット放電を異なる垂直同期期間で行うので，それぞれのリセット放電による背景発光の輝度を低くすることができ，かつフリッカの発生も抑制できる。 In addition, since the two reset discharges are performed in different vertical synchronization periods, the luminance of the background light emission due to each reset discharge can be lowered, and the occurrence of flicker can be suppressed.
　図１４，１５は，本実施の形態における第２の黒表示動作での駆動波形の変型例を示す図である。図１４は，図５，８のグランドＧＮＤを中心にする駆動波形に対応し，図１５は，図６，９の＋Ｖｓを中心にする駆動波形に対応する。 FIGS. 14 and 15 are diagrams showing modified examples of drive waveforms in the second black display operation in the present embodiment. 14 corresponds to the drive waveform centered on the ground GND in FIGS. 5 and 8, and FIG. 15 corresponds to the drive waveform centered on + Vs in FIGS.
　図１４において，第２のリセット放電は，Ｘ電極をグランドＧＮＤに維持してＹ電極に負極性の鈍波リセットパルスＰｒｅｓｎを印加してＹ電極とアドレス電極間で発生させるリセット放電と，Ｘ電極を電圧＋Ｖｘに維持してＹ電極に負極性の鈍波リセットパルスＰｒｅｓｎを印加してＹ電極とＸ電極間で発生させるリセット放電とを有する。この第２のリセット放電によれば，第２のリセット放電において，Ｙ電極とアドレス電極間の放電と，Ｘ，Ｙ電極間の放電とを別々に実行するので，より高精度に壁電荷量の調整を行うことができる。 In FIG. 14, the second reset discharge includes a reset discharge generated between the Y electrode and the address electrode by applying a negative blunt wave reset pulse Presn to the Y electrode while maintaining the X electrode at the ground GND, and the X electrode. Is maintained at the voltage + Vx, and a negative discharge wave reset pulse Presn is applied to the Y electrode to generate a reset discharge generated between the Y electrode and the X electrode. According to the second reset discharge, since the discharge between the Y electrode and the address electrode and the discharge between the X and Y electrodes are separately performed in the second reset discharge, the wall charge amount can be more accurately determined. Adjustments can be made.
　図１５においても，第２のリセット放電は，Ｘ電極を電圧Ｖｓに維持してＹ電極に負極性の鈍波リセットパルスＰｒｅｓｎを印加してＹ電極とアドレス電極間で発生させるリセット放電と，Ｘ電極を電圧＋２Ｖｘに維持してＹ電極に負極性の鈍波リセットパルスＰｒｅｓｎを印加してＹ電極とＸ電極間で発生させるリセット放電とを有する。 Also in FIG. 15, the second reset discharge includes a reset discharge generated between the Y electrode and the address electrode by maintaining the X electrode at the voltage Vs and applying a negative blunt wave reset pulse Presn to the Y electrode, A reset discharge is generated between the Y electrode and the X electrode by maintaining the electrode at the voltage + 2Vx and applying a negative blunt wave reset pulse Presn to the Y electrode.
　上記の第２の黒表示動作において，正極性の鈍波パルスによる第１のリセット放電を発生する第１の垂直同期期間と，負極性の鈍波パルスによる第２のリセット放電を発生する第２の垂直同期期間との間を徐々に長く，すなわち第１，第２の垂直同期期間を間欠的に発生させることで，黒表示における画面の輝度値をさらに下げることができる。 In the second black display operation, a first vertical synchronization period in which a first reset discharge is generated by a positive obtuse wave pulse and a second reset discharge is generated by a negative obtuse wave pulse. The luminance value of the screen in black display can be further lowered by gradually increasing the period between the vertical synchronization periods, that is, by intermittently generating the first and second vertical synchronization periods.
　以上，本実施の形態によれば，第２の黒表示動作において，異なる垂直同期期間において，正極性の鈍波リセットパルスによる第１のリセット放電と，負極性の鈍波リセットパルスによる第２のリセット放電とを別々に実行するので，リセット放電による背景発光の輝度を低減することができ，白表示と黒表示の輝度比であるコントラストを改善することができる。 As described above, according to the present embodiment, in the second black display operation, in the different vertical synchronization periods, the first reset discharge by the positive obtuse wave reset pulse and the second reset by the negative obtuse wave reset pulse are performed. Since the reset discharge is executed separately, the luminance of the background light emission due to the reset discharge can be reduced, and the contrast which is the luminance ratio between the white display and the black display can be improved.
　さらに，第１の黒表示動作と第２の黒表示動作とを組み合わせることで，通常表示動作から黒表示動作に移行したときの画面の輝度値の変化を違和感なく低減することができる。 Further, by combining the first black display operation and the second black display operation, it is possible to reduce the change in the luminance value of the screen when the normal display operation is shifted to the black display operation without any sense of incongruity.
本発明は，プラズマディスプレイ装置に適用することで有用な結果を得ることができる。 The present invention can obtain useful results when applied to a plasma display device.

Claims (7)

  1. 　複数の表示電極と前記表示電極に交差する複数のアドレス電極とを有する表示パネルと，
    　前記表示電極およびアドレス電極を駆動する駆動ユニットとを有し，
    　前記駆動ユニットは，入力映像データが黒表示に対応しない通常表示状態では，連続する垂直同期期間において，前記表示電極に第１のリセット放電と第２のリセット放電とを発生させるリセット期間と，前記入力映像データに基づく表示データに対応してセルを選択させるアドレス期間と，選択セルに維持放電を発生させるサステイン期間とを有するサブフィールドの駆動を所定数の垂直同期期間に少なくとも１回行い，
    　前記駆動ユニットは，前記入力映像データが黒表示に対応する黒表示状態では，第１の垂直同期期間において少なくとも１つのサブフィールドで前記第１のリセット放電を発生させ，前記第１の垂直同期期間の後の第２の垂直同期期間において少なくとも１つのサブフィールドで前記第２のリセット放電を発生させる黒表示駆動を行うことを特徴とするプラズマディスプレイ装置。     A display panel having a plurality of display electrodes and a plurality of address electrodes intersecting the display electrodes;
    A drive unit for driving the display electrode and the address electrode;
    In the normal display state where the input video data does not correspond to black display, the drive unit includes a reset period for generating a first reset discharge and a second reset discharge in the display electrode in a continuous vertical synchronization period; A subfield having an address period for selecting a cell corresponding to display data based on input video data and a sustain period for generating a sustain discharge in the selected cell is driven at least once in a predetermined number of vertical synchronization periods;
    The drive unit generates the first reset discharge in at least one subfield in the first vertical synchronization period when the input video data is in a black display state corresponding to black display, and the first vertical synchronization period A black display drive for generating the second reset discharge in at least one subfield in a second vertical synchronization period after the plasma display device.
  2. 　請求項１において，
    　前記駆動ユニットは，前記リセット期間において，第１の表示電極に正極性の鈍波リセットパルスを印加して前記第１のリセット放電を発生させ，前記第１の表示電極に負極性の鈍波リセットパルスを印加して前記第２のリセット放電を発生させることを特徴とするプラズマディスプレイ装置。     In claim 1,
    In the reset period, the driving unit applies a positive blunt wave reset pulse to the first display electrode to generate the first reset discharge, and negative blunt wave reset to the first display electrode. A plasma display apparatus, wherein a pulse is applied to generate the second reset discharge.
  3. 　請求項１または２において，
    　前記駆動ユニットは，前記黒表示状態では，前記アドレス期間においてセルを選択するパルスを前記表示電極及びアドレス電極に印加せず，前記サステイン期間において前記維持放電を発生させるパルスを前記表示電極に印加させないことを特徴とするプラズマディスプレイ装置。     In claim 1 or 2,
    In the black display state, the driving unit does not apply a pulse for selecting a cell to the display electrode and the address electrode in the address period, and does not apply a pulse for generating the sustain discharge to the display electrode in the sustain period. A plasma display device.
  4. 　請求項１または２において，
    　前記第１，第２の垂直同期期間は，交互に発生することを特徴とするプラズマディスプレイ装置。     In claim 1 or 2,
    The plasma display apparatus, wherein the first and second vertical synchronization periods occur alternately.
  5. 　請求項１または２において，
    　前記第１，第２の垂直同期期間は，それらの間に第３の垂直同期期間を挟んで交互に発生することを特徴とするプラズマディスプレイ装置。     In claim 1 or 2,
    The plasma display apparatus, wherein the first and second vertical synchronization periods are alternately generated with a third vertical synchronization period between them.
  6. 　請求項１または２において，
    　前記駆動ユニットは，前記黒表示状態では，前記第１の垂直同期期間内において，単一のサブフィールドで前記第１のリセット放電を発生させ，前記第２の垂直同期期間内において，単一のサブフィールドで前記第２のリセット放電を発生させることを特徴とするプラズマディスプレイ装置。     In claim 1 or 2,
    In the black display state, the driving unit generates the first reset discharge in a single subfield in the first vertical synchronization period, and generates a single reset signal in the second vertical synchronization period. A plasma display apparatus, wherein the second reset discharge is generated in a subfield.
  7. 　請求項２において，
    　前記黒表示駆動において，前記第２のリセット放電が，２回の負極性の鈍波リセットパルスの印加による，表示電極とアドレス電極間のリセット放電と，表示電極間のリセット放電とを有することを特徴とするプラズマディスプレイ装置。     In claim 2,
    In the black display driving, the second reset discharge includes a reset discharge between the display electrode and the address electrode and a reset discharge between the display electrodes due to the application of two negative obtuse wave reset pulses. A characteristic plasma display device.
PCT/JP2007/001454 2007-12-21 2007-12-21 Plasma display unit WO2009081450A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10301528A (en) * 1997-04-24 1998-11-13 Mitsubishi Electric Corp Driving method of plasma display
JP2003066900A (en) * 2001-08-24 2003-03-05 Sony Corp Plasma display and its driving method
JP2004004513A (en) * 2002-04-25 2004-01-08 Fujitsu Hitachi Plasma Display Ltd Driving method for plasma display panel, and plasma display device
JP2005122120A (en) * 2003-10-16 2005-05-12 Samsung Sdi Co Ltd Driving method and driving device for plasma display panel
JP2006091295A (en) * 2004-09-22 2006-04-06 Matsushita Electric Ind Co Ltd Driving method of plasma display panel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10301528A (en) * 1997-04-24 1998-11-13 Mitsubishi Electric Corp Driving method of plasma display
JP2003066900A (en) * 2001-08-24 2003-03-05 Sony Corp Plasma display and its driving method
JP2004004513A (en) * 2002-04-25 2004-01-08 Fujitsu Hitachi Plasma Display Ltd Driving method for plasma display panel, and plasma display device
JP2005122120A (en) * 2003-10-16 2005-05-12 Samsung Sdi Co Ltd Driving method and driving device for plasma display panel
JP2006091295A (en) * 2004-09-22 2006-04-06 Matsushita Electric Ind Co Ltd Driving method of plasma display panel

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