WO2009072860A2 - Insulation method for micromechanical device - Google Patents

Insulation method for micromechanical device Download PDF

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Publication number
WO2009072860A2
WO2009072860A2 PCT/MY2008/000175 MY2008000175W WO2009072860A2 WO 2009072860 A2 WO2009072860 A2 WO 2009072860A2 MY 2008000175 W MY2008000175 W MY 2008000175W WO 2009072860 A2 WO2009072860 A2 WO 2009072860A2
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WO
WIPO (PCT)
Prior art keywords
layer
dielectric layer
wafer
micromechanical
insulating
Prior art date
Application number
PCT/MY2008/000175
Other languages
French (fr)
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WO2009072860A3 (en
Inventor
Ramdzan Buyong Muhamad
Original Assignee
Mimos Berhad
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Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2009072860A2 publication Critical patent/WO2009072860A2/en
Publication of WO2009072860A3 publication Critical patent/WO2009072860A3/en

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Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
    • F04B43/00—Machines, pumps, or pumping installations having flexible working members
    • F04B43/02—Machines, pumps, or pumping installations having flexible working members having plate-like flexible members, e.g. diaphragms
    • F04B43/04—Pumps having electric drive
    • F04B43/043—Micropumps
    • F04B43/046—Micropumps with piezoelectric drive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
    • B81B7/0012—Protection against reverse engineering, unauthorised use, use in unintended manner, wrong insertion or pin assignment
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04B—POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS
    • F04B53/00—Component parts, details or accessories not provided for in, or of interest apart from, groups F04B1/00 - F04B23/00 or F04B39/00 - F04B47/00
    • F04B53/08—Cooling; Heating; Preventing freezing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Definitions

  • the present invention relates generally to a method for insulating a micromechanical device and more particularly to a method for insulating an electrostatically actuated micropump.
  • Micro Electromechanical system and structures are miniature devices such as micropumps that enable the operation of complex system. They are used in various technical fields, particularly in the automotive, medical, consumer, industrial and aerospace. In the medical field and in biotechnology field, a new type of micropump that can supply micro liquid and gas flow has urgently been demanded. It is the purpose of the present invention to develop a type of micropump that has the characteristic of flexibility, reliability and safety. In order to achieve that, the present invention takes count all specification in the design, fabrication and packaging.
  • Electrostatically actuated micropump has several disadvantages such as leaking electric current, safety in body application and so on.
  • the present invention has overcome the drawbacks of the existing methods and provides significantly improved method for insulating the micromechanical devices.
  • the present invention can be used for the future development of advanced broad range microfludic, including fluid control devices and application such as BioMEMS, Micro total analysis system ( ⁇ TAS) , Lab on chip (LOC) and ⁇ Dosing system for human as well as for agricultural such as plants and animal farming, and aquaculture such as aguafarming.
  • fluid control devices and application such as BioMEMS, Micro total analysis system ( ⁇ TAS) , Lab on chip (LOC) and ⁇ Dosing system for human as well as for agricultural such as plants and animal farming, and aquaculture such as aguafarming.
  • ⁇ TAS Micro total analysis system
  • LOC Lab on chip
  • ⁇ Dosing system for human as well as for agricultural such as plants and animal farming
  • aquaculture such as agua
  • Another object of the present invention is to provide the insulating method by using a method for planarization the surface of the semiconductor device.
  • a method of insulating a micromechanical wafer comprises the steps of depositing a dielectric layer over the micromechanical wafer using a spinning technique and curing the dielectric layer.
  • the dielectric layer is a layer of spin-on glass which is applied to a thickness of between 0.2 to 5 micrometers and has a dielectric constant of a value approximately to 3.1.
  • the method further comprises the step of heating the dielectric layer for removing water from the dielectric layer.
  • the dielectric layer is deposited on top of the upper surface of the micromechanical wafer and on bottom of the lower surface of the micromechanical wafer. Additional dielectric layer may be deposited as necessary prior to the curing step.
  • Figure 1 shows a sectional view of a micromechanical device before a passivation layer of SOG is applied thereto in accordance to the present invention
  • Figure 2 depicts a sectional view of the micromechanical device of Figure 1 with a passivation layer of SOG applied thereto;
  • Figure 3 is a flow diagram showing the process in which the passivation layer of SOG is applied to the micromechanical device.
  • FIG. 1 shown there is a cross-sectional view of a micromechanical device (10) which typically inclusive a silicon substrate (11) with layer of oxide (12) and a thin dielectric film layer (13) on top of the oxide layer (12) .
  • the dielectric layer (13) is typically a layer of silicon nitride which is deposited on top of the oxide layer
  • the oxide layer (12) and the silicon nitride layer (13) have been etched for a hole respectively.
  • the process continues with a deposition of bottom polysilicon conductor (14) which is fabricated over the first silicon nitride layer
  • a second layer of silicon nitride (15) is deposited on the bottom polysilicon conductor (14) .
  • a sacrificial layer of the PhosphoSilicate glass (PSG) (16) is then deposited over the second layer of the silicon nitride (15) .
  • the PSG layer (16) is then selectively etched to create a plurality of holes.
  • Another third layer of silicon nitride (17) is then deposited on top of the sacrificial layer (16) .
  • a top polysilicon conductor (18) is then deposited on the third silicon nitride layer (17) .
  • the top polysilicon conductor (18) is then etched using wet or dry etching to form plurality of holes and the third layer of the silicon nitride (17) is etched through the etch holes of the top polysilicon conductor (18) .
  • the unwanted portion of the PSG layer (16) is then etched through the etch holes of the top polysilicon conductor (18) and the third layer of the silicon nitride layer (17) by using concentrated hydrofluoric acid (HF) and thereby forming a trench (21) thereof to perform the diaphragm etching.
  • HF concentrated hydrofluoric acid
  • Etch holes of the top polysilicon conductor (18) and the third layer of the silicon nitride layer (17) are then sealed by LPCVD with a final fourth layer of the silicon nitride (20) for completing the formation of diaphragm process.
  • the sealing silicon nitride (20) does not fill the trench (21) .
  • the deposition is performed under low pressure therefore preserved the low pressure in the trench (21) .
  • the unwanted portions at one side of the wafer of the top polysilicon conductor (18), the third layer of the silicon nitride layer (17) and the PSG layer (16) are also etched and thus exposing partial of the second silicon nitride layer (15) .
  • a portion of the exposed area of the second silicon nitride layer (15) is then etched for receiving a bottom metal contact (19) which is able to connect to the bottom polysilicon conductor (14) as shown in figure 1.
  • a hole at the fourth layer of the silicon nitride (20) is etched down to the top polysilicon conductor (18).
  • Metal contact (22) for voltage supply is then etched to the hole of the fourth layer of the silicon nitride (20) .
  • a coat or low dielectric layer (23) is then deposited over the fabricated micromechanical device (10) as described above using a spinning technique which is able to fill small gaps and even fill submicron gaps in-side.
  • the low dielectric layer (23) used for this operation is an undoped spin-on glass (SOG) which is spun onto the micromechanical device (10) at front side and back side of the wafer to form a passivation coating layer (23) .
  • the thickness typical as spun is illustratively within the range of 0.2 to 5 micrometers.
  • the wafer surface with the added spin-on glass layer is shown in figure 2.
  • the spin-on glass (SOG) material is used in this operation as SOG has a lower dielectric constant of approximately 3.1 and thus provides for better electrical insulation.
  • SOG is an interlevel dielectric material that is applied to a silicon wafer in liquid form and consequently SOG films fill narrow spaces while planarizing the surfaces.
  • SOG processes offer low defect density, low cost, repeatability and high throughput. After cure, SOG films exhibit good uniformity, higher crack resistance, low stress, high thermal stability, good adhesion and wide controlled thickness range
  • the process is initiated by providing (24) the micromechanical device (10) with a passivation SOG layer (23) by spinning method.
  • the low dielectric SOG material (23) is spun on top of the upper surface of the micromechanical device (10) and on bottom of the lower surface of the micromechanical device
  • the thickness of the passivation layer (23) is based upon the spin rate.
  • the process is then followed with a heating process which is carried out by heating (25) the SOG material (23) and allows the SOG material (23) to be solidified and additional layer of SOG may be deposited (27) as necessary and solidified into a highly planarized dielectric layer.
  • the SOG layer (23) is then cured to remove all trapped low-boiling point trapped organics or solvents as represented by block (26) as shown in figure 3. It is cured in an oven furnace or on a hot plate at a predetermined temperature where a typical curing step is performed at a temperature of 400 0 C for a duration of one hour in an ambient atmosphere of air or a mixture of nitrogen (Na) and oxygen (O2) .
  • the resulting insulating structure of the present invention is therefore having a spin-on glass (SOG) layer as pre-packaging process which acts as a protective coating that provides a good dielectric constant with the characteristic of safety, flexibility and reliability.
  • SOG spin-on glass

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method of insulating a micromechanical wafer with a dielectric layer over said micromechanical wafer using a spinning technique. The dielectric layer is then heated to remove water and cured the layer of the micromechanical device to provide a protective coating to the micromechanical device.

Description

Insulation Method for Micromechanical Device
Field of Invention
The present invention relates generally to a method for insulating a micromechanical device and more particularly to a method for insulating an electrostatically actuated micropump.
Background of the Invention
Micro Electromechanical system and structures are miniature devices such as micropumps that enable the operation of complex system. They are used in various technical fields, particularly in the automotive, medical, consumer, industrial and aerospace. In the medical field and in biotechnology field, a new type of micropump that can supply micro liquid and gas flow has urgently been demanded. It is the purpose of the present invention to develop a type of micropump that has the characteristic of flexibility, reliability and safety. In order to achieve that, the present invention takes count all specification in the design, fabrication and packaging.
Electrostatically actuated micropump has several disadvantages such as leaking electric current, safety in body application and so on. The present invention has overcome the drawbacks of the existing methods and provides significantly improved method for insulating the micromechanical devices. The present invention can be used for the future development of advanced broad range microfludic, including fluid control devices and application such as BioMEMS, Micro total analysis system (μTAS) , Lab on chip (LOC) and μDosing system for human as well as for agricultural such as plants and animal farming, and aquaculture such as aguafarming. In addition including in gas control devices for microsystem application.
Accordingly, it is an object of the present invention to provide a simple and effective insulating method to insulate the micromechanical devices based on the safety and reliability issues.
Another object of the present invention is to provide the insulating method by using a method for planarization the surface of the semiconductor device.
Other objects of this invention will become apparent on the reading of this entire disclosure.
Summary of the Invention
In the present invention, a method of insulating a micromechanical wafer comprises the steps of depositing a dielectric layer over the micromechanical wafer using a spinning technique and curing the dielectric layer.
Preferably the dielectric layer is a layer of spin-on glass which is applied to a thickness of between 0.2 to 5 micrometers and has a dielectric constant of a value approximately to 3.1.
Preferably the method further comprises the step of heating the dielectric layer for removing water from the dielectric layer.
Preferably the dielectric layer is deposited on top of the upper surface of the micromechanical wafer and on bottom of the lower surface of the micromechanical wafer. Additional dielectric layer may be deposited as necessary prior to the curing step.
Brief Description of the Drawings
Other objects, features, and advantages of the invention will be apparent from the following description when read with reference to the accompanying drawings. In the drawings, wherein like reference numerals denote corresponding parts throughout the several views: Figure 1 shows a sectional view of a micromechanical device before a passivation layer of SOG is applied thereto in accordance to the present invention;
Figure 2 depicts a sectional view of the micromechanical device of Figure 1 with a passivation layer of SOG applied thereto; and
Figure 3 is a flow diagram showing the process in which the passivation layer of SOG is applied to the micromechanical device.
Detailed Description of the Preferred Embodiments
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those or ordinary skill in the art that the invention may¬ be practiced without these specific details. In other instances, well-known methods, procedures and/or components have not been described in detail so as not to obscure the invention. Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings . With reference to figure 1, shown there is a cross-sectional view of a micromechanical device (10) which typically inclusive a silicon substrate (11) with layer of oxide (12) and a thin dielectric film layer (13) on top of the oxide layer (12) . The dielectric layer (13) is typically a layer of silicon nitride which is deposited on top of the oxide layer
(12) . The oxide layer (12) and the silicon nitride layer (13) have been etched for a hole respectively. The process continues with a deposition of bottom polysilicon conductor (14) which is fabricated over the first silicon nitride layer
(13) and filled into the holes as shown in figure 1.
A second layer of silicon nitride (15) is deposited on the bottom polysilicon conductor (14) . A sacrificial layer of the PhosphoSilicate glass (PSG) (16) is then deposited over the second layer of the silicon nitride (15) . The PSG layer (16) is then selectively etched to create a plurality of holes. Another third layer of silicon nitride (17) is then deposited on top of the sacrificial layer (16) . A top polysilicon conductor (18) is then deposited on the third silicon nitride layer (17) . The top polysilicon conductor (18) is then etched using wet or dry etching to form plurality of holes and the third layer of the silicon nitride (17) is etched through the etch holes of the top polysilicon conductor (18) . The unwanted portion of the PSG layer (16) is then etched through the etch holes of the top polysilicon conductor (18) and the third layer of the silicon nitride layer (17) by using concentrated hydrofluoric acid (HF) and thereby forming a trench (21) thereof to perform the diaphragm etching.
Etch holes of the top polysilicon conductor (18) and the third layer of the silicon nitride layer (17) are then sealed by LPCVD with a final fourth layer of the silicon nitride (20) for completing the formation of diaphragm process. The sealing silicon nitride (20) does not fill the trench (21) . The deposition is performed under low pressure therefore preserved the low pressure in the trench (21) . The unwanted portions at one side of the wafer of the top polysilicon conductor (18), the third layer of the silicon nitride layer (17) and the PSG layer (16) are also etched and thus exposing partial of the second silicon nitride layer (15) .
A portion of the exposed area of the second silicon nitride layer (15) is then etched for receiving a bottom metal contact (19) which is able to connect to the bottom polysilicon conductor (14) as shown in figure 1. A hole at the fourth layer of the silicon nitride (20) is etched down to the top polysilicon conductor (18). Metal contact (22) for voltage supply is then etched to the hole of the fourth layer of the silicon nitride (20) . A coat or low dielectric layer (23) is then deposited over the fabricated micromechanical device (10) as described above using a spinning technique which is able to fill small gaps and even fill submicron gaps in-side. The low dielectric layer (23) used for this operation is an undoped spin-on glass (SOG) which is spun onto the micromechanical device (10) at front side and back side of the wafer to form a passivation coating layer (23) . The thickness typical as spun is illustratively within the range of 0.2 to 5 micrometers. The wafer surface with the added spin-on glass layer is shown in figure 2. The spin-on glass (SOG) material is used in this operation as SOG has a lower dielectric constant of approximately 3.1 and thus provides for better electrical insulation.
SOG is an interlevel dielectric material that is applied to a silicon wafer in liquid form and consequently SOG films fill narrow spaces while planarizing the surfaces. The main purpose of SOG as for interlevel dielectric film beside of that it can be as and protective coating applications. With well established SOG processes offer low defect density, low cost, repeatability and high throughput. After cure, SOG films exhibit good uniformity, higher crack resistance, low stress, high thermal stability, good adhesion and wide controlled thickness range The process for applying the passivation layer (23) to the micromechanical device (10) of the present invention will now be described with reference to the flow diagram of figure 3.
The process is initiated by providing (24) the micromechanical device (10) with a passivation SOG layer (23) by spinning method. The low dielectric SOG material (23) is spun on top of the upper surface of the micromechanical device (10) and on bottom of the lower surface of the micromechanical device
(10) . The thickness of the passivation layer (23) is based upon the spin rate.
The process is then followed with a heating process which is carried out by heating (25) the SOG material (23) and allows the SOG material (23) to be solidified and additional layer of SOG may be deposited (27) as necessary and solidified into a highly planarized dielectric layer. The SOG layer (23) is then cured to remove all trapped low-boiling point trapped organics or solvents as represented by block (26) as shown in figure 3. It is cured in an oven furnace or on a hot plate at a predetermined temperature where a typical curing step is performed at a temperature of 4000C for a duration of one hour in an ambient atmosphere of air or a mixture of nitrogen (Na) and oxygen (O2) .
The resulting insulating structure of the present invention is therefore having a spin-on glass (SOG) layer as pre-packaging process which acts as a protective coating that provides a good dielectric constant with the characteristic of safety, flexibility and reliability.
As will be readily apparent to those skilled in the art, the present invention may easily be produced in other specific forms without departing from its essential characteristics. The present embodiments is, therefore, to be considered as merely illustrative and not restrictive, the scope of the invention being indicated by the claims rather than the foregoing description, and all changes which come within therefore intended to be embraced therein.

Claims

Claims
1. A method of insulating a itiicromechanical wafer comprising the steps of: depositing a dielectric layer over said micromechanical wafer using a spinning technique; and curing said dielectric layer.
2. The method of insulating a micromechanical wafer as claimed in claim 1, wherein said dielectric layer is a layer of spin- on glass.
3. The method of insulating a micromechanical wafer as claimed in claim 2, wherein said dielectric layer is applied to a thickness of between 0.2 to 5 micrometers.
4. The method of insulating a micromechanical wafer as claimed in claim 3, wherein said dielectric layer has a dielectric constant of a value approximately to 3.1.
5. The method of insulating a micromechanical wafer as claimed in claim 1, wherein said method further comprising the step of heating said dielectric layer for removing water from the dielectric layer.
6. The method of insulating a micromechanical wafer as claimed in claim 1, wherein said curing step comprises baking said wafer at a temperature of about 4000C for a duration of one hour in an ambient atmosphere of air or a mixture of nitrogen (N2) and oxygen (O2) •
7. The method of insulating a micromechanical wafer as claimed in claim 1, wherein said dielectric layer is deposited on top of the upper surface of said micromechanical wafer and on bottom of the lower surface of said micromechanical wafer.
8. The method of insulating a micromechanical wafer as claimed in claim I1 wherein said additional dielectric layer may be deposited as necessary prior to the curing step.
PCT/MY2008/000175 2007-12-05 2008-12-05 Insulation method for micromechanical device WO2009072860A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI20072171A MY155581A (en) 2007-12-05 2007-12-05 Insulation method for micromechanical device
MYPI20072171 2007-12-05

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WO2009072860A2 true WO2009072860A2 (en) 2009-06-11
WO2009072860A3 WO2009072860A3 (en) 2009-08-20

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292558A (en) * 1991-08-08 1994-03-08 University Of Texas At Austin, Texas Process for metal deposition for microelectronic interconnections
US20020012744A1 (en) * 2000-06-21 2002-01-31 Seth Miller Re-coating MEMS devices using dissolved resins
US7288435B2 (en) * 2002-02-19 2007-10-30 Infineon Technologies Ag Method for producing a cover, method for producing a packaged device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292558A (en) * 1991-08-08 1994-03-08 University Of Texas At Austin, Texas Process for metal deposition for microelectronic interconnections
US20020012744A1 (en) * 2000-06-21 2002-01-31 Seth Miller Re-coating MEMS devices using dissolved resins
US7288435B2 (en) * 2002-02-19 2007-10-30 Infineon Technologies Ag Method for producing a cover, method for producing a packaged device

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Publication number Publication date
MY155581A (en) 2015-11-03
WO2009072860A3 (en) 2009-08-20

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