WO2009040670A3 - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method therefor Download PDFInfo
- Publication number
- WO2009040670A3 WO2009040670A3 PCT/IB2008/003119 IB2008003119W WO2009040670A3 WO 2009040670 A3 WO2009040670 A3 WO 2009040670A3 IB 2008003119 W IB2008003119 W IB 2008003119W WO 2009040670 A3 WO2009040670 A3 WO 2009040670A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- manufacturing
- semiconductor device
- method therefor
- plasma
- barrier layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention is a method of forming a barrier layer, which includes an insulator, on a fluorocarbon film formed on a substrate, the method including the steps of producing a plasma from a gas, forming the barrier layer on the fluorocarbon film by using the plasma and exposing the surface of the substrate to the plasma including a nitrogen to dope the nitrogen to the surface of the barrier layer.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US99543207P | 2007-09-26 | 2007-09-26 | |
US60/995,432 | 2007-09-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009040670A2 WO2009040670A2 (en) | 2009-04-02 |
WO2009040670A3 true WO2009040670A3 (en) | 2009-10-15 |
Family
ID=40511956
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2008/003119 WO2009040670A2 (en) | 2007-09-26 | 2008-09-25 | Semiconductor device and manufacturing method therefor |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2009040670A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104752400B (en) * | 2013-12-31 | 2019-06-04 | 中芯国际集成电路制造(上海)有限公司 | Connected medium layer, its production method and the semiconductor devices including it |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1187342A (en) * | 1996-11-28 | 1999-03-30 | Sony Corp | Method of forming inter-layer dielectric |
JP2003218109A (en) * | 2002-01-17 | 2003-07-31 | Internatl Business Mach Corp <Ibm> | Method for forming metallic pattern using sacrifice hard mask |
JP2003531493A (en) * | 2000-04-03 | 2003-10-21 | シャープ株式会社 | Method for enhancing adhesion of silicon nitride to low dielectric constant fluorine-containing amorphous carbon using silicon carbide adhesion promoter layer |
JP2005217142A (en) * | 2004-01-29 | 2005-08-11 | Semiconductor Leading Edge Technologies Inc | Process for fabricating semiconductor device |
WO2006137384A1 (en) * | 2005-06-20 | 2006-12-28 | Tohoku University | Interlayer insulating film and wiring structure, and process for producing the same |
-
2008
- 2008-09-25 WO PCT/IB2008/003119 patent/WO2009040670A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1187342A (en) * | 1996-11-28 | 1999-03-30 | Sony Corp | Method of forming inter-layer dielectric |
JP2003531493A (en) * | 2000-04-03 | 2003-10-21 | シャープ株式会社 | Method for enhancing adhesion of silicon nitride to low dielectric constant fluorine-containing amorphous carbon using silicon carbide adhesion promoter layer |
JP2003218109A (en) * | 2002-01-17 | 2003-07-31 | Internatl Business Mach Corp <Ibm> | Method for forming metallic pattern using sacrifice hard mask |
JP2005217142A (en) * | 2004-01-29 | 2005-08-11 | Semiconductor Leading Edge Technologies Inc | Process for fabricating semiconductor device |
WO2006137384A1 (en) * | 2005-06-20 | 2006-12-28 | Tohoku University | Interlayer insulating film and wiring structure, and process for producing the same |
Also Published As
Publication number | Publication date |
---|---|
WO2009040670A2 (en) | 2009-04-02 |
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