WO2009030278A1

WO2009030278A1 - Asynchronous digital signal detection

Info

Publication number: WO2009030278A1
Application number: PCT/EP2007/059342
Authority: WO
Inventors: Thomas Hoefer
Original assignee: Agilent Technologies, Inc.
Priority date: 2007-09-06
Filing date: 2007-09-06
Publication date: 2009-03-12

Abstract

The invention refers to determining a first sequence of digital values (D1 ) from a digital signal (S1 ) being transmitted with a first data rate (T1 ), comprising sampling the digital signal (S1 ) at a second sampling rate (T2) being greater than the first data rate (T1 ), and generating a corresponding second sequence of digital values (D2), detecting an indication about a time position (PH) of the values of the first sequence of digital values (D1 ) with respect to a reference time base, by filtering the second sequence of digital values (D2), and evaluating a corresponding filtering result (D3), and detecting the first sequence of digital values (D1 ) from the second sequence of digital values (D2) according to the indication about the time position (PH).

Description

DESCRIPTION

TITLE

ASYNCHRONOUS DIGITAL SIGNAL DETECTION

BACKGROUND ART

[0001] The present invention relates to detecting a digital data signal.

[0002] In serial digital communication systems, information between nodes is being exchanged as sequences of digital values e.g. as sequences of binary values. For transmitting such information, such a sequence of digital values is transformed into an analog signal by a signal driver that might perform an amplitude modulation of a physical source, e.g. an electrical current or voltage, according to the digital values, wherein the modulation frequency is controlled by a clock signal that might be generated by a local or remote data clock. The modulation frequency corresponds to the rate of the digital values, also being referred to as data rate (e.g. being expressed as a number of digital values per second). Such analog signal carrying digital information is often being referred to as digital signal.

[0003] In a receiver, a received digital signal is transformed back into a digital data stream, or in other words, the data content of the digital signal is recovered. Digital data recovery is usually performed by sampling the received digital signal at suitable timing points at the data rate of the digital signal. Preferably, the digital signal is sampled each in the middle between possible signal transitions between adjacent values within the digital signal. If the receiver is provided with the same clock signal as being used for signal generation in the transmitter, the timing points can be derived directly from the clock signal. Alternatively, the receiver might recover the data clock from the received digital signal. Data recovery using the data clock for sampling is often being referred to a synchronous data sampling.

[0004] An alternative to synchronous data sampling is a so-called asynchronous sampling method that does not require any data clock signal for data recovery. In such method, the digital signal is oversampled at a sampling rate higher than the data clock rate, and the digital data stream is derived from selecting certain bits out of the oversampled values.

[0005] The application note titled "A 3/4/5/6X Oversampling Circuit for 200 Mb/s to 1000 Mb/s Serial Interfaces" of Jerry Chuang, XAPP572 (v1.0) November 18, 2004 of the company Xilinx, Inc., being available under the internet address: http://www.xilinx.com/bvdQCs/appnotes/xapp572.pdf, discloses using an oversampling module to be attached to high speed serializer or de-serializer devices to extend these devices to lower frequency ranges.

[0006] Asynchronous signal detection might be preferably used in case that no information about the phase of the digital data signal is available since e.g. no synchronous reference clock is available or no clock data recovery -CDR- with a proper bandwidth is available to generate such reference clock.

DISCLOSURE OF THE INVENTION

[0007] It is an object of the invention to provide an improved asynchronous detection of digital data. The object is solved by the independent claims. Preferred embodiments are shown by the dependent claims.

[0008] In an embodiment of the invention, a digital receiver is provided for receiving a digital signal with a first sequence of digital values having a first data rate. The digital values of the first sequence are time positioned according to a data clock having a clock frequency corresponding to the first data rate one value after another value, being delimited by so-called transition points (in ideal cases) or transition areas. At the transition points, signal edges occur depending on the adjacent digital values (a positive or rising edge will occur, if a high value follows a low value, and a negative or falling edge will occur, if a low value follows a high value). The digital receiver samples the digital signal at a second sampling rate being greater than the first data rate, detects a timing information about time positions of the digital values with respect to a reference time, and determines the digital values of the first sequence by using the derived timing information.

[0009] The digital signal received at the digital receiver might have the first data rate being constant (in ideal case). Alternatively, the data rate of the received digital signal varies at least slightly over the time about the first data rate, such variation also being referred to as jitter that might be regarded as being induced into the digital signal.

[0010] A sampling at a sampling rate greater than the data rate of the sampled signal is often being referred to as oversampling. An oversampled signal is said to be oversampled by a certain factor, wherein said factor corresponds to the ratio of the data rate of the second sequence of digital values and the first sequence of digital values. This factor might be a natural number greater than 1.

[0011] In an embodiment, the data rate (or the average data rate) of the digital signal to be recovered is known, and a corresponding reference clock signal is generated, having (at least substantially) the same frequency as the data clock (but an unknown phase relation).

[0012] In an embodiment, the digital values of the first sequence of digital values are binary values (out of a set of consisting of a "low" or "0" value and a "high" or "1 " value) or so-called bits.

[0013] In an embodiment, the timing information is an information about the transition points or the center time of the digital values (i.e. the time in the middle between two adjacent transition points) with respect to corresponding clock pulses of the reference clock signal. In the following, the time distance between the transition points and the reference clock points related to the unity time is referred to as phase information.

[0014] In an ideal case, if the first sequence is a binary or bit sequence out of a set of a low value or a high value, the digital signal only shows one of a high value or a low value between the transition points delimiting the bits. In real cases, disturbances or interferences are induced into the digital signal (e.g. while traveling along the communication lines between the communication nodes of a digital communication system). The disturbances can vary from short time events or glitches smaller than a time period corresponding to the oversampling ratio (such events would not always be sampled), as wide as one or multiple samples up to the inverting of the value of whole bits or bit sequences. Such disturbances might lead to a wrong detection of a transition and therewith to a wrong phase information.

[0015] In order to reduce or even avoid such miss-detection, the phase information is determined by evaluating a plurality of subsequent sets of values of the second sequence of digital values. Evaluating a plurality of subsequent sets of values of the second sequence might be regarded as performing a (time discrete) filtering of the second sequence, thereby generating a filtered or third digital sequence at the same second data rate.

[0016] In a further embodiment, a linear filtering is performed, wherein the filter characteristic can be described by a time discrete transfer function, the transfer function describing an output sequence of such filter in response to a unity pulse (time- discrete Dirac pulse). The filter might be a so-called Infinite Impulse Response -MR- filter having a transfer function with an infinite number of values, or a so-called Finite Impulse response -FIR- filter having a transfer function with a finite number of values. In an embodiment the filter is chosen having low pass characteristics.

[0017] In a further embodiment the filter is a FIR filter with a transfer function being a sequence of consecutive values. In an embodiment the number of the consecutive values is equal to the oversampling ratio.

[0018] In a further embodiment, the values of the transfer function are all equal, so that the filter performs a moving average over the second sequence.

[0019] In a further embodiment, the sequence of values being derived by comparing a linear filtering result (e.g. the moving average) with a threshold value, e.g. with a mean value between the low value and the high value, and the high value is assigned, if the filter result is above the threshold and the low value is assigned, if the filtering result is below the threshold.

[0020] In an embodiment, in a first step, at a certain point in time the average of n latest succeeding samples (of the second sequence) is determined, wherein n is the oversampling ratio. If the average is above a certain threshold, e.g. the mean between the low value and the high value, the high value is assigned to the filtering result (if the oversampling ratio is an uneven number, e.g. 5, such assignment can be carried out by a majority voting of the succeeding samples. In a next step, an average building is performed by using the four latest samples and the next sample that follows the group. In further steps, the average building is each performed with the four latest samples and the actual sample (in other words, a moving average performed by shifting a window over the second sequence according to the second data rate). In parallel, it is checked, whether a transition occurred, e.g. by comparing the average values or the assigned values.

[0021] The phase can only be determined, if a transition occurred. For an undisturbed signal, a timing of the first sequence might be determined by detecting n (n being a natural number greater 1 ) succeeding samples with the same value. After a transition, the first sample position of n succeeding samples with the same value marks the phase of the data signal. For a disturbed signal, the first sample position of n succeeding samples with the highest average value marks the phase of the data signal.

[0022] In an embodiment, if the reference clock varies slightly compared to the data-rate, the sample position of n-1 to n succeeding samples with the same value (undisturbed signal) or the highest average value (disturbed signal) marks the phase of the data signal; this is important if there occurs already a transition after the bit currently sampled.

[0023] The phase position can be continuously monitored and corrected by the methods described above.

[0024] An advantage of detecting the phase or edge information from a filter result of the oversampled signal avoids a misdetection of edges e.g. due to short term disturbances or noise affecting the digital signal traveling on a communication channel.

[0025] In an embodiment, the transfer function of the filter is designed to compensate for certain disturbance or noise patterns or at least reduce the effect of such disturbance or noise to the data detection, so that the oversampling algorithm will find the proper phase relation of the disturbed data signal to the reference time base.

[0026] Further, the asynchronous signal detection might be advantageously applied, if the data rate of the data signal is known in principle, but is out of bandwidth of a CDR, which does not allow locking the CDR to the data rate.

[0027] In an embodiment, an actual value of the disturbances is determined, e.g. by measuring a Bit Error Ratio (BER) in limits from BER = 0 to a maximum value (e.g. BER = 1 ^*10-2). Thereto, disturbances might be applied to the digital signal to be varied on purpose in corresponding limits. The disturbances can vary from short-time events or glitches smaller than a time period corresponding to the oversampling ratio (such events would not always be sampled), as wide as one or multiple samples up to the inverting of the value of whole bits or bit sequences. For this reason the oversampling algorithm is selected not to filter the signal in a way to suppress glitches or recover whole bits since this would influence the measurement result (e.g.: result in a lower measured BER than the real BER).

[0028] In an embodiment, determining the digital values of the first sequence of digital values is performed by selecting certain digital values of the second sequence of digital values according to the determined phase information.

[0029] In an embodiment thereto, one value out of each data block is being selected each at a defined fixed position (phase locked), e.g. only one sample in or close to the middle of the bit borders being determined on the base of the phase information. This selection might be carried out without any filtering (e.g. averaging). Such selected values can e.g. be used to measure the quality of the received signal (e.g. the BER).

[0030] In an embodiment, to tune the results of this measurement (e.g. adapt to a certain characteristic) several samples within the borders of the bit at the detected phase can be selected to be filtered, e.g. for suppressing certain effects, e.g. interferences that occur close to a signal edge which might influence the phase detection resulting in locking to a wrong phase.

[0031] Such filtering might make data detection robust to interferences, thus increasing the liability of digital data communication.

[0032] In a further embodiment, to make the algorithm more robust to interferences, the phase is locked on a clean signal (if possible), before interferences starts.

[0033] Embodiments of the invention can be partly or entirely embodied or supported by one or more suitable software programs, which can be stored on or otherwise provided by any kind of data carrier, and which might be executed in or by any suitable data processing unit.

BRIEF DESCRIPTION OF DRAWINGS

[0034] Other objects and many of the attendant advantages of embodiments of the present invention will be readily appreciated and become better understood by reference to the following more detailed description of embodiments in connection with the accompanied drawings. Features that are substantially or functionally equal or similar will be referred to by the same reference signs.

[0035] Fig. 1 shows an exemplary block diagram of a digital communication system comprising a transmitter for transmitting a digital signal with digital data and a receiver for detecting the digital data from the digital signal,

[0036] Fig. 2 shows a more detailed exemplary block diagram of a phase detector of the receiver of Fig.1 ,

[0037] Fig. 3 shows a more detailed exemplary block diagram of a selector for selecting values of an oversampled sequence based on a phase information determined by the phase detector of Fig.2, and

[0038] Fig. 4 shows a section of an exemplary course of the digital signal received at the receiver and further shows a set of sequences generated from the received digital signal.

[0039] Fig. 1 shows a communication system comprising a transmitter 10 and a receiver 20. The transmitter 10 comprises a signal driver 11 and a data clock 12. The data clock 12 provides a data clock signal T1 to the signal driver 11 that generates a digital signal S1 of a first sequence of digital values D1 at a first data rate corresponding to the frequency (or the pulse rate) of the data clock signal T1.

[0040] The receiver comprises a sampling circuit 21 , a phase detector 22, a value selector 23, and a reference clock 24. The reference clock generates a sampling clock signal T2 having a multiple frequency compared to the data clock signal T1. The ratio between the frequency of the data clock signal and the sampling clock signal is being referred to as oversampling ratio; for the following examples, this ratio is chosen to be

5. The sampling circuit 21 samples the received digital signal at sampling points corresponding to the sampling clock signal and generates a second sequence of digital values D2 at a second data rate corresponding to the frequency (or the pulse rate) of the sampling clock signal T2.

[0041 ] The reference clock 24 further generates a reference time base T1 ' having the same frequency as the data signal D1 , but an initially unknown phase relation. The phase detector 22 detects a time position PH of the values of the first sequence of digital values D1 with respect to the reference time base TV, e.g. the time distance between the clock pulses and the bit edges or transitions of the values of the first sequence D1 related to the duration of one bit (also being referred to as unity interval); this time information is also being referred to as phase information or phase PH in the following. The phase detector thereto performs a filtering of the second sequence of digital values D2 resulting in a third sequence of digital values D3 (i.e. the filtering result), and detects the phase PH from events or patterns within this sequence D3. Exemplary filtering processes will be described in more details under Fig.2.

[0042] The selector 23 generates a detected sequence of digital values D1 ' out of the second sequence of digital values D2 on a base of a selection process being time- controlled by the phase PH; in other words, the selector 23 detects digital content (i.e. the first sequence of digital values D1 ) of the digital signal S1. The detected sequence of digital values D1 ' corresponds to the first sequence of digital values D1. In ideal case, i.e. if no detection error occurs, the detected sequence of digital values D1 ' is a time-shifted copy of the first sequence of digital values D1. Exemplary selection processes will be described in more details under Fig.3. [0043] Fig.2 shows a more detailed exemplary block diagram of the phase detector 22. The phase detector exemplary comprises a first filter circuit 221 and an evaluation circuit 222. The first filter circuit 221 receives the second sequence of digital values D2, and generates a third sequence of digital values D3 as filtering result that is provided to the evaluation circuit 222. The evaluation circuit determines the phase PH by evaluation of the third sequence of digital values D3.

[0044] The first filter circuit 221 might comprise a linear filter having a transfer function being a sequence of consecutive values, wherein the number of the consecutive values is preferably equal to the oversampling ratio. The values of the transfer function might be chosen to be all equal.

[0045] For an oversampling ratio equal to 5, in a first step, at a certain point in time the average of the 5 latest succeeding samples (of the second sequence) is determined. Such averaging can be carried out by a majority voting of the succeeding samples). In a next step, an averaging is performed by using the 4 latest samples and the next or actual sample that follows the group and a corresponding value is assigned to a next value of the filtering result D3. In further steps, the average building is each performed with the four latest samples and the actual sample (in other words, a moving average performed by shifting a window over the second sequence according to the second data rate).

[0046] The evaluation circuit 222 detects a phase information PH from the filtering result D3. Depending on the kind of disturbances, different evaluation processes might be applied. In a case of a substantially undisturbed signal, after an occurrence of a transition, a first consecutive sequence of 5 similar values within the filtering result might be detected. The position of such detected sequence marks the time position of the corresponding bit value with an (accuracy of 1/5 of the bit interval). In the case of a significantly disturbed signal, the first sample position of 5 succeeding samples with the highest average value might be chosen to mark the phase PH of the digital signal S1.

[0047] Fig.3 now shows a more detailed exemplary block diagram of the selector 23. The selector 23 exemplary comprises a second filter circuit 231 and an output circuit 232. The second filter circuit 231 receives the second sequence of digital values D2, and generates a fourth sequence of digital values D4 as filtering result that is provided to the output circuit 232. The output circuit selects values of the a fourth sequence of digital values D4 controlled by the phase PH as output of the receiver 20, wherein the output corresponds to the detected sequence of digital values D1 '.

[0048] As described above, the digital signal S1 might be disturbed by disturbances or interferences induced into the digital signal S1. Depending on the kind of such disturbances, different selection processes might be applied.

[0049] In a first alternative, e.g. for detecting substantially undisturbed signals, one value out of each data block is selected each at a defined fixed position with respect to the reference clock T1 ' (phase locked). In this case the second digital filter 231 might be bypassed (e.g. by means of a switch not being shown here). In this case the fourth sequence D4 equals to the second sequence D2. The output circuit 232 consecutively selects one sample in or close to the middle of the bit borders derived from the phase PH (e.g. corresponding to a phase of 180 degree); for an exemplary oversampling ratio of 5, every 5^th bit each at or close to the middle between the bit borders is selected. Such selection process can also be used to measure the quality of a disturbed received signal (e.g. by determining a bit error ratio value -BER-).

[0050] In a second alternative, e.g. for detecting significantly disturbed signals the second digital filter might perform a filtering by determining an average of a certain number of samples, wherein this number might be chosen to be smaller than the oversampling ratio, e.g. 3 for an oversampling ratio of 5. This allows for suppressing certain effects, e.g. interferences that occur close to a signal edge which might influence the phase detection resulting in a wrong phase. Such filtering might also help to make data detection robust to interferences, i.e. to achieve a detection with a low

BER.

[0051 ] If the reference clock varies slightly compared to the data rate, the sample position of 4 to 5 succeeding samples with the same value (e.g. in case of an undisturbed signal) or the highest average value (e.g. in case of a disturbed signal) marks the phase of the data signal; this is important if there occurs already a transition after the bit which is the currently sampled bit.

[0052] In a further embodiment, to make the algorithm more robust to interferences, if possible the phase PH is determined before interferences are induced into the digital signal S1. This phase PH is now kept until a next phase without disturbances occurs. After locking to the kept phase PH, the phase position is now fixed. This works also as long as the data rate T1 and the reference clock frequency T2 do not drift widely, which means that the data rate T1 and the reference clock frequency T2 are stable in certain limits.

[0053] The bit border (and therewith the correct phase) can only be found if there is a change of the bit value which results in a transition; but as long as there is no transition the actual value of the signal can still be determined since every sample has the same value which is also the value of the succeeding bits; this value can already be used before phase locking as oversampling result for the second stage.

[0054] Optionally, a certain run-length of a maximum number of succeeding bits with the same value is defined; if there does not occur any transition within a time period of such defined maximum number, the phase-locking mechanism might abort; in this case an information might be provided informing that the phase could not be found.

[0055] Fig. 4 shows a section of an exemplary course of the digital signal S1 over the time t received at the receiver. The digital signal S1 exemplary shows a "010" sequence representing an exemplary. Further the digital signal shows exemplary disturbances (noise and glitches) being added to such sequence. Below the digital sequence a train of arrows symbolized the clock pulses of the sampling clock signal

T2. Below, the second sequence of digital values D2 is shown as an exemplary result of sampling the data signal S1 at the clock pulses T2. It can be seen that sampling errors occurs at the 8^th position and the 12^th position of the second sequence of digital values D2. Below the second sequence of digital values D2, an exemplary filter result sequence D3 is shown as result of a moving average of 5 samples. It can be seen that the maximum value of this sequence is close to the middle of the "1 " value of the digital signal, although a sampling error occurred just at this position. In the row below, a phase PH is exemplary derived from the position of the maximum value of D3. Alternatively, the phase PH might be derived from the minimum value(s) of D3, or from a combination of minimum and maximum values of D3. In the last row, selected values of the fourth sequence of digital values D4 being derived by a majority voting of 3 samples at each the center of the bit intervals of the first data signal being marked by the phase PH are shown; the sequence of these values form the detection result D1 ' of the receiver 20.

Claims

1. A digital receiver (20) for receiving a digital signal (S1 ) comprising a first sequence of digital values (D1 ) being transmitted with a first data rate (T1 ), comprising:

a sampling circuit (21 ) adapted for sampling the digital signal (S1 ) at a second sampling rate (T2) being greater than the first data rate (T1 ), and generating a corresponding second sequence of digital values (D2),

an phase detector (22) adapted for detecting an indication about a time position (PH) of the values of the first sequence of digital values (D1 ) with respect to a reference time base, by filtering the second sequence of digital values (D2) according to a first filter function (221 ), and evaluating a corresponding filtering result (D3), and

a selector (23) adapted for detecting the first sequence of digital values (D1 ) from the second sequence of digital values (D2) according to the indication about the time position (PH).

2. The digital receiver (20) of the preceding claim, wherein the reference time base is a reference clock signal having a frequency corresponding to the first data rate, and wherein the indication about the time position is an information of the phase of the second sequence of digital values with respect to the reference clock.

3. The digital receiver (20) of claim 1 or any one of the preceding claims, wherein a ratio of the second data rate (T2) and the first data rate (T 1 ) is a natural number greater than 1.

4. The digital receiver (20) of claim 1 or any one of the preceding claims, wherein the first filter function (221 ) comprises a linear filtering having a finite impulse response characteristic with a filter transfer function having an finite number of values, wherein the number is preferably equal to the ratio of the second data rate (T2) and the first data rate (T1 ).

5. The digital receiver (20) of the preceding claim, wherein the values of the transfer function are all equal, so that a moving average over the second sequence of digital values (D2) is performed.

6. The digital receiver (20) of claim 1 or any one of the preceding claims, wherein the phase detector (22) is adapted for identifying the time position (PH) as a position of one of: a relative maximum, and a relative minimum of the filtering result (D3).

7. The digital receiver (20) of claim 1 or any one of the preceding claims, wherein the selector (23) is adapted for detecting the first sequence of digital values (D1 ) by providing a filtering of the second sequence of digital values (D2) according to a second filter function (231 ), and selecting values of a correspondingly filtered sequence of digital values (D4) in dependency of the indication about the time position (PH).

8. The digital receiver (20) of the preceding claim, further comprising a switch for selecting a filter characteristic of the second filter function (231 ) out of a plural ity of different characteristics.

9. The digital receiver (20) of the preceding claim, wherein one of the different characteristics is a by-pass function.

10. The digital receiver (20) of claim 8 or the preceding claim, wherein at least one of the different characteristics is a moving average function over a selected number of values.

11. The digital receiver (20) of claim 1 or any one of the preceding claims 2-6, wherein the selector (23) is adapted for detecting the first sequence of digital values (D1 ) from the second sequence of digital values (D2) by selecting a plurality of values of each set of values of the second sequence of digital values

(D2) depending on the indication about the time position (PH), preferably a defined number of values closest to the center of each value of the first sequence of digital values (D1 ), and determining each the values of the first sequence of digital values (D1 ) as a function of the each selected values.

12. The digital receiver (20) of the preceding claim, wherein the values of the first sequence of digital values (D1 ) are each determined by one of: determining an average of the selected values, and performing a majority vote of the each selected values.

13. The digital receiver (20) of claim 1 or any one of the preceding claims 2-6, wherein the selector (23) is adapted for detecting the first sequence of digital values (D1¹) from the second sequence of digital values (D2) by selecting one value out of each set of values of the second sequence of digital values (D2) depending on the indication about the time position (PH), preferably each the value closest to the center of the values of the first sequence of digital values

(D1 ).

14. A method determining a first sequence of digital values (D1 ) from a digital signal (S1 ) being transmitted with a first data rate (T1 ), comprising:

sampling the digital signal (S1 ) at a second sampling rate (T2) being greater than the first data rate (T1 ), and generating a corresponding second sequence of digital values (D2),

detecting an indication about a time position (PH) of the values of the first sequence of digital values (D1 ) with respect to a reference time base, by filtering the second sequence of digital values (D2), and evaluating a corresponding filtering result (D3), and

detecting the first sequence of digital values (D1 ) from the second sequence of digital values (D2) according to the indication about the time position (PH).

15. A software program or product, preferably stored on a data carrier, for executing the method of the preceding claim, when run on a data processing system such as a computer.