WO2009022517A1 - 配線基板、及び、液晶表示装置 - Google Patents
配線基板、及び、液晶表示装置 Download PDFInfo
- Publication number
- WO2009022517A1 WO2009022517A1 PCT/JP2008/062898 JP2008062898W WO2009022517A1 WO 2009022517 A1 WO2009022517 A1 WO 2009022517A1 JP 2008062898 W JP2008062898 W JP 2008062898W WO 2009022517 A1 WO2009022517 A1 WO 2009022517A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- row
- wiring board
- liquid crystal
- display device
- crystal display
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Structure Of Printed Boards (AREA)
- Liquid Crystal (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200880102513A CN101779526A (zh) | 2007-08-10 | 2008-07-17 | 配线基板和液晶显示装置 |
US12/673,440 US20120006584A1 (en) | 2007-08-10 | 2008-07-17 | Wiring board and liquid crystal display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007210336 | 2007-08-10 | ||
JP2007-210336 | 2007-08-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009022517A1 true WO2009022517A1 (ja) | 2009-02-19 |
Family
ID=40350572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/062898 WO2009022517A1 (ja) | 2007-08-10 | 2008-07-17 | 配線基板、及び、液晶表示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20120006584A1 (ja) |
CN (1) | CN101779526A (ja) |
WO (1) | WO2009022517A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013065364A (ja) * | 2011-09-15 | 2013-04-11 | Dainippon Printing Co Ltd | サスペンション用基板、サスペンション、素子付サスペンション、ハードディスクドライブ、およびサスペンション用基板の製造方法 |
JP2015133165A (ja) * | 2015-02-23 | 2015-07-23 | 大日本印刷株式会社 | サスペンション用基板、サスペンション、ヘッド付サスペンション、およびハードディスクドライブ |
JP2017097040A (ja) * | 2015-11-19 | 2017-06-01 | 三菱電機株式会社 | 液晶表示装置 |
JP2022003399A (ja) * | 2014-09-05 | 2022-01-11 | 株式会社半導体エネルギー研究所 | 表示装置 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI423410B (zh) * | 2010-12-31 | 2014-01-11 | Au Optronics Corp | 金屬導電結構及其製作方法 |
CN102655131A (zh) * | 2011-03-04 | 2012-09-05 | 元太科技工业股份有限公司 | 电极阵列及电极阵列制作方法 |
US9508618B2 (en) * | 2014-04-11 | 2016-11-29 | Globalfoundries Inc. | Staggered electrical frame structures for frame area reduction |
CN105093758A (zh) * | 2015-09-07 | 2015-11-25 | 深圳市华星光电技术有限公司 | 一种液晶显示面板及装置 |
CN205264316U (zh) * | 2015-12-30 | 2016-05-25 | 京东方科技集团股份有限公司 | 阵列基板及显示器件 |
CN106338866B (zh) * | 2016-10-18 | 2019-08-02 | 武汉华星光电技术有限公司 | 一种液晶面板的焊盘区域结构 |
CN107422551A (zh) * | 2017-07-25 | 2017-12-01 | 武汉天马微电子有限公司 | 一种显示装置 |
CN107167971A (zh) * | 2017-07-28 | 2017-09-15 | 武汉天马微电子有限公司 | 显示面板和显示装置 |
KR102481818B1 (ko) | 2017-08-22 | 2022-12-28 | 삼성디스플레이 주식회사 | 전자 부품 및 이를 포함하는 전자 장치 |
WO2021077334A1 (zh) * | 2019-10-23 | 2021-04-29 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11282012A (ja) * | 1998-03-30 | 1999-10-15 | Seiko Epson Corp | アクティブマトリクス基板および液晶表示装置 |
JP2002202522A (ja) * | 2000-12-13 | 2002-07-19 | Lg Phillips Lcd Co Ltd | 液晶ディスプレイパネル及びその製造方法 |
JP2004252466A (ja) * | 2003-02-20 | 2004-09-09 | Samsung Electronics Co Ltd | 駆動ic及びこれを具備したディスプレイ装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1195243C (zh) * | 1999-09-30 | 2005-03-30 | 三星电子株式会社 | 用于液晶显示器的薄膜晶体管阵列屏板及其制造方法 |
CN1592866A (zh) * | 2000-11-08 | 2005-03-09 | 西铁城时计株式会社 | 液晶显示装置 |
KR100795344B1 (ko) * | 2001-05-29 | 2008-01-17 | 엘지.필립스 엘시디 주식회사 | 액정표시장치용 어레이 기판 및 그의 제조방법 |
TW200530655A (en) * | 2004-03-05 | 2005-09-16 | Toppoly Optoelectronics Corp | Display panel, lead pad structure, lead pad array structure and method of fabricating the same |
-
2008
- 2008-07-17 CN CN200880102513A patent/CN101779526A/zh active Pending
- 2008-07-17 US US12/673,440 patent/US20120006584A1/en not_active Abandoned
- 2008-07-17 WO PCT/JP2008/062898 patent/WO2009022517A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11282012A (ja) * | 1998-03-30 | 1999-10-15 | Seiko Epson Corp | アクティブマトリクス基板および液晶表示装置 |
JP2002202522A (ja) * | 2000-12-13 | 2002-07-19 | Lg Phillips Lcd Co Ltd | 液晶ディスプレイパネル及びその製造方法 |
JP2004252466A (ja) * | 2003-02-20 | 2004-09-09 | Samsung Electronics Co Ltd | 駆動ic及びこれを具備したディスプレイ装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013065364A (ja) * | 2011-09-15 | 2013-04-11 | Dainippon Printing Co Ltd | サスペンション用基板、サスペンション、素子付サスペンション、ハードディスクドライブ、およびサスペンション用基板の製造方法 |
JP2022003399A (ja) * | 2014-09-05 | 2022-01-11 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP2015133165A (ja) * | 2015-02-23 | 2015-07-23 | 大日本印刷株式会社 | サスペンション用基板、サスペンション、ヘッド付サスペンション、およびハードディスクドライブ |
JP2017097040A (ja) * | 2015-11-19 | 2017-06-01 | 三菱電機株式会社 | 液晶表示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101779526A (zh) | 2010-07-14 |
US20120006584A1 (en) | 2012-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2009022517A1 (ja) | 配線基板、及び、液晶表示装置 | |
WO2009017828A3 (en) | Semiconductor device with dynamic array section | |
TW200622364A (en) | Electro-optical device and electronic apparatus | |
TW200733284A (en) | Structure and method for monitoring stress-induced degradation of conductive interconnects | |
TW200715491A (en) | The arrangement of conductive pads on grid array package and on circuit board | |
EP2447815A3 (en) | Touch screen panel and display device having the same | |
WO2010104744A3 (en) | Electronic devices formed of two or more substrates bonded together, electronic systems comprising electronic devices and methods of making electronic devices | |
TW200629570A (en) | Semiconductor device, electronic device, and method of manufacturing semiconductor device | |
GB2481771A (en) | Printed circuit board cooling assembly | |
WO2009022522A1 (ja) | 配線基板、及び、液晶表示装置 | |
TWI264816B (en) | Substrate for liquid crystal display device and liquid crystal display device having the same | |
TW200734731A (en) | Multi-domain vertically alignment liquid crystal display panel | |
JP2006330711A5 (ja) | ||
WO2010126954A3 (en) | Chiplet display with oriented chiplets and busses | |
TW200802708A (en) | Semiconductor device having carbon nanotube interconnects and method of fabrication | |
TW200745704A (en) | Flat-panel display devices and manufacturing method therefor | |
TW200702864A (en) | Array substrate and display device having the same | |
TW200700852A (en) | Liquid crystal display panel and pixel structure | |
WO2009044583A1 (ja) | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、及び、液晶表示装置 | |
TW200802275A (en) | Dual-scan display | |
WO2009041112A1 (ja) | 表示装置 | |
TWI264127B (en) | Chip package and substrate thereof | |
TW200701412A (en) | Package substrate with improved structure for thermal dissipation and electronic device using the same | |
WO2009075220A1 (ja) | プローブカード | |
WO2009032506A3 (en) | Systems and methods for ball grid array (bga) escape routing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200880102513.6 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08778240 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12673440 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08778240 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: JP |