WO2009000122A1 - Dispositif et procédé pour mesurer le taux d'utilisation d'un processeur - Google Patents

Dispositif et procédé pour mesurer le taux d'utilisation d'un processeur Download PDF

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Publication number
WO2009000122A1
WO2009000122A1 PCT/CN2007/003784 CN2007003784W WO2009000122A1 WO 2009000122 A1 WO2009000122 A1 WO 2009000122A1 CN 2007003784 W CN2007003784 W CN 2007003784W WO 2009000122 A1 WO2009000122 A1 WO 2009000122A1
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WO
WIPO (PCT)
Prior art keywords
processor
measuring
utilization
counter
bus
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Application number
PCT/CN2007/003784
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English (en)
Chinese (zh)
Inventor
Zhiqiang Liu
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Zte Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zte Corporation filed Critical Zte Corporation
Publication of WO2009000122A1 publication Critical patent/WO2009000122A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/349—Performance evaluation by tracing or monitoring for interfaces, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

Definitions

  • the present invention relates to a processor utilization measurement technique, and more particularly to an apparatus and method for real-time measurement of processor utilization or load, which is particularly suitable for an embedded system processor. Utilization measurement. BACKGROUND OF THE INVENTION Since embedded systems have very strict requirements on hardware cost and power consumption, the selection of a processor and its associated clock frequency and power supply voltage are the main factors of concern, and the utilization rate of the processor during normal system operation. It is the main reference for determining these factors. Moreover, some embedded systems can adjust the 4f frequency or operating voltage of the processor in real time according to the measurement result, thereby reducing the system power consumption.
  • Processor utilization is relative to a statistical period of time, that is, the ratio of the actual work done by the processor during this statistical time to the full load of the processor. Therefore, what metrics are used to measure the processor's workload and how it is measured becomes the key to processor utilization measurement.
  • the current known methods for measuring processor utilization are mainly the following: One method is to use a periodic timer as a trigger source for sampling the processor load, which is determined by the operating system each time the timer expires. Whether the processor is executing valid code or idle code and counting accordingly.
  • the timer expires as the full load indicator of the processor, and the value minus the number of executed idle code samples is taken as the payload indicator of the processor during the period, and their ratio is that the processor is The utilization of this statistical time.
  • this method first needs operating system support, and the accuracy of the measurement depends on the period of the timer. The smaller the period, the higher the accuracy, but the greater the impact on system performance.
  • Another way is to define an idle process that accumulates a global variable. In an hour, let the operating system run only the idle process, and use the accumulated value of the obtained global variable as the processor full load indicator. In the latter statistical period, the difference of the global variable is used as the processor payload indicator.
  • the time of the statistical period is taken as the processor full load indicator, and the difference between the processor core counter and the counting period is multiplied by the counting clock period, and the obtained time is taken as the processor payload index, and the ratio between the two is that the processor is in the processor.
  • the utilization of the segment statistics time The premise of the above method is that the processor must comply with certain specifications, which is very rare for embedded processors. Therefore, it can be seen from the above description that the technology currently used has a problem of dependence on the operating system, and has defects such as large measurement error and affecting system performance. Based on such a background, if it is possible to provide an independent operating system, A universal processor utilization measurement device is undoubtedly ideal for the independence and accuracy of processor utilization measurements and system maintenance.
  • the present invention has been made in view of the above problems in the related art. To this end, the present invention aims to provide a measurement technique for the utilization of an embedded system processor. First, a general-purpose processor utilization measuring device independent of an operating system is provided, and thereafter, a basic device is proposed. A processor utilization measurement method that can be used for measurement in a single statistical period or multiple statistical periods.
  • the technical solution of the present invention is as follows.
  • a measurement device for processor utilization of an embedded system comprising: a system bus connected to a bus monitor, a counter, and a processor; a bus monitor for monitoring a system bus, generating a counter when the expected bus feature is identified Trigger signal; timer, set the timing of the utilization statistics period by setting its timing period; the interrupt controller is used to generate an interrupt trigger signal when the timer period of the timer arrives.
  • the processor generates an expected bus feature on the system bus when performing the predetermined measurement procedure.
  • the counter counts the expected bus characteristics as the processor's workload metric.
  • a method for measuring processor utilization comprising: Step one: pre-setting a measurement procedure of a processor full load indicator; Step two, in a system booting phase, running a measurement program within a predetermined time The full load indicator of the processor is measured, and the value of the counter is read as the raw data of the full load indicator.
  • Step 3 During the running of the system, during the statistical period of the measurement utilization, the corresponding data is obtained according to the original data. The current full load indicator, and the processor's payload indicator is obtained according to the current full load indicator and the counter value; Step 4, the processor utilization rate in the statistical period is calculated according to the effective load indicator and the current full load indicator.
  • the measurement program is a piece of processor executable code that, when executed, produces the expected bus characteristics, and the system triggers the counter to start counting when the expected bus characteristics are detected.
  • the timer is set to a single timing mode, and the timing period is the duration of the statistical period.
  • the timer is set to the periodic timing mode, and the timer is automatically restarted after expiration.
  • the processor utilization is calculated by a calculation program.
  • FIG. 1 is a schematic diagram showing the functional structure of a measuring device for measuring processor utilization according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing the functional structure of an example 1 of the measuring device shown in FIG. 1.
  • FIG. Schematic diagram of the functional structure of the example 2 of the measuring device
  • FIG. 4 is an operating system of the method for measuring the utilization of the processor according to the embodiment of the method of the present invention
  • Figure 5 is a flow chart showing a method of measuring processor utilization in accordance with an embodiment of the method of the present invention
  • Figure 6 is a diagram showing the execution of a system boot phase measurement procedure in a method in accordance with an embodiment of the present invention; The execution of the measurement program after the normal operation of the system in the method according to the embodiment of the method of the present invention;
  • FIG. 1 is a schematic diagram showing the functional structure of a measuring device for measuring processor utilization according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing the functional structure of an example 1 of the measuring device shown in FIG.
  • FIG. 8 is a schematic diagram of the circular data buffer and the effective indicator storage of each time period in the method according to the method embodiment of the present invention
  • FIG. 9a- Figure 9d shows the main processing flow of the technical solution of the present invention
  • Figure 9a shows the processing flow of the processor full-load index measurement in the system boot phase
  • Figure 9b shows the interrupt of the processor full-load index measurement in the system boot phase.
  • Process flow Figure 9c shows the processing flow of the processor full load indicator measurement after the system is running normally
  • Figure 9d shows the interrupt processing flow of the processor full load indicator measurement after the system is running normally.
  • a measuring device for processor utilization is provided.
  • a processor-executable code is defined as a processor load indicator measurement program (hereinafter referred to as a measurement program), and when the processor executes the measurement program, an expected bus feature is generated on a system bus (or a processor bus), and the bus monitors The counter starts counting when the expected bus feature is detected, wherein the system bus may be a combination of a control bus or a data bus or an address bus that is not limited to one, and the count value of the bus feature is used as a processor workload indicator.
  • the measuring device of the processor utilization comprises: a processor 101, a bus monitoring The device 102, the counter 103, the timer 104, the interrupt controller 105, and the processor system bus 106.
  • system bus 106 is coupled to bus monitor 102, counter 103, and processor 101.
  • the bus monitor 102 directly monitors the system bus 106.
  • a counter trigger signal 107 is generated which causes the counter 103 to begin counting.
  • the duration of the utilization statistics period is set by setting the timing period of the timer 104.
  • the interrupt controller 105 generates an interrupt trigger signal 108 when the timer cycle of the timer 104 arrives, and processes and saves the value of the counter through a timer interrupt service (Interrupt Service Routine, ISR for short), and processes it when necessary.
  • the device utilization calculation program (hereinafter referred to as the calculation program) is used to calculate the processor utilization rate of the statistical period.
  • processor 101 generates an expected bus feature on system bus 106 when performing a predetermined measurement procedure.
  • the count value of the counter 103 for the expected bus feature is used as the workload indicator of the processor 101.
  • Example 1 Figure 2 shows a processor and its peripherals as a core part of an embedded system.
  • the embedded processor Since the embedded processor is basically a System On Chip (SOC), it integrates a central processing unit (CPU) and many functions, including timers, interrupt controllers, counters, etc. .
  • the processor 201 includes a timer and an interrupt controller, so only one programmable logic device (Programmable Logic Device, PLD for short) 202 is implemented to implement the bus monitor and the counter, and the processor system is further included.
  • the bus 106 is a read only memory (ROM) 203 for storing a program or executing a program, and a random access memory (RAM) 204.
  • the control signal 205 is generated by a timer for suspending the measurement of the full load indicator of the processor during the booting phase.
  • Example 2 Another example of an embodiment of the apparatus of the present invention is shown in FIG.
  • the processor 301 integrates counters, timers, and interrupt controllers with only one system bus having the desired characteristics as the trigger signal 302 for the counter. Similar to the previous example 1, a processor bus 106 and a read only memory (ROM) 203, a random access memory (RAM) 204 for storing programs or executing programs are also included.
  • ROM read only memory
  • RAM random access memory
  • the difference between this example and the example 2 is that on the one hand, there is no need for a programmable logic device (PLD) on the hardware, on the other hand, the software is different, especially how to stop at the system booting stage.
  • PLD programmable logic device
  • Measurements made by the processor's full load indicator uses the following method: Timeout with a timer and an interrupt is generated, and the measurement indication is terminated in the timer ISR. Specifically, the processor full load indicator is measured at the appropriate timing during the system boot phase. The timer period is set, for example, 1 second before the measurement, and then the timer is started and measurement is started. After 1 second, the timer expires and an interrupt is generated. In the interrupt service routine, the measurement flag is modified to be false. The measurement program determines that the measurement flag is false and then aborts execution, and saves the acquired test data for use. Other aspects of the details of this example are substantially the same as in Example 1. Method Embodiment In this embodiment, a method of measuring processor utilization is provided. Preferably, the above-described measuring device is used. Of course, other suitable devices may be used to implement the present invention. 4 is a diagram showing the operational architecture of a measurement method in accordance with an embodiment of the method of the present invention. Measuring procedure
  • the method for measuring processor utilization in the method embodiment of the present invention includes the following processing: Step S502 (step one;), preset a measurement program of the processor full load indicator, for example, a processor may be defined.
  • Step S504 (Step 2), in the system boot phase, the measurement program is run, the full load indicator of the processor is measured within a predetermined time, and the value of the counter is read as the raw data of the full load indicator.
  • Step S506 (step 3), after the normal operation of the system, in the statistical period of measurement utilization, obtain the current full load indicator corresponding to the statistical period according to the original data, and obtain the processor according to the current full load index and the value of the counter.
  • the load indicator (equal to the difference between the current full load indicator and the value of the counter);
  • Step S508 (step 4), the calculation process is used to calculate the utilization rate of the processor in the statistical period according to the effective load indicator and the current full load indicator.
  • step S506 in the case of measuring a statistical period, the timer is set to a single timing mode, and the timing period is the duration of the statistical period; In the case of setting the timer to the periodic timing mode, the timer is automatically restarted after the expiration, so that in step S506, for each statistical period, the corresponding payload indicator needs to be stored in the data buffer. in.
  • a function as the execution code of the processor full-load indicator measurement during the system boot phase, and also use it as the idle process scheduled by the operating system when the processor is idle after the system is running normally.
  • the core part of the function is the measurement program, which is cyclically executed according to the measurement flag.
  • the execution of the measurement program produces the expected bus characteristics for the bus monitor to recognize and trigger the counter count (step S502).
  • a standard processor utilization minimum statistical period T is set, which is also referred to as a statistical period, such as 100 milliseconds, and the processor load indicator is relative to the time period.
  • the duration of the measurement period should be many times T, such as the value of the counter after one second measurement, then the processor full load indicator Cm (i.e., the current full load indicator described above) is obtained by dividing the value of this counter by 10 (step S504).
  • the processor payload index is obtained by subtracting the value Ci of the statistical period counter from Cm (Cm - Ci ) (step S506).
  • the processor utilization calculation program calculates the utilization rate U of the processor according to the following formula (Formula 1): (Step S508)
  • FIG. 7 shows the case where the application 701 and the measurement program are executed by the processor when the system is operating normally.
  • the processor payload indicator is measured at different statistical periods.
  • the period of the timer should be configured to be equal to the duration of the period, the counter is cleared and the timer is started.
  • the timer ISR reads the value of the counter and is calculated by the calculation program according to the above formula (1) to obtain the processor utilization rate for the period.
  • the method uses a ring buffer 801.
  • the size of the buffer determines the length of the longest statistical period. For the statistical period T is 100 milliseconds, if you want to get the processor utilization in the past 10 minutes, then the data.
  • the buffer needs to store 6000 data. During this longest period of time, multiple processor utilizations can be obtained, such as processor utilization Uls, U10s in the past 1 second, 10 seconds, 1 minute, 5 minutes, 10 minutes, etc. , Ulm, U5m and U10m.
  • the timer In order to keep measuring the processor's payload index, the timer should be configured as the periodic timing mode after the system is running normally. That is, the timer will be automatically restarted after the timer expires.
  • the timing period is set to the statistical period T, that is, 100 milliseconds.
  • T the statistical period
  • FIGS. 9a-9d show the main processing flow of the technical solution of the present invention.
  • Figure 9a shows the processing flow of the processor full-load indicator measurement during the system boot phase (corresponding to Example 1);
  • Figure 9a and Figure 9b show the processing flow of the processor full-load indicator measurement during the system boot phase (corresponding to Example 2) ).
  • Figure 9c shows the processing flow of the processor payload indicator measurement during normal system operation (corresponding to Example 1), which is used to calculate the processor utilization rate for a certain period of time in the future.
  • FIG. 9c and FIG. 9d show a processing flow of the processor payload indicator measurement during normal operation of the system, and are used for counting processor utilization times of a plurality of time periods in the past.
  • the timer when starting the measurement, the timer is first configured in a single timing mode with a period of 1 second. The measurement flag is then cycled through the measurement program to generate the expected characteristics of the bus, which counts the feature. When the timer expires, a control signal is sent to the PLD, so that the measurement flag is modified, and the current measurement is aborted.
  • Fig. 9b shows the processing flow of the example 2 to change the measurement flag by the ISR during the system booting phase.
  • Figure 9c shows the processing flow for measuring the processor utilization all the time.
  • the configuration timer is the periodic timing mode, the timing period is set to T, that is, 100 milliseconds, and then the timer is started, and the measurement flag is always true.
  • the measurement procedure is executed cyclically under the conditions.
  • Figure 9d shows that after each timer expires and an interrupt is generated, the timer ISR obtains the counter value, and then calculates the processor payload index for each period, and saves the counter value. After the counter is cleared, the ISR is exited and waited.
  • the multi-period measurement method provided by the present invention can display the processor utilization through the graphical human-machine interface, greatly facilitating the evaluation of the embedded system, especially the performance of the processor, and as a system design and processor selection. Important reference for the process of clock frequency determination.
  • the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

La présente invention concerne un dispositif pour mesurer le taux d'utilisation d'un processeur de système intégré comprenant : un bus système relié à un moniteur de bus, un compteur et le processeur ; le moniteur de bus est destiné à surveiller le bus système et générera un signal de déclenchement de compteur quand une caractéristique de bus anticipée est identifiée ; un minuteur pour régler l'écart de temps d'un intervalle de temps pour la statistique de taux d'utilisation en réglant son cycle de minuterie ; un contrôleur d'interruption pour générer un signal de déclenchement d'interruption quand le cycle de minuterie du minuteur arrive. En outre, la présente invention concerne également un procédé pour mesurer le taux d'utilisation d'un processeur de système intégré.
PCT/CN2007/003784 2007-06-25 2007-12-25 Dispositif et procédé pour mesurer le taux d'utilisation d'un processeur WO2009000122A1 (fr)

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TW201119285A (en) * 2009-07-29 2011-06-01 Ibm Identification of underutilized network devices
CN102662822B (zh) 2012-04-26 2015-02-04 华为技术有限公司 负载监控装置和方法
US10216526B2 (en) 2015-01-14 2019-02-26 Mediatek Inc. Controlling method for optimizing a processor and controlling system
CN105573885A (zh) * 2015-10-30 2016-05-11 北京中电华大电子设计有限责任公司 一种监测并统计底层硬件行为的方法及装置
CN108809299B (zh) * 2018-08-30 2022-07-08 歌尔光学科技有限公司 信号频率测量***
CN112540886B (zh) * 2020-11-26 2024-07-05 北京和利时***工程有限公司 Cpu负荷值检测方法和装置

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