WO2008155804A1 - 同時マルチスレッドの命令完了制御装置 - Google Patents

同時マルチスレッドの命令完了制御装置 Download PDF

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Publication number
WO2008155804A1
WO2008155804A1 PCT/JP2007/000662 JP2007000662W WO2008155804A1 WO 2008155804 A1 WO2008155804 A1 WO 2008155804A1 JP 2007000662 W JP2007000662 W JP 2007000662W WO 2008155804 A1 WO2008155804 A1 WO 2008155804A1
Authority
WO
WIPO (PCT)
Prior art keywords
thread
entry
completion
threads
select circuit
Prior art date
Application number
PCT/JP2007/000662
Other languages
English (en)
French (fr)
Inventor
Yasunobu Akizuki
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000662 priority Critical patent/WO2008155804A1/ja
Priority to EP07790188.2A priority patent/EP2159691B1/en
Priority to JP2009520145A priority patent/JP5201140B2/ja
Publication of WO2008155804A1 publication Critical patent/WO2008155804A1/ja
Priority to US12/637,273 priority patent/US20100095305A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/507—Low-level

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Programmable Controllers (AREA)

Abstract

　同時に複数スレッドを走らせプログラムを実行するシステムにおいて、ＣＳＥ１７の内部のエントリを、スレッドの数のグループに分割する。各グループは連続した記憶領域を割り当てるようにする。そして、各グループのエントリの最初の位置をポインタとしてポインタレジスタ選択回路３５において保持する。ポインタは各スレッドに対応させる。スレッド選択回路３６は、命令の実行完了判定を行なうスレッドを１つ選択し、エントリ選択回路３７に、ＣＳＥ１７からそのスレッドのエントリのコピーを完了対象エントリ３８に格納させ、完了判定部３９で完了判定させ、プログラマブルな資源の更新をさせる。スレッドの選択は、１つのスレッドに偏らないように行なう。
PCT/JP2007/000662 2007-06-20 2007-06-20 同時マルチスレッドの命令完了制御装置 WO2008155804A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/000662 WO2008155804A1 (ja) 2007-06-20 2007-06-20 同時マルチスレッドの命令完了制御装置
EP07790188.2A EP2159691B1 (en) 2007-06-20 2007-06-20 Simultaneous multithreaded instruction completion controller
JP2009520145A JP5201140B2 (ja) 2007-06-20 2007-06-20 同時マルチスレッドの命令完了制御装置
US12/637,273 US20100095305A1 (en) 2007-06-20 2009-12-14 Simultaneous multithread instruction completion controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000662 WO2008155804A1 (ja) 2007-06-20 2007-06-20 同時マルチスレッドの命令完了制御装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/637,273 Continuation US20100095305A1 (en) 2007-06-20 2009-12-14 Simultaneous multithread instruction completion controller

Publications (1)

Publication Number Publication Date
WO2008155804A1 true WO2008155804A1 (ja) 2008-12-24

Family

ID=40155969

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000662 WO2008155804A1 (ja) 2007-06-20 2007-06-20 同時マルチスレッドの命令完了制御装置

Country Status (4)

Country Link
US (1) US20100095305A1 (ja)
EP (1) EP2159691B1 (ja)
JP (1) JP5201140B2 (ja)
WO (1) WO2008155804A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11755329B2 (en) 2018-12-06 2023-09-12 Fujitsu Limited Arithmetic processing apparatus and method for selecting an executable instruction based on priority information written in response to priority flag comparison

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* Cited by examiner, † Cited by third party
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US8166146B2 (en) * 2008-09-29 2012-04-24 International Business Machines Corporation Providing improved message handling performance in computer systems utilizing shared network devices
US9304702B2 (en) 2014-05-29 2016-04-05 Netapp, Inc. System and method for parallelized performance data collection in a computing system
US9256477B2 (en) * 2014-05-29 2016-02-09 Netapp, Inc. Lockless waterfall thread communication
US9477521B2 (en) 2014-05-29 2016-10-25 Netapp, Inc. Method and system for scheduling repetitive tasks in O(1)
CN105592400A (zh) * 2014-10-24 2016-05-18 中兴通讯股份有限公司 一种应用专有节点的注册方法、通信方法和节点
CN108093380B (zh) * 2016-11-22 2022-11-08 中兴通讯股份有限公司 注册状态的确定方法、装置及***、cse

Citations (2)

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Publication number Priority date Publication date Assignee Title
US20040210743A1 (en) 2003-04-21 2004-10-21 International Business Machines Corporation Dynamically shared group completion table between multiple threads
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

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US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
GB0013336D0 (en) * 2000-06-01 2000-07-26 Sgs Thomson Microelectronics Forming an executable program
JP3727887B2 (ja) * 2002-02-19 2005-12-21 富士通株式会社 マルチスレッドプロセッサにおける共有レジスタファイル制御方式
FI116166B (fi) * 2002-06-20 2005-09-30 Nokia Corp Menetelmä ja järjestelmä sovellusistuntojen suorittamiseksi elektroniikkalaitteessa, ja elektroniikkalaite
US20050138333A1 (en) * 2003-12-19 2005-06-23 Samra Nicholas G. Thread switching mechanism
US7890734B2 (en) * 2004-06-30 2011-02-15 Open Computing Trust I & II Mechanism for selecting instructions for execution in a multithreaded processor
JP4956891B2 (ja) * 2004-07-26 2012-06-20 富士通株式会社 演算処理装置，情報処理装置および演算処理装置の制御方法
JP2006059068A (ja) * 2004-08-19 2006-03-02 Matsushita Electric Ind Co Ltd プロセッサ装置
KR100806274B1 (ko) * 2005-12-06 2008-02-22 한국전자통신연구원 멀티 쓰레디드 프로세서 기반의 병렬 시스템을 위한 적응형실행 방법
US8407715B2 (en) * 2007-04-30 2013-03-26 National Tsing Hua University Live range sensitive context switch procedure comprising a plurality of register sets associated with usage frequencies and live set information of tasks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040210743A1 (en) 2003-04-21 2004-10-21 International Business Machines Corporation Dynamically shared group completion table between multiple threads
JP2006343872A (ja) * 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2159691A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11755329B2 (en) 2018-12-06 2023-09-12 Fujitsu Limited Arithmetic processing apparatus and method for selecting an executable instruction based on priority information written in response to priority flag comparison

Also Published As

Publication number Publication date
JPWO2008155804A1 (ja) 2010-08-26
EP2159691A1 (en) 2010-03-03
JP5201140B2 (ja) 2013-06-05
EP2159691A4 (en) 2010-10-13
US20100095305A1 (en) 2010-04-15
EP2159691B1 (en) 2013-08-28

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