WO2008153330A1

WO2008153330A1 - Method and apparatus for transmitting/receiving data in mobile communication system

Info

Publication number: WO2008153330A1
Application number: PCT/KR2008/003289
Authority: WO
Inventors: Jong-Soo Choi; Yan Xin
Original assignee: Samsung Electronics Co., Ltd.
Priority date: 2007-06-15
Filing date: 2008-06-12
Publication date: 2008-12-18

Abstract

Disclosed is a method and apparatus for transmitting/receiving data in a mobile communication system. In the method and apparatus, when a data sequence subjected to parallel interleaving is mapped to a modulation symbol in consideration of priority and the modulation symbol with the data sequence mapped thereto is transmitted, a sub-block including only S bits or a majority of S bits is allocated to a higher reliable bit position, and a sub-block including only P bits or a majority of P bits is allocated to a lower reliable bit position.

Description

METHOD AND APPARATUS FOR TRANSMITTING/RECEIVING DATA IN MOBILE COMMUNICATION SYSTEM

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for transmitting/receiving data in a mobile communication system, and more particularly to a method and apparatus for transmitting/receiving data in a mobile communication system employing parallel interleaving.

2. Description of the Related Art

With the rapid progress of mobile communication systems, it is desired to develop technology capable of mass data transmission with a capacity close to the wired network capacity in a wireless network. In this way, as there is an increasing demand for a high-speed and high-capacity communication system capable of processing and transmitting various information, such as images and wireless data, while departing from voice-oriented services, it is requisite to improve system performance by using an appropriate channel coding scheme for enhancing system transmission efficiency. However, in view of system characteristics, a mobile communication system experiences information data loss due to the occurrence of inevitable errors that are caused by noise, interference, fading, and the like depending on channel conditions during data transmission.

Thus, various error control schemes for reducing information data loss due to error occurrence are used according to the types of channels, which leads to improvement in the reliability of a mobile communication system. The most popular ones among such error control techniques use an error-correcting code. Typical examples of the error-correcting code include a turbo code, a convolutional code, etc.

The turbo code is known to be excellent in performance gain at highspeed data transmission, as compared to the convolutional code that has been mainly used for error correction up to now, and has an advantage in that it can enhance the reliability of data transmission by effectively correcting errors due to noise occurring in a transmission channel.

FIG. 1 illustrates a structure of a transmitter in a typical mobile communication system employing parallel interleaving.

A channel encoder 110 channel-encodes input data, and outputs the encoded data. An output from the channel encoder 110 may be divided into systematic bits (S bits) and parity bits (P bits) according to encoding techniques used in the channel encoder 110. The encoded S and P bits are input into a rate matching unit 120.

The rate matching unit 120 conducts rate matching adaptive to a data transfer rate through bit puncturing or bit repetition. The S and P bits that have been subjected to rate matching are input into a distributor 130.

The distributor 130 distributes and outputs the rate-matched S and P bits to two parallel interleavers, that is, first and second interleavers 140, 150.

The first and second interleavers 140, 150 interleave the distributed S and P bits respectively, and then outputs the interleaved S and P bits to a parallel-to- serial converter 160. Typically, an interleaver prevents the occurrence of an burst error by causing adjacent symbols or bits to be affected by irregular channel fading.

The parallel-to-serial converter 160 converts the two interleaved data bits into serial bits, and outputs them to an M-ary modulator 170.

The M-ary modulator 170 symbol-maps the interleaved encoded bits according to a certain modulation scheme, such as 8PSK (Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 32QAM, and 64QAM, and transmits the symbol-mapped bits.

The method as illustrated in FIG. 1 improves performance by dividing information output from the channel encoder 110 into S and P bits, and symbol- mapping the S and P bits based on priority thereof. Such a method has been already known as SMP (Symbol Mapping based on Priority) technology.

In applying the SMP technology, the first interleaver 140 of the two interleavers connected in parallel with each other performs interleaving for the S bits, and the second interleaver 150 performs interleaving for the P bits. Subsequently, the M-ary modulator 170 symbol-maps the interleaved S and P bits according to a code rate and the reliability pattern of a high-order modulation scheme. When the SMP is applied to a data block to be transmitted, the number of bits that may be considered highly reliable is determined by the reliability pattern (e.g. [H H L L] in the case of 16QAM, and [H H M M L L] in the case of 64QAM) of a modulation scheme used in the M-ary modulator 170. In applying the SMP technology, a bit with higher priority (e.g. S bit) is allocated to a higher reliable bit position H₅ and a bit with lower priority (e.g. P bits) is allocated to a lower reliable bit position L. However, a high-order modulation symbol includes a medium reliable bit position M, the reliability of which is intermediate between those of H and L.

Therefore, when a bit (or sequence) block encoded by the channel encoder 110 is divided into only S and P bits, and the divided S and P bits are forwarded to the interleavers in a system supporting various code rates and data transfer rates, there is the following problem:

For example, it is assumed that a data transfer rate d of 0.37, 0.55, 0.65, 0.74, 0.88, 0.95, 1.0, or the like is used. The channel encoder 110 performs channel encoding, and then the rate matching unit 120 performs rate matching adaptive to a data transfer rate. If a data transfer rate <i is 1.0, only S bits remain in a data block and no P bit remains after the rate matching is performed because all P bits are punctured. Then, there is no data to be input into the second interleaver 150 (i.e. interleaver for P bits).

Also, if a data transfer rate d is 0.95, 95% of bits remaining in a data block after the rate matching are S bits, and 5% thereof are P bits, which is problematic in that unbalanced parallel interleaving is performed. In this way, the effect of parallel interleaving vanishes.

Therefore, there is a need for a method and apparatus for efficiently dividing rate-matched data by using a reliability pattern according to a high-order modulation scheme.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve at least the above-mentioned problems occurring in the prior art, and the present invention provides a method and apparatus for transmitting/receiving data in a mobile communication system, in which a data sequence channel-encoded in a transmitter using a parallel interleaver structure for performance improvement is divided (or distributed) into sub-blocks.

Further, the present invention provides a method and apparatus for transmitting/receiving data in a mobile communication system, in which when a data sequence subjected to parallel interleaving is mapped to a modulation symbol in consideration of priority and the modulation symbol with the data sequence mapped thereto is transmitted, a sub-block including only S bits or a majority of S bits is allocated to a higher reliable bit position, and a sub-block including only P bits or a majority of P bits is allocated to a lower reliable bit position.

In accordance with an aspect of the present invention, there is provided a method of transmitting data in a mobile communication system, the method including the steps of channel-encoding the data to be transmitted; subjecting the encoded data to rate-matching adaptive to a predetermined data transfer rate, and outputting the rate-matched data; and dividing systematic bits and parity bits constituting the rate-matched data into sub-block A and sub-block B, symbol mapping the sub-blocks A and B according to a predetermined modulation scheme, and then transmitting the symbol-mapped sub-blocks A and B, wherein in the step of dividing the systematic and parity bits into the sub-blocks A and B, a ratio of the number of the systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub-block B is determined according to the modulation scheme.

In accordance with another aspect of the present invention, there is provided an apparatus for transmitting data in a mobile communication system, the apparatus including a channel encoder for channel-encoding the data to be transmitted; a rate matching unit for subjecting the encoded data to rate-matching adaptive to a predetermined data transfer rate, and outputting the rate-matched data; a distributor for dividing systematic bits and parity bits constituting the rate- matched data into sub-block A and sub-block B, and outputting the divided sub- blocks A and B; and a modulator for symbol mapping the sub-blocks A and B according to a predetermined modulation scheme, and transmitting the symbol- mapped sub-blocks A and B, wherein the distributor determines a ratio of the number of the systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub-block B according to the modulation scheme.

In accordance with yet another aspect of the present invention, there is provided a method of receiving data in a mobile communication system, the method including the steps of redistributing sub-blocks A and B constituting received data into a systematic bit block and a parity bit block; converting the systematic and parity bit blocks into a plurality of systematic bit sub-blocks and a plurality of parity bit sub-blocks respectively; and channel-decoding the systematic and parity bit sub-blocks one by one, wherein a ratio of the number of systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub-block B is determined according to a modulation scheme used in a transmitter.

In accordance with still yet another aspect of the present invention, there is provided an apparatus for receiving data in a mobile communication system, the apparatus including a redistributor for redistributing sub-blocks A and B constituting received data into a systematic bit block and a parity bit block; a serial-to-parallel converter for converting the systematic and parity bit blocks into a plurality of systematic bit sub-blocks and a plurality of parity bit sub-blocks respectively; and a decoder for channel-decoding the systematic and parity bit sub-blocks one by one, wherein a ratio of the number of systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub-block B is determined according to a modulation scheme used in a transmitter.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a structure of a transmitter in a typical mobile communication system employing parallel interleaving;

FIG. 2 is a view illustrating an example of a bit reliability pattern for an M-ary modulation symbol;

FIG. 3 a is a view illustrating an example of dividing a data sequence into sub-block sequences in a mobile communication system in accordance with an exemplary embodiment of the present invention;

FIG. 3b is a block diagram illustrating an interleaver for parallel- interleaving divided sub-blocks in a mobile communication system in accordance with an exemplary embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method of dividing a data sequence into sub-block sequences in a mobile communication system in accordance with an exemplary embodiment of the present invention; FIG. 5 is a block diagram illustrating a structure of a transmitter employing parallel interleaving for several RLC data blocks;

FIG. 6 is a view illustrating results of N RLC data blocks that pass through respective distributors and then are processed by a parallel-to-serial converter;

FIG. 7a is a view illustrating a method of dividing an RLC data block into sub-blocks A and B in consideration of a bit space occupied by PAN data in the sub-block A when the PAN data is considered data with higher priority;

FIG. 7b is a view illustrating a method of dividing an RLC data block into sub-blocks A and B in consideration of a bit space occupied by PAN data in the sub-block B when the PAN data is considered data with lower priority;

FIG. 8a is a view illustrating an example of attaching PAN data as a postamble or preamble of sub-block A or B;

FIG. 8b is a view illustrating an example of attaching PAN data as a postamble or preamble of sub-block A or B for N RLC data blocks;

FIG. 8c is a view illustrating an example of attaching PAN data to sub- block AOr B';

FIG. 9 is a block diagram illustrating another structure of a transmitter employing parallel interleaving for several RLC data blocks;

FIG. 10 is a block diagram illustrating a structure of a receiver corresponding to the transmitter in FIG. 5; and

FIG. 11 is a block diagram illustrating a structure of a receiver corresponding to the transmitter in FIG. 9.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENT

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the similar components are designated by similar reference numerals although they are illustrated in different drawings. Also, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may obscure the subject matter of the present invention. Further, it should be noted that only parts essential for understanding the operations according to the present invention will be described and a description of parts other than the essential parts will be omitted in order not to obscure the gist of the present invention.

The present invention provides a method of dividing S and P bits into sub-blocks in the distributor 130 of the transmitter 100 illustrated in FIG. 1 so as to improve system performance.

As illustrated in FIG. 1, a data sequence channel-encoded in the channel encoder 110 are divided into systematic bits (S bits) and parity bits (P bits). In the present invention, the distributor 130 reflects the bit reliability of a high-order modulation scheme and a high-order modulation symbol in dividing the S and P bits into sub-blocks.

FIG. 2 illustrates an example of a reliability pattern for an M-ary modulation symbol.

As illustrated in FIG. 2, a high-order M-ary modulation symbol (M > 7) may be divided into higher reliable bit positions (hereinafter referred to as "H"), medium reliable bit positions (hereinafter referred to as "M"), and lower reliable bit positions (hereinafter referred to as "L") according to their bit error likelihoods. However, it can be easily noted that there are other types of bit reliability patterns according to a Gray symbol pattern and an I/Q (In- phase/Quadrature) bit configuration at symbol transmission, which are used in the constellation of a modulation scheme.

Referring to FIG. 2, a reliability pattern for a modulation symbol is as follows:

In applying SMP technology to symbol mapping, a bit with higher priority (e.g. S bit) is allocated to H, and a bit with lower priority (e.g. P bits) is allocated to L. In this way, a symbol with bits allocated thereto is transmitted. However, a high-order modulation symbol of 32QAM/64QAM/128QAM includes a medium reliable bit position M, the reliability of which is intermediate between those of H and L. In other words, the bit error likelihood of a bit corresponding to M lies at about an average of those for H and L. Thus, symbol mapping may be performed by assigning M as H or L according to circumstances. For example, when S bits more than P bits exist in a data block to be transmitted, symbol mapping may be performed by assigning M as H. Contrarily, when P bits more than S bits exist in a data block, symbol mapping may be performed by assigning M as L.

In the present invention, a data block including S and P bits, which has been encoded and subjected to rate matching, can be divided into two sub-blocks in the distributor 130 by considering the number of bits occupied by each of H, M and L included in each symbol. Supposing that the two sub-blocks are sub- block A and sub-block B, division ratios of the number of sub-block bits (A:B) for the respective high-order modulation schemes can be summarized as presented below in Table 1.

Table 1

FIG. 3 a illustrates a procedure of dividing a channel-encoded data sequence into two sub-block sequences A and B according to an exemplary embodiment of the present invention.

For example, it is assumed that the channel encoder 110 uses a turbo code with a code rate r of 1/3, and a data transfer rate d is 0.5. A data sequence encoded by the channel encoder 110 consists of S and P bits. A data block whose number of bits corresponds to the data transfer rate is generated from the encoded data sequence through rate matching in which a repetition or puncturing operation for encoded bits is performed, and the generated data block is input into a distributor 330.

The distributor 330 divides the input data block into two sub-blocks A and B. The ratio of the number of the S and P bits included in the sub-block A to the number of the S and P bits included in the sub-block B is determined according to a reliability pattern for a high-order modulation symbol, as exemplified in Table 1. As illustrated in FIG. 3a, the distributor 330 divides the data block in such a manner as to include the S bits in the sub-block A and to include the P bits in the sub-block B. However, depending on the ratio between the numbers of bits included in the sub-blocks A and B, a part of bits included in the sub-block A may include P bits, and a part of bits included in the sub-block B may include S bits. The ratio between the numbers of bits included in the sub- blocks A and B is selected according to modulation scheme used in data transmission. That is, a ratio of 2:1 may be selected when 8PSK is used in data transmission, a ratio of 1:1 may be selected when 16QAM is used in data transmission, a ratio of 3:2 or 2:3 may be selected when 32QAM is used in data transmission, a ratio of 2:1, 1:2, or 1:1 may be selected when 64QAM is used in data transmission, and a ratio of 4:3, 2:5, or 3:4 may be selected when 128QAM is used in data transmission.

FIG. 3b illustrates a structure of an interleaver for parallel-interleaving divided sub-blocks according to an exemplary embodiment of the present invention.

The sub-blocks A and B divided by the distributor 330 are input into and interleaved by first and second interleavers 340, 350 respectively. Sub-blocks A' and B' passing through the parallel interleaver are symbol-mapped using the SMP technology, and are transmitted through an M-ary modulator. Here, bits included in the sub-block A' are inserted into higher reliable bit positions because all or most of them are S bits, and bits included in the sub-block B' are inserted into lower reliable bit positions because all or most of them are P bits.

The interleaver may be omitted according to mobile communication systems. For example, in the case of a transmission system that requires no additional external interleaver because independent interleaving is already performed in a rate matching process, the sub-blocks A and B can be symbol- mapped using the SMP technology.

Also, from a viewpoint of system performance improvement, two interleavers used in the parallel interleaver must be designed in such a manner as to efficiently disperse transmitted data bits. That is, bursts, bits in the same burst, and bits in the same symbol must be efficiently dispersed.

FIG. 4 illustrates a method of transmitting data in a mobile communication system according to an exemplary embodiment of the present invention.

First of all, in step 401, the channel encoder 110 channel-encodes data to be transmitted, and then outputs encoded S and P bits to the rate matching unit 120.

In step 403, the rate matching unit 120, 320 performs rate matching adaptive to a data transfer rate through repetition or puncturing of the S and P bits to thereby generate a data block whose number of bits corresponds to the data transfer rate, and then outputs the generated data block to the distributor 130, 330.

In step 405, the distributor 130, 330 divides the rate-matched S and P bits into sub-blocks, and then outputs the divided sub-blocks to the respective interleavers 140/340, 150/350. Here, the ratio of the number of bits included in the sub-block A to the number of bits included in the sub-block B is selected according to which modulation scheme is used.

In step 407, the first interleaver 140/340 and the second interleaver 150/350 interleave the data divided into the sub-blocks respectively, and output the interleaved data to the M-ary modulator 170.

In step 409, the M-ary modulator 170 symbol-maps the data according to a predetermined modulation scheme, and then transmits the symbol-mapped data.

Although it is assumed in the above embodiment that only one RLC (Radio Link Control) data block is transmitted, several RLC data blocks are independently channel-encoded, interleaving is performed for all the data, the interleaved data is divided in a plurality of bursts, and then the bursts are transmitted in an actual mobile communication system. For example, in MSC (Modulation Coding Scheme)-7, MSC-8, and MSC-9 of EGPRS (Enhanced General Packet Radio Service), two RLC data blocks constitute a payload transmitted per radio block. Also, in evolved EGPRS, the payload of one radio block may be constituted by a maximum of four data blocks. The structure of the transmitter in FIG. 1 may be generalized by the structure in FIG. 5, in which N RLC data blocks constitute a payload.

That is, N RLC data blocks are divided into systematic bit sub-blocks S₁, S₂, '", S_N and parity bit sub-blocks Pi, P₂, ^•", P_# via channel encoders 510, 511 and rate matching units 520, 521. The systematic and parity bit sub-blocks are distributed into sub-blocks Ai, A₂, ^{• • •}, A_# and sub-blocks B₁, B₂, ' ", B_JV by distributors 530, 531 in a manner as described above. A parallel-to-serial converter 540 incorporate the respective sub-bocks into two data blocks A = [Ai, A₂, ^{• • •}, A_N] and B = [Bi, B₂, ^{■ • •}, B_N], and then inputs the data blocks A and B into first and second interleavers 550, 551 respectively. The first and second interleavers 550, 551 output interleaved data A' and B', which in turn pass through a parallel-to-serial converter 560 and then are forwarded to am M-ary modulator 570 via a series of processes, such as burst mapping.

According to the GERAN (GSM EDGE Radio Access Network) standard release 7, EGPRS supports an FANR (Fast ACK/NACK Reporting) function for reduced latency (hereinafter referred to as "RL"). This EGPRS is called RL- EGPRS. A terminal supporting such an FANR function identifies PAN (Piggybacked ACK/NACK) report data by using a PANI (PAN Indicator) field in the header part. The PAN report data experiences independent channel encoding, and then is transmitted together with payload data.

Thus, in the case of using PAN report data, when channel-encoded payload data is punctured in the rate matching unit so as to adapt it to a data transfer rate, the rate matching unit must puncture the payload data in consideration of a space occupied by the PAN report data. That is, the number of bits output from the rate matching unit is given by the following equation:

no. of bits output from rate matching unit =

(no. of transmitted data bits — no. of PAN bits) (1)

Also, the distributor must consider the PAN report data when dividing an output from the rate matching unit, that is, S bit data and P bit data, into sub- blocks A and B. In other words, the PAN report data may be included in the sub-block A or sub-block B, but it is preferred that the PAN report data is included in the sub-block A because the PAN report data is a control signal with higher priority than that of user data.

FIGS. 7a and 7b each illustrate a method of dividing an RLC data block into sub-blocks A and B in the distributor by taking account of PAN report data when one RLC data block is transmitted as user data (payload). The PAN report data is considered data with relatively higher priority in FIG. 7a, and is considered data with relatively lower priority in FIG. 7b.

Even when two or more data blocks constitute user data, the sub-block division method illustrated in FIG. 7a or 7b is also employed in each distributor 730, 731, provided that each rate matching unit 720, 721 and each distributor 730, 731 consider only PAN report data whose number of bits corresponds to the overall number of PAN bits divided by the number of an RLC data block. That is, for N RLC data blocks, the number of bits of PAN data to be considered in an rth RLC data block (7 = 1, 2, "-, N) satisfies the following equation:

no. of bits of Hh PAN report data =

{overall no. of bits of PAN report data/N) (2)

PAN report data is channel-encoded separately from user data. PAN report data is attached to user data, is subjected to symbol mapping, and then is transmitted. A point of time when PAN report data is attached to user data may be before or after (parallel) interleaving is performed in FIG. 3b or FIG. 5.

FIG. 8a illustrates a method of attaching PAN report data before performing interleaving. In FIG. 8a, one RLC data block constitutes a payload, and PAN report data is attached in the form of the postamble or preamble of sub- block A and is interleaved along with the sub-block A. Also, in some cases, the PAN report data may be attached in the form of the postamble or preamble of sub- block B and be interleaved along with the sub-block B.

FIG. 8b illustrates an example of attaching PAN report data when NRLC data blocks constitute a payload, and FIG. 8c illustrates an example of performing interleaving for user data A and B and then attaching interleaved PAN report data. In FIG. 8c, channel-encoded PAN report data is also subjected to independent interleaving, and then the interleaved PAN report data is attached to interleaved sub-block A' or B' in the form of a postamble or preamble.

FIG. 9 illustrates another structure of a transmitter employing parallel interleaving for several RLC data blocks.

In FIG. 9, a distributor is located in the rear of an interleaver, dissimilar to the transmitter in FIG 5. That is, systematic bit sub-blocks Si, S₂, '", S_N and parity bit sub-blocks P₁, P₂, "", Pj_V that have passed through channel encoders 910, 911 and rate matching units 920, 921 are subjected to parallel-to-serial conversion 930, and interleaving for each of the S bit sub-blocks and the P bit sub-blocks is performed in each of interleavers 940, 941. The distributor 950 divides two interleaved data blocks A' and B' into data blocks A and B according to the inventive distribution scheme. Thus, when N RLC data blocks are transmitted, the transmitter in FIG. 5 requires N distributors, but the transmitter in FIG. 9 requires only one distributor.

Also, since the two interleavers 940, 941 performs wholly independent interleaving for the S and P bits, and then the distributor 950 distributes the interleaved S' and P' into two data blocks A and B, it is advantageous to performance improvement in decoding of a turbo code.

FIG. 10 illustrates a structure of a receiver corresponding to the transmitter in FIG. 5.

Referring to FIG. 10, each received data burst is subjected to signal processing, such as equalization and demodulation, in a signal processor 1010, and then is divided into data blocks A' and B' in a parallel-to-serial converter 1020. The two data blocks A' and B' output from the parallel-to-serial converter 1020 are deinterleaved in first and second deinterleavers 1030, 1031 respectively, and are output into data blocks A and B. A redistributor 1040 redistributes the interleaved data blocks A and B into a systematic bit block S and a parity bit block P, and outputs the redistributed bit blocks S and P. A serial-to-parallel converter 1050 converts the bit blocks S and P into systematic bit sub-blocks Si, S₂, - ", S_JV and parity bit sub-blocks Pi, P₂, ^{■ ■ •} , V_N, and stores the converted S and P sub-blocks in N buffers 1060, 1061 respectively. The data stored in the buffers 1060, 1061 are decoded into N RLC data blocks through N channel decoders 1070, 1071. Even when PAN report data is used, it can be processed in the same meaner as described above.

FIG. 11 illustrates a structure of a receiver corresponding to the transmitter in FIG. 9.

The receiver in FIG. 11 is the same as the receiver in FIG. 10, except that a redistributors 1130 is transposed with deinterleavers 1140, 1141.

That is, each received data burst is subjected to signal processing, such as equalization and demodulation, in a signal processor 1110, and then is divided into data blocks A' and B' in a parallel-to-serial converter 1120. The two data blocks A' and B' output from the parallel-to-serial converter 1120 are redistributed into a systematic bit block S' and a parity bit block P' through the redistributors 1130. The bit blocks S' and P' output from the redistributors 1130 are deinterleaved in first and second deinterleavers 1140, 1141 respectively. A serial-to-parallel converter 1150 converts the deinterleaved bit blocks S and P into systematic bit sub-blocks Si, S₂, -", S^ and parity bit sub-blocks Pi, P₂, " ', ¹P_N, and stores the converted S and P sub-blocks in N buffers 1160, 1161 respectively. The data stored in the buffers 1160, 1161 are decoded into N RLC data blocks through N channel decoders 1170, 1171. Even when PAN report data is used, it can be processed in the same meaner as described above.

As describe above, the present invention solves a problem of unbalanced data (particularly when a data transfer rate d is large, that is, d approximates to 1.0) supplied to a parallel interleaver by efficiently dividing a channel-encoded data sequence into sub-blocks, performing symbol mapping, such as SMP, and then transmitting the symbol-mapped data in a mobile communication system using a parallel interleaver structure for improving system performance.

While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method of transmitting data in a mobile communication system, the method comprising the steps of: channel-encoding the data to be transmitted; subjecting the encoded data to rate-matching adaptive to a predetermined data transfer rate, and outputting the rate-matched data; and dividing systematic bits and parity bits constituting the rate-matched data into sub-block A and sub-block B, symbol mapping the sub-blocks A and B according to a predetermined modulation scheme, and then transmitting the symbol-mapped sub-blocks A and B, wherein in the step of dividing the systematic and parity bits into the sub- blocks A and B, a ratio of the number of the systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub-block B is determined according to the modulation scheme.

2 The method as claimed in claim 1, wherein in the step of dividing the systematic and parity bits into the sub-blocks A and B, a ratio of the number of bits constituting the sub-block A to the number of bits constituting the sub- block B is determined as 2:1 when the modulation scheme is 8PSK (Phase Shift Keying), as 1:1 when the modulation scheme is 16QAM (Quadrature Amplitude Modulation), as 3:2 or 2:3 when the modulation scheme is 32QAM, as 2:1, 1:2, or 1:1 when the modulation scheme is 64QAM, and as 4:3, 2:5, or 3: 4 when the modulation scheme is 128QAM.

3. The method as claimed in claim 1, wherein the sub-block A includes the systematic bits more than the parity bits, and the sub-block B includes the parity bits more than the systematic bits.

4. The method as claimed in claim 1, further comprising the step of interleaving the divided sub-blocks A and B respectively.

5. The method as claimed in claim 1, further comprising, before the step of dividing the systematic and parity bits into the sub-blocks A and B, the step of interleaving the rate-matched systematic and parity bits respectively.

6. The method as claimed in claim I₅ further comprising the step of channel encoding PAN (Piggy-backed ACK/NACK) report data, and inserting the channel-encoded PAN report data into the sub-block A or B, wherein the step of dividing the systematic and parity bits into the sub-blocks A and B comprises the step of dividing the systematic and parity bits into the sub-blocks A and B in consideration of the number of bits of the PAN report data.

7. The method as claimed in claim I₅ a size of the sub-block A is different form a size of the sub-block B.

8. An apparatus for transmitting data in a mobile communication system, the apparatus comprising: a channel encoder for channel-encoding the data to be transmitted; a rate matching unit for subjecting the encoded data to rate-matching adaptive to a predetermined data transfer rate, and outputting the rate-matched data; a distributor for dividing systematic bits and parity bits constituting the rate-matched data into sub-block A and sub-block B, and outputting the divided sub-blocks A and B; and a modulator for symbol mapping the sub-blocks A and B according to a predetermined modulation scheme, and transmitting the symbol-mapped sub- blocks A and B, wherein the distributor determines a ratio of the number of the systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub-block B according to the modulation scheme.

9. The apparatus as claimed in claim 8, wherein the distributor determines a ratio of the number of bits constituting the sub-block A to the number of bits constituting the sub-block B as 2:1 when the modulation scheme is 8PSK (Phase Shift Keying), as 1:1 when the modulation scheme is 16QAM (Quadrature Amplitude Modulation), as 3:2 or 2:3 when the modulation scheme is 32QAM₅ as 2:1, 1:2, or 1:1 when the modulation scheme is 64QAM, and as 4:3, 2:5, or 3: 4 when the modulation scheme is 128QAM.

10. The apparatus as claimed in claim 8, wherein the sub-block A includes the systematic bits more than the parity bits, and the sub-block B includes the parity bits more than the systematic bits.

11. The apparatus as claimed in claim 8, further comprising first and second interleavers for interleaving the divided sub-blocks A and B respectively.

12. The apparatus as claimed in claim 8, further comprising first and second interleavers for interleaving the rate-matched systematic and parity bits and outputting the interleaved systematic and parity bits to the distributor respectively.

13. The apparatus as claimed in claim 8₅ wherein the channel encoder channel encodes PAN (Piggy-backed ACK/NACK) report data separately from the data to be transmitted, and the distributor inserts the channel-encoded PAN report data into the sub-block A or B and divides the systematic and parity bits into the sub-blocks A and B in consideration of the number of bits of the PAN report data.

14. The apparatus as claimed in claim 8, a size of the sub-block A is different form a size of the sub-block B.

15. A method of receiving data in a mobile communication system, the method comprising the steps of: redistributing sub-blocks A and B constituting received data into a systematic bit block and a parity bit block; converting the systematic and parity bit blocks into a plurality of systematic bit sub-blocks and a plurality of parity bit sub-blocks respectively; and channel-decoding the systematic and parity bit sub-blocks one by one, wherein a ratio of the number of systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub- block B is determined according to a modulation scheme used in a transmitter.

16. The method as claimed in claim 15, wherein a ratio of the number of bits constituting the^' sub-block A to the number of bits constituting the sub-block B is determined as 2:1 when the modulation scheme is 8PSK (Phase Shift Keying), as 1 :1 when the modulation scheme is 16QAM (Quadrature Amplitude Modulation), as 3:2 or 2:3 when the modulation scheme is 32QAM, as 2:1, 1:2, or 1:1 when the modulation scheme is 64QAM, and as 4:3, 2:5, or 3: 4 when the modulation scheme is 128QAM.

17. The method as claimed in claim 15, wherein the sub-block A includes the systematic bits more than the parity bits, and the sub-block B includes the parity bits more than the systematic bits.

18. The method as claimed in claim 15, further comprising the step of deinterleaving the redistributed systematic and parity bit blocks respectively.

19. The method as claimed in claim 15, further comprising, before the step of redistributing the sub-blocks A and B into the systematic and parity bit blocks, the step of deinterleaving the sub-blocks A and B respectively.

20. An apparatus for receiving data in a mobile communication system, the apparatus comprising: a redistributor for redistributing sub-blocks A and B constituting received data into a systematic bit block and a parity bit block; a serial-to-parallel converter for converting the systematic and parity bit blocks into a plurality of systematic bit sub-blocks and a plurality of parity bit sub-blocks respectively; and a decoder for channel-decoding the systematic and parity bit sub-blocks one by one, wherein a ratio of the number of systematic and parity bits included in the sub-block A to the number of the systematic and parity bits included in the sub- block B is determined according to a modulation scheme used in a transmitter.

21. The apparatus as claimed in claim 20, wherein a ratio of the number of bits constituting the sub-block A to the number of bits constituting the sub-block B is determined as 2:1 when the modulation scheme is 8PSK (Phase Shift Keying), as 1:1 when the modulation scheme is 16QAM (Quadrature Amplitude Modulation), as 3:2 or 2:3 when the modulation scheme is 32QAM, as 2:1, 1 :2, or 1:1 when the modulation scheme is 64QAM, and as 4:3, 2:5, or 3: 4 when the modulation scheme is 128QAM.

22. The apparatus as claimed in claim 20, wherein the sub-block A includes the systematic bits more than the parity bits, and the sub-block B includes the parity bits more than the systematic bits.

23. The apparatus as claimed in claim 20, further comprising first and second deinterleavers for deinterleaving the redistributed systematic and parity bit blocks and outputting the deinterleaved systematic and parity bits to the serial-to-parallel converter respectively.

24. The apparatus as claimed in claim 20, further comprising first and second deinterleavers for deinterleaving the sub-blocks A and B and outputting the deinterleaved systematic and parity bits to the redistributor respectively.