WO2008146211A1 - A tillable sensor device - Google Patents

A tillable sensor device Download PDF

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Publication number
WO2008146211A1
WO2008146211A1 PCT/IB2008/052017 IB2008052017W WO2008146211A1 WO 2008146211 A1 WO2008146211 A1 WO 2008146211A1 IB 2008052017 W IB2008052017 W IB 2008052017W WO 2008146211 A1 WO2008146211 A1 WO 2008146211A1
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WO
WIPO (PCT)
Prior art keywords
substrate
integration
sensor
sensor device
chip
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PCT/IB2008/052017
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French (fr)
Inventor
Ronald Dekker
Jean-Marc Yannou
Nicolaas J. A. Van Veen
Wibo D. Van Noort
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Koninklijke Philips Electronics N.V.
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Publication of WO2008146211A1 publication Critical patent/WO2008146211A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
    • H01L25/042—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

  • the present invention relates to a sensor device with a sensor chip on an integration substrate. It also relates to a detector device that comprises a plurality of sensor devices. The invention also relates to a method for fabricating a sensor device, and to a method for fabricating a detector device.
  • US 2005/0098732 Al describes an x-ray detector device that comprises an array of sensor chips, which are arranged on a base plate in a matrix arrangement.
  • the individual sensor chips form tiles of a large-area detector device.
  • the individual tiles are positioned and precisely aligned on the base plate and subsequently glued to the base plate in this arrangement.
  • Connection lines between the neighboring tiles are fabricated by printing after the gluing and alignment.
  • the connection lines form an interconnection network on the front-side of the sensor array.
  • the interconnection network is connectable to external control circuitry by means of connection pads, which are arranged on separate tiles at the edge of the sensor device on separate connection tiles.
  • the detector device of US 2005/0098732 Al has the disadvantage that a complicated and sensitive alignment process of the tiles on the base plate is required. A misalignment of the tiles with respect to each other could lead to a disturbed connectivity between neighboring tiles. This in turn could affect the operation of the detector device as a whole because the connection lines between the individual tiles are integrated into a large interconnect network on the front-side of the detector device. This interconnect network connects all individual sensors on each sensor chip to respective connect pads at the edge of the sensor device. An interconnect element that is malfunctioning due to misalignment thus would affect all sensors of a line or column on different sensor devices of the sensor matrix formed by the detector device.
  • a further disadvantage of the detector device of US 2005/0098732 Al is a large area that is required for the interconnects between the neighboring sensor chips.
  • the required chip area is further increased by additional tiles on the edge of the detector device, which contain contact pads for connection with external circuitry.
  • a sensor device comprising an integration substrate including a plurality of through- substrate vias, which have an electrically conductive via core; a sensor chip, which has a first sensor-chip side that comprises at least one sensor and which is attached and electrically connected to the integration substrate on its first integration-substrate side; and a circuit chip, which is attached and electrically connected to the integration substrate on its second integration-substrate side and which comprises an integrated circuit, which is electrically connected with the sensors by means of at least one of the through- substrate vias.
  • the sensor chip and the circuit chip are arranged on opposite signs of the integration substrate. Providing the sensor chip and the circuit chip in the same sensor device without having to increase the lateral extension of the sensor device is very useful for high integration and small overall size of the detector device.
  • the sensor device of the present invention forms a system- in-package, in which the effective sensor area on the sensor chip can be increased in comparison with that of the sensor chips of US 2005/0098732 Al, given the same area of the sensor device.
  • the sensor device of the present invention uses an integration substrate with a plurality of through-substrate vias for electrically connecting the sensors with a circuit chip.
  • the sensor device of the present invention allows for providing an application-specific integrated circuit, such as for instance a signal processing IC or a signal preprocessing IC in the sensor device.
  • an ASIC can be provided on every tile.
  • the sensor device has the advantage of integrating the sensor chip and the circuit chip in one device, but still allowing a fabrication of the two chips in different technologies.
  • the sensor chip can often be fabricated in a relatively simple and cheap processing technology. It can therefore be large without becoming prohibitively expensive.
  • the circuit chip on the other hand, is usually fabricated using an expensive IC technology, and usually requires much less chip area than the sensor chip.
  • the combination of both technologies that is enabled by the sensor device after present invention provides an inexpensive way to produce a highly integrated sensor device with sensors and integrated circuit in the same sensor device.
  • a further advantage in this context is that the sensor chip and the circuit chip in many applications require different types of substrates.
  • photo detectors used high-resistivity float-zone (FZ) substrates
  • CMOS ASICs are processed in Czochralski (CZ) substrates with 10 to 20 ⁇ xcm resistivity.
  • a further advantage of the sensor device of the present invention is that it allows obtaining the sensor chip and the integrated circuit from different vendors.
  • preferred embodiments of the sensor device of the first aspect of the invention will be described. Unless explained otherwise explicitly, the embodiments can be combined with each other.
  • the integration substrate preferably has a thickness less than 200 microns, suitably less than 100 microns, advantageously less than 50 microns and in some embodiments even in the range of 10-30 microns. In one embodiment, the integration substrate has a thickness of less that 100 micrometer. This implies that there is no lateral region, where the integration substrate as such has a thickness of more than 100 micrometer. For the purpose of definition of the thickness of the integration substrate, only the substrate material or wafer material of the integration substrate is considered, and not additional layers or structures deposited on this material on either of the integration- substrate sides.
  • a through- substrate via typically connects at least one first electrically conductive element on a first integration-substrate side with at least one second electrically conductive element on a second integration-substrate side.
  • the conductive elements are formed of layers deposited on the integration substrate, such as metallization layers, there thickness shall not count under the present definition.
  • the thickness include an extension of solder balls or bumps that can be present on one of the integration- substrate sides, for the purpose of the present definition.
  • the present embodiment has an integration substrate, in which the through-substrate vias are particularly short. As will be shown in the context of the description of the method aspects of the present invention, such vias can be fabricated without making holes in the integration substrate. In fact, technologies for making trenches that are known as such can be used.
  • the thickness of the integration substrate is further reduced to a thickness between 15 and 40 micrometer.
  • the thickness of the integration substrate is reduced to the minimum amount required form containing passive electric components that maybe required according the specific application.
  • passive components may for instance be trench compositors.
  • One embodiment combines a thickness of the integration substrate of less that 100 micrometer with an aspect ratio of the through- substrate vias that is larger than 5.
  • the sensor device of this embodiment therefore has through-substrate vias in the integration substrate, which are particularly short and, due to their high aspect ratio, at the same time have a particularly small lateral extension.
  • this combination of features allows combining a very high integration density on the integration substrate with very low parasitic lead inductances of the vias. Both requirements are important for advanced high- frequency applications, like sensor devices for radio-frequency (RF) applications. Both requirements can therefore now be met at the same time.
  • RF radio-frequency
  • the aspect ratio of a through-substrate via is the quotient of a depth extension of the through-substrate via between its ends on the first and second integration-substrate sides, and of a lateral extension of the trench that is formed to fabricate the through- substrate in the integration substrate.
  • the lateral trench extension can be derived from the finished integration substrate of the system- in-package, even after filling of the trench during further processing. Suitable analytic techniques are for instance known microscopic methods, like for instance optical microscopy or electron microscopy on a cross section of the integration substrate.
  • the lateral trench extension of a single trench may vary when following its extension in the depth direction. That means, the trench may be wider in some depth regions and smaller in other depth regions.
  • the lateral trench extension shall be considered to be the mean value of the lateral trench extension over along the extension in depth direction.
  • the inductance of the through- substrate vias scales in a superlinear manner with the length of the through-substrate vias, i.e., their extension in the depth direction, while its dependence on the aspect ratio is only sublinear. Therefore, even though a high integration density is achieved with relatively high aspect ratios of the through-substrate vias, which tends to increase the parasitic lead inductance for a given thickness of the integration substrate, the parasitic lead inductances of the through- substrate vias are at particularly low values.
  • the low thickness of the integration substrate corresponds with the length of the through-substrate vias.
  • a method aspect correlated with the present embodiment overcomes this problem and allows achieving the aforementioned advantages by providing a support, which is attached to the integration substrate on its first integration-substrate side and which is suitable for mechanically supporting the integration substrate.
  • the sensor device of the embodiment can thus be produced on wafer scale with good yield and lifetime according to industry standards.
  • the sensor chip comprises an array of sensors for electromagnetic radiation.
  • the sensors are for instance arranged for exposure to electromagnetic radiation to be detected on the first sensor-chip side, and the sensors are electrically connected to the integration substrate via an opposite second sensor-chip side.
  • This embodiment allows further reducing the area required for interconnections between neighbouring sensor devices in comparison with US 2005/0098732 Al.
  • interconnects to neighbouring tiles in a detector device that contains a plurality of sensor devices of this embodiment can be routed through the integration substrate.
  • the effective sensor area on the first senor-chip side is particularly large in this embodiment.
  • This embodiment can for instance contain photodiodes, which are illuminated on their backside, which forms the first sensor-chip side. This maximizes the active sensor area. For instance, in an application, where the sensor area is used to detect photons emitted from a scintillator layer that converts X-rays to visible or infrared light. Such X-ray detectors are useful for an application in computer-tomography (CT) scanners.
  • CT computer-tomography
  • a cavity in the integration substrate that is open to the second integration-substrate side.
  • the cavity can for instance be arranged underneath a coil (inductance) on the first integration-substrate side. Cavities are also useful in applications, where the sensor device is exposed to radiation that may damage the integrated circuitry on the circuit chip.
  • a cavity that is open to the second integration-substrate side can be arranged in the integration substrate.
  • the cavity preferably extends laterally over at least a fraction of the lateral extension of the circuit chip.
  • a first radiation shield is arranged inside the cavity, the first radiation shield beings suitable for absorbing radiation of a predetermined kind, such as, for instance, X-rays. For absorbing X-rays, tungsten is an example of a suitable material for the first radiation shield.
  • the through-substrate vias or other filled trench structures such as trench capacitors in one embodiment have a ring-type shape, when seen in a top view from the first integration- substrate side.
  • a ring-type shape is used here as a generic term and includes other closed shapes beside the actual ring shape, for instance shapes having the outline of a rectangle, a square, an ellipse or an oval.
  • the via filling forms the closed shape.
  • a ring-type shape can be used to electrically or optically insulate functional components arranged inside the ring on the integration substrate.
  • optical insulation includes insulation from electromagnetic radiation that covers high- energy regions of the spectrum, like X-rays.
  • the through-substrate vias have a coaxial structure, i.e., a via for a signal line is surrounded by vias for ground.
  • the filled trench structures can be fabricated at the same time as the through- substrate vias. They therefore preferably have the same lateral extension as the through- substrate vias.
  • a detector device comprising a plurality of sensor devices according to the first aspect of the invention or one of its embodiments.
  • the sensor devices are attached and electrically connected to a base substrate.
  • the detector device of the second aspect of the invention has an increased integration density. It provides integrated circuits in the individual sensor devices without having to sacrifice sensor area.
  • the detector device can be fabricated at relatively low cost due to its modular structure. This has also be explained in the context of the explanation of advantages of the sensor device of the first aspect of the invention.
  • the base substrate is in one embodiment a printed circuit board. It may provide for electrical connectivity of the detector device to external devices. It also may provide the interconnections between different sensor devices comprised by the detector devices.
  • the detector device comprises an X-ray-converter layer.
  • the X-ray-converter layer is preferably arranged on top of the sensor chips of the sensor devices. It is arranged and configured to convert electromagnetic radiation from the X-ray spectral range into radiation of a lower-energetic spectral range.
  • a scintillator layer is an example of a suitable X-ray-converter layer.
  • Further embodiments of detector device of the present invention correspond to those of the sensor device of the first aspect of the invention.
  • a example of a useful detector device of the second aspect of the invention is an X-ray detector for scanners in computer tomography.
  • other detector devices can form useful embodiments of the invention as well.
  • the sensor chip that forms a part of the sensor device can comprise antennas as sensors form radio frequency (RF) radiation.
  • RF radio frequency
  • a method for a fabricating a sensor device comprises the steps: providing an integration substrate; - fabricating trench structures in the integration substrate on the first integration- substrate side; fabricating an electrically conductive via core in at least a first plurality of the trench structures, which forms a subset of the trench structures; attaching and electrically connecting a sensor substrate to the integration substrate on its first integration substrate side, the sensor substrate comprising one sensor or a plurality of sensors; fabricating at least one second conductive element on the second substrate side, which connects with the through-substrate via, and electrically connecting and attaching a circuit chip to the integration substrate on its second integration-substrate side.
  • trench structure refers to any suitable shape of recess that is formed in the integration substrate on its first integration-substrate side.
  • a suitable trench structure extends through the integration substrate after the processing.
  • the term trench structure is in other contexts also used to denote the structure after filling, as will be clear from the respective context of usage of the term.
  • the trench structures have a larger extension in a direction perpendicular to the first integration-substrate side, which is also called depth direction herein, than in directions parallel to the first integration-substrate side, which are also referred to as lateral directions herein.
  • Some embodiments have trench structures with a shape resembling that of a column.
  • the method comprises thinning the integration substrate from its second integration-substrate side to a thickness below 100 micrometer, such that only a bottom face of the via course of the first plurality of trench structures is exposed.
  • the sensor substrate is preferably selected suitable for mechanically supporting the integration substrate during thinning to the reduced integration-substrate thickness of less than 100 micrometer. Experience shows that a thinning of the integration substrate down to less than
  • the present embodiment overcomes this problem by attaching a support in the form of the sensor substrate to the integration substrate on its first integration- substrate side before the thinning step.
  • the support is selected so that it provides the mechanical stability required to avoid a breakage during the known processing conditions of thinning, later processing, and handling of the integration substrate.
  • trench structures for through-substrate vias and other trench structures, such as trench capacitors are fabricated in a single step, which typically is an etching step. This is a particularly simple processing for such different structures. However, it should be noted there is no requirement to fabricate trench structures for different purposes.
  • fabricating the sensor device as a system- in-package with through-substrate vias in the integration substrate can be performed without having to fabricate holes crossing through the complete integration substrate.
  • This as such is known, for instance from US 2002/0084513.
  • the processing disclosed in US 2002/0084513 has several disadvantages.
  • the protruding via provided by this technique is used as a bump and as such is mechanically sensitive, unless fabricated with considerable thickness to provide sufficient mechanical strength.
  • the thinning of the wafer during the processing disclosed in US 2002/0084513 Al increases the risk of wafer-breakage during handling, in particular during further processing of the wafer and the assembly made with it.
  • parasitic lead inductances due to the through-substrate via are rather high in the structure of US 2002/0084513 Al.
  • fabricating the first plurality of trench structures is performed employing reactive ion etching (RIE).
  • RIE reactive ion etching
  • the disadvantage of these prior-art processing techniques is that the use of RIE makes the fabrication of through- substrate via holes with larger depth and lateral extensions a relatively slow and expensive process.
  • the use of RIE in the context of the processing of the method of the third aspect of the invention enables reducing the etching time as much as possible. For the depth and the lateral extensions of the trench structures are significantly reduced due to the decreased thickness of the integration substrate in the finished sensor device, and due to the large aspect ratio of the through-substrate vias.
  • RIE etching
  • first and third plurality of trench structures are etched concurrently, i.e., in a common etching step.
  • the etching comprises forcing smaller lateral extensions for the third plurality of trench structures than for the first plurality of trench structures.
  • This embodiment makes use of the finding that RIE tends to etch wider trenches faster than narrower trenches. Therefore, this effect can be employed to create two depth levels of trenches in one etching step by forcing two different lateral extensions for the first and third plurality of trench structures.
  • the different lateral extensions can be forced for instance by providing suitable lateral extensions of mask openings for the etching step.
  • the third plurality of trench structures can for instance be used for fabricating trench capacitors in later processing steps.
  • the thinning of the integration substrate comprises mechanically grinding the integration substrate from the second integration- substrate side to a thickness that just avoids exposure of the first plurality of trenches; spin-etching the integration substrate using a first etching agent that leaves the via insulation layer intact; removing a part of the via insulation layer by etching, using a second etching agent that leaves the via core intact. This processing allows a very precise control of the material removal on the second integration-substrate side.
  • a silicon-on-insulator (SOI) substrate as the sensor substrate.
  • the SOI substrate preferably has the sensor in a silicon layer facing the integration substrate.
  • the method of this embodiment comprises a step of thinning the SOI substrate to remove a substrate material including the insulator layer of the SOI substrate, such that a silicon layer comprising the sensors remains after thinning.
  • a temporary support substrate is preferably attached to the thinned integration substrate on its second integration substrate side before the step of thinning the SOI substrate.
  • the temporary support substrate is removed after thinning the SOI substrate.
  • a radiation shield or other components into an additional functional layer of the system- in-package that forms the sensor device of the present invention is enabled by fabricating an opening in the integration substrate that is open on the second integration-substrate side.
  • a first radiation shield is attached to the integration substrate in the opening.
  • the process of the method of the second aspect of the invention has the advantage of allowing wafer scale processing. That means, the individual sensor devices are separated from the wafer only as a last step, i.e., after electrically connecting and attaching the circuit chip to the integration substrate.
  • the processing of this embodiment is particularly economic.
  • Fig. 1 to Fig. 8 shows an integration substrate during different initials stages of its fabrication, illustrating an embodiment of the method of the invention, in which through- substrate vias and trenches of different steps are integrated in one integration substrate.
  • Fig. 9 to Fig. 18 shows a sensor device in different processing stages of another embodiment of the method of the invention, for fabricating a detector with a sensor device.
  • Figs. 1 to 8 show a schematic, cross-sectional views of an integration substrate during different stages of an embodiment of a fabrication method.
  • Fig. 1 shows a carrier or integration substrate 102.
  • the integration substrate 102 has a first integration- substrate side 104 and a second integration- substrate side 106.
  • the first integration-substrate side will herein after also be referred to as the front side
  • the second integration-substrate side will also be referred to as the back side.
  • use of the terms "front side” and “back side” shall not be understood as a restriction to a specific arrangement of the integration substrate.
  • Trenches 108 and 110 laterally define an inductor area 112, the lateral extension of which is indicated by a double arrow 114.
  • the trenches 110 and 116 laterally define a capacitor area 118, the lateral extension of which is indicated by a double arrow 120.
  • the trenches 116 and 122 laterally define a through- substrate or, in other words, through-wafer via array 124, the lateral extension of which is indicated by a double arrow 126.
  • the trenches 108, 110, 116, and 122 are also referred to as isolation trenches.
  • capacitor area 118 In the capacitor area 118, three capacitor trenches 128, 130, and 132 have been formed.
  • the number of capacitor trenches is of purely exemplary nature.
  • the lateral extension of the capacitor area is chosen here only for the purposes of graphical representation. It is understood that the lateral extension of the capacitor area 118 and the number of capacitor trenches is to be chosen according to the needs of a particular application. The fabrication method described here does not impose limits on the lateral extension or the number of capacitor trenches.
  • the through-wafer via array 124 is shown to have four via trenches 134, 236,
  • the number of via trenches and the lateral extension of the through- wafer via array are of purely exemplary nature in the present example.
  • the integration substrate 102 is formed by a silicon wafer. However, this is not a necessary requirement. Other substrate materials can be used as well for the integration substrate 102. Suitable examples are for instance InP, GaN, AlN, glass, GaAs, etc.
  • RIE reactive ion etching
  • suitable etching conditions can be found to achieve a trench depth d2 of 27 ⁇ m with a trench width of 1.5 ⁇ m, while a trench width of 5,0 ⁇ m can be used to achieve a trench depth dl of 47 ⁇ m.
  • the trenches may in an alternative embodiment be etched separately, for instance in view of process control requirements.
  • the trenches may be etched partially simultaneously, for instance by etching the isolation trenches 108, 110, 116, and 122, as well as the via trenches 134 to 140 to a certain depth in a first step, using an auxiliary masking layer.
  • etching of the isolation trenches and the via trenches is continued and at the same time the capacitor trenches 128 to 132 are etched, after removing the auxiliary masking layer.
  • Fig. 1 shows the integration substrate 102 at a later processing stage, in which a dielectric layer 142 has been deposited or grown.
  • a suitable fabrication technique for the isolation layer is for instance the growth of a thermal oxide.
  • the oxide layer 142 covers the front side 104 of the integration substrate 102 and is also present at side walls and bottom faces of the trenches. Note that intermediate steps involving the removal of a resist etc. have not been illustrated.
  • a phosphorous- doped polysilicon layer 144 has been deposited to such a thickness that it completely fills the capacitor trenches 128 to 132.
  • the isolation trenches 108, 110, 116, and 122 are not completely filled by the P-doped polysilicon layer 144.
  • the P-doping can be performed in- situ during the deposition of the polysilicon layer.
  • a silicon nitride layer 146 is deposited and patterned for definition of capacitors in the capacitor area 118.
  • the silicon nitride layer 146 can be deposited by low-pressure chemical vapor deposition (LPCVD).
  • the silicon nitride layer 146 is used as a mask during a subsequent thermal oxidation step, in which the exposed polysilicon-layer regions, which are not covered by the silicon nitride layer 146, are oxidized outside the capacitor area 118.
  • an oxide layer 148 of approximately 1 to 1.5 ⁇ m thickness is formed, cf. Fig. 4.
  • the oxide layer 148 extends on the front side 104 of the integration substrate 102 and in the isolation and via trenches.
  • the isolation trenches 108, 110, 116, and 122 and the via trenches 134 to 140 are filled with tungsten.
  • This can for instances be achieved by plasma enhanced chemical vapor deposition.
  • the tungsten, which is in this step deposited on the surface of the integration substrate 102 is removed. This can be achieved for instances by an etching step.
  • a suitable etchant is for instance SF 6 .
  • An alternative removal method is chemical-mechanical polishing (CMP).
  • the tungsten filling of the isolation trenches 108, 110, 116, and 122 in the via trenches 134 to 140 forms an electrically conductive via core 150 to 164, while the oxide layer 148 that separates the via core from the substrate forms a via insulation layer, which prevents a direct electrical convention between the via core and the integration substrate 102.
  • the via cores have a lateral extension 1 of less than 3 ⁇ m. Note that the via cores 150 to 164 are completely filled with tungsten. A partial filling of the trenches with tungsten is not advisable because tungsten layers posses high levels of stress.
  • a dielectric layer 166 is deposited and patterned to cover the isolation trenches 108, 110, 116 and 122.
  • the dielectric layer 166 can for instances be deposited by PECVD.
  • the dielectric layer can for instance be made of silicon dioxide.
  • the patterning of the dielectric layer 166 allows contacting the capacitor trenches 128 to 132 and the via trenches 134 to 140 with an electrically conductive contact structure 168 and 170, respectively. Note that in an embodiment not shown here, some of the tungsten via cores 134 to 140 may be kept floating. Such trenches can be used to electrically isolate the different components in the process.
  • interconnect stack 172 is schematically represented in Fig. 8 by two interconnect levels with an intermediate interlevel dielectric layer 174 and a second metal level 176.
  • interconnect stack 172 is schematically represented in Fig. 8 by two interconnect levels with an intermediate interlevel dielectric layer 174 and a second metal level 176.
  • any suitable number of interconnect levels can be chosen for the particular application.
  • An inductor 178 has been fabricated on the second interconnect level 176 in the inductor area 112.
  • Figs. 9 to 17 show cross-sectional views of a sensor device according to an embodiment of the device aspect of the invention during different stages of its fabrication according to one embodiment of the method aspect of the invention.
  • Fig. 18 shows an embodiment of a detector device that comprises the sensor device.
  • Fig. 10 shows an integration substrate 202.
  • the integration substrate 202 has two integration- substrate sides 204 and 206, corresponding to the integration-substrate sides 104 and 106 of the first embodiment shown in Figs. 1 to 8.
  • the integration substrate 202 of Fig. 10 is shown in a processing stage, at which trenches 210 to 218 have been fabricated and filled with an insulation layer 224 and via cores 226 to 238.
  • the trenches 210, 216 and 218 have ring shape or another closed shape, for instance with the outline of a square or rectangle, when seen from the top.
  • the via cores have been covered with either an insulating layer 240 or with electrically conductive contact elements, shown by way of illustrative examples under the reference labels 242 and 244 in Fig. 10.
  • the contact element 242 is connected with via core 230 of the trench 214.
  • the contact element 244 is connected with the via cores 234 and 236 of the trench 218.
  • the via cores 226, 228, 232, and 238 are not electrically connected to electrically conductive elements on the first integration- substrate side 204.
  • solder bumps 246 to 252 have been fabricated, which are connected with interconnect elements on a second metallization level. Even though, not explicitly shown in Fig. 10, it is ensured that an electrical connection between the solder bumps 246 to 250 with the via cores 230, 234 and 236 is provided where required according to the needs of the specific application.
  • a SOI wafer 254 contains a silicon layer 256, an insulation layer 258 and a silicon handle wafer 260 on the insulation layer 258.
  • the silicon layer 256 is in the present embodiment formed by a thick film of silicon, which was deposited on the insulation layer 258 during prior processing.
  • the silicon layer 256 contains active circuitry.
  • the silicon layer 256 contains an active diode matrix (not shown) and will form a sensor chip after removal of the silicon handle wafer and the insulation layer.
  • the reference label 256 will therefore also be used for denoting the sensor chip containing the active diode matrix contained in the silicon layer.
  • Contact elements 262 are provided and arranged on the silicon layer 256 in a manner that fits to the arrangement of the solder bumps 246 to 252.
  • the SOI wafer 254 and the integration substrate 202 are connected by wafer-scale solder bumping and an underfill layer 264.
  • the integration substrate 202 is thinned, followed by an etch step, in which the isolation layer 224 is exposed and subsequently removed from the bottom of the trenches 210 to 222.
  • the isolation layer 224 is then removed from the bottom of the trenches, cf. Fig. 12.
  • a metallization scheme 266 is formed on the second integration substrate side 206. It thus becomes clear from Fig. 13 that the trenches 210 and 216 do not serve for electrical-connection purposes even though they are fabricated during the same processing steps as the through- substrate vias, which are formed of the trenches 214 and 218. To avoid confusion, the reference labels 214 and 218 will in the following also be used for the finished through- substrate vias formed from the original trenches 214 and 218. It can also be seen that trenches of different shapes can be formed with the same processing at the same time.
  • the through-substrate via 218 is formed in the shape of a hollow cylinder (filled with integration-substrate material), whereas the through- substrate via 214 has the shape of a full cylinder.
  • the thickness of the wall of the hollow cylinder 218 corresponds to the thickness of the full cylinder 214.
  • the subsequent processing which is shown in Figs. 14 and 15, comprises the formation of an opening 267 in the integration substrate 202 from the second integration- substrate side 206.
  • the opening is specific for the application purpose of the present illustrative example. It serves for accommodating a tungsten sheet 268, which is fixed to the integration substrate 202 by means of an adhesive (not shown).
  • the SOI wafer 254 as a whole serves as a support substrate or, in other words, handle wafer that protects the integration substrate 202 from damage due to mechanical stress that occurs in the processing.
  • a second temporary handle wafer 270 is attached to the second integration- substrate side 206.
  • the temporary handle wafer can for instance be a glass substrate.
  • the handle wafer 270 is attached to the integration substrate 202 be means of a thermal releasing tape 272.
  • a suitable thermal releasing tape is known as 9OC
  • the processing stage after attaching the second temporary handle wafer 268 is shown in Fig. 16.
  • the silicon layer of the SOI substrate 254 is removed. This can for instance be achieved by mechanical grinding until only the silicon layer/ sensor chip with the active diode matrix 256 is left. This remaining material can then be etched in an HF/FINO 3 etchant using a spin etching process. Subsequently, the second temporary substrate 268 is removed from the integration substrate 202 by a thermal release.
  • a circuit chip 274 that for instance contains an ASIC (not shown) is attached to the second integration-substrate side 206 via solder balls 276 and 278 and a respective underfilling 280, 282.
  • the circuit chip 274 comprises in one embodiment an integrated circuit for preprocessing or processing signals received from the active diode matrix in the sensor chip 256.
  • a solder ball 284 is applied. Finally, the wafer is diced into individual sensor devices (not visible in Fig. 18), which are then attached and electrically connected to a contact element 286 of a base plate in the form of a printed circuit board 288, cf. Fig. 18.
  • Fig. 18 thus shows a schematic cross-sectional view of a detector device 290 with sensor devices of the type of the sensor device 200 according to an embodiment of the invention.
  • the detector device 290 of Fig. 18 comprises a large-area sensor array, which is formed a matrix of sensor devices 200, which themselves contain the sensor chips 256 with active diode matrices and are arranged on the base plate 288.
  • the detector device 290 can form the basis for an X-ray detector for scanners in computer tomography.
  • the detector device has a scintillator (not shown) on top of the active diode matrix of the sensor chip 256, for converting the X-rays to visible light, and the active diode matrix serves to detect the light emitted by the scintillator.
  • the active diode matrix serves to detect the light emitted by the scintillator.
  • backside illuminated diodes are typically used. These diodes are fabricated on high-resistivity material to reduce capacitances. Shielding of the ASIC in circuit chip 274 from the X-rays is provided by the tungsten sheet 268.
  • the detector device 290 therefore forms a highly integrated, area efficient modular device that can be produced at relatively low cost.

Abstract

The present invention relates to a sensor device, comprising an integration substrate with a plurality of through-substrate vias, which have an electricallyconductive via core. Further, a sensor chip is provided, which has a first sensor-chip side that comprises at least one sensor and which is attached and electrically connected to the integration substrate on its first integration-substrate side. Also, a circuit chip, which is attached and electrically connected to the integration substrate on its second integration-substrate side comprises an integrated circuit, which is electrically connected with the sensors by means of at least one of the through-substrate vias. The sensor device forms a basis for a highly integrated, area- efficient large-area detector device that can be fabricated at low cost.

Description

A tillable sensor device
FIELD OF THE INVENTION
The present invention relates to a sensor device with a sensor chip on an integration substrate. It also relates to a detector device that comprises a plurality of sensor devices. The invention also relates to a method for fabricating a sensor device, and to a method for fabricating a detector device.
BACKGROUND OF THE INVENTION
US 2005/0098732 Al describes an x-ray detector device that comprises an array of sensor chips, which are arranged on a base plate in a matrix arrangement. The individual sensor chips form tiles of a large-area detector device. The individual tiles are positioned and precisely aligned on the base plate and subsequently glued to the base plate in this arrangement. Connection lines between the neighboring tiles are fabricated by printing after the gluing and alignment. The connection lines form an interconnection network on the front-side of the sensor array. The interconnection network is connectable to external control circuitry by means of connection pads, which are arranged on separate tiles at the edge of the sensor device on separate connection tiles.
The detector device of US 2005/0098732 Al has the disadvantage that a complicated and sensitive alignment process of the tiles on the base plate is required. A misalignment of the tiles with respect to each other could lead to a disturbed connectivity between neighboring tiles. This in turn could affect the operation of the detector device as a whole because the connection lines between the individual tiles are integrated into a large interconnect network on the front-side of the detector device. This interconnect network connects all individual sensors on each sensor chip to respective connect pads at the edge of the sensor device. An interconnect element that is malfunctioning due to misalignment thus would affect all sensors of a line or column on different sensor devices of the sensor matrix formed by the detector device.
A further disadvantage of the detector device of US 2005/0098732 Al is a large area that is required for the interconnects between the neighboring sensor chips. The required chip area is further increased by additional tiles on the edge of the detector device, which contain contact pads for connection with external circuitry.
SUMMARY OF THE INVENTION According to a first aspect of the invention, a sensor device is provided that comprises an integration substrate including a plurality of through- substrate vias, which have an electrically conductive via core; a sensor chip, which has a first sensor-chip side that comprises at least one sensor and which is attached and electrically connected to the integration substrate on its first integration-substrate side; and a circuit chip, which is attached and electrically connected to the integration substrate on its second integration-substrate side and which comprises an integrated circuit, which is electrically connected with the sensors by means of at least one of the through- substrate vias.
The sensor chip and the circuit chip are arranged on opposite signs of the integration substrate. Providing the sensor chip and the circuit chip in the same sensor device without having to increase the lateral extension of the sensor device is very useful for high integration and small overall size of the detector device. The sensor device of the present invention forms a system- in-package, in which the effective sensor area on the sensor chip can be increased in comparison with that of the sensor chips of US 2005/0098732 Al, given the same area of the sensor device. The sensor device of the present invention uses an integration substrate with a plurality of through-substrate vias for electrically connecting the sensors with a circuit chip. This way, the sensor device of the present invention allows for providing an application- specific integrated circuit, such as for instance a signal processing IC or a signal preprocessing IC in the sensor device. In a detector device that contains a plurality of sensor devices as tiles, an ASIC can be provided on every tile.
Furthermore the sensor device has the advantage of integrating the sensor chip and the circuit chip in one device, but still allowing a fabrication of the two chips in different technologies. For instance, the sensor chip can often be fabricated in a relatively simple and cheap processing technology. It can therefore be large without becoming prohibitively expensive. The circuit chip, on the other hand, is usually fabricated using an expensive IC technology, and usually requires much less chip area than the sensor chip. The combination of both technologies that is enabled by the sensor device after present invention provides an inexpensive way to produce a highly integrated sensor device with sensors and integrated circuit in the same sensor device.
A further advantage in this context is that the sensor chip and the circuit chip in many applications require different types of substrates. For instance, photo detectors used high-resistivity float-zone (FZ) substrates, while CMOS ASICs are processed in Czochralski (CZ) substrates with 10 to 20 Ωxcm resistivity.
A further advantage of the sensor device of the present invention is that it allows obtaining the sensor chip and the integrated circuit from different vendors. In the following, preferred embodiments of the sensor device of the first aspect of the invention will be described. Unless explained otherwise explicitly, the embodiments can be combined with each other.
The integration substrate preferably has a thickness less than 200 microns, suitably less than 100 microns, advantageously less than 50 microns and in some embodiments even in the range of 10-30 microns. In one embodiment, the integration substrate has a thickness of less that 100 micrometer. This implies that there is no lateral region, where the integration substrate as such has a thickness of more than 100 micrometer. For the purpose of definition of the thickness of the integration substrate, only the substrate material or wafer material of the integration substrate is considered, and not additional layers or structures deposited on this material on either of the integration- substrate sides. A through- substrate via typically connects at least one first electrically conductive element on a first integration-substrate side with at least one second electrically conductive element on a second integration-substrate side. Where the conductive elements are formed of layers deposited on the integration substrate, such as metallization layers, there thickness shall not count under the present definition. Nor thus the thickness include an extension of solder balls or bumps that can be present on one of the integration- substrate sides, for the purpose of the present definition. The present embodiment has an integration substrate, in which the through-substrate vias are particularly short. As will be shown in the context of the description of the method aspects of the present invention, such vias can be fabricated without making holes in the integration substrate. In fact, technologies for making trenches that are known as such can be used.
In another embodiment, the thickness of the integration substrate is further reduced to a thickness between 15 and 40 micrometer. In this embodiment, the thickness of the integration substrate is reduced to the minimum amount required form containing passive electric components that maybe required according the specific application. Such passive components may for instance be trench compositors.
One embodiment combines a thickness of the integration substrate of less that 100 micrometer with an aspect ratio of the through- substrate vias that is larger than 5. The sensor device of this embodiment therefore has through-substrate vias in the integration substrate, which are particularly short and, due to their high aspect ratio, at the same time have a particularly small lateral extension. In synergy, this combination of features allows combining a very high integration density on the integration substrate with very low parasitic lead inductances of the vias. Both requirements are important for advanced high- frequency applications, like sensor devices for radio-frequency (RF) applications. Both requirements can therefore now be met at the same time.
The aspect ratio of a through-substrate via is the quotient of a depth extension of the through-substrate via between its ends on the first and second integration-substrate sides, and of a lateral extension of the trench that is formed to fabricate the through- substrate in the integration substrate. The lateral trench extension can be derived from the finished integration substrate of the system- in-package, even after filling of the trench during further processing. Suitable analytic techniques are for instance known microscopic methods, like for instance optical microscopy or electron microscopy on a cross section of the integration substrate. The lateral trench extension of a single trench may vary when following its extension in the depth direction. That means, the trench may be wider in some depth regions and smaller in other depth regions. For the purpose of definition, in such an embodiment the lateral trench extension shall be considered to be the mean value of the lateral trench extension over along the extension in depth direction.
Assuming a cylindrical geometry for the vias, the inductance of the through- substrate vias scales in a superlinear manner with the length of the through-substrate vias, i.e., their extension in the depth direction, while its dependence on the aspect ratio is only sublinear. Therefore, even though a high integration density is achieved with relatively high aspect ratios of the through-substrate vias, which tends to increase the parasitic lead inductance for a given thickness of the integration substrate, the parasitic lead inductances of the through- substrate vias are at particularly low values. The low thickness of the integration substrate corresponds with the length of the through-substrate vias.
This synergy is achieved by the fabrication technology described later herein, which allows providing the integration-substrate with a thickness below 100 micrometer. Integration substrates with a thickness below 100 micrometer bear a very high risk of breakage by the required processing during fabrication, especially during wafer-scale processing, or during dicing. A method aspect correlated with the present embodiment overcomes this problem and allows achieving the aforementioned advantages by providing a support, which is attached to the integration substrate on its first integration-substrate side and which is suitable for mechanically supporting the integration substrate. The sensor device of the embodiment can thus be produced on wafer scale with good yield and lifetime according to industry standards.
In one embodiment, the sensor chip comprises an array of sensors for electromagnetic radiation. The sensors are for instance arranged for exposure to electromagnetic radiation to be detected on the first sensor-chip side, and the sensors are electrically connected to the integration substrate via an opposite second sensor-chip side.
This embodiment allows further reducing the area required for interconnections between neighbouring sensor devices in comparison with US 2005/0098732 Al. In other words, interconnects to neighbouring tiles in a detector device that contains a plurality of sensor devices of this embodiment can be routed through the integration substrate. The effective sensor area on the first senor-chip side is particularly large in this embodiment.
This embodiment can for instance contain photodiodes, which are illuminated on their backside, which forms the first sensor-chip side. This maximizes the active sensor area. For instance, in an application, where the sensor area is used to detect photons emitted from a scintillator layer that converts X-rays to visible or infrared light. Such X-ray detectors are useful for an application in computer-tomography (CT) scanners.
For several application purposes, it is useful to it is useful to provide a cavity in the integration substrate that is open to the second integration-substrate side. The cavity can for instance be arranged underneath a coil (inductance) on the first integration-substrate side. Cavities are also useful in applications, where the sensor device is exposed to radiation that may damage the integrated circuitry on the circuit chip. Also here, a cavity that is open to the second integration-substrate side can be arranged in the integration substrate. The cavity preferably extends laterally over at least a fraction of the lateral extension of the circuit chip. A first radiation shield is arranged inside the cavity, the first radiation shield beings suitable for absorbing radiation of a predetermined kind, such as, for instance, X-rays. For absorbing X-rays, tungsten is an example of a suitable material for the first radiation shield.
It should be noted that the through-substrate vias or other filled trench structures such as trench capacitors in one embodiment have a ring-type shape, when seen in a top view from the first integration- substrate side. A ring-type shape is used here as a generic term and includes other closed shapes beside the actual ring shape, for instance shapes having the outline of a rectangle, a square, an ellipse or an oval. The via filling forms the closed shape. In some embodiments, a ring-type shape can be used to electrically or optically insulate functional components arranged inside the ring on the integration substrate. Here, optical insulation includes insulation from electromagnetic radiation that covers high- energy regions of the spectrum, like X-rays.
In other embodiments, which are particularly suited for operation at high frequencies, the through-substrate vias have a coaxial structure, i.e., a via for a signal line is surrounded by vias for ground.
As will be explained in the context of embodiments of the method aspects of the invention, the filled trench structures can be fabricated at the same time as the through- substrate vias. They therefore preferably have the same lateral extension as the through- substrate vias.
According to a second aspect of the present invention a detector device is provided that comprises a plurality of sensor devices according to the first aspect of the invention or one of its embodiments. The sensor devices are attached and electrically connected to a base substrate. The detector device of the second aspect of the invention has an increased integration density. It provides integrated circuits in the individual sensor devices without having to sacrifice sensor area.
The detector device can be fabricated at relatively low cost due to its modular structure. This has also be explained in the context of the explanation of advantages of the sensor device of the first aspect of the invention.
The base substrate is in one embodiment a printed circuit board. It may provide for electrical connectivity of the detector device to external devices. It also may provide the interconnections between different sensor devices comprised by the detector devices. In one embodiment, the detector device comprises an X-ray-converter layer.
The X-ray-converter layer is preferably arranged on top of the sensor chips of the sensor devices. It is arranged and configured to convert electromagnetic radiation from the X-ray spectral range into radiation of a lower-energetic spectral range. For instance, a scintillator layer is an example of a suitable X-ray-converter layer. Further embodiments of detector device of the present invention correspond to those of the sensor device of the first aspect of the invention. A example of a useful detector device of the second aspect of the invention is an X-ray detector for scanners in computer tomography. However, other detector devices can form useful embodiments of the invention as well. For instance, the sensor chip that forms a part of the sensor device can comprise antennas as sensors form radio frequency (RF) radiation.
According to a third aspect of the invention, a method for a fabricating a sensor device is provided. The method comprises the steps: providing an integration substrate; - fabricating trench structures in the integration substrate on the first integration- substrate side; fabricating an electrically conductive via core in at least a first plurality of the trench structures, which forms a subset of the trench structures; attaching and electrically connecting a sensor substrate to the integration substrate on its first integration substrate side, the sensor substrate comprising one sensor or a plurality of sensors; fabricating at least one second conductive element on the second substrate side, which connects with the through-substrate via, and electrically connecting and attaching a circuit chip to the integration substrate on its second integration-substrate side.
The term trench structure, as used herein, refers to any suitable shape of recess that is formed in the integration substrate on its first integration-substrate side. A suitable trench structure extends through the integration substrate after the processing. The term trench structure is in other contexts also used to denote the structure after filling, as will be clear from the respective context of usage of the term. The trench structures have a larger extension in a direction perpendicular to the first integration-substrate side, which is also called depth direction herein, than in directions parallel to the first integration-substrate side, which are also referred to as lateral directions herein. Some embodiments have trench structures with a shape resembling that of a column. That the advantages of the method of the third aspect of the present invention correspond to those of the sensor device of the first aspect of the invention and those of the detector device of the second aspect of the invention. In the following, embodiments of the method of the invention will be described. It is understood, that embodiments can be combined which each other, unless otherwise stated explicitly.
In one embodiment, the method comprises thinning the integration substrate from its second integration-substrate side to a thickness below 100 micrometer, such that only a bottom face of the via course of the first plurality of trench structures is exposed. In this embodiment, the sensor substrate is preferably selected suitable for mechanically supporting the integration substrate during thinning to the reduced integration-substrate thickness of less than 100 micrometer. Experience shows that a thinning of the integration substrate down to less than
100 micrometer strongly increases the risk of substrate breakage during thinning, later processing or handling of the integration substrate. However, the present embodiment overcomes this problem by attaching a support in the form of the sensor substrate to the integration substrate on its first integration- substrate side before the thinning step. The support is selected so that it provides the mechanical stability required to avoid a breakage during the known processing conditions of thinning, later processing, and handling of the integration substrate.
Not only can the integration density be driven to very high values in this embodiment, but also can parasitic lead inductances of the through-substrate vias be made very low. This is made possible without having to use though- wafer via holes with a conductive copper core. For on one hand, copper would seem attractive for the via core due to its low resistivity. On the other hand, however, being able to avoid the use of copper is a great advantage in the present context. The use of copper would require the provision of a copper diffusion barrier in the via holes. From a processing point of view, this is undesirable. For at the moment, this can only be achieved using atomic layer deposition (ALD) equipment and therefore involves an extremely low deposition rate. This increases processing costs. Furthermore, copper processing and the processing of copper-containing integration substrates, such as silicon wafers, is usually also undesirable due to possible contaminations introduced by the presence of copper. Additionally, fully copper-filled via holes could pose a reliability risk due to differences in thermal-expansion coefficients in comparison with surrounding material, such as silicon. In contrast, being able to stay with established processing technology allows using for instance tungsten as a via core material. Tungsten can be deposited fast, for instance by chemical vapor deposition (CVD) or plasma-enhanced (PE)CVD. In some embodiments, trench structures for through-substrate vias and other trench structures, such as trench capacitors, are fabricated in a single step, which typically is an etching step. This is a particularly simple processing for such different structures. However, it should be noted there is no requirement to fabricate trench structures for different purposes.
Fabricating the sensor device as a system- in-package with through-substrate vias in the integration substrate can be performed without having to fabricate holes crossing through the complete integration substrate. This as such is known, for instance from US 2002/0084513. However, the processing disclosed in US 2002/0084513 has several disadvantages. The protruding via provided by this technique is used as a bump and as such is mechanically sensitive, unless fabricated with considerable thickness to provide sufficient mechanical strength. Furthermore, the thinning of the wafer during the processing disclosed in US 2002/0084513 Al increases the risk of wafer-breakage during handling, in particular during further processing of the wafer and the assembly made with it. Furthermore, parasitic lead inductances due to the through-substrate via are rather high in the structure of US 2002/0084513 Al.
In one embodiment, fabricating the first plurality of trench structures is performed employing reactive ion etching (RIE). RIE has proven very useful in fabricating trench structures with lateral extensions, which are substantially reduced in comparison with standard through-substrate via holes as known from prior-art processing techniques. The disadvantage of these prior-art processing techniques is that the use of RIE makes the fabrication of through- substrate via holes with larger depth and lateral extensions a relatively slow and expensive process. The use of RIE in the context of the processing of the method of the third aspect of the invention, however, enables reducing the etching time as much as possible. For the depth and the lateral extensions of the trench structures are significantly reduced due to the decreased thickness of the integration substrate in the finished sensor device, and due to the large aspect ratio of the through-substrate vias.
Further advantages of the use of RIE can be achieved in an embodiment, where a third plurality of trench structures in the integration substrate is fabricated with smaller depth extensions in comparison with the first plurality of trench structures. In this embodiment, the first and third plurality of trench structures are etched concurrently, i.e., in a common etching step. The etching comprises forcing smaller lateral extensions for the third plurality of trench structures than for the first plurality of trench structures. This embodiment makes use of the finding that RIE tends to etch wider trenches faster than narrower trenches. Therefore, this effect can be employed to create two depth levels of trenches in one etching step by forcing two different lateral extensions for the first and third plurality of trench structures. The different lateral extensions can be forced for instance by providing suitable lateral extensions of mask openings for the etching step.
The third plurality of trench structures can for instance be used for fabricating trench capacitors in later processing steps.
In a further embodiment, the thinning of the integration substrate comprises mechanically grinding the integration substrate from the second integration- substrate side to a thickness that just avoids exposure of the first plurality of trenches; spin-etching the integration substrate using a first etching agent that leaves the via insulation layer intact; removing a part of the via insulation layer by etching, using a second etching agent that leaves the via core intact. This processing allows a very precise control of the material removal on the second integration-substrate side.
In embodiments, which employ a described thinning of the integration substrate, it has proved useful to employ a silicon-on-insulator (SOI) substrate as the sensor substrate. The SOI substrate preferably has the sensor in a silicon layer facing the integration substrate. The method of this embodiment comprises a step of thinning the SOI substrate to remove a substrate material including the insulator layer of the SOI substrate, such that a silicon layer comprising the sensors remains after thinning.
For supporting the sensor device during thinning of the SOI substrate, a temporary support substrate is preferably attached to the thinned integration substrate on its second integration substrate side before the step of thinning the SOI substrate. The temporary support substrate is removed after thinning the SOI substrate.
The integration of a radiation shield or other components into an additional functional layer of the system- in-package that forms the sensor device of the present invention is enabled by fabricating an opening in the integration substrate that is open on the second integration-substrate side. In one embodiment, a first radiation shield is attached to the integration substrate in the opening.
The process of the method of the second aspect of the invention has the advantage of allowing wafer scale processing. That means, the individual sensor devices are separated from the wafer only as a last step, i.e., after electrically connecting and attaching the circuit chip to the integration substrate. The processing of this embodiment is particularly economic.
Embodiments of the invention are also defined in the dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be explained in more detail with reference to the drawings in which
Fig. 1 to Fig. 8 shows an integration substrate during different initials stages of its fabrication, illustrating an embodiment of the method of the invention, in which through- substrate vias and trenches of different steps are integrated in one integration substrate.
Fig. 9 to Fig. 18 shows a sensor device in different processing stages of another embodiment of the method of the invention, for fabricating a detector with a sensor device.
DETAILED DESCRIPTION OF EMBODIMENTS
Figs. 1 to 8 show a schematic, cross-sectional views of an integration substrate during different stages of an embodiment of a fabrication method.
Fig. 1 shows a carrier or integration substrate 102. The integration substrate 102 has a first integration- substrate side 104 and a second integration- substrate side 106. The first integration-substrate side will herein after also be referred to as the front side, and the second integration-substrate side will also be referred to as the back side. However, use of the terms "front side" and "back side" shall not be understood as a restriction to a specific arrangement of the integration substrate.
On the first integration-substrate side 104, a number of trenches has been fabricated at the processing stage shown in Fig. 1. Trenches 108 and 110 laterally define an inductor area 112, the lateral extension of which is indicated by a double arrow 114. The trenches 110 and 116 laterally define a capacitor area 118, the lateral extension of which is indicated by a double arrow 120. The trenches 116 and 122 laterally define a through- substrate or, in other words, through-wafer via array 124, the lateral extension of which is indicated by a double arrow 126. The trenches 108, 110, 116, and 122 are also referred to as isolation trenches.
In the capacitor area 118, three capacitor trenches 128, 130, and 132 have been formed. The number of capacitor trenches is of purely exemplary nature. Of course, also the lateral extension of the capacitor area is chosen here only for the purposes of graphical representation. It is understood that the lateral extension of the capacitor area 118 and the number of capacitor trenches is to be chosen according to the needs of a particular application. The fabrication method described here does not impose limits on the lateral extension or the number of capacitor trenches. The through-wafer via array 124 is shown to have four via trenches 134, 236,
238, and 140. Than, the number of via trenches and the lateral extension of the through- wafer via array are of purely exemplary nature in the present example.
In the present embodiment, the integration substrate 102 is formed by a silicon wafer. However, this is not a necessary requirement. Other substrate materials can be used as well for the integration substrate 102. Suitable examples are for instance InP, GaN, AlN, glass, GaAs, etc. In one embodiment of a processing method, all trenches provided at the present processing stage have been fabricated in one reactive ion etching (RIE) process. This processing makes use of the fact that in a RIE process like the Bosch process wider trenches tent to be etched faster than narrower trenches. It is thus achieved that two different depths dl and d2 of trenches can be fabricated in one etching step by using two different trench widths. For instance, suitable etching conditions can be found to achieve a trench depth d2 of 27 μm with a trench width of 1.5 μm, while a trench width of 5,0 μm can be used to achieve a trench depth dl of 47 μm. However, the trenches may in an alternative embodiment be etched separately, for instance in view of process control requirements. As a further alternative, the trenches may be etched partially simultaneously, for instance by etching the isolation trenches 108, 110, 116, and 122, as well as the via trenches 134 to 140 to a certain depth in a first step, using an auxiliary masking layer. In a second step, the etching of the isolation trenches and the via trenches is continued and at the same time the capacitor trenches 128 to 132 are etched, after removing the auxiliary masking layer. Fig. 1 shows the integration substrate 102 at a later processing stage, in which a dielectric layer 142 has been deposited or grown. A suitable fabrication technique for the isolation layer is for instance the growth of a thermal oxide. The oxide layer 142 covers the front side 104 of the integration substrate 102 and is also present at side walls and bottom faces of the trenches. Note that intermediate steps involving the removal of a resist etc. have not been illustrated.
In a subsequent processing stage, which is shown in Fig. 2, a phosphorous- doped polysilicon layer 144 has been deposited to such a thickness that it completely fills the capacitor trenches 128 to 132. The isolation trenches 108, 110, 116, and 122 are not completely filled by the P-doped polysilicon layer 144. The P-doping can be performed in- situ during the deposition of the polysilicon layer.
Subsequently, as shown in Fig. 3, a silicon nitride layer 146 is deposited and patterned for definition of capacitors in the capacitor area 118. The silicon nitride layer 146 can be deposited by low-pressure chemical vapor deposition (LPCVD).
The silicon nitride layer 146 is used as a mask during a subsequent thermal oxidation step, in which the exposed polysilicon-layer regions, which are not covered by the silicon nitride layer 146, are oxidized outside the capacitor area 118. In this "LOCOS style " oxidation step, an oxide layer 148 of approximately 1 to 1.5 μm thickness is formed, cf. Fig. 4. The oxide layer 148 extends on the front side 104 of the integration substrate 102 and in the isolation and via trenches.
Subsequently, as shown in Fig. 5, the isolation trenches 108, 110, 116, and 122 and the via trenches 134 to 140 are filled with tungsten. This can for instances be achieved by plasma enhanced chemical vapor deposition. The tungsten, which is in this step deposited on the surface of the integration substrate 102 is removed. This can be achieved for instances by an etching step. A suitable etchant is for instance SF6. An alternative removal method is chemical-mechanical polishing (CMP). The tungsten filling of the isolation trenches 108, 110, 116, and 122 in the via trenches 134 to 140 forms an electrically conductive via core 150 to 164, while the oxide layer 148 that separates the via core from the substrate forms a via insulation layer, which prevents a direct electrical convention between the via core and the integration substrate 102. The via cores have a lateral extension 1 of less than 3 μm. Note that the via cores 150 to 164 are completely filled with tungsten. A partial filling of the trenches with tungsten is not advisable because tungsten layers posses high levels of stress.
In a subsequent processing step, the result of which is shown in Fig. 6, a dielectric layer 166 is deposited and patterned to cover the isolation trenches 108, 110, 116 and 122. The dielectric layer 166 can for instances be deposited by PECVD. The dielectric layer can for instance be made of silicon dioxide.
The patterning of the dielectric layer 166 allows contacting the capacitor trenches 128 to 132 and the via trenches 134 to 140 with an electrically conductive contact structure 168 and 170, respectively. Note that in an embodiment not shown here, some of the tungsten via cores 134 to 140 may be kept floating. Such trenches can be used to electrically isolate the different components in the process.
Subsequently, after the deposition of the first metal layer comprising the contacts 168 and 170, the fabrication of an interconnect stack 172 proceeds in a well-known manner. The interconnect stack 172 is schematically represented in Fig. 8 by two interconnect levels with an intermediate interlevel dielectric layer 174 and a second metal level 176. However, any suitable number of interconnect levels can be chosen for the particular application. An inductor 178 has been fabricated on the second interconnect level 176 in the inductor area 112.
Figs. 9 to 17 show cross-sectional views of a sensor device according to an embodiment of the device aspect of the invention during different stages of its fabrication according to one embodiment of the method aspect of the invention. Fig. 18 shows an embodiment of a detector device that comprises the sensor device. Reference is first made to Figs. 9 and 10 in parallel. Fig. 10 shows an integration substrate 202. The integration substrate 202 has two integration- substrate sides 204 and 206, corresponding to the integration-substrate sides 104 and 106 of the first embodiment shown in Figs. 1 to 8. The integration substrate 202 of Fig. 10 is shown in a processing stage, at which trenches 210 to 218 have been fabricated and filled with an insulation layer 224 and via cores 226 to 238. The trenches 210, 216 and 218 have ring shape or another closed shape, for instance with the outline of a square or rectangle, when seen from the top.
Subsequently, the via cores have been covered with either an insulating layer 240 or with electrically conductive contact elements, shown by way of illustrative examples under the reference labels 242 and 244 in Fig. 10. The contact element 242 is connected with via core 230 of the trench 214. The contact element 244 is connected with the via cores 234 and 236 of the trench 218. The via cores 226, 228, 232, and 238 are not electrically connected to electrically conductive elements on the first integration- substrate side 204. Additionally, solder bumps 246 to 252 have been fabricated, which are connected with interconnect elements on a second metallization level. Even though, not explicitly shown in Fig. 10, it is ensured that an electrical connection between the solder bumps 246 to 250 with the via cores 230, 234 and 236 is provided where required according to the needs of the specific application.
As can be seen from the forgoing description, the integration substrate 202 has been processed in a manner corresponding to that described in the context of Figs. 1 through 9. Therefore, reference is made to a cited earlier description with regard to details of the processing, the result of which is shown in Fig. 10. Note that the processing is performed on a complete wafer, and not on individual dies. Turning now to Fig. 9, a SOI wafer 254 contains a silicon layer 256, an insulation layer 258 and a silicon handle wafer 260 on the insulation layer 258. The silicon layer 256 is in the present embodiment formed by a thick film of silicon, which was deposited on the insulation layer 258 during prior processing. The silicon layer 256 contains active circuitry. As an illustrative example, it will be assumed for the following description that the silicon layer 256 contains an active diode matrix (not shown) and will form a sensor chip after removal of the silicon handle wafer and the insulation layer. The reference label 256 will therefore also be used for denoting the sensor chip containing the active diode matrix contained in the silicon layer. Contact elements 262 are provided and arranged on the silicon layer 256 in a manner that fits to the arrangement of the solder bumps 246 to 252.
Turning to Fig. 11, the SOI wafer 254 and the integration substrate 202 are connected by wafer-scale solder bumping and an underfill layer 264.
Subsequently, the integration substrate 202 is thinned, followed by an etch step, in which the isolation layer 224 is exposed and subsequently removed from the bottom of the trenches 210 to 222. The isolation layer 224 is then removed from the bottom of the trenches, cf. Fig. 12.
Subsequently, as shown in Fig. 13, a metallization scheme 266 is formed on the second integration substrate side 206. It thus becomes clear from Fig. 13 that the trenches 210 and 216 do not serve for electrical-connection purposes even though they are fabricated during the same processing steps as the through- substrate vias, which are formed of the trenches 214 and 218. To avoid confusion, the reference labels 214 and 218 will in the following also be used for the finished through- substrate vias formed from the original trenches 214 and 218. It can also be seen that trenches of different shapes can be formed with the same processing at the same time. In particular, the through-substrate via 218 is formed in the shape of a hollow cylinder (filled with integration-substrate material), whereas the through- substrate via 214 has the shape of a full cylinder. The thickness of the wall of the hollow cylinder 218 corresponds to the thickness of the full cylinder 214.
The subsequent processing, which is shown in Figs. 14 and 15, comprises the formation of an opening 267 in the integration substrate 202 from the second integration- substrate side 206. The opening is specific for the application purpose of the present illustrative example. It serves for accommodating a tungsten sheet 268, which is fixed to the integration substrate 202 by means of an adhesive (not shown).
In this step, the SOI wafer 254 as a whole serves as a support substrate or, in other words, handle wafer that protects the integration substrate 202 from damage due to mechanical stress that occurs in the processing. Subsequently, a second temporary handle wafer 270 is attached to the second integration- substrate side 206. The temporary handle wafer can for instance be a glass substrate. In the present embodiment, the handle wafer 270 is attached to the integration substrate 202 be means of a thermal releasing tape 272. A suitable thermal releasing tape is known as 9OC The processing stage after attaching the second temporary handle wafer 268 is shown in Fig. 16.
In a subsequent processing step, the result of which is shown in Fig. 17, the silicon layer of the SOI substrate 254 is removed. This can for instance be achieved by mechanical grinding until only the silicon layer/ sensor chip with the active diode matrix 256 is left. This remaining material can then be etched in an HF/FINO3 etchant using a spin etching process. Subsequently, the second temporary substrate 268 is removed from the integration substrate 202 by a thermal release.
After that, a circuit chip 274 that for instance contains an ASIC (not shown) is attached to the second integration-substrate side 206 via solder balls 276 and 278 and a respective underfilling 280, 282. The circuit chip 274 comprises in one embodiment an integrated circuit for preprocessing or processing signals received from the active diode matrix in the sensor chip 256.
Also, a solder ball 284 is applied. Finally, the wafer is diced into individual sensor devices (not visible in Fig. 18), which are then attached and electrically connected to a contact element 286 of a base plate in the form of a printed circuit board 288, cf. Fig. 18.
Fig. 18 thus shows a schematic cross-sectional view of a detector device 290 with sensor devices of the type of the sensor device 200 according to an embodiment of the invention.
The detector device 290 of Fig. 18 comprises a large-area sensor array, which is formed a matrix of sensor devices 200, which themselves contain the sensor chips 256 with active diode matrices and are arranged on the base plate 288.
The detector device 290 can form the basis for an X-ray detector for scanners in computer tomography. To that end, the detector device has a scintillator (not shown) on top of the active diode matrix of the sensor chip 256, for converting the X-rays to visible light, and the active diode matrix serves to detect the light emitted by the scintillator. For maximizing the area of the active diodes, backside illuminated diodes are typically used. These diodes are fabricated on high-resistivity material to reduce capacitances. Shielding of the ASIC in circuit chip 274 from the X-rays is provided by the tungsten sheet 268. The detector device 290 therefore forms a highly integrated, area efficient modular device that can be produced at relatively low cost.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.
Any reference signs in the claims should not be construed as limiting the scope

Claims

CLAIMS:
1. A sensor device (200), comprising an integration substrate (202) including a plurality of through-substrate vias (214, 218), which have an electrically conductive via core (230); a sensor chip (256), which has a first sensor-chip side that comprises at least one sensor and which is attached and electrically connected to the integration substrate on its first integration-substrate side (204); and a circuit chip (274), which is attached and electrically connected to the integration substrate on its second integration-substrate side (206)and which comprises an integrated circuit, which is electrically connected with the at least one sensor by means of at least one of the through-substrate vias (214).
2. The sensor device of claim 1, wherein the integration substrate has a thickness of less than 100 Micrometer.
3. The sensor device of claim 2, wherein the through-substrate vias (214) have an aspect ratio larger than 5
4. The sensor device of claim 3, wherein the aspect ratio of the through- substrate vias is between 15 and 25.
5. The sensor device of claim 1, wherein the sensor chip (256) comprises an array of sensors for electromagnetic radiation, the sensors being arranged for exposure to electromagnetic radiation to be detected on the first sensor-chip side and electrically connected to the integration substrate (202) via an opposite second sensor-chip side.
6. The sensor device of claim 1, comprising a cavity (267) in the integration substrate that is open to the second integration- substrate side (206).
7. The sensor device of claim 1, wherein the cavity (267) laterally extends over at least a fraction of the lateral extension of the circuit chip (274), and wherein a first radiation shield (268) is arranged inside the cavity, the first radiation shield being suitable for absorbing radiation of a predetermined kind.
8. The sensor device of claim 1, comprising a filled trench structure (210, 216) that has the same lateral extension as the through-substrate vias (214).
9. The sensor device of claim 1 or 8, wherein either a through- substrate via (218) or the filled trench structure (210) or both, as seen in a top view from the first integration- substrate side, have a ring-type shape.
10. A detector device (290) comprising a plurality of sensor devices (200) of claim 1, which are attached and electrically connected to a base substrate (288).
11. The detector device of claim 10, comprising an x-ray-converter layer arranged on top of the sensor chips of the sensor devices, the x-ray converter layer being arranged to convert electromagnetic radiation from the x-ray spectral range into radiation of a lower- energetic spectral range.
12. A method for fabricating a sensor device (200), comprising: providing an integration substrate (202); fabricating trench structures (214) in the integration substrate on the first integration-substrate side (204); - fabricating an electrically conductive via core (230) in at least a first plurality of the trench structures, which forms a subset of the trench structures; attaching and electrically connecting a sensor substrate (254) to the integration substrate on its first integration substrate side, the sensor substrate comprising one sensor or a plurality of sensors; - fabricating at least one second conductive element (266) on the second substrate side (206), which connects with the through-substrate via (214); and electrically connecting and attaching a circuit chip (274) to the integration substrate on its second integration-substrate side.
13. The method of claim 12, wherein the sensor substrate (254) is selected suitable for mechanically supporting the integration substrate during thinning to a reduced integration- substrate thickness of less than 100 micrometer, and the method comprises a step of - thinning the integration substrate (202) from its second integration-substrate side (206) to a thickness below 100 micrometer, such that only a bottom face of the via cores (230) of the first plurality of trench structures is exposed.
14. The method of claim 13, wherein thinning the integration substrate comprises - mechanically grinding the integration substrate (202) from the second integration- substrate side to a thickness that just avoids exposure of the first plurality of trenches; spin-etching the integration substrate using a first etching agent that leaves a via insulation layer (224) intact; - removing a part of the via insulation layer by etching, using a second etching agent that leaves the via core (230) intact.
15. The method of claim 13, comprising using a silicon-on- insulator substrate (254) as the sensor substrate, the silicon-on-insulator substrate having the sensor in a silicon layer (256) that is arranged next to the integration substrate, and comprising a step of thinning the silicon-on-insulator substrate to remove substrate material including an insulator layer (258) of the silicon-on-insulator substrate such that a silicon layer (256) comprising the sensors remains after the thinning step.
16. The method of claim 14, wherein a temporary support substrate (270) is attached to the thinned integration substrate (202) on its second integration-substrate side (206) before the step of thinning the silicon-on-insulator substrate (254), and wherein the temporary support substrate is removed after thinning the silicon-on-insulator substrate.
17. The method of claim 12, comprising fabricating a cavity (267) in the integration substrate that is open on the second integration-substrate side, and attaching a first radiation shield (268) to the integration substrate in the cavity.
18. The method of claim 12, which is performed on wafer scale, and comprises a dicing step for separating individual sensor devices.
PCT/IB2008/052017 2007-05-29 2008-05-22 A tillable sensor device WO2008146211A1 (en)

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