WO2008142750A1 - 演算ユニット、プロセッサ及びプロセッサアーキテクチャ - Google Patents

演算ユニット、プロセッサ及びプロセッサアーキテクチャ Download PDF

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Publication number
WO2008142750A1
WO2008142750A1 PCT/JP2007/060161 JP2007060161W WO2008142750A1 WO 2008142750 A1 WO2008142750 A1 WO 2008142750A1 JP 2007060161 W JP2007060161 W JP 2007060161W WO 2008142750 A1 WO2008142750 A1 WO 2008142750A1
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WO
WIPO (PCT)
Prior art keywords
processor
pipe line
calculation unit
calculation
architecture
Prior art date
Application number
PCT/JP2007/060161
Other languages
English (en)
French (fr)
Inventor
Hideki Yoshizawa
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to CN200780052666A priority Critical patent/CN101689108A/zh
Priority to JP2009515020A priority patent/JP5126226B2/ja
Priority to EP07743596A priority patent/EP2148272B1/en
Priority to KR1020097019456A priority patent/KR101190937B1/ko
Priority to PCT/JP2007/060161 priority patent/WO2008142750A1/ja
Publication of WO2008142750A1 publication Critical patent/WO2008142750A1/ja
Priority to US12/618,954 priority patent/US8281113B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

　プロセッサ１の実行ステージにおいて所定桁長の演算を行う演算ユニット１７は、所定桁長の演算を桁方向に分割した各演算をそれぞれ異なるパイプラインステージにおいて実行する複数の部分演算ユニット２０１～２０４と、各パイプラインステージ間を各々区切る複数のパイプラインレジスタ２１１～２１３、２２１～２２７、２３１～２３７、２４１～２４６と、を備え、各パイプラインレジスタ２１１～２１３、２２１～２２７、２３１～２３７、２４１～２４６は、入力トリガに同期して出力値を更新するフリップフロップモードと、入力値をそのまま出力するトランスペアレントモードと、２つの動作モード間で切り替え可能に動作する。
PCT/JP2007/060161 2007-05-17 2007-05-17 演算ユニット、プロセッサ及びプロセッサアーキテクチャ WO2008142750A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN200780052666A CN101689108A (zh) 2007-05-17 2007-05-17 运算单元、处理器和处理器体系结构
JP2009515020A JP5126226B2 (ja) 2007-05-17 2007-05-17 演算ユニット、プロセッサ及びプロセッサアーキテクチャ
EP07743596A EP2148272B1 (en) 2007-05-17 2007-05-17 Calculation unit, processor, and processor architecture
KR1020097019456A KR101190937B1 (ko) 2007-05-17 2007-05-17 연산 유닛, 프로세서 및 프로세서 아키텍처
PCT/JP2007/060161 WO2008142750A1 (ja) 2007-05-17 2007-05-17 演算ユニット、プロセッサ及びプロセッサアーキテクチャ
US12/618,954 US8281113B2 (en) 2007-05-17 2009-11-16 Processor having ALU with dynamically transparent pipeline stages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/060161 WO2008142750A1 (ja) 2007-05-17 2007-05-17 演算ユニット、プロセッサ及びプロセッサアーキテクチャ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/618,954 Continuation US8281113B2 (en) 2007-05-17 2009-11-16 Processor having ALU with dynamically transparent pipeline stages

Publications (1)

Publication Number Publication Date
WO2008142750A1 true WO2008142750A1 (ja) 2008-11-27

Family

ID=40031477

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/060161 WO2008142750A1 (ja) 2007-05-17 2007-05-17 演算ユニット、プロセッサ及びプロセッサアーキテクチャ

Country Status (6)

Country Link
US (1) US8281113B2 (ja)
EP (1) EP2148272B1 (ja)
JP (1) JP5126226B2 (ja)
KR (1) KR101190937B1 (ja)
CN (1) CN101689108A (ja)
WO (1) WO2008142750A1 (ja)

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JP5849962B2 (ja) * 2010-10-29 2016-02-03 日本電気株式会社 署名処理装置

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JP5480793B2 (ja) * 2010-12-10 2014-04-23 株式会社日立製作所 プログラマブルコントローラ
US8804764B2 (en) 2010-12-21 2014-08-12 International Business Machines Corporation Data path for data extraction from streaming data
US20120198213A1 (en) * 2011-01-31 2012-08-02 International Business Machines Corporation Packet handler including plurality of parallel action machines
GB2537523B (en) * 2014-09-30 2017-09-27 Imagination Tech Ltd Multimode variable length execution pipeline
CN107357561A (zh) * 2017-05-17 2017-11-17 苏州大学 基于sdr的面向物联网的asip架构及设计方法
US11132233B2 (en) * 2018-05-07 2021-09-28 Micron Technology, Inc. Thread priority management in a multi-threaded, self-scheduling processor
CN110728364A (zh) * 2018-07-17 2020-01-24 上海寒武纪信息科技有限公司 一种运算装置和运算方法
CN110045989B (zh) * 2019-03-14 2023-11-14 合肥雷芯智能科技有限公司 一种动态切换式低功耗处理器
CN110597622A (zh) * 2019-08-13 2019-12-20 欣扬电脑股份有限公司 多节点异质运算装置及多节点异质运算***

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JPS54143036A (en) * 1978-04-28 1979-11-07 Toshiba Corp Decentralized addition and subtraction system
JPS60123930A (ja) * 1983-12-09 1985-07-02 Hitachi Ltd 高速演算方式
JPH04238533A (ja) * 1991-01-23 1992-08-26 Hitachi Ltd パイプライン制御方法を使用した演算器
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US20050251645A1 (en) 1998-03-31 2005-11-10 Patrice Roussel Method and apparatus for staggering execution of an instruction

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JPS54143036A (en) * 1978-04-28 1979-11-07 Toshiba Corp Decentralized addition and subtraction system
JPS60123930A (ja) * 1983-12-09 1985-07-02 Hitachi Ltd 高速演算方式
JPH04238533A (ja) * 1991-01-23 1992-08-26 Hitachi Ltd パイプライン制御方法を使用した演算器
US20050251645A1 (en) 1998-03-31 2005-11-10 Patrice Roussel Method and apparatus for staggering execution of an instruction
JP2004102988A (ja) 1999-08-30 2004-04-02 Ip Flex Kk データ処理装置
JP2003216416A (ja) * 2002-01-25 2003-07-31 Ando Electric Co Ltd 論理演算回路
JP2005011324A (ja) * 2003-06-12 2005-01-13 Arm Ltd データ処理装置を使用する場合のフレキシビリティの改善
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JP5849962B2 (ja) * 2010-10-29 2016-02-03 日本電気株式会社 署名処理装置

Also Published As

Publication number Publication date
JP5126226B2 (ja) 2013-01-23
CN101689108A (zh) 2010-03-31
KR20100005035A (ko) 2010-01-13
KR101190937B1 (ko) 2012-10-12
US20100058030A1 (en) 2010-03-04
EP2148272A1 (en) 2010-01-27
EP2148272A4 (en) 2011-03-09
US8281113B2 (en) 2012-10-02
JPWO2008142750A1 (ja) 2010-08-05
EP2148272B1 (en) 2012-08-08

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