WO2008133620A1

WO2008133620A1 - High power t/r switch using stacked transistors

Info

Publication number: WO2008133620A1
Application number: PCT/US2007/010295
Authority: WO
Inventors: Haifeng Xu; Kenneth K. O
Original assignee: University Of Florida
Priority date: 2007-04-26
Filing date: 2007-04-26
Publication date: 2008-11-06

Abstract

A T/R switch circuit is provided. In a preferred embodiment, T/R switch circuit designs are provided that increase IP1dB for T/R switches while maintaining IL less than ~1 dB. In an embodiment, the T/R switch circuit can incorporate a series transistor on the TX leg, 3-stack transistors on the RX leg, shunt 3-stack transistors on the TX node, and a shunt transistor on the RX node. The transistors can be formed using sub-design-rule (SDR) channel length to reduce insertion loss (IL) and can be located in isolated p-wells to provide an improved floating body. In addition, feed-forward metal capacitors can be included to improve the total voltage swing of stacked transistors. This circuit can be implemented in the UMC 130-nm mixed mode triple-well CMOS process.

Description

DESCRIPTION

HIGH POWER T/R SWITCH USING STACKED TRANSISTORS

Background of Invention

The Transmit/Receive (T/R) switch is a key building block of a Radio Frequency (RF) front end of most time-division duplexing (TDD) communication systems. A typical TDD communication system includes a transmitter, receiver, T/R switch, and antenna. Figure 1 shows a block diagram of an example of a TDD communication system. As illustrated, a T/R switch follows the Power Amplifier (PA), and usually needs to sustain the highest voltage swing. The performance of the T/R switch depends on certain operating performance parameters that are taken into consideration in its design. The key parameters tend to be the 1-dB compression point at input (IPiaβ), insertion loss (IL) and isolation. The 1-dB compression point, or IP)dB_> describes the switch's ability to handle large input power when the switch is turned on. The IPidB is defined as the input power at which the insertion loss has increased by 1 dB from its low-power value. Power handling capabilities of certain stacked transistors are described by T. Ohnakado, et al., "21.5-dBm Power-Handling 5-GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration With Depletion-Layer-Extended Transistors (DETs)," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 577-584, April 2004.

The IL of the switch can be determined from the difference between the available power at an input node and the power that is delivered to a load at an output node. IL tends to depend on resistances of the switch transistors. In one approach to T/R switch design, silicon-on-insulator (SOI) technology is utilized. For example, Burgener et al. and Kelly et al. in U.S. Patent No. 7,123,898 and U.S. Patent Application No. 2006/0194567, respectively, provide examples of stacked transistor groupings for improving T/R switch characteristics for high voltage/power.

In SOI processes, this stacking is practical because all transistors are isolated. However, these stacking designs are difficult to accomplish in CMOS processes due to the softly connected substrate for all NMOS transistors.

In bulk CMOS technologies, low breakdown voltage of transistors and parasitic diodes at drain and source junctions limit the power handling capability of bulk CMOS T/R switches. Techniques, such as floating body, stacked transistors and DC bias of drain/source, have been used to improve this performance. However, it is still difficult to implement CMOS T/R switches with Pi_dB higher than 3OdBm and IL lower than IdB. This impedes the realization of low cost RF systems using foundry CMOS processes.

Z.-B. Li, et al. (2003) and T. Ohnakado, et al. (2004) have shown that by connecting the body nodes of NMOS transistors through a high resistance, the power handling capability can be improved while slightly degrading IL [Z.-B. Li, et al., "5.8- GHz CMOS T/R Switches With High and Low Substrate Resistances in a 0.18-um CMOS Process," IEEE Microwave and Wireless Components Letters, vol. 13, no. 1, pp. 1-3, Jan. 2003],[T. Ohnakado, et al., "21.5-dBm Power-Handling 5-GHz Transmit/Receive CMOS Switch Realized by Voltage Division Effect of Stacked Transistor Configuration With Depletion-Layer-Extended Transistors (DETs)," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 577-584, April 2004]. As another technique, N. A. Talwalkar, et al. (2004) achieved Pi_dB of 28.5 dBm and IL of 1.5 dB at 2.4 GHz by making the high impedance connection to the body using a parallel LC tank [N. A. Talwalkar, et al., "Integrated CMOS Transmit- Receive Switch Using LC-Tuned Substrate Bias for 2.4-GHz and 5.2-GHz Applications," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 863-870, June 2004]. However, an LC tank consumes a large area and makes the switch narrow band. It has been suggested that similar performance should be achievable while eliminating the need for an LC tank by using NMOS transistors in isolated p-wells of triple well CMOS processes. However, to date, the highest input referred 1-dB compression point (IPidβ) reported for switches using isolated p-wells is only 21.3 dBm with IL of 0.7 dB at 2.4 GHz [M.-C. Yeh, et al., "A Miniature Low-Insertion-Loss, High-Power CMOS SPDT Switch Using Floating-Body Technique for 2.4- and 5.8-GHz Applications," IEEE RFIC Symp. Dig., pp. 451-454, 2005]. Accordingly, it has been difficult to implement CMOS T/R switches with IP_IJB higher than 3OdBm and IL lower than IdB, which impedes the realization of low cost RF systems using foundry CMOS processes.

Brief Summary Embodiments of the present invention pertain to improved T/R switch circuit designs. Embodiments of the subject invention can be used in time-division duplexing (TDD) CMOS transceivers with high transmitting power. hi many embodiments, the power handling capability of T/R switches using foundry CMOS processes can be increased, while keeping the insertion loss low. A high level of integration can be possible such that low cost solutions of wireless communication systems can be provided on a single chip.

In an embodiment, the subject TVR switch can provide an improved power handling capability and can be implemented using foundry CMOS processes. In a specific embodiment, the T/R switch can be implemented in bulk CMOS. In a preferred embodiment, the T/R switch circuit incorporates a series transistor on the TX leg, 3-stack transistors on the RX leg, shunt 3-stack transistors on the TX node, and a shunt transistor on the RX node. The transistors can be formed using sub-design-rule (SDR) channel length to reduce insertion loss (IL). The transistors can be located in isolated p- wells to provide an improved floating body. In addition, feed-forward capacitors can be included to balance the voltage swing among the stack transistors. In one embodiment, the feedforward capacitors can be metal capacitors. In another embodiment, the feed-forward capacitors can be MIM capacitors.

In a specific embodiment, to form "isolation-improved' transistors in triple-well CMOS processes, transistors can be formed in separate p-wells placed within n-wells in a stacked formation. This method significantly increases the power handling capability. Second, to compensate the power loss due to stacking, SDR channel length MOS transistors can be utilized. Feedforward capacitance is another method that can be incorporated to distribute the voltage swing evenly among the stack transistors, and therefore improve power capability.

Brief Description of Drawings

Figure 1 is a block schematic showing a T/R switch in a typical TDD communication system. Figure 2 shows a simplified schematic of T/R switch with 3-stack sub-design-rule

(SDR) length transistors according to an embodiment of the subject invention.

Figure 3 shows a cross-section of 3-stack MOS transistors in a SDR T/R switch according to an embodiment of the subject invention.

Figure 4 shows a die photo of a 3-stack SDR T/R switch according to an embodiment of the subject invention.

Figure 5 is a plot of measured insertion loss of a SDR CMOS T/R switch using 3- stack transistors according to an embodiment of the subject invention, compared to that of a switch using 2-stack 0.34-μm length 3.3-V transistors. Figure 6 is a plot of measured isolation and return loss for the SDR CMOS T/R switch using 3-stack SDR channel length transistors.

Figure 7 is a plot of IP ^₈ and IIP₃ measurement results of the 3-stack SDR T/R switches with source/drain biased at 3V and OV, and with and without the feed-forward capacitors.

Figure 8 is a table providing a performance summary of stacked T/R switches.

Detailed Disclosure Embodiments of the subject invention pertain to T/R switch circuit designs for improved characteristics for T/R switches. In a preferred embodiment, T/R switch circuit designs are provided that can increase IPidB above 30 dBm for T/R switches while maintaining IL less than —1 dB. An exemplary embodiment involves a 900 MHz single- pole-double-throw (SPDT) switch with IP M_B of 31.3 dBm, and IL' s of 0.5 dB and 1 dB in transmit (TX) and receive (RX) modes at 900 MHz. In addition, for this exemplary embodiment, isolation is better than 29 dB up to 1 GHz. Another exemplary embodiment involves a 2.4 GHz SPDT switch with IP_KJB of 28 dBm, and IL' s of 0.8 dB and 1.2 dB in TX and RX modes. For this exemplary embodiment, isolation is better than 24 dB up to 2.4 GHz. As illustrated by the exemplary embodiments, in a specific embodiment, switches can be fabricated using 3.3-V transistors of UMC (United Microelectronics Corporation) 130-nm mixed mode CMOS process with a thicker gate oxide layer. In this way the switches can support the required voltage swing.

An embodiment of the subject T/R switch circuit is illustrated in Figure 2. Stacked transistors can be used on the RX leg and can be used as shunt transistors for the TX node. Figure 2 indicates three stacked transistors. However, the number of stacked series and shunt transistors can be modified. The number of transistors for the stacked transistors in the stacked series and stacked shunt can be the same number. The transistors may be N- type or P-type. However, N-type transistors are preferred. In a specific embodiment where P-type transistors are used, isolated n-wells can be formed in a simpler way, e.g. a twin- well process. An embodiment of the T/R switch can be implemented in a 130-nm mixed mode triple-well CMOS process. As shown in Figure 2, the T/R switch circuit can be formed with a series transistor M4 on the TX leg, 3-stack transistors M6-M8 on the RX leg, shunt 3-stack transistors M1-M3 on the TX node, and a shunt transistor M5 on the RX node. In a specific embodiment, all the transistors use 3.3-V thick-gate-oxide MOSFETs. Here, the stacked shunt transistors M1-M3 and series transistors M6-M8 are used to improve the power handling.

However, stacking can degrade (e.g., increase) the IL of the RX leg. To mitigate this degradation and to lower the IL of TX leg, in an embodiment, all of the transistors can be implemented using sub-design-rule (SDR) channel length. In a further embodiment, the transistors can be implemented using SDR channel length with lower on-resistance. Referring to the embodiment shown in Figure 2, the drawn length of transistors can be 0.26 μm instead of 0.34 μm currently required for 3.3-V transistors. Since the thin-gate- oxide and thick-gate-oxide layers for the 3.3-V and 1.2-V transistors in the process can be simultaneously formed, the SDR channel length transistors can be formed without any process modifications. SDR switches can be fabricated in foundry CMOS technologies with no extra cost. Specific embodiments of the switch do not utilize impedance transformation to increase IPidB and demonstrate the broadband characteristics. In addition, the peak-to-peak voltage the switch needs to handle is ~20 V at 30 dBm input power. In one embodiment, isolation of the transistors can be accomplished by locating the transistors in isolated p-wells to allow the body node to float and to follow the RF input. This increases IPi_dB similarly to that which happens in switches fabricated in silicon on sapphire (SOS) and silicon on insulator (SOI) processes. To make sure the isolated p-wells are not AC grounded through the series combination of p-well-to-deep-n-well and deep-n- well-to-p-substrate junction capacitances, the substrate resistance can be increased by using a p-well implantation block (for example, having a width of ~20 μm), using a small number (for example, 4 per transistor) of substrate contacts, and adding a 1 kΩ resistor in series with the substrate contacts as shown in Figure 3.

Embodiments of the subject switch can incorporate feed-forward techniques, as those taught in K. Miyatsuji, and D. Ueda, "A GaAs High Power RF Single Pole Dual Throw Switch IC for Digital Mobile Communication System," IEEE J. of Solid-State Circuits, vol. 30, no. 9, pp. 979-983, which is hereby incorporated by reference in its entirety, such as capacitors (shown as C3, C4, C5 and C6) between the drain and body nodes of M3 and M8 and between the drain and gate nodes of M3 and M8 as shown in Figure 2. The feed-forward capacitors C3, C4, C5 and C6 can be metal capacitors. In one embodiment, the capacitors C3, C4, C5 and C6 can be MIM capacitors. The body-to- substrate parasitic junction capacitances make the voltage swing unevenly distributed among the gates and bodies of 3-stack transistors. Typically, M3 and M8 sustain higher gate-to-body and drain-to-gate voltages than Ml and M6. The extra capacitances can help the body/gate nodes of M3 and M8 better follow the high swing nodes, and can make the voltage swing at TX and ANT nodes more evenly distributed among the gates and bodies of the stacked transistors. This enables the stack as a whole to withstand a larger voltage swing before any one transistor is turned on or damaged. The metal capacitors can be formed using metal layers 1 through 3 and can be incorporated as part of the transistor layout.

For operation, TX and RX nodes as well as the sources of Ml and M5 can be biased at 3 V, and the switches can be turned on and off by varying the control voltage (G_TX, G_RX) from 2 to 6 V.^' Referring to Figure 2, metal capacitors Cl and C2, which can be formed using metal layers 1 through 8, can be connected to the sources of Ml and M5 to block the DC current and provide AC ground.

The switches can be controlled using a circuit similar to that taught by R. Point et al., An RF CMOS Transmitter Integrating a Power Amplifier and a Transmit/Receive Switch for 802.11b Wireless Local Area Network Applications," Proc. of 2003 RFIC Symposium, pp. 431-434, Philadelphia, PA, which is hereby incorporated by reference in its entirety, and the control voltages can be generated using a voltage doubler. A die photograph of the circuit is shown in Figure 4. The active area is about 300 μm by 380 μm or ~0.1 mm². This is ~6X smaller than the —0.6 mm² of the switch using an LC-tank connection to the body node as taught by N. A. Talwalkar et al. (2004).

Measured insertion loss, isolation and return loss for the embodiment shown in Figure 2 are shown in Figures 5 and 6. Referring to Figure 5, at 900 MHz, IL of the 3- stack SDR switch is 0.5 and 1.0 dB for TX and RX mode, respectively. A T/R switch, using only 2-stack 0.34-μm length transistors instead of 3-stack 0.26-μm length transistors is also measured for comparison. As shown in Figure 5, the non-SDR CMOS T/R switch's IL of RX leg is ~0.2 dB higher than that for the switch using 3-stack SDR channel length transistors. In addition, referring to Figure 6, the isolation of the SDR CMOS T/R switch is better than 29 dB for both TX and RX modes.

Figure 7 shows the linearity of the SDR CMOS T/R switch at 900 MHz. The measured IP_WB at the TX node is above 31.3 dBm, which is the highest IPi_dB currently reported for bulk CMOS T/R switches. It is also ~ 5 dB higher than that for the switch with 2-stack 0.34-μm length transistors. The UP₃ of the SDR CMOS switch is 42 dBm. When the source and drain nodes are biased at 0 V, IPmβ drops to 26 dBm. The linearity measurements of the SDR CMOS T/R switches with and without the additional feedforward capacitors are also compared in Figure 7. The IPidB for the switch with the additional capacitors (extra capacitance) is ~ 1 dB higher. At high input power, the output power abruptly drops with input power and limits the power handling. This effect may be reversible in that when the input power is lowered, the output power is increased back. Currently, it appears that the cause of this effect is that the 3-transistor stack (M1-M3) is breaking down. A positive consequence of this may be that when the switch is severely mismatched, the resulting high voltage will be clamped, thus protecting the switch from permanent damages. The performances of the 3-stack SDR switch with capacitors and the 3-stack SDR switch without capacitors are summarized in the table shown in Figure 8.

Also included are the measurement results of a 2-stack SDR switch operating at 2.4 GHz.

Its IPid_B is greater than 28 dBm, while IL is 0.8 and 1.2 dB for TX and RX legs at 2.4 GHz.

The reliability characteristics of the exemplary SDR CMOS T/R switch was examined by stressing the switch at IPidB for 10 hours. The stress was done for both when ANT pad is connected to 50-Ω load, and when it is left open to examine the effects of mismatch. The measured S-parameters showed no difference before and after the stresses.

Although the examples of embodiments of the present invention are provided in reference to bulk CMOS processes, embodiments of the present invention can be implemented for all FET processes such as MOSFET and MESFET. In addition, the processes can include other processes such as SOI processes and GaAs based processes.

It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application.

Claims

Claims What is claimed is:

1. A bulk CMOS T/R switching circuit, comprising: a TX transistor in series between a TX node and an ANT node; an RX stacked transistor configuration in series between an RX node and the ANT node, wherein the RX stacked transistor configuration comprises a first plurality of transistors; a shunt RX transistor coupled to the RX node; and a shunt TX stacked transistor configuration coupled to the TX node, wherein the shunt TX stacked transistor configuration comprises a second plurality of transistors, wherein the TX transistor, RX stacked transistor configuration, RX transistor, and TX stacked transistor configuration are formed using bulk CMOS processes.

2. The circuit according to claim 1, further comprising: feed-forward capacitors formed between the drain and body nodes of a transistor of the RX stacked transistor configuration, between the drain and gate nodes of the transistor of the RX stacked transistor configuration, between the drain and body nodes of a transistor of the TX stacked transistor configuration, and between the drain and gate nodes of a transistor of the TX stacked transistor configuration.

3. The circuit according to claim 2, wherein the feed-forward capacitors are metal capacitors.

4. The circuit according to claim 3, wherein the metal capacitors are formed using metal layers 1 through 3.

5. The circuit according to claim 3, wherein the metal capacitors are formed using metal layers 1 through 8.

6. The circuit according to claim 2, wherein the feed-forward capacitors are MIM capacitors.

7. The circuit according to claim 1, further comprising metal capacitors for blocking the DC current and providing AC ground, the metal capacitors being connected to the sources of a transistor of the TX stacked transistor configuration and the RX transistor.

8. The circuit according to claim 7, wherein the TX node, the RX node, the source of the transistor of the TX stacked transistor configuration, and the source of the RX transistor bias at 3 V; and wherein the TX transistor, the transistors of the RX stacked transistor configuration, the shunt RX transistor, and the transistors of the shunt TX stacked transistor configuration are capable of being turned on and off by varying a control voltage from 2 to 6 V.

9. The circuit according to claim 1, wherein the RX stacked transistor configuration comprises three stacked NMOS transistors formed in isolated p-wells, wherein the p-wells are isolated through a triple well process.

10. The circuit according to claim 1, wherein the shunt TX stacked transistor configuration comprises three stacked NMOS transistors formed in isolated p-wells, wherein the p-wells are isolated through a triple well process.

11. The circuit according to claim 1, wherein the TX transistor, the transistors of the RX stacked transistor configuration, the shunt RX transistor, and the transistors of the shunt TX stacked transistor configuration are formed having sub-design-rule (SDR) channel lengths.

12. The circuit according to claim 11, wherein the channel length of the transistors is about 0.26 μm for a 0.34 μm design rule 3.3-V transistor.

13. The circuit according to claim 1, wherein the TX stacked transistor configuration and the RX stacked transistor configuration comprise NMOS transistors formed in isolated p-wells, wherein the p-wells are isolated through a triple well process, the circuit further comprising: a p-well implantation block formed between each isolated p-well, a small number of substrate contacts, and a resistor in series with the substrate contacts.

14. The circuit according to claim 13, wherein four substrate contacts are formed per transistor.

15. The circuit according to claim 13, wherein the p-well implantation block formed between each isolated p-well has a width of about 20 μm.

16. The circuit according to claim 1, wherein a same number of transistors is used for the first plurality of transistors of the RX stacked transistor configuration and the second plurality of transistors of the shunt TX stacked transistor configuration.

17. The circuit according to claim 1, wherein the TX stacked transistor configuration and the RX stacked transistor configuration comprise NMOS transistors formed in isolated p-wells, wherein the p-wells are isolated through a triple well process, the circuit further comprising: feed-forward capacitors formed between the drain and body nodes of a transistor of the RX stacked transistor configuration, between the drain and gate nodes of the transistor of the RX stacked transistor configuration, between the drain and body nodes of a transistor of the TX stacked transistor configuration, and between the drain and gate nodes of a transistor of the TX stacked transistor configuration, wherein the TX transistor, the transistors of the RX stacked transistor configuration, the shunt RX transistor, and the transistors of the shunt TX stacked transistor configuration are formed having sub-design-rule (SDR) channel lengths.

18. The circuit according to claim 1, wherein the TX transistor and the shunt RX transistor are formed of different sizes.

19. A T/R switching circuit, comprising: a TX transistor in series between a TX node and an ANT node; an RX stacked transistor configuration in series between an RX node and the ANT node, wherein the RX stacked transistor configuration comprises a first plurality of transistors; a shunt RX transistor coupled to the RX node; and a shunt TX stacked transistor configuration coupled to the TX node, wherein the shunt TX stacked transistor configuration comprises a second plurality of transistors; wherein the TX transistor, the transistors of the RX stacked transistor configuration, the shunt RX transistor, and the transistors of the shunt TX stacked transistor configuration are formed having sub-design-rule (SDR) channel lengths.

20. The T/R switching circuit according to claim 19, further comprising: feed-forward capacitors formed between the drain and body nodes of a transistor of the RX stacked transistor configuration, between the drain and gate nodes of the transistor of the RX stacked transistor configuration, between the drain and body nodes of a transistor of the TX stacked transistor configuration, and between the drain and gate nodes of a transistor of the TX stacked transistor configuration.