WO2008128160A1 - Hemt basé sur des structures si/nitrure - Google Patents

Hemt basé sur des structures si/nitrure Download PDF

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Publication number
WO2008128160A1
WO2008128160A1 PCT/US2008/060200 US2008060200W WO2008128160A1 WO 2008128160 A1 WO2008128160 A1 WO 2008128160A1 US 2008060200 W US2008060200 W US 2008060200W WO 2008128160 A1 WO2008128160 A1 WO 2008128160A1
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WO
WIPO (PCT)
Prior art keywords
gan
substrate
algan
transistor device
etched
Prior art date
Application number
PCT/US2008/060200
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English (en)
Inventor
Tomas Palacios
Jinwook Chung
Original Assignee
Massachusetts Institute Of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massachusetts Institute Of Technology filed Critical Massachusetts Institute Of Technology
Publication of WO2008128160A1 publication Critical patent/WO2008128160A1/fr
Priority to US12/577,892 priority Critical patent/US8188459B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the invention relates to the field of transistor structures, and in particular to a transi stor formed using S i/nitride structures .
  • GaN transistors are normally grown on SiC substrates. In spite of the excellent performance of these devices, their commercialization is severely hindered by the high cost of SiC wafers. To reduce cost, GaN transistors have also been grown on Si substrates (normally >10 times cheaper than SiC). However, the performance of these devices is limited by the high electrical conductivity and poor thermal conductivity of the Si substrate.
  • a transistor device includes a substrate.
  • a buffer region is positioned on the substrate.
  • a GaN/ AlGaN layer is positioned on the buffer region.
  • a method of forming a transistor device includes providing a substrate and forming a buffer region on the substrate. Moreover, the method includes forming a GaN/ AlGaN structure on the buffer region.
  • FIGs. IA- 1C are process flow graphs for the selective removal of a Si substrate below AlGaN/GaN HEMTs
  • FIG. 2 is a scanning electron micrograph (SEM) of the selective etch if Si substrate in accordance with the invention
  • FIGs. 3A-3F are process flow graphs of the selective removal of the Si wafer and Si-doped GaN material in the buffer of an AlGaN/GaN HEMT;
  • FIG. 4 is a schematic diagram illustrating a thin-body AlGaN/GaN HEMT formed in accordance with invention
  • FIG. 5 is a schematic diagram illustrating a double gate GaN HEMT formed in accordance with the invention
  • FIGs. 6A-6D are examples of a process flow graph for the implantation of Si from the back side of the wafer to improve the activation yield of Si implanted species.
  • FIGs. 7A-7E are examples of a process flow graph for the integration of Si CMOS electronics in GaN-on-Si wafers.
  • the invention involves several new technologies to improve the performance of GaN HEMTs grown on Si substrates.
  • This invention also allows the fabrication of completely new devices as well as the development of hybrid circuits with GaN HEMTs and Si MOSFETs in close proximity.
  • the first technology which is called GaN-on- nothing technology, will allow the fabrication of GaN transistors grown on Si without the frequency performance limitations traditionally shown on GaN-on-Si devices.
  • This technology is based on the reduction of parasitic substrate capacitances through the full etching of the Si wafer below the GaN transistors. This technology will also help to reduce buffer leakage currents and to improve the transistor reliability.
  • the technology also has important beneficial effects in the implantation yield in nitrides, ohmic contact resistance as well as in the carrier confinement and gate electrostatic control in these devices. All these new characteristics will allow GaN-on-Si devices to reach a performance level at least similar to the one on GaN-on-SiC devices, at a fraction of the total cost and in a much more scalable technology.
  • the second key technology will allow the fabrication of Si devices in close proximity to GaN HEMTs in a GaN-on-Si wafer. This technology is based on the selective removal of the AlGaN/GaN epilayer and subsequent processing of the exposed Si (111) wafer.
  • FIG. IA shows an as grown AlGaN/GaN structure on GaN- on-Si wafer 2, as shown in step 12 of FIG. IB.
  • Photoresists 6 or other masking materials are deposited and defined on the Si substrate ⁇ of wafer 2 as shown in step 14 and a dry etch is used to remove a portion of the Si substrate 8 so as to expose a portion of the bottom layer of the GaN buffer layer 10 of wafer 4, as shown in step 16 of FIG. 1C.
  • FIG. 2 shows an electron micrograph 18 of some via holes fabricated in Si wafers in MTL. Due to the extremely high chemical stability of nitride semiconductors, the GaN buffer layer will act as a etch stop layer to the Bosch etch (SF ⁇ -based etch). There are many other technologies that can be used to etch Si and they should not reduce the generality of the invention.
  • the selective removal of the Si material below the AlGaN/GaN transistor is the first step to improve the performance of these devices.
  • FIGs. 3A-3F shows a process flow graph illustrating the formation of an AlGaN/GaN transistor.
  • An AlGaN/GaN wafer 22 is shown in step 20 of FIG. 3A includes a Si-doped GaN buffer layer 24 grown on a Si substrate 26.
  • Photoresist layers 28, 30 are deposited on the bottom side of the Si substrate 26, as shown in step 32 of FIG. 3B.
  • a portion of the Si substrate 26 is removed using a dry etch exposing the Si-doped GaN buffer layer 24, as shown in step 34 of FIG. 3C.
  • AlGaN/GaN transistors grown on Si have important parasitic capacitances due to both the relative high conductivity of the Si substrate 26 and the diffusion of Si atoms into the GaN buffer layer 24 during the high temperature growth of the GaN epilayer 35.
  • the first component of the parasitic capacitances is eliminated.
  • a portion of the GaN buffer layer 24 is etched with a Cl 2 -based plasma to remove the Si-doped conductive region, as shown in step 36 of FOG. 3D.
  • This approach will significantly reduce the buffer conductivity and improve the high frequency performance of AlGaN/GaN devices grown on Si. It is expected that the removal of the Si substrate 26 and Si-doped buffer 24 will reduce the parasitic buffer capacitance at least by 50 % and the buffer leakage current.
  • the photoresist layers 28, 30 are also removed in step 38 of FIG. 3E.
  • a high temperature annealing may be performed in the structure.
  • gate 42, source 44, and drain 46 contacts are formed using lithography and deposition while being aligned with wafer backside 46.
  • FIG. 4 shows an ultra thing body AlGaN/GaN HEMT structure 51 formed in accordance with the invention as shown in FIG. 3. If the etch of the GaN buffer layer 24 is carefully controlled, it is possible to etch most of the GaN buffer 50 and fabricate ultra thin body AlGaN/GaN HEMT 50 where only 5-100 nm of the GaN buffer layer 50 is left after the etch, as shown in FIG. 4.
  • This device geometry will improve the carrier confinement and the modulation efficiency of the gate, which will significantly increase the high frequency performance of these devices.
  • the proposed device geometry will also be useful to increase the reliability and lifetime of the GaN transistor as it alleviates the internal stress due to the high piezoelectric coefficients and electric fields of these transistors.
  • Thin etch stop layers made of AlGaN, InGaN or InAlGaN layers 52 can be used in the buffer to assure a reproducible etch.
  • the inventive ultrathin body devices could also benefit from the possibility of depositing metallic contacts in the back side of the wafer, for example on the GaN buffer layer 60. Due to this new technology, devices with a top 62 and bottom gate 64 could be fabricated for the first time in the GaN system, as show in FIG. 5. These devices will significantly improve the electrostatic control of the channel by the gate, enhancing the pinch-off of the devices and increasing the frequency performance.
  • Si implantation is being investigated by several groups to reduce the access resistances in AlGaN/GaN HEMTs, however it has only achieved a limited success due to the poor activation yield of implanted Si in the AlGaN
  • FIGs. 6A-6D shows the process steps of this improved implantation technology.
  • FIG. 6 A shows a AlGaN/GaN wafer 72 having portions of the wafer's Si substrate 74, Si- doped GaN buffer layer 76, a GaN layer 78 being etched, as shown step 70.
  • Step 80 of FIG. 6B shows Si implantation being performed in the etched regions.
  • Step 82 of FIG. 6C shows high temperature activation of the regions 86 of Si planted atoms.
  • Step 84 of FIG. 6D shows the formation of a source 88, gate 90, and drain 92 on the regions 86 of Si planted atoms using metal deposition. Note the source and drain can be formed on the backside of the wafer 72 as well.
  • the invention also protects the use of the Si substrate of the GaN-on-Si wafer to process the Si electronics required by the hybrid GaN-Si circuits.
  • the standard orientation of Si wafers used in the microelectronics industry is (100)
  • Si (111) has also been used by industry in the fabrication of high performance Si electronics.
  • the processing of the Si devices has to be done after the growth of the AlGaN/GaN epilayers.
  • FIG. 7A show a AlGaN/GaN wafer 112 having a AlGaN layer 116, a GaN epilayer 118, and a Si substrate 114, as shown in step 110.
  • Photoresist layers 122 are formed on the wafer 112, as show in step 120 of FIG. 7B.
  • Portions of the AlGaN layer 116 and GaN epilayer 118 are etched to expose the top surface of the Si substrate 114 as shown in FIG. 7C.
  • the etching of the AlGaN/GaN epilayer can be done with a dry etching system with a combination of Cl 2 and BCI 3 chemistries. This etching has been proven successful in the etching of thick GaN layers during the process of GaN HEMTs and lasers, as shown in step 126 of FIG. 1C.
  • the photoresist layers 122 are removed as shown in step 128 of FIG. 7D.
  • Step 130 of FIG. 7E shows a Si-based MOSFET structure 132 being formed on the exposed top surface of the Si substrate 1 14.
  • the invention allows a substantial reduction in the cost of GaN-based transistors which will revolutionize the high frequency electronic market.
  • the tremendous performance, at an affordable price, of these new devices will allow the introduction of a great variety of new applications, from cell phone base stations, to anti-collision radar systems, digital electronics, or the like.
  • the new devices enabled by the proposed technology such as double gate and ultra-low access resistance transistors, will allow the use of these devices at much higher frequencies and it may even allow the use of these devices in a future beyond-Si digital electronics.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Dans la présente invention, un transistor comprend un substrat. Une région tampon est positionnée sur le substrat et une couche GaN/ AlGaN est positionnée sur la région tampon.
PCT/US2008/060200 2007-04-12 2008-04-14 Hemt basé sur des structures si/nitrure WO2008128160A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/577,892 US8188459B2 (en) 2007-04-12 2009-10-13 Devices based on SI/nitride structures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92309407P 2007-04-12 2007-04-12
US60/923,094 2007-04-12

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100065923A1 (en) * 2008-09-16 2010-03-18 Alain Charles Iii-nitride device with back-gate and field plate and process for its manufacture
US20110062448A1 (en) * 2009-09-11 2011-03-17 Samsung Electronics Co., Ltd. Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices
EP2662896A3 (fr) * 2012-05-07 2014-09-10 Forschungsverbund Berlin e.V. Structure de couche semi-conductrice
JP6625287B1 (ja) * 2019-02-19 2019-12-25 三菱電機株式会社 半導体装置、および、半導体装置の製造方法
WO2022223214A1 (fr) * 2021-04-21 2022-10-27 Robert Bosch Gmbh Dispositif semi-conducteur au gan sur substrat de silicium comportant une tranchée de face arrière et son procédé de fabrication
WO2022228948A1 (fr) * 2021-04-27 2022-11-03 Robert Bosch Gmbh Nitrure de gallium sur dispositif à semi-conducteur de silicium comprenant des tranchées de face arrière et de séparation dans le substrat de silicium, et son procédé de production

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US20050173728A1 (en) * 2004-02-05 2005-08-11 Saxler Adam W. Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same
US20060138457A1 (en) * 2003-09-05 2006-06-29 Sanken Electric Co., Ltd. Nitride-based semiconductor device of reduced current leakage
US20070051977A1 (en) * 2005-08-24 2007-03-08 Kabushiki Kaisha Toshiba Nitride semiconductor device

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Publication number Priority date Publication date Assignee Title
US20020117681A1 (en) * 2001-02-23 2002-08-29 Weeks T. Warren Gallium nitride material devices and methods including backside vias
US20050006639A1 (en) * 2003-05-23 2005-01-13 Dupuis Russell D. Semiconductor electronic devices and methods
US20060138457A1 (en) * 2003-09-05 2006-06-29 Sanken Electric Co., Ltd. Nitride-based semiconductor device of reduced current leakage
US20050173728A1 (en) * 2004-02-05 2005-08-11 Saxler Adam W. Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same
US20070051977A1 (en) * 2005-08-24 2007-03-08 Kabushiki Kaisha Toshiba Nitride semiconductor device

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Title
BUTTARI D ET AL: "SYSTEMATIC CHARACTERIZATION OF CL2 REACTIVE ION ETCHING FOR GATE RECESSING IN ALGAN/GAN HEMTS", 1 March 2002, IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, PAGE(S) 118 - 120, ISSN: 0741-3106, XP001101703 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100065923A1 (en) * 2008-09-16 2010-03-18 Alain Charles Iii-nitride device with back-gate and field plate and process for its manufacture
US9112009B2 (en) * 2008-09-16 2015-08-18 International Rectifier Corporation III-nitride device with back-gate and field plate for improving transconductance
US20150357458A1 (en) * 2008-09-16 2015-12-10 International Rectifier Corporation III-Nitride Device with Improved Transconductance
US20110062448A1 (en) * 2009-09-11 2011-03-17 Samsung Electronics Co., Ltd. Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices
US9450071B2 (en) * 2009-09-11 2016-09-20 Samsung Electronics Co., Ltd. Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices
EP2662896A3 (fr) * 2012-05-07 2014-09-10 Forschungsverbund Berlin e.V. Structure de couche semi-conductrice
JP6625287B1 (ja) * 2019-02-19 2019-12-25 三菱電機株式会社 半導体装置、および、半導体装置の製造方法
WO2022223214A1 (fr) * 2021-04-21 2022-10-27 Robert Bosch Gmbh Dispositif semi-conducteur au gan sur substrat de silicium comportant une tranchée de face arrière et son procédé de fabrication
WO2022228948A1 (fr) * 2021-04-27 2022-11-03 Robert Bosch Gmbh Nitrure de gallium sur dispositif à semi-conducteur de silicium comprenant des tranchées de face arrière et de séparation dans le substrat de silicium, et son procédé de production

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