WO2008120418A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2008120418A1
WO2008120418A1 PCT/JP2007/073308 JP2007073308W WO2008120418A1 WO 2008120418 A1 WO2008120418 A1 WO 2008120418A1 JP 2007073308 W JP2007073308 W JP 2007073308W WO 2008120418 A1 WO2008120418 A1 WO 2008120418A1
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WO
WIPO (PCT)
Prior art keywords
electrode
semiconductor device
source
drain
gate
Prior art date
Application number
PCT/JP2007/073308
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English (en)
French (fr)
Inventor
Kazutaka Takagi
Original Assignee
Kabushiki Kaisha Toshiba
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Priority to US12/514,933 priority Critical patent/US8278685B2/en
Priority to KR1020097008283A priority patent/KR101156779B1/ko
Priority to EP07832928A priority patent/EP2133909A4/en
Publication of WO2008120418A1 publication Critical patent/WO2008120418A1/ja

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/095Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

 接地インダクタンスを低減化した半導体装置およびその製造方法。  半絶縁性基板11の第1表面に配置され,複数のフィンガーを有するゲート電極、ソース電極およびドレイン電極と、第1表面とは反対側の第2表面に配置された接地導体26と、ゲート電極、ソース電極およびドレイン電極ごとに複数のフィンガーをそれぞれ束ねて形成したゲート端子電極14、ソース端子電極18およびドレイン端子電極12と、ゲート電極、ソース電極およびドレイン電極の下部の半絶縁性基板11上に形成された動作層と、第1表面近傍の小口径VIAホール30と第2表面近傍の大口径VIAホール20とからなる多段VIAホールと、多段VIAホールの内壁面および第2表面に形成され、ソース端子電極18に対して第2表面側の接地導体から接続された接地電極23とを備える半導体装置およびその製造方法。
PCT/JP2007/073308 2007-04-02 2007-12-03 半導体装置およびその製造方法 WO2008120418A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/514,933 US8278685B2 (en) 2007-04-02 2007-12-03 Semiconductor device used with high frequency band
KR1020097008283A KR101156779B1 (ko) 2007-04-02 2007-12-03 반도체 장치 및 그 제조 방법
EP07832928A EP2133909A4 (en) 2007-04-02 2007-12-03 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-096851 2007-04-02
JP2007096851A JP5100185B2 (ja) 2007-04-02 2007-04-02 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
WO2008120418A1 true WO2008120418A1 (ja) 2008-10-09

Family

ID=39808006

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/073308 WO2008120418A1 (ja) 2007-04-02 2007-12-03 半導体装置およびその製造方法

Country Status (6)

Country Link
US (1) US8278685B2 (ja)
EP (1) EP2133909A4 (ja)
JP (1) JP5100185B2 (ja)
KR (1) KR101156779B1 (ja)
TW (1) TWI385788B (ja)
WO (1) WO2008120418A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010068872A1 (en) * 2008-12-12 2010-06-17 Qualcomm Incorporated Via first plus via last technique for ic interconnect
CN106847679A (zh) * 2015-10-09 2017-06-13 英飞凌科技股份有限公司 通过去除非晶化的部分来制造碳化硅半导体器件的方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8143654B1 (en) * 2008-01-16 2012-03-27 Triquint Semiconductor, Inc. Monolithic microwave integrated circuit with diamond layer
US20110018013A1 (en) * 2009-07-21 2011-01-27 Koninklijke Philips Electronics N.V. Thin-film flip-chip series connected leds
JP5631607B2 (ja) * 2009-08-21 2014-11-26 株式会社東芝 マルチチップモジュール構造を有する高周波回路
CN102263192B (zh) * 2010-05-31 2016-02-03 精材科技股份有限公司 发光二极管次基板、发光二极管封装及其制造方法
JP5649357B2 (ja) * 2010-07-30 2015-01-07 住友電工デバイス・イノベーション株式会社 半導体装置及び製造方法
JP5760394B2 (ja) * 2010-11-05 2015-08-12 三菱電機株式会社 ビアホールの製造方法およびビアホールを有する半導体素子の製造方法
US8853857B2 (en) 2011-05-05 2014-10-07 International Business Machines Corporation 3-D integration using multi stage vias
KR101813180B1 (ko) * 2011-06-28 2017-12-29 삼성전자주식회사 고 전자 이동도 트랜지스터 및 그 제조방법
WO2013136422A1 (ja) * 2012-03-12 2013-09-19 三菱電機株式会社 太陽電池セルの製造方法
KR101988893B1 (ko) 2012-12-12 2019-09-30 한국전자통신연구원 반도체 소자 및 이를 제조하는 방법
US10672877B2 (en) * 2018-02-06 2020-06-02 Integrated Device Technology, Inc. Method of boosting RON*COFF performance
US10629526B1 (en) 2018-10-11 2020-04-21 Nxp Usa, Inc. Transistor with non-circular via connections in two orientations
JP2021052025A (ja) * 2019-09-20 2021-04-01 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置
US11356070B2 (en) 2020-06-01 2022-06-07 Wolfspeed, Inc. RF amplifiers having shielded transmission line structures
US11670605B2 (en) 2020-04-03 2023-06-06 Wolfspeed, Inc. RF amplifier devices including interconnect structures and methods of manufacturing
US11837457B2 (en) * 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers
US20240096968A1 (en) * 2021-02-17 2024-03-21 Mitsubishi Electric Corporation Nitride semiconductor device and method for manufacturing nitride semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62211962A (ja) * 1986-03-12 1987-09-17 Fujitsu Ltd 高周波半導体装置の製造方法
JPS63278368A (ja) * 1987-05-11 1988-11-16 Nec Corp 半導体基板のバイアホ−ル形成方法
JPH02307219A (ja) * 1989-05-23 1990-12-20 Oki Electric Ind Co Ltd 半導体素子の電極の製造方法
JPH06326064A (ja) * 1993-05-14 1994-11-25 Nec Corp 半導体装置及びその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07118619B2 (ja) 1989-04-27 1995-12-18 三菱電機株式会社 抵抗帰還型増幅器
JPH06310547A (ja) * 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5343071A (en) 1993-04-28 1994-08-30 Raytheon Company Semiconductor structures having dual surface via holes
JP2001028425A (ja) * 1999-07-15 2001-01-30 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2002026270A (ja) * 2000-07-10 2002-01-25 Nec Corp 半導体装置の製造方法
JP2002217194A (ja) * 2001-01-15 2002-08-02 Hitachi Ltd 半導体装置
JP2003078127A (ja) * 2001-08-31 2003-03-14 Kyocera Corp 半導体装置およびその製造方法
US7378342B2 (en) 2004-08-27 2008-05-27 Micron Technology, Inc. Methods for forming vias varying lateral dimensions
EP1693891B1 (en) * 2005-01-31 2019-07-31 IMEC vzw Method of manufacturing a semiconductor device
JP4821214B2 (ja) * 2005-08-26 2011-11-24 三菱電機株式会社 カスコード接続回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62211962A (ja) * 1986-03-12 1987-09-17 Fujitsu Ltd 高周波半導体装置の製造方法
JPS63278368A (ja) * 1987-05-11 1988-11-16 Nec Corp 半導体基板のバイアホ−ル形成方法
JPH02307219A (ja) * 1989-05-23 1990-12-20 Oki Electric Ind Co Ltd 半導体素子の電極の製造方法
JPH06326064A (ja) * 1993-05-14 1994-11-25 Nec Corp 半導体装置及びその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2133909A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010068872A1 (en) * 2008-12-12 2010-06-17 Qualcomm Incorporated Via first plus via last technique for ic interconnect
US7939926B2 (en) 2008-12-12 2011-05-10 Qualcomm Incorporated Via first plus via last technique for IC interconnects
US7985620B2 (en) 2008-12-12 2011-07-26 Qualcomm Incorporated Method of fabricating via first plus via last IC interconnect
US8076768B2 (en) 2008-12-12 2011-12-13 Qualcomm Incorporated IC interconnect
CN106847679A (zh) * 2015-10-09 2017-06-13 英飞凌科技股份有限公司 通过去除非晶化的部分来制造碳化硅半导体器件的方法

Also Published As

Publication number Publication date
KR101156779B1 (ko) 2012-06-18
US20100059791A1 (en) 2010-03-11
US8278685B2 (en) 2012-10-02
TW200841455A (en) 2008-10-16
EP2133909A4 (en) 2011-03-16
KR20090084825A (ko) 2009-08-05
JP2008258281A (ja) 2008-10-23
EP2133909A1 (en) 2009-12-16
JP5100185B2 (ja) 2012-12-19
TWI385788B (zh) 2013-02-11

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