WO2008114434A1 - 実装基板及びその製造方法と半導体装置及びその製造方法 - Google Patents

実装基板及びその製造方法と半導体装置及びその製造方法 Download PDF

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Publication number
WO2008114434A1
WO2008114434A1 PCT/JP2007/055730 JP2007055730W WO2008114434A1 WO 2008114434 A1 WO2008114434 A1 WO 2008114434A1 JP 2007055730 W JP2007055730 W JP 2007055730W WO 2008114434 A1 WO2008114434 A1 WO 2008114434A1
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Prior art keywords
producing
same
connection
semiconductor device
electrode
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PCT/JP2007/055730
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English (en)
French (fr)
Inventor
Toshiya Akamatsu
Daisuke Mizutani
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Fujitsu Limited
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Priority to PCT/JP2007/055730 priority Critical patent/WO2008114434A1/ja
Publication of WO2008114434A1 publication Critical patent/WO2008114434A1/ja

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Abstract

　バンプ接合構造を有する実装基板を備えた半導体装置において、基板１の上方に形成され且つ突起電極１７が接続される接続電極８と、他の突起電極１７の接続領域から分離されて且つ少なくとも接続電極８の下に孤立パターンとして形成される応力緩和層４と、応力緩和層４の下の配線２と第１接続電極８を接続する接続導電層７と、応力緩和層４の周囲に形成される隙間５と、突起電極１７に電気的に接続される半導体チップ１５を有する。
PCT/JP2007/055730 2007-03-20 2007-03-20 実装基板及びその製造方法と半導体装置及びその製造方法 WO2008114434A1 (ja)

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PCT/JP2007/055730 WO2008114434A1 (ja) 2007-03-20 2007-03-20 実装基板及びその製造方法と半導体装置及びその製造方法

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PCT/JP2007/055730 WO2008114434A1 (ja) 2007-03-20 2007-03-20 実装基板及びその製造方法と半導体装置及びその製造方法

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WO2008114434A1 true WO2008114434A1 (ja) 2008-09-25

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199406A (ja) * 2009-02-26 2010-09-09 Nec Corp 配線基板、配線基板の製造方法及び半導体装置実装構造
WO2010106703A1 (ja) 2009-03-19 2010-09-23 富士通株式会社 半導体装置とその製造方法、電子装置、及び電子部品
WO2012131807A1 (en) * 2011-03-25 2012-10-04 Kabushiki Kaisha Toshiba Light emitting device, light emitting module, and method for manufacturing light emitting device
EP2768293A1 (de) * 2013-02-15 2014-08-20 Automotive Lighting Reutlingen GmbH Leiterplatte für elektrische Schaltungen
WO2018104090A1 (de) * 2016-12-08 2018-06-14 Conti Temic Microelectronic Gmbh Leiterplattenaufbau zur reduzierung des mechanischen stresses
WO2023176238A1 (ja) * 2022-03-15 2023-09-21 株式会社村田製作所 配線基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154672A (ja) * 1997-08-06 1999-02-26 Matsushita Electric Ind Co Ltd 電子部品および電子部品の製造方法ならびに電子部品の実装構造
JPH11186335A (ja) * 1997-12-25 1999-07-09 Hitachi Ltd 回路基板とその製造方法及びこれを用いた電子機器
JP2000277923A (ja) * 1999-03-29 2000-10-06 Nec Corp マザーボードプリント配線板およびその製造方法
JP2004079721A (ja) * 2002-08-15 2004-03-11 Nec Corp 半導体装置とその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154672A (ja) * 1997-08-06 1999-02-26 Matsushita Electric Ind Co Ltd 電子部品および電子部品の製造方法ならびに電子部品の実装構造
JPH11186335A (ja) * 1997-12-25 1999-07-09 Hitachi Ltd 回路基板とその製造方法及びこれを用いた電子機器
JP2000277923A (ja) * 1999-03-29 2000-10-06 Nec Corp マザーボードプリント配線板およびその製造方法
JP2004079721A (ja) * 2002-08-15 2004-03-11 Nec Corp 半導体装置とその製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199406A (ja) * 2009-02-26 2010-09-09 Nec Corp 配線基板、配線基板の製造方法及び半導体装置実装構造
WO2010106703A1 (ja) 2009-03-19 2010-09-23 富士通株式会社 半導体装置とその製造方法、電子装置、及び電子部品
US9318425B2 (en) 2009-03-19 2016-04-19 Fujitsu Limited Semiconductor device
US9565755B2 (en) 2009-03-19 2017-02-07 Fujitsu Limited Electronic component
US9585246B2 (en) 2009-03-19 2017-02-28 Fujitsu Limited Electronic device
WO2012131807A1 (en) * 2011-03-25 2012-10-04 Kabushiki Kaisha Toshiba Light emitting device, light emitting module, and method for manufacturing light emitting device
US8946738B2 (en) 2011-03-25 2015-02-03 Kabushiki Kaisha Toshiba Light emitting device, light emitting module, and method for manufacturing light emitting device
EP2768293A1 (de) * 2013-02-15 2014-08-20 Automotive Lighting Reutlingen GmbH Leiterplatte für elektrische Schaltungen
WO2018104090A1 (de) * 2016-12-08 2018-06-14 Conti Temic Microelectronic Gmbh Leiterplattenaufbau zur reduzierung des mechanischen stresses
WO2023176238A1 (ja) * 2022-03-15 2023-09-21 株式会社村田製作所 配線基板

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