WO2008104958A2

WO2008104958A2 - Data recovery system and method

Info

Publication number: WO2008104958A2
Application number: PCT/IB2008/050741
Authority: WO
Inventors: Jingwen Mao; Volker Meyer; Tao Wang
Original assignee: Nxp B.V.
Priority date: 2007-03-01
Filing date: 2008-02-29
Publication date: 2008-09-04
Also published as: WO2008104958A3

Abstract

A data recovery circuit has a delay locked loop circuit (22) for providing clock recovery from an input and generating a multi-phase clock signal (44). This is used to sample input data. A phase locked loop circuit (24) generates an output clock (50), and this is used to clock the output data. The data recovery circuit architecture uses both DLL and PLL circuits and takes advantage of the positive features of both PLL and DLL circuits, to provide correct sampling of received data as well as filtering out any phase jitter in the recovered clock signal.

Description

DESCRIPTION

DATA RECOVERY SYSTEM AND METHOD

This invention relates to a data recovery system and method, in particular for digital data recovery.

There is an ever-increasing use of digital data transmission and recovery. Digital signals are less susceptible than analogue signals to noise and are compatible with the rapid advancements in digital technologies and digital signal processing techniques. Digitally encoded speech, for example, can be transmitted over a long distance with almost no degradation in signal quality. Digital data recovery systems have wide applications.

In some data transmission systems, data and timing references are transmitted. At the receiving end, clock signals are recovered from the timing reference, and the edges of the recovered clock signal are used to sample the received data to determine the data values.

An ideal data recovery circuit should be able to sample the input data correctly, and it should also be able to filter any jitter (in the amplitude, frequency or phase of successive cycles) in the input data and clock signals and send clean signals to succeeding data processing blocks.

One standard data recovery circuit employs a phase-locked loop (PLL). This is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input ("reference") signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase.

Figure 1 shows one standard circuit implementation of a PLL for recovering a clock signal from an input signal Fin. A phase detector 2 compares the input signal Fin with a feedback signal, and generates an output which depends on the phase difference between the two inputs. This output is filtered by filter 4 and provided to a voltage controlled oscillator 6. If the inputs differ in frequency, a periodic output is obtained at the difference frequency. This signal causes the voltage controlled oscillator 6 to alter its output until it has locked to the input frequency. The filtered phase detector signal is then a dc signal. The divide by N counter 8 enables the output to be clocked at a multiple of the input frequency, but the counter can of course be omitted for applications in which the output frequency is simply a recovered clock signal from the input signal.

This type of mechanism is widely used in radio, telecommunications, computers and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. PLL circuits are widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to many gigahertz.

A delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal oscillator. A DLL can be used to change the phase of a clock signal, usually to enhance the timing characteristics of integrated circuits (such as DRAM devices). DLLs can also be used for clock recovery.

A DLL compares the phase of one of its outputs to the input clock to generate an error signal which is then integrated and fed back as the control to all of the delay elements. The integration allows the error to go to zero while keeping the control signal, and thus the delays, where they need to be for phase lock. Since the control signal directly impacts the phase this is all that is required. A DLL uses a first order feedback system, which is significantly easier to stabilize than the feedback system used in a PLL. This is a major advantage of DLLs.

The main component of a DLL is a delay chain composed of many delay gates connected back-to-back. The input of the chain (and thus of the DLL) is connected to the clock that is to be negatively delayed. The output of the DLL is the resulting, negatively delayed clock signal. The phase shift can be specified either in constant terms (in delay chain gate units), or as a proportion of the clock period, or both.

Figure 2 shows in simplified form this known type of charge pump DLL circuit. A series of delay elements 10 provides a voltage controlled delay line (VCDL). The input signal Fin and output signal Fdelayed are applied to a phase detector 12. The output of the phase detector 12 controls a drive circuit

14 which drives the delay elements 10 (via a low pass filter 16).

The different delay points provide a multi-phase signal derived from the input signal, with phase numbers 0 to n+1 , as shown. Although not shown in Figure 2, the control of each delay element can use a multiplexer connected to each stage of the delay chain, with the control selector for the multiplexers automatically updated by a control circuit to produce the negative delay effect.

Both PLLs and DLLs can be used as a clock generator at the receiving end of a system to recover the clock signals. However, these systems are not suitable to be used in applications where there is a strong phase modulation on the input signals.

For a PLL, if it is used to sample input data with strong phase modulation, the loop bandwidth should be made as large as possible. This is sometimes unpractical due to stability considerations.

For a DLL, it is able to sample the input data, but the output clock signal still has phase jitter. If the data and clock signals from a DLL circuit are sent to succeeding digital processing blocks, the digital part may fail due to the very large jitter.

According to the invention, there is provided a data recovery circuit, comprising: a delay locked loop circuit for providing clock recovery from an input and generating a multi-phase clock signal; a data sampler for sampling input data using the recovered multi-phase clock signal; a phase locked loop circuit, the phase locked loop circuit generating an output clock; and a data output circuit providing output data clocked using the output clock from the phase locked loop circuit. The invention thus provides a data recovery circuit architecture which uses both DLL and PLL circuits. This invention takes advantage of the positive features of both PLL and DLL circuits, and enables correct sampling of the received data using a DLL-recovered clock signal, as well as filtering out any phase jitter in the recovered clock signal by generating a PLL-recovered output clock signal.

The PLL filters the jitter in the input data and clock so that subsequent baseband processing of the signal is facilitated.

The architecture of the invention is thus composed of two stages; a DLL stage and a PLL stage. These DLL and PLL circuits can be conventional, and the circuit provides a data recovery circuit essentially of a DLL and PLL circuit in series.

The phase locked loop circuit can generate the output clock from the input clock or from a recovered clock signal from the delay locked loop circuit.

Preferably, the data sampler comprises a serial to parallel converter, so that the first stage of the circuit consists of a DLL circuit and a serial to parallel converter circuit. This implements the required serial to parallel conversion from a clocked serial input stream to a parallel data format for IC data processing.

The data output circuit preferably comprises a synchronisation circuit, so that the second stage consists of a PLL circuit and a synchronization circuit.

The first stage can sample and deserialize input data correctly even when there is a strong modulation on the input data. The second stage can filter out noise to a very low value to provide clean data and clock signals to succeeding data processing blocks. The invention also provides a method of generating output data and a recovered clock, comprising: using a delay locked loop circuit to provide clock recovery from an input clock to obtain a recovered multi-phase clock signal; sampling input data using the recovered multi-phase clock signal; using a phase locked loop circuit to generate an output clock; and providing the sampled input data as output data, and clocked using the output clock from the phase locked loop circuit.

The invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows a known PLL circuit;

Figure 2 shows a known DLL circuit; Figure 3 shows the data recovery circuit of the invention; Figure 4 shows the timing of operation of the circuit of Figure 3; and Figure 5 shows the method of data and clock recovery of the invention.

As shown in Figure 3, the data recovery circuit 20 of the invention has two stages. The first stage consists of a DLL circuit 22 and a serial to parallel block circuit 21. The second stage consists of a PLL circuit 24 and a synchronization circuit 23. The first stage can sample and deserialize the input data correctly even there is a strong modulation on the input data. The second stage can filter out noise to a very low value to provide clean data and clock signals to succeeding blocks.

The input data to the circuit is in serial form. Assuming a data stream of

N bits, corresponding to the width of a parallel data bus used in the circuit, this data is applied to the serial to parallel converter circuit 21. The input clock is applied to the DLL circuit 22 to generate N pulses of output clock signal with precise timing.

The N output clock pulses are applied to the converter circuit 21 to sample the N bits of data. The converter circuit 21 transforms the sampled N bits of serial data to a parallel data word.

The output of the converter circuit 21 is applied to the synchronization circuit 23. The input clock is also applied to the PLL circuit 24. The PLL circuit 24 generates the same output phase as the input clock. The PLL circuit filters out phase jitter in the input clock, and can generate a cleaner clock signal with less phase jitter. The bandwidth of the PLL circuit 24 can be selected to be narrow, so as to attenuate the output jitter. The output clock of PLL circuit 24 forms the output of the data recovery circuit and is also applied to the synchronization circuit 23 to synchronize the output data of the serial to parallel converter circuit 21. The synchronization circuit 23 and PLL circuit 24 thus generate the output data and output clock with small jitter.

Figure 4 is a timing diagram to illustrate the operation of the circuit of Figure 3.

The input clock signal is shown as 40, and the timing of the serial input data is shown in plot 42. The serial to parallel converter 21 is clocked using the multi-phase output clock from the DLL circuit, shown as phases 0 to 6 in plots 44.

The output of the serial to parallel converter 21 is shown as plots 46.

During one input clock phase, a seven bit parallel word is obtained, corresponding to the seven phases (phases 0 to 6). This parallel word is provided as output data (plot 48) under the timing of the output clock (plot 50) which is obtained by the PLL clock recovery circuit 24.

The circuit thus combines data sampling with timing derived from the DLL recovered clock, but provides an output clock and output data timing based on a PLL recovered clock. The method of data and clock recovery is shown in Figure 5. The DLL clock recovery is shown as 60, and this produces the multi-phase clock signal used to sample the input data in step 62.

The input clock is also provided to the PLL for PLL clock recovery in step 64. The input data sampled by the DLL-recovered clock is provided as output data but timed by the PLL-recovered clock, in step 66. The PLL- recovered clock is also output as the output clock in step 68. A clock recovery circuit receives a serial data stream, whereas data processing on an IC is typically based on parallel data streams. The circuit of the invention combines the clock recovery with the required serial to parallel data conversion. The invention can be applied in the receiver in data communications system, for example in an LCD panel timing controller IC. However, the invention is widely and generally applicable to the processing of serial data to provide accurately clocked output data and clock signals.

The PLL and DLL circuits may take many different forms, including the known basic circuits in Figures 1 and 2. These circuits have not been described in detail, as they will be well known to those skilled in the art. The invention generally takes advantage of the benefits of data sampling using a

DLL-recovered clock and data and clock output using a PLL-recovered clock.

The circuit of the invention can easily be implemented, for example in CMOS technology.

In the example above, the PLL circuit uses the input clock to derive the output clock, but it may instead use one of the phases of the DLL recovered clock.

Various modifications will be apparent to those skilled in the art.

Claims

1. A data recovery circuit, comprising: a delay locked loop circuit (22) for providing clock recovery from an input (40) and generating a multi-phase clock signal (44); a data sampler (21) for sampling input data using the recovered multiphase clock signal (44); a phase locked loop circuit (24), the phase locked loop circuit generating an output clock (50); and a data output circuit (23) providing output data clocked using the output clock (50) from the phase locked loop circuit (24).

2. A data recovery circuit as claimed in claim 1 , wherein the input clock is provided to the phase locked loop circuit (24).

3. A data recovery circuit as claimed in claim 1 , wherein a recovered clock signal from the delay locked loop circuit (22) is provided to the phase locked loop circuit (24),

4. A data recovery circuit as claimed in any preceding claim, wherein the data sampler comprises a serial to parallel converter (21).

5. A data recovery circuit as claimed in any preceding claim, wherein the data output circuit comprises a synchronisation circuit (23).

6. A method of generating output data and a recovered clock, comprising:

(60) using a delay locked loop circuit (22) to provide clock recovery from an input clock (40) to obtain a recovered multi-phase clock signal (44);

(62) sampling (21) input data using the recovered multi-phase clock signal (44); using a phase locked loop circuit (24) to generate (68) an output clock (50); and (66) providing the sampled input data as output data (48), and clocked using the output clock (50) from the phase locked loop circuit (24).

7u A method as claimed in claim 6, comprising providing the input clock to the phase locked loop circuit (24).

8. A method as claimed in claim 6, comprising providing a recovered clock signal from the delay locked loop circuit (22) to the phase locked loop circuit (24).

9. A method as claimed in claim 6, 7 or 8, wherein sampling the input data comprises performing serial to parallel conversion (21).