WO2008100227A1

WO2008100227A1 - Device, system and method using dual decision decoders for error correction in optical receivers

Info

Publication number: WO2008100227A1
Application number: PCT/SG2008/000050
Authority: WO
Inventors: Jian Chen; Yixin Wang; Chao Lu
Original assignee: Agency For Science, Technology And Research
Priority date: 2007-02-12
Filing date: 2008-02-12
Publication date: 2008-08-21

Abstract

Embodiments of the present invention provide an error correction device providing dual decision levels with internal dynamic decision level adjustments in an optical receiver, the error correction device comprising: a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; a counter for receiving and counting the plurality of ambiguous bits over a period of time; and a decision level adjuster for receiving a count of the plurality of ambiguous bits from the counter, and adjusting the first and second decision levels based on said count.

Description

DEVICE, SYSTEM AND METHOD USING DUAL DECISION DECODERS FOR ERROR CORRECTION IN OPTICAL RECEIVERS

FIELD OF INVENTION

Embodiments of the present invention provide a device, system, and method using dual decision decoders in optical data transmission systems to improve error correction capabilities.

BACKGROUND

Optical fiber communications systems are widely used to transmit data. A typical optical fiber communications system uses an optoelectronic transceiver to transmit and receive this data. An optoelectronic transceiver receives a plurality of bits in an electrical form and then transforms and transmits the bits in an optical form and/or receives a plurality of bits in an optical form and then transforms and transmits the bits in an electrical form.

In order to ensure effective communication between devices, there are various systems in place to ensure that the received data is relatively free from errors. One measure of the errors of such a system is the bit error rate (BER). The BER is a ratio of bits received, processed, and/or transmitted with errors to a total number of bits received, processed, and/or transmitted over a given period of time. If, for example, a transmission has 1 million bits and one of these bits is in error (e.g., a bit is in a first logic state instead of a second logic state), the transmission has a BER of 10^"6. For optical systems, the logic states are typically known as "1" or "0".

In a typical optical receiver, the receiver is configured as a "hard decider", which always decides whether the incoming signal is a "1" or "0" depending on whether the received power is higher or lower than a specified threshold. Various software related methods can also be used to further enhance the error detection and correction capabilities of simple systems. Such systems can use, among other techniques, correlated data reception and/or iterative calculation algorithms to enhance error correction capabilities. As transmission rates increase, the requirement to effectively identify and minimize bit and data error rates becomes even more important, as well as more difficult. Advanced modulation methods, such as differential phase shift keying (DPSK), and on-off-keying (OOK) are used to increase the data rates.

In recent years, a number of methods have been proposed to improve optical receiver data reception. One method uses a balanced receiver, which can achieve approximately a ~3 decibel (dB) sensitivity improvement using the DPSK format. Receivers with adaptive decision thresholds implemented by complicated error detection circuits were targeted to minimized the error probability by balancing the contribution from "1" and "0" codes. Various equalization methods have been applied to reduce the intersymbol interference that can be caused, for example, by filtering, chromatic dispersion (CD), polarization mode dispersion (PMD), etc. Recently, there have been a number of theoretical works published on adaptively alternating the receiver bandwidth or decision level to enhance the tolerance of optical receivers. However, these works still use the optical receiver as a single decision hard decoder.

As data speeds increase, different data encoding schemes have been developed in an attempt to enhance data transmission rates while reducing data error rates and associated overhead. One example of such an encoding scheme is Reed-Solomon (RS) code. RS code produces redundant information that gets concatenated with the signal to be transmitted. This additional information can then be used on the receive interface to help identify and correct transmission errors. The RS encoding was chosen because of its low complexity, relatively high error correction capability and low error burst sensitivity.

Previous systems sometimes use a technique known as forward error correction (FEC) to enhance the error correction capability. FEC is a system of error control for data transmission, whereby the sender adds redundant data to its messages, also known as an error correction code. This allows the receiver to detect and correct errors (within some bound) without the need to ask the sender for additional data. The advantage of forward error correction is that a back-channel is not required, or that retransmission of data can often be avoided, at the cost of higher bandwidth requirements on average. FEC can be used in situations where retransmissions are relatively costly or impossible. When applied to RS code, FEC can be used to separate the frame data into 16 data streams, where up to 8 errored bytes can be corrected per stream. The protocol uses one overhead byte and 238 data bytes to compute 16 parity bytes to form 255 byte blocks— the RS(255,239) algorithm.

In optical systems, RS(255,239) code is applied to obtain approximately 5.6 dB of coding gain. In these systems, the decision and FEC stages are independent. The use of a low-density parity check and turbo codes may also further improve receiver sensitivity. However, the data transmission rate for these optical systems is relatively low. Computation complexity, especially the iterative calculations required for turbo code, limits their application on bit rates over 10 Gb/s.

It would therefore be a great improvement in the art if a device, system, and method could be developed to enhance error detection/correction capability at higher data rates.

SUMMARY

One aspect of the present invention provides an error correction device providing dual decision levels with internal dynamic decision level adjustments in an optical receiver, the error correction device comprising: a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; a counter for receiving and counting the plurality of ambiguous bits over a period of time; and a decision level adjuster for receiving a count of the plurality of ambiguous bits from the counter, and adjusting the first and second decision levels based on said count.

In alternate embodiments, the error correction device of claim may further include a switch that provides an output signal from the device, the switch having a first and a second position, wherein the first output provides a control signal to the switch such that the output signal is the first decision output in the first position, and the output signal is the input signal containing the ambiguous data bits in the second position. Erasure decoding may be applied to the output signal. Forward error correction may also be applied to the output signal.

In alternate embodiments, the error correction device may provide for burst error correction. The device may be capable of operating at data speeds up to 40 gigabytes per second. The optical receiver may be an On-Off-Keying optical receiver. In other alternate embodiments, the decision level adjuster may provide dynamic adjustments of the first and second decision levels.

An alternate aspect of the present invention provides an error correction device providing dual decision levels with internal dynamic decision level adjustments in an optical receiver, the error correction device comprising: a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; a counter for receiving and counting the plurality of ambiguous bits over a period of time; and a switch that provides an output signal from the device, the switch having a first and a second position, wherein the first output provides a control signal to the switch such that the output signal is the first decision output in the first position, and the output signal is the input signal containing the ambiguous data bits in the second position. In alternate embodiments, erasure decoding may be applied to the output signal.

A further aspect of the present invention provides a method for providing internal dynamic decision level adjustments in an optical receiver to minimize an error rate, the method comprising the steps of: providing a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; providing a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; providing an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; providing a counter for receiving and counting the plurality of ambiguous bits over a period of time; providing a decision level adjuster; receiving a count of the plurality of ambiguous bits from the counter at the decision level adjuster; and adjusting the first and second decision levels based on said count to minimize said error rate.

In alternate embodiments, the adjusting step may include: determining an initial value for said first and second decision levels; determining an initial count using said initial values; incrementally increasing said initial values by a predetermined amount; determining an adjusted count; comparing said adjusted count to said initial count; if the adjusted count is greater than said initial count, decreasing said incrementally increased values in a next period by twice the predetermined amount;

If the adjusted count is less than said initial count, increasing said incrementally increased values in a next period by the predetermined amount; repeating said comparing step until said adjusted count increases for two consecutive periods; and averaging the values for said first decision level and said second decision level over a last two successive periods.

In other alternate embodiments the adjusting step may include: determining an initial value for said first and second decision levels; determining an initial count using said initial values; incrementally decreasing said initial values by a predetermined amount; determining an adjusted count; comparing said adjusted count to said initial count such that; if the adjusted count is less than said initial count, increasing said incrementally decreased values in a next period by twice the predetermined amount;

If the adjusted count is greater than said initial count, decreasing said incrementally decreased values in a next period by the predetermined amount; repeating said comparing step until said adjusted count increases for two consecutive periods; and averaging the values for said first decision level and said second decision level over a last two successive periods.

In some embodiments the increment may be in a range of a difference between the first and second decision levels divided by 100, and a difference of the first and second decision levels divided by 2. In alternate embodiments, the method may further include a step for providing a switch that provides an output signal from the device, the switch having a first and a second position, wherein the first output provides a control signal to the switch such that the output signal is the first decision output in the first position, and the output signal is the input signal containing the ambiguous data bits in the second position, after said step of providing the decision level adjuster.

In alternate embodiments, the method may further include applying erasure decoding to the output signal, and applying forward error correction to the output signal. The input signal may operate at data speeds up to 40 gigabytes per second.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which: Figure 1 illustrates a block diagram of one embodiment of an optical receiver with dual adaptive decision levels according to the present invention;

Figure 2 illustrates a circuit diagram of the decision stage circuits of the receiver of Figure 1 according to one embodiment of the present invention;

Figure 3 illustrates a graph of one embodiment of a dual decision level that can be used in the decision stage circuits of Figure 2;

Figure 4 illustrates a graph of a sliding decision level that can be used in the decision stage circuits of Figure 2;

Figure 5 provides a method flow chart illustrating one method of dynamically adjusting the dual decision levels using the decision stage circuits of Figure 2;

Figure 6 is a graph showing the relation between the input error probability and the output error probability under a standard or erasure decoding scheme for RS(255,239) code;

Figure 7 is a graph illustrating the output BER dependence on the position and separation of the dual decision levels for a system without an optical amplifier using the decision stage circuits of Figure 2;

Figure 8 is a graph illustrating the output BER dependence on the position and separation of the dual decision levels for a system with an optical amplifier using the decision stage circuits of Figure 2;

Figure 9 is a graph showing the variance of the decision thresholds d1 , d0 as Q varies, using the decision circuits of Figure 2; and

Figure 10 is a graph showing the relationship between PMD tolerance, optimal signal to noise ration (OSNR), and an optimal decision level obtained using the decision circuits of Figure 2. DETAILED DESCRIPTION

Figure 1 illustrates a block diagram of one embodiment of an optical receiver, designated generally as reference numeral 100, according to the present invention. The receiver 100 can receive input from a photodiode 101 , which passes a signal through a transimpedance amplifier 102 to a master amplifier 104 and a clock and data recovery (CDR) device 106 using various electrical connections, represented as reference numeral 108. It is understood that the drawing is provided as a general illustration only, and that many other electrical connections may exist between the components 101 , 102, 106, and 108. A dual threshold circuit 120 can be located within the CDR 106. The CDR 106 may also include a data out signal line 110, and a clock signal 112. In preferred embodiments, the receiver 100 is an On-OfT Keying (OOK) receiver. While the embodiment shown in Figure 1 provides the dual threshold circuit 120 within the CDR 106, it is understood that the dual threshold circuit 120 could be implemented as a separate component within the receiver 100.

Figure 2 illustrates one embodiment of a circuit diagram of the novel decision stage dual threshold circuit 120 of the receiver 100 of Figure 1. However, it is understood that the dual threshold circuit 120 may also be implemented as a separate component for use in unamplified optical systems. The dual threshold circuit 120 can include a first and second decision decoder 130, 140, respectively, that each feed an electrical signal into an XOR gate 150. The dual threshold circuit 120 can also include a counter 160, a decision level adjustment circuit 170, and a switch 180.

As illustrated in Figure 2, the dual threshold circuit 120 can receive an input signal 122 from the master amp 106. The input signal 122 may then be split into a first input signal 132 for first decision decoder 130, a second input signal 142 for second decision decoder 140, and a pass through signal 124 that is directed to one side 184 of the switch 180. A decision level c/1, illustrated with reference numeral 134, may also be input to the first decision decoder 130. Similarly, a decision level dθ, illustrated with reference numeral 144, may also be input to the first decision decoder 130. The decision decoder 130 provides an output signal 136. The output signal 136 is directed to an input of the XOR gate 150 and to an opposite side 182 of the switch 180. The output signal 146 is also directed to an input for the XOR gate 150.

Figure 3 provides a graphical illustration, designated generally as reference numeral 200, of one embodiment of a dual decision level that can be used in the decision stage circuits of Figure 2. Graph 200 provides a received signal level 202 on the "x" axis, and an error probability 204 on the "y" axis. In a perfect system, the output will always be either a logical "0", represented by line 206, or a logical "1", represented by line 208. However, due to various factors, including but not limited to, burst signal noise, optical drift in the received signal, chromatic dispersion (CD), polarization mode dispersion (PMD), fiber non-linearities, amplified spontaneous emissions (ASE), etc., perceived errors in the output will occur. In prior art systems, a single decision decoder providing a single decision level "D", illustrated with reference numeral 210, is used to determine erroneous or ambiguous bits. As discussed in the background section, this single decoder does not work well at higher data rates.

With continued reference to Figures 2 and 3, embodiments of the present invention use the dual decision decoders 130, 140, each having a respective decision level e/1 (134) and dO (144). These two close decision levels c/1 (134) and c/0 (144) can then be used for both optimal decision threshold tracking and the implementation of erasure decoding based on standard Reed Solomon RS(255,239) code, as will be described in more detail below. The XOR gate 150 output out2 188 indicates the bits whose levels fall in between c/1 134 and c/0 144. Those bits, which are called ambiguous or erasure bits, are counted using the counter 160 based on a clock signal 162, and cleared on a periodic basis using an input counter 164. The clock signal 162 may also be output to the clock 112 of the CDR 106. In some embodiments, the input counter 164 may clear the input based on the received bit rate. Other periods may also be used. In order to avoid an unnecessary bit error rate (BER) increase, it may be desirable that the decision levels c/1 134 and c/0 144 be as close as possible. This will be discussed in more detail below.

Figure 4 illustrates a graph, designated generally as reference numeral 250, of a sliding decision level that can be used in the decision stage circuits of Figure 2. The signal level 202, error probability 204, "0" line 206 and "1" line 208 are as identified above with respect to Figure 3. Depending on the various factors discussed above with respect to Figure 3, the ambiguous zone may "slide" to the left or right, as indicated by reference numerals 252, 254, respectively. This sliding indicates that the probability of the occurrence of errors is changing. The minimum probability is commensurate with the minimum error probability when the traditional single decision level 210 is the intersection point of the error probability functions for "1" and "0". Embodiments of the present invention can be used to determine the range between d1 and d0 that provide the optimized level preferable in designing and operating an optical receiver.

In order to optimize the receiver to minimize errors, the decision levels d1 and c/0 can be dynamically determined with respect to the incoming signal. There are two cases where the decision levels may be adjusted to optimize the error characteristics of the receiver 100. Firstly, an initial design for the application has not yet been optimized; secondly, the distribution of the error probability for "1" and "0" is changed because of some disturbance, such as the PMD effect. A specific application of the dual threshold circuit 120 to alleviate the PMD effect is discussed below with reference to Figure 10. The aggregated number of ambiguous symbols over a sufficiently long period can be used instead of the probability of occurrence to effect adaptive decision level searching. Such a definite period should be long enough to distinguish ambiguous symbols under different decision levels. If this period is too long, it could be difficult to effectively apply the dual threshold circuit 120 to suppress medium length error bursts. In some embodiments, the period may be identical to the period provided by the counter 164. It is understood that other periods may also be used.

Using the inputs 136, 146 from the two hard decision decoders 130, 140, the XOR gate 150 identifies the positions of ambiguous symbols. This logical information is output through an "out.₂" port 188. Simultaneously, this logical information can be used as a controlling signal of the switch 180, which either outputs the passed through the digital logic signal 136 through the "OUt₁" port 186 at position 0 (182), or the analogue level of the identified ambiguous symbols of the pass through signal 124 at position 1 (182). The "0" position 182 of the switch 180 is therefore used for normal output, whereas the "1" position 184 is used for the ambiguous symbols identified by the XOR gate 150. The ambiguous symbols require additional processing when an advanced FEC technique with erasure decoding is applied. However, the positions and level values of those ambiguous symbols are provided simultaneously, which greatly reduces the arithmetic burden of the successive circuits for erasure decoding. Recursive calculations can be avoided, thus making the technique particularly applicable to high speed (10 Gb/s or higher) applications.

The ambiguous bits that are output 154 from the XOR gate 150 are counted using the counter 160. They are converted from digital to analogue converted periodically so as to provide a reference for the decision level adjustment circuit 170. The "ctr" signal 164, which resets the counter periodically, has a period hundreds or thousands of times higher than the "elk" signal 162. The decision level adjustment circuit thus functions at a low cut-off frequency (10MHz~100 MHz). In this way, it is possible to avoid the complicated error detection circuit of traditional optical receivers, which works at a high cut-off f req uency.

The decision level adjustment circuit 170 uses the periodic input from the counter 160 to adjust the values of c/0 144, c/1 134, and or the spacing between c/0 144 and c/1 134. In preferred embodiments, the values of c/1 134, c/0 144 are adjusted without simultaneously adjusting the spacing between c/1 134 and c/0 144. However, at the "cold-start" of an optical receiver, it is suggested to optimize the values of c/1 134, c/0 144 first based on a pre-selected spacing provided by numerical optimization at the design stage. This spacing is discussed below with reference to Figures 7-9. Once the spacing is selected, generally as a percentage of the swing of the received signal, it can be kept unchanged during the optimization of c/1 134 and c/0 144.

Figure 5 illustrates one method, designated generally as reference numeral 300, for implementing the procedure of adaptive optimization of the dual decision levels of c/1 134 and c/0 144. In the beginning of one adaptive adjustment period, the method 300 includes a step of setting the initial values of c/1 134 and c/0 144, and determining an initial value of ambiguous symbols for a period, as represented by reference numeral 302. In a "cold-start" optical receiver 100, the width between the two decision levels may be tentatively chosen as 10% of the signal swing. It is understood that other widths may also be used. The next step is to incrementally increase the two decision levels 134, 144 by a small amount, and determine an adjusted count for the period, as represented by reference numeral 304. In some embodiments, the increment may be calculated as (d1-dO)/1OO. In alternate embodiments, an increment up to (c/1-dO)/2 may be used. It is understood that many other increments, both calculated and chosen, may also be used. In the next step, represented by reference numeral 306, at the end of the period, if the count of the aggregated ambiguous symbols increases, the decision levels 134, 144 should be decreased (increased) in the next period by twice the initial amount. If the aggregated count of the ambiguous symbols decreases, the levels 134, 144 should be increased (decreased) in the next period by the same amount. Step 306 is then repeated in the following periods until the count of the ambiguous symbols increases in two successive periods, as represented by reference numeral 308. .

The next step is to determine if the ambiguous symbol count has increased for two period in a row, as represented by reference numeral 308. If the answer is no, then step 306 is repeated. If the answer is yes, the final step, as indicated with reference numeral 310 is to average the respective decision levels 134, 144 on either the "0" or "1" side in the two successive periods to determine the optimum decision levels 134, 144. In some embodiments, the width between the two decision levels 134, 144 may also be adjusted, and the method 300 repeated to determine an optimum decision level 134, 144.

In some embodiments, the input from a forward error correction (FEC) device can be used to provide an estimation of the ambiguous bits. As discussed above, the switch 180, which is controlled with the output signal from out2 188, provides the signal level information for the erasure bits. The erasure bits are the same as the abovementioned ambiguous bits that are output from the XOR gate 150, and that are used for the decision level adjustment. The switch 180 output outλ 186 also provides a binary decision for non-erasure bits, which facilitates erasure decoding together with the erasure position information from out2 188. In such a way, erasure decoding can be implemented using the switch 180 without tedious iterative computations, which makes the high speed application of this method over 10 Gb/s possible. The performance of erasure decoding for standard Reed-Solomon code can be evaluated based on theoretical derivation. The output BER expression can then be expressed as Equation 1 below:

(1 )

where

(2) and

n n — i

Ks2 ^~ T + i / 2 n n — % T pi pj pn—t-j reS^rrS^rcS i = 0 j=jm2(i) n

(3)

with jmλ{i) = max(0, d - 2i) and jm2(i) = max{0, d - i + 1 ). The notations for the parameters in Equations 1-3 are based on symbols rather than bits because of the characteristic of Reed-Solomon code. In RS code, n is the codeword length of 255 for RS(255,239), and d is the minimum distance of 16 between codewords. P_e$ is the input symbol error probability, P_rS is the input symbol erasure probability and P_cs is the input correct symbol probability, respectively.

The capability of erasure decoding for Reed-Solomon code can be evaluated using output symbol error probability P_osi and P_oS2- When the error number / and erasure number j in a codeword satisfy 2/ + j ≤ d, all errors can be corrected, so that the output error probability is 0. Identifying more erasures instead of errors at the decision stage of an OOK receiver can enhance the error correction capability of the receiver 100. If there are more errors and erasures but / +j ≤ d, the nearest codeword is selected, which may at most cause d number of symbol errors with an overall probability of P_osi. When i+j > d, the decoder directly outputs the original codewords and randomly decides erasures into the resultant symbols with 1/2 of the decision error rate. In this case, the output error probability is P_oS2- To estimate the total BER of the output binary stream, we consider the different relationship between the symbol error rate (SER) and BER for P₀₅₁ and P₀₈₂.

Figure 6 is a graph, designated generally as reference numeral 400, showing the relation between the input error probability 402 and the output error probability 404 under a standard or erasure decoding scheme for RS(255,239) code. The graph 400 provides plots for a normal SER 406, a normal BER 408, an erasure SER 410, and an erasure BER 412. The graph 400 assumes that P_rS = 0 for standard decoding and P_eS = 0 for erasure decoding to show the error correction capability difference between the two schemes. As can be seen from the figure, if we leave part of 'errors' undecided at the decision stage of an optical receiver, and pass them as 'erasures' to the erasure decoder (switch 180), the overall error correction performance may be improved. The erasure bits passed to the erasure decoder include both errors with high probability and correct bits, because they are undecided by the decision stage in the proposed dual decision level receiver. The enhanced error correction capability of erasure decoding can be degraded by the inclusion of those correct bits, which might finally be decoded as error bits. Optimization of positions and the width of the two decision levels could thus minimize overall output error probability. In the traditional single decision level OOK receiver, its decision output BER is denoted by

Q = (/si " 'so)/(σi + σ₀) (4)

at the optimal decision threshold

l_d = (/S1_O0 + /soσi)/(σi + σ₀) (5)

under Gaussian assumption, where /^'si, /^'so are the average signal levels and σ-i, σ₀ are the standard deviations at "1" and "0" rails respectively. By using normalized parameters Ci = /^'so/'si and C₂ =

we can get Q = (1 -C₁K(I +c₂)-/_Si/σi (6)

and

/,Z = (C₁ + C₂)/(1+C₂)-/si. (7)

Now let us consider that the decision threshold l_d is split into two with /_d1 = X₁ l_d at the side of "1" and l_d0 = X₀I_d at the side of "0", where X₁ or X₀ is the ratio relative to l_d. In the output of the proposed dual-level decision stage, the bit erasure probability P_rb within the erasure zone between l_do and

is

and the BER, P_ebι of the partial decision outside the erasure zone is

(9)

Where

(10)

(11)

and

(13)

In the subsequent erasure decoder stage, the received signal 122 is processed based upon byte symbols rather than bits. To evaluate its performance by combining Formulas 1-3 with Formulas 8-13, the relationship between the input bit error/erasure probability PebiP_rb) and the symbol error/erasure probability P_es(P_rs), which depends on the signal channel characteristics and decoding policy, should be considered. If the transmitted signal undergoes continuous stochastic interference, errors/erasures occur as burst errors, and the neighboring bits are correlated. In this case, we can assume P_eS = Peb, Prs = Prb and P_cS = 1 - P_eS - P_rS-

When the transmitted signal is only affected by additive white noise from optical amplifiers and the detector, the neighboring bits are statistically independent and it depends on our decoding policy to determine the occurrence of symbol errors/erasures. In attempting to enhance the erasure decoding capability, we try to maximize the erasure symbol probability by considering that one symbol erasure encapsulates any number of bit erasures and that one error symbol has no erasure bit. In this way, the input bit/symbol probability relationship can be expressed as:

and

PeS = O - Prbf - 0 - Prb - Pebf (16) The derived output BER from the erasure decoder shows the implicit relation between the dual decision thresholds /_d1 and l_d0. In this case, the search for the optimized decision levels to provide a minimized output BER should be done numerically according to the method described above with reference to Figure 5.

Figures 7 and 8 illustrate the output BER dependence on the position and separation of the dual thresholds c/1 , cfO when burst errors dominate. The figures are drawn with the assumption that Q = 3 and the extinction ratio is infinite with C₁ = 0.

Figure 7 is a graph, designated generally with reference numeral 500, illustrating the output BER dependence on the position and separation of the dual thresholds d1 , d0 for a system without an optical amplifier. In such a system, it is given that C₂ = 1. The graph 500 shows the decision threshold at the "0" side in percent on the "x" axis, designated generally with reference numeral 502. The graph 500 shows the decision threshold at the "1" side in percent on the "y" axis, designated generally with reference numeral 504. Various output bit error rates are shown as a plurality of lines 506. As can be seen from Figure 7, for the situation described above, the optimized thresholds should be equally deviated from the traditional single threshold on either side by about ±11 %.

Figure 8 is a graph, designated generally with reference numeral 600, illustrating the output BER dependence on the position and separation of the dual thresholds d1 , d0 for a system using an optical amplifier. The graph 600 illustrates an amplified system with C₂ = 0.3. The graph 600 shows the decision threshold at the "0" side in percent on the "x" axis, designated generally with reference numeral 602. The graph 600 shows the decision threshold at the "1" side in percent on the "y" axis, designated generally with reference numeral 604. Various output bit error rates are shown as a plurality of lines 606. In the system illustrated by graph 600, the optimized thresholds are deviated unequally by +24.5% on the "1" side and -6% on the "0" side. The spacing between the two thresholds is thus approximately 7% relative to the signal swing.

In both cases shown in Figures 7 and 8, the output BER achieves a minimum value of 10^~12 with the same Q. This provides about 1.8 dB of Q value advantage compared with the traditional single threshold receiver using the standard RS(255,239) decoding method.

Figure 9 is a graph, designated generally with reference numeral 700 showing the variance of the decision thresholds c/1 , dQ as Q varies. The Q value is plotted on the "y" axis 702. The bit error rate is plotted on the left axis 704. The Threshold deviation in percent is plotted on the right axis 706. The BER versus Q is plotted as line 708. The value of (l_d1 /I_d) - 1 , expressed as a percent, is plotted as line 712, while the value of (l_d0 /l_d) - 1 , expressed as a percent is plotted as line 710. The graph 700 illustrates that fact that the two optimum thresholds c/1, c/0 discussed above are almost independent of a change in the Q value. It is thus not necessary to readjust the relative decision levels to adapt to the received optical power fluctuation, which simplifies the receiver circuit design. In presence of polarization mode dispersion, the proposed receiver can be adjusted to the increased threshold levels and then adapted to the optimal threshold spacing to successively enhance the performance of the erasure decoding method described.

As previously discussed, it can be difficult to provide PMD tolerance at higher data rates when using a fixed threshold receiver from the prior art. PMD effects occur in a time frame of milliseconds or longer. Figure 10 is a graph, designated generally as reference numeral 800, showing the relationship between PMD tolerance, optimal signal to noise ration (OSNR), and an optimal decision level obtained using the device and method of the disclosed embodiments. In the graph 800, the OSNR (dB) is plotted on the "x" axis 802. An optimal relative threshold in percent 804 is plotted on the left side of the graph 800, while a mean differentiate group delay (DGD)/bit interval in percent 806 is plotted on the right side. Line 808 is the Optimal relative threshold in percent. The situation in which there is no threshold adjustment is plotted as line 810, while the situation in which threshold adjustment is performed according to embodiments of the present invention is plotted as line 812. The graph 600 demonstrates that by increasing the optical signal-to- noise ratio (OSNR) and decision levels accordingly, the PMD tolerance can be effectively enhanced.

As discussed above, embodiments of the present invention provide for ambiguous bits estimation based on the input of the FEC device, instead of its output. The feedback signal for the decision level adjustment is not slow (10 MHz-100 MHz), especially for a "cold-start" optical receiver, because it works for a higher error rate of 10^"3~10^~4 before FEC. In the mean time, the difference of the two close levels is approximately around 10% of the range between the average "1" and "0". It is preferable that the difference be as narrow as possible so as to consider the trade-off between signal level resolution and the speed of adjustment. When applying advanced FEC with erasure decoding, the optimal width for better performance should be considered simultaneously.

Embodiments of the present invention provide several advantages over the prior art. The proposed dual decision level optical receiver is capable of tracking the optimal decision level adaptively. Simultaneously, it provides position and level information for erasure decoding to effectively enable advanced FEC. When the decision level and erasure decoding are optimized together, the performance of the optical receiver can be improved up to 1.6 dB.

The proposed invention provides a novel "ambiguous symbol counting" concept instead of the detecting and counting the occurrence of errors. The preferred decision level is thus adaptively tracked without regard to the cause of the errors and their statistical distribution. Embodiments of the present invention are easily adapted to optical wireless communications applications.

The present invention provides a dual decision level optical receiver that applies two close decision levels to monitor ambiguous bits instead of error bits upon reception. Compared with prior art, the application of these decision levels has the following advantages:

Transmitted signal quality monitoring is greatly simplified.

The dual decision decoder can automatically track the optimal decision level and ensure errors from "1" and "0" are balanced.

Simultaneously, it is possible to optimize the decision level of the optical receiver and enhance FEC capability.

Non-Gaussian error distribution is supported, regardless of the causes of the errors.

High speed applications, up to and even exceeding 40Gb/s can be achieved with acceptable error rates. It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.

Claims

CLAIMSWe Claim:

1. An error correction device providing dual decision levels with internal dynamic decision level adjustments in an optical receiver, the error correction device comprising: a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; a counter for receiving and counting the plurality of ambiguous bits over a period of time; and a decision level adjuster for receiving a count of the plurality of ambiguous bits from the counter, and adjusting the first and second decision levels based on said count.

2. The error correction device of claim 1 , further comprising a switch that provides an output signal from the device, the switch having a first and a second position, wherein the first output provides a control signal to the switch such that the output signal is the first decision output in the first position, and the output signal is the input signal containing the ambiguous data bits in the second position.

3. The error correction device of claim 2, wherein erasure decoding is applied to the output signal.

4. The error correction device of claims 2 or 3, wherein forward error correction is applied to the output signal.

5. The error correction device of any one of the previous claims, wherein the device provides burst error correction.

6. The error correction device of any one of the previous claims, wherein the device is capable of operating at data speeds up to 40 gigabytes per second.

7. The error correction device of any one of the previous claims, wherein the optical receiver is an On-Off-Keying optical receiver.

8. The error correction device of any one of the previous claims, wherein said decision level adjuster provides dynamic adjustments of the first and second decision levels.

9. An error correction device providing dual decision levels with internal dynamic decision level adjustments in an optical receiver, the error correction device comprising: a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; a counter for receiving and counting the plurality of ambiguous bits over a period of time; and a switch that provides an output signal from the device, the switch having a first and a second position, wherein the first output provides a control signal to the switch such that the output signal is the first decision output in the first position, and the output signal is the input signal containing the ambiguous data bits in the second position.

10. The error correction device of claim 9, wherein erasure decoding is applied to the output signal.

11. A method for providing internal dynamic decision level adjustments in an optical receiver to minimize an error rate, the method comprising the steps of: providing a first decision decoder capable of receiving an input signal and of providing a first decision output based on a first decision level; providing a second decision decoder capable of receiving the input signal and of providing a second decision output based on a second decision level; providing an XOR gate for receiving the first and second decision outputs, the XOR gate providing a first output of a plurality of ambiguous data bits; providing a counter for receiving and counting the plurality of ambiguous bits over a period of time; providing a decision level adjuster; receiving a count of the plurality of ambiguous bits from the counter at the decision level adjuster; and adjusting the first and second decision levels based on said count to minimize said error rate.

12. The method of claim 11 , wherein said adjusting step comprises: determining an initial value for said first and second decision levels; determining an initial count using said initial values; incrementally increasing said initial values by a predetermined amount; determining an adjusted count; comparing said adjusted count to said initial count; if the adjusted count is greater than said initial count, decreasing said incrementally increased values in a next period by twice the predetermined amount; If the adjusted count is less than said initial count, increasing said incrementally increased values in a next period by the predetermined amount; repeating said comparing step until said adjusted count increases for two consecutive periods; and averaging the values for said first decision level and said second decision level over a last two successive periods.

13. The method of claim 11 , wherein said adjusting step comprises: determining an initial value for said first and second decision levels; determining an initial count using said initial values; incrementally decreasing said initial values by a predetermined amount; determining an adjusted count; comparing said adjusted count to said initial count such that; if the adjusted count is less than said initial count, increasing said incrementally decreased values in a next period by twice the predetermined amount;

14. The method of claims 12 or 13, wherein said increment is in a range of a difference between the first and second decision levels divided by 100, and a difference of the first and second decision levels divided by 2.

15. The method of any one of claims 11-14, further comprising a step for providing a switch that provides an output signal from the device, the switch having a first and a second position, wherein the first output provides a control signal to the switch such that the output signal is the first decision output in the first position, and the output signal is the input signal containing the ambiguous data bits in the second position, after said step of providing the decision level adjuster.

16. The method of claim 15, further comprising applying erasure decoding to said output signal.

17. The method of claims 15 or 16, further comprising applying forward error correction to the output signal.

18. The method of any one of claims 11-17, wherein said input signal operates at data speeds up to 40 gigabytes per second.