WO2008073529A2

WO2008073529A2 - Integrated semiconductor and transition-metal oxide nanostructures and methods for preparing same

Info

Publication number: WO2008073529A2
Application number: PCT/US2007/074871
Authority: WO
Inventors: Jonathan E. Spanier; Stephen S. Nonnenmann; Rahul Sabu Joseph
Original assignee: Drexel University
Priority date: 2006-07-31
Filing date: 2007-07-31
Publication date: 2008-06-19
Also published as: WO2008073529A3

Abstract

This invention encompasses methods for the preparation of a series of nanostructures and nanostructured devices, as well as the devices prepared by this method. The innovation pertains to methods of materials synthesis for producing bottom-up nanostructures with integration of technologically important semiconductor materials (Si, SiGe, Ge, GaAs, GaN, CdSe and other group IV, III- V and II- VI) with a class of technologically important functional oxide materials known as transition metal oxides. The methods benefit from being inexpensive, robust, and controllable in terms of component composition, hierarchal design flexibility, and component thicknesses. The nanostructures produced by these methods have the added benefit of their transferability to other non-traditional substrates and/or platforms. The devices enabled by this method include semiconductor nanostructures that are enhanced by transition metal oxide components for non-volatile memories, nanoscale magnetoresistive spintronic devices, transistors, transducers, and single-molecule detectors. The bottom-up nanotechnology and scales approaching one-dimensional behavior translate to reduced fabrication cost and increased device performance.

Description

INTEGRATED SEMICONDUCTOR AND TRANSITION-METAL OXIDE NANOSTRUCTURES AND METHODS FOR PREPARING

SAME

BACKGROUND OF THE INVENTION

1. Statement of Government Interest

This invention was reduced to practice with Government support under Grant No. W911NF0410308 awarded by The U.S. Army Research Office; the Government is therefore entitled to certain rights to this invention.

2. Field of the Invention

The invention relates to the field of nanostructures. In particular the invention relates to using ferroelectrics in the preparation of integrated semiconductor and transition-metal oxide nanostructures.

3. Description of the Related Technology

The ongoing trend of miniaturization of devices demands an understanding of the effects of finite size and shape on electronic, optical, magnetic and mechanical properties of solids. While the controlled variation of these properties with finite size and shape and its application in materials and devices are central themes in nanoscience and nanotechnology, there is significant interest in developing chip-scale, silicon-based microsystems with high functional densities. Many of the processing methods associated with functional materials such as ferroelectrics are not generally compatible with established silicon fabrication and processing technologies, and relatively little has been accomplished in clearly elucidating the finite-size scaling of the properties of functional materials, particularly those of ferroelectrics. Integration of these materials with emerging nanostructure device platforms based on silicon would provide a new family of hybrid nanostructures having desirable functional densities with expanded sets of capabilities. Integration of these materials would permit the possible combination of electrical, mechanical, optical and other domains within individual logic, memory, sensing, actuation and signal processing to exist within individual nanostructures. The instant invention integrates this important class of materials with a platform of emerging importance in nanotechnology: nanowires grown by vapor- liquid-solid (VLS) methods. The idea of using the stable polarization states of ferroelectric ("FE") materials for non- volatile memory devices was identified shortly after the discovery of ferroelectricity in 1921, it has only been within recent years that significant material and device issues involving retention, fatigue and imprint have been overcome to permit the widespread commercialization and use of FE non- volatile memories in military, industrial and consumer sectors. Among the current state-of-the-art devices is a 1.3V, 64 Mbit, non- volatile embedded FE random access memory (eFRAM) device with a density of 1.13 Mb/mm. 128 Mbit devices are also being developed. As issues associated with scalability, assembly, connectivity and integration of bottom-up approaches to nanoelectronics are resolved (such as the use of nano wire-based crossbar arrays as address decoders for integrated nanosystems) and commercialization becomes more practical, it will become increasingly important to provide the unique functions, performances and capabilities associated with ferroelectric and smart materials in these and related bottom-up fabricated platforms.

Over the last ten years there has been tremendous growth in the library of single- crystal nanostructured elemental and binary materials produced by chemical synthesis methods. Controlled preparation of high-quality single-crystal ternary nanostructures, particularly single-crystal perovskite oxide nanostructures, has remained elusive. Recently, however, single crystal BaTiO₃ nanodots, nanowires and nanotubes have been synthesized, and these syntheses have been extended to produce SrTiO₃ nanodots, nanowires, nanotubes, PbTiO₃ and lead zirconate titanate (PZT) nanocrystals, and LαxBal-xMnO₃ nanocubes. These chemical synthesis routes involve the decomposition of a selected alkoxide precursor in the presence of a coordinating solvent, followed by nucleation and growth of nanostructures in inverse micelle arrangements, sol-gel syntheses, or hydrothermal methods. Larger nanostructures, such as polycrystalline nanotubes OfBaTiO₃, PbTiO₃, PZT and strontium bismuth tantalite having outer diameters as small as 20 nm have also been produced. These structures were prepared using commercially available polymeric precursors (sol-gel based) and porous alumina templates.

Nanostructured nonferroelectric piezoelectric materials such as ZnO have been prepared as nanowires, nanobelts and nanoribbons using vapor-liquid-solid growth processes. There has, however, been no evaluation of the piezoelectric properties of any nanostructures produced by bottom-up methods. There are numerous reports of top-down fabricated and sol- gel processed ferroelectric piezoelectric film-based device structures. One particularly interesting approach has involved the use of the technique of crystal ion slicing of the high performance, single-crystal relaxor ferroelectric lead zinc niobate-lead titanate (PZN-PT) to produce mesoscopic (about 1 μm) thin films for actuators in microfluidics.

The drive to further miniaturize microelectromechanical devices and systems well below the micron scale and to use new materials has led to an explosion in research and development activities in this area, providing opportunities for example, in high sensitivity detection of mass at the nanoscale, ultra-high frequency (RF) resonator elements, and elaborate systems for memory and computation based on microfluidics. In addition, piezoresistive cantilevers have been used for large arrays of data storage cantilevers, ultra- small high bandwidth devices, and biochemical mass sensing, such as DNA mass in microfluidic channels, because they can easily be adapted in areas where optical detection may be difficult to apply. There has been an increasing interest, however, in integration of these and other scaled device capabilities and functionality onto common platforms or within chip-scale microsystems in order to provide stand-alone systems that can operate at reduced power consumption, have enhanced portability, and/or can be deployed remotely.

There have been several developments in recent years with respect to meeting the challenges presented by the incompatibility of perovskite oxides and Si or Ge. Nevertheless, many important functional materials, particularly perovskite oxides involve growth and processing methods which have traditionally not been compatible with established silicon fabrication processing technologies. Notwithstanding, the emergence of semiconducting silicon nanowires produced by chemical vapor deposition (CVD) methods has opened significant new possibilities for electronics on a nanoscale. A device platform that takes advantage of the large body of knowledge of and experience with Si processing, as well as one that incorporates important, high-performance functional materials (such as ferroelectrics) would enable integration of important properties within individual nanostructures. The result would integrate silicon-based nanoelectronics with, e.g., non- volatile memory, mechanical sensing and actuation, and pyroelectric detection within individual nano wires. Further, the nanowire device platform opens the possibility of transfer of these nanostructures from substrates to solution, and then to other substrates- even non- conventional ones.

First order phase transitions, such as the ferroelectric (FE) phase transition, play a central role in the functional properties of materials. Detailed microscopic characterization of the first-order solid-solid transformation has been difficult because bulk measurements often obscure the crucial importance of the surface and defects. Recently, methods have been developed that produce high-quality single-crystal nanostructures. Experimental investigations of size-dependent scaling of phase transitions have yielded valuable insights into surface effects on the thermodynamic stability and the role of defects in determining the kinetic barrier. Most of the experiments to date have been performed on ensembles of nanocrystalline samples, however, and have been limited to specific model systems where the preparation of nanocrystals with uniform size distribution was possible.

Among these structural phase transitions, FE phase transitions of perovskite-based oxides have significant technological implications. FE materials play significant roles in a diverse number of important applications in both commercial and military sectors: electronics and photonics, ultrasonic medical imaging and diagnostics, telecommunications, and surveillance. Normal FE perovskites possess a spontaneous electric polarization that can be reoriented by an external electric field. For temperature greater than a critical temperature, Tc, these oxides undergo a polar-to-centrosymmetric structural transformation and lose their ferroelectricity. The size-dependent evolution of Tc dictates, in part, the ultimate size limit of FE nonvolatile memory and related devices. Previous studies, however, have yielded widely varying results on Tc evolution and its related properties due to difficulties of preparing high quality nanocrystalline samples, size dispersion in the samples, limitations of bulk experimental techniques at the nanoscale, or electrode effects in thin film devices. Despite intense activity in the research and development of the properties and applications of perovskite thin films, a clear understanding of the finite-size scaling of ferroelectricity and its related properties is only beginning to emerge. Such an understanding is related to the performance of FE devices as scales are progressively reduced; in addition, size-based control of phase diagrams may enable new process routes for materials growth. The potential benefits of reducing the scale of these advanced materials extend well beyond the realm of achieving a higher density of the associated devices. With the growing "toolbox" of inorganic crystalline nanostructured materials, the use of ferroelectric nanostructured materials in a manner that integrates their advanced functionality with an emerging nanostructured platform (nanowires) would provide new opportunities for multi-functionality within individual nanostructures.

With respect to experimental methods of probing nano-scaled ferroelectrics, a number of groups have studied the FE properties of thin films and the top-down-fabricated (etched) or otherwise fabricated slabs and islands as small as 75 nm in lateral size using scanning force, or piezoresponse force microscopy (PFM). In PFM, the dynamic and spatially resolved contact-mode deflection of the ferroelectric is collected in response to an ac voltage applied between the conductive tip (in contact with the top surface of the ferroelectric) and the underlying conductive substrate. While this technique is quite powerful in its ability to spatially resolve the normal and in-plane piezoelectric response in ferroelectric materials, signal-to-noise limitations make evaluation of the piezoelectric response and the identification of ferroelectric stability progressively more difficult for films below about 10 nm in thickness. Furthermore, the nominal radius of curvature of atomic force microscopy (AFM) tips, typically about 20 nm, also makes evaluation of narrower nanostructures challenging. To date, the smallest FE slabs that have been processed and studied are still one to two orders of magnitude larger than the smallest chemically synthesized nanostructures.

The direct materials integration of semiconductors and transition metal oxides facilitates fabrication, operation and commercialization of new types of semiconducting devices that benefit from the functions of selected transition metal oxide thin-film materials. These include, for example, ferroelectric and multiferroic materials for non-volatile memory using non-destructive read-out, silicon-compatible nonlinear optical devices and piezoelectric devices, and magnetic perovskites for colossal and giant magnetoresistive materials (CMR and GMR). With respect to down-scaling of devices, much progress has been made with fabricating a range of electronic devices in nanostructures produced by bottom-up methods: bipolar, metal-oxide-semiconductor, array decoders, shift registers, photodetectors, lasers and other devices and components have been conceived based on nanowires with axial and radial modulation of composition. To date, however, there have been no reports of the integration of technologically relevant semiconductors (Si, Ge, GaAs, GaN) with transition metal oxides in nanostructures produced by bottom-up synthesis methods. The advanced performance characteristics of nanomaterials and nanodevices opens new possibilities for technologies that have a smaller form factor, have higher performance, are able to integrate multiple functions, and are capable of being made on non-traditional platforms.

The current practice of nanowire devices does not include integration of the above- mentioned classes of materials. The current practice of thin film growth has recently addressed this, but the requirement for molecular beam epitaxy (MBE), or atomic layer deposition or epitaxy is expected to severely limit the availability of materials for further device development. Also, such top-down methods are not expected to produce so-called one-dimensional nanostructures that may have significant advantages in terms of reduced scattering and unique response of collective excitations to external perturbation.

Due to structural differences and lattice mismatches, the integration of transition metal oxides (e.g. binary oxides, perovskites, etc.) with elemental and binary semiconductors traditionally has not been possible. Within the last seven years, progress has been made in growing such film materials directly on a silicon surface using molecular beam epitaxy (MBE) in ultrahigh vacuum (UHV). Though this atomic layer-by-layer growth procedure provides a perfect registry between these oxide materials and silicon, it remains extremely expensive and is limited to laboratory research.

The combination of (a) a method of controlled preparation of ferroelectric nanostructures of arbitrary size/thickness, (b) with the possibility of preparing small enough nanostructures for finite-size effects to be realized, (c) and further with an architecture that enables logical integration with emerging nanostructured platform(s) has not, however, been accomplished to date.

SUMMARY OF THE INVENTION

Accordingly, it is an object of certain embodiments of the invention to provide a combination of (a) a method of controlled preparation of ferroelectric nanostructures of arbitrary size/thickness, (b) with the ability to prepare sufficiently small nanostructures for finite-size effects to be realized, and (c) with an architecture that enables logical integration with emerging nanostructured platforms.

Different bottom-up synthesis methods possess distinct advantages with respect to shape, shape anisotropy and structural control, process temperature, composition, hierarchal control, and/or compatibility with other processes. For example, solution-phase routes based on one or more surfactant-controlled homogeneous nucleation and growth stages permit flexible and dynamic control of surface chemistry during growth, and allow synthesis temperatures in which the use of multiple organics and their different coordination with different surfaces can promote and alter anisotropic growth in real time. Significantly, solution-phase routes offer the possibility of achieving superior control of nanocrystal size and size dispersion — to within one monolayer in some cases. However, vapor-phase methods enable superior shape anisotropy for realizing extremely long aspect ratio nanowires, and feature direct growth on substrates. With respect to vapor-liquid-solid (VLS)-grown nanowires, the ability to grow with axial modulation of composition or dopant in the form of multiple segments of different materials represents important design flexibility for a range of novel low-dimensional electronic and photonic devices. Such vapor-phase methods have also been used to produce branched nanostructures.

The invention provides a method of preparing devices that have integrated nanowire materials that contain both semi-conducting and transition metal oxide components for use in advanced electronic, photonic, and optoelectronic devices, sensors and actuators. The resulting integrated, co-axial nanostructures will enable fabrication of a range of new nanowire-based devices, including, but not limited to non-volatile memories, feπoelectric field-effect transistors, and single-monolayer-sensitivity detectors.

These and various other advantages and features of novelty that characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described a preferred embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 shows a schematic of a partially hollow core-shell nanowire structure consisting of a single semiconducting material core A, a highly doped semiconducting shell B, and a ferroelectric piezoelectric shell C.

FIGURE 2 shows electron-beam lithographically patterned metal electrodes as fabricated in the lab of the PI onto which semiconductor-ferroelectric core-shell nanowires (upper right inset) have been deposited using dielectrophoresis in the lab of the PI.

FIGURES 3(a)-3(b) show secondary and backscattered electron microscopy images from multi-segment metal Au and Ag segments electrodeposited within nano-scaled templates, respectively.

FIGURE 3(c) shows the structures of Figs. 3(a)-3(b) following a selective etching of the Ag segments, leaving shorter Au segments for seeding metal-catalyzed silicon nanowire growth.

FIGURE 3(d) shows the structures of Figs. 3(a)-3(b) following a selective etching of the template, revealing the chemical vapor deposition growth product of silicon nanowires within the ferroelectric shells which have been deposited on the pore walls.

FIGURE 3(e) shows a schematic of the resulting semiconductor-ferroelectric core- shell hybrid nanostructure. FIGURE 3(f) shows a representative long-integration time Raman scattering spectrum collected from an individual hybrid nanostrucrure shown in FIGURE 3(d); the appearance of observable Raman shift peaks are evidence of the presence of crystalline Si and PZT in these nanostructures. FIGURE 4(a) shows a topographic atomic force microscopy (AFM) image of a 12-nm diameter nanowire (scale bar is 1 μm).

FIGURES 4(b)-4(d) show successive electrostatic force microscopy (EFM) images demonstrating that nanowire polarizations along the length of the nanowire, perpendicular to the long axis of the nanowire, as denoted by the arrows. FIGURE 5(a) shows the experimentally determined evolution of T₀ versus diameter as probed in individual, single-crystalline BaTiO₃ nanowires in an ultrahigh vacuum environment; in the inset the data are plotted versus inverse diameter, confirming the expected inverse scaling law. Ferroelectricity is seen to be stable even in a 3-nm diameter nanowire at 300K. FIGURE 5(b) shows infrared transmission spectrum of nanowire ensemble collected in N₂ showing absorption peaks associated with molecular adsorbates.

FIGURE 6(a) shows ferroelectric hysteresis as measured in nanowire.

FIGURE 6(b) shows the stability of ferroelectric polarization in different nanowires in excess of one week. FIGURE 7(a) shows the calculated fully-relaxed BaTiO₃ structures for different molecular adsorbates as shown in the figure; the charge of the molecule (and in general, of the chemisorbed end group) is understood to influence the polarization direction, as denoted by the arrows.

FIGURE 7(b) shows the calculated polarization (normalized) as a function of position within the nanowire for different configurations as shown in the legend.

FIGURE 8 is a schematic of basic layout of core-shell semiconductor-ferroelectric field effect transistor.

FIGURE 9(a) shows a process of producing chemically functionalized and Au- nanoparticle coated and nanocones for investigations of local electric field enhancement. FIGURE 9(b) shows an SEM image of an individual Si nanocone coated with Au nanoparticles

FIGURE 9(c) shows Raman enhancement showing that the Raman scattering efficiency of a monolayer of PATP on Au nanoparticles near the tip of a Si nanocone (top trace) is measurably larger than even that for the molecules on Au particles on a planar substrate (bottom trace).

FIGURE 10 shows a schematic diagram of a single degenerately doped core- ferroelectric shell nanowire for use as a multi-element, non- volatile memory.

FIGURE 11 (a) shows the calculated Gibbs free energy change associated with the chemisorption of OH^" onto BaO(100)-terminated ultrathin film under the experimental vacuum and range of temperatures, indicating that molecules are stable on FE surfaces even in UHV. Figure 1 l(b) shows evolution of the internal FE polarization with film thickness.

FIGURE 12 shows a CMOS-based dielectrophoretic assembly and read out architecture for assembling large numbers of nanowires and for monitoring their states during landing and as individual device elements. Left: flow schematic; upper right: full array diagram; lower right: schematic of a single nanowire site.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

The present invention provides a method of preparing integrated nanostructures that contain both semi-conducting and transition metal oxide components for use in advanced electronic, photonic, and optoelectronic devices, sensors and actuators. The resulting integrated, co-axial nanostructures will enable fabrication of a range of new nano wire-based devices, including, but not limited to, non- volatile memories, ferroelectric field-effect transistors, and single-monolayer-sensitivity detectors. The method allows for a range of different semiconductor and transition metal oxide materials, thicknesses, compositions (e.g. doping), and axial and radial modulation thereof. The integrated nanostructures can be transferred to a variety of substrates, can be functionalized, and/or can be further integrated with other materials and devices. One of the useful features of the invention is that the native oxide, which typically forms on semiconductor surfaces (and nanowires), and which can significantly lower the effective electric field and degrade device performance, is not a factor.

Since the vapor-phase growth of most nanowire materials frequently requires a eutectic alloy nanodroplet melt, some bottom-up produced single-crystalline nanostructures having more complex chemistries (e.g. oxide perovskites) are more accessible via wet solution-based methods. Thus, the present synthesis methods which combine aspects of solution-phase and vapor-phase routes provide new pathways for the production of novel hybrid materials.

The methods of the invention can be used with a variety of materials. Such materials include LiNbO₃, and LaMnO₃ and other technologically relevant perovskites and skudderudites. Compatibility with core materials Ge, GaAs, GaN and other technologically relevant Group IV, III- V and II- VI materials is also achieved using the methods of the present invention. The present invention permits fabrication of nanocrystal heterostructures made of two or more nanocrystalline domains of different materials fused together.

A number of core-shell and core-multishell semiconductor nanodots and nanorods have been prepared using chemical synthesis methods, and recently, core-shell and core- multishell nanowires have been synthesized using chemical vapor deposition. Si-Si core-shell homoepitaxial nanowires, Ge-Si core-shell, and Si-Ge-Si core-shell nanowires have been grown. Furthermore coaxially-gated nanowire transistors based on a p-type Si core, and successive growth of concentric shells of intrinsic Ge, SiOx, and p-type Ge have been fabricated. In fabricating these devices, the feasibility of multilayer shell growth and selective electrical contact to the various shell layers has been demonstrated. Without optimizing the design and fabrication of the transistors, the performance of these transistors as (measured by their transconductance) was observed to be comparable to carbon nanotube FETs.

The instant invention builds upon previous successful work in the growth of the ferroelectric perovskites PbTiO₃ and PZT. In support of these and other related activities, a vapor-liquid-solid (VLS) nanowire growth system was constructed. The configuration enables the growth of Si, Ge and SiGe-alloy-based n and p-type nanowires with control of diameter, and of composition and doping in the axial direction.

Following growth of sets of degenerately doped n-type Si nanowire cores of arbitrary diameters, the substrates (with nanowires oriented normal to the substrate) are carefully removed from the furnace tube and placed in a metal organic chemical vapor deposition (MOCVD) reactor. Ultrathin layers of perovskite oxides are deposited on the nanowire cores using a specially designed flash evaporator precursor delivery system. The two-dimensional epitaxial growth of SrTiO₃ directly on Si(OOl) via molecular beam epitaxy and successful growth of epitaxial nanowire core-shell heteroj unctions suggests that it should be possible to produce high quality perovskite oxide shells directly on oxide-free Si nanowire cores.

The reactor used is a scaled-down and simplified version of a commercially available rotating disk system design. With a base pressure of 10^"3 torr, it is designed to be a relatively simple system for testing a variety of chemistries through a wide temperature range, requiring less pumping and less consumables. The following precursors for the MOCVD deposition of PbTiO₃ and PZT are used: Pb(thd)₂(OiPr)₂, Ti(thd)₂(OiPr)₂, Zr(thd)₂(OiPr)₂, where "thd" is 2,6 tetramethyl-3,5 heptanedionanate[(CH₃)₃CCOCH=COC(CH₃)₃] and OiPr is isopropoxide [OCH(CH₃)₂]₄. The nanoshell coating depositions were carried out at between 450-650 ⁰C, and at an operating pressure of aboutl 0-40 torr, with N₂ or Ar as a carrier gas. It is well known that the deposition of perovskite ferroelectrics such as PbTiO₃ or PZT directly on Si substrates can result in inter-diffusion of Si atoms into the PbTiO₃ or PZT, or of Pb atoms into the Si substrate, leading to degradation in device performance and/or failure. MOCVD deposited cerium manganese oxide (CMO) is an alternative to the conventional perovskite ferroelectrics for ferroelectric devices in cases where a stable ferroelectric-semiconductor interface without barrier or buffer layers is required. Data indicates that the CMO is indeed stable on Si substrates and demonstrates stable and reproducible ferroelectric hysteresis.

The MOCVD process for growing the FE shells may be accomplished within an enhanced nanowire growth system. Alternatively, the MOCVD system may be adapted to grow the semiconductor nanowire cores. The choice to grow the semiconductor cores and shells, and functional oxide shells in separate systems is judged to be a cost-effective and practical choice. Ultimately, it may be possible to grow complex nanostructures containing smart and/or ferroic components in several growth stages within the same system. The resulting MOCVD nanowire core-ferroic shell nanostructures are characterized using a number of techniques: the composition of the nanowire shells in particular are examined using SEM, EDS, TEM and XRD.

SEM, TEM and converging beam election diffraction (CBED) is utilized to image the structure and orientations of the overgrown films. Electron microscopy of the cross-section of the nanowires is used to determine shell thickness, and is used to probe the structure at the interface between the core and the shell, since diffusion of perovskite metal ions across the interface with Si is often an issue in thin film depositions. Raman microscopy is used to verify the phase, to examine the average strain state in the shells, and to evaluate possible effects of phonon confinement on Raman peak position and line shape.

Depending upon the structure and composition of the deposited shells, the nanostructures are annealed at high temperatures following the deposition in N₂ or Ar, in an oxidizing or in a reducing atmosphere. In addition, since it has been noted that an ensemble of larger diameter nanowires (>15 nm diameter) usually possess a majority of nanowires with the <111> orientation along their axes, whereas smaller diameter nanowires typically have the <110> direction along their axes, the availability of different ranges of nanowire diameters and corresponding nanowire orientations and surface structures may be an important consideration in the FE shell growth optimization and in selected device applications.

Another result of the process is the formation of hollow ferroelectric shells with or without interior, electrically accessible semiconducting or conducting shell layers extending beyond either or both ends of a semiconductor nanowire. A schematic drawing showing an example of one of the structures is shown in Fig. 1. Fig. 1 shows a schematic of a partially hollow core-shell nanowire structure consisting of a single semiconducting material core A, a highly doped semiconducting shell B, and a ferroelectric piezoelectric shell C. The core A has been selectively etched from one end with respect to the inner and outer shells B and C, leaving a hollow cylindrical capacitor C₂ and an inner shell contact B extending along the axis of the nanowire behind the dashed plane. Alternatively, core A may be grown with segments of different composition that can serve as an etch stop for the controlled removal of A and from one end only if desired. Exterior metallic contact(s) on C₂ may then be applied. Instead, the shell B may also be removed, leaving C₂ without an inner contact beyond the dashed plane. In this latter case, an electrode will be deposited on C₁ near the dashed plane.

Such structures may, for example, enable piezoelectric sensing or actuation in a nanostructure and enable integrated on-chip detection of acceleration or pressure. The surfaces of the piezoelectric nanostructures can be functionalized with molecular receptors, for example, to provide site-specific binding of proteins, enabling high-sensitivity detection of chemical or biological species via changes in the amplitude or phase of the vibration of the piezoelectric nanostructure.

Three approaches for fabrication of nanostructures may be employed within the scope of the present invention. The first approach involves the growth of a semiconducting core and single FE shell. The semiconductor core may be Si, Ge or SiGe. Following the growth of the shell layer, wet etchants, such as KOH or TMAH ((CH₃)₄NOH, H₂O), and mixtures of BPA (buffered HF, H₂O₂ and CH₃COOHn are used to partially etch the semiconductor cores composed of Si and SiGe (and in a selective manner with respect to the FE shells) from one or both ends, leaving nano wires with hollow piezoelectric shells near the ends of each of the wires.

The second approach is a refinement of the first approach, taking advantage of composition modulation along the long axes of the nano wires as a means of achieving better control of processing. Nanowire cores are grown with sharp changes in doping (i.e. intrinsic/n++) and/or composition (e.g. Si/SiGe) along the nanowire axis. Following the growth of FE shells, these relatively sharp changes (within about 10 monolayers) in doping or composition will serve as etch stops for the removal of semiconductor core material. Selectivity in wet etching of as much as 20:1 between Si and SiGe has been achieved using TMAH and BPA. The third approach involves the use of distinct semiconductor core and shell layers of different composition and/or doping, along with the exterior FE shell as before. One scheme involves the growth of a semiconductor core of composed of Si with a semiconductor shell (interior shell) consisting of SiGe. Another route is based on a Ge core and a highly doped Si shell. In these cases, selective etching is utilized to produce hollow cylindrical shells of ferroelectric piezoelectrics with interior (and exterior) contacts.

In the first and second approaches, ultrathin films are evaporated and patterned on the shells in the vicinity of the end of the etched core for electrical contact, and electrical contact to the degenerately doped semiconductor core is established elsewhere along the nanowire. With the application of AC voltages across one part of the shell, piezoelectric coupling of the field along a radial direction leads to strain both in that direction, as well as strain along the axis of the shell extending along the hollow portion, resulting in a bending displacement of the shell.

Evaluations of the piezoelectric response as a function of frequency using an AFM and associated electronics are then made. Discrete electrical contacts to the surfaces of the structures produced using the third approach are also made, enabling the formation of a nanocylindrical capacitor, with addressable contacts on the interior and exterior of the piezoelectric shells.

The above processes result in controlled growth of ferroelectric shells of a range of thicknesses on semiconducting nanowire cores of arbitrary diameters, lengths, dopant types and resistivities. In addition, structures consisting of hollow ferroelectric piezoelectric shells attached to semiconductor nanowires have been fabricated.

The FE and related properties of the semiconductor-core FE shell nanowire structures are probed using room temperature and variable-temperature scanning probe microscopy. In particular independent manipulation of nanoscale ferroelectric domains is demonstrated and ferroelectric hysteresis and retention within structures of arbitrary shell diameter and shell thickness are measured. In addition, Kelvin probe microscopy, electrostatic force microscopy (EFM) 2 ω response and piezoresponse force microscopy are also used to probe, the surface potential, dielectric permittivity, and piezoelectric properties of individual structures, including more detailed investigations of the hollow shell structures discussed above. Both a variable-temperature scanning probe microscope as well as Omicron ultrahigh vacuum (UHV) variable temperature scanning probe microscope are used.

In order to fabricate the device structures, selective etching of, and patterning of, core and shell layers are required. Selective wet etching, reactive ion etching, focused ion beam lithography, photolithography and electron beam lithography are used to extend demonstrations of selective electrical contact in core-shell nanowire structures, as shown in Figure 2.

Various synthetic routes allow for the controlled growth of specific classes of materials. Here, template-assisted alkoxide precursor chemistry, electrochemistry and metal- catalyzed CVD are leveraged to provide a robust solution to the challenge of producing semiconductor-ferroelectric core-shell nanostructures. Though the synthesis involves a number steps, it does provide for a high degree of controllability and adaptability of the compositions. The synthesis route involves growth of ferroelectric nanotubes using an alkoxide polymeric precursor in anodic aluminium oxide (AAO) templates. The tube growth is followed by back-side metal evaporation and subsequent electrodeposition of Ag and Au segments (Fig. 3(a)-(b)). When the Ag is selectively etched, short Au segments remain (Fig. 3(c)) and serve as sites for catalytic decomposition of, e.g. SiH₄, and growth of undoped or P- or B-doped Si nanowires through the ferroelectric shells. Following this, the AAO templates are selectively etched, leaving core-shell nanostructures (Fig. 3(d)). A schematic of the resulting structure is shown in Fig. 3(e). This method offers a number of advantages including a more straightforward contact to the nanowire core. As confirmed by the peaks exhibited in Raman scattering spectra collected from a number of individual core-shell nanostructures, each possesses a crystalline Si and a shell of PZT (Fig. 3(f)). This strategy can be implemented in much smaller-diameter templates, to control the thickness of the ferroelectric shells, and to introduce doping and/or composition modulation in the cores. These data indicate that this process route is a viable means of producing these nanostructures with high yield.

The present invention also combines chemical vapor and solution-phase grown nanostructures with atomic layer deposition (ALD). Atomic layer deposition (ALD) is an excellent and now increasingly cost-effective method for achieving conformal coatings composed of a variety of materials systems, including binary oxides and transition and noble metals, as is particularly well-suited to controlled conformal deposition on nanostructures for high-k applications. Its distinguishing feature is that, unlike CVD, multiple precursors are used and kept separated in the gas phase. This is realized by first exposing the surface on which deposition is to occur to a gaseous precursor, leading to chemisorption of the first species. The chamber is then purged with an inert gas to remove unreacted precursor. Next, exposure to a second gaseous precursor leads to a surface reaction which forms the desired film layer. This may be followed by a subsequent purging with an inert gas to remove reaction by-products. In short, a feature of ALD useful for achieving layer-by-layer control is its self-limiting reaction chemistry.

The functionality and performance of the nanostructures of the present invention are enhanced by applying ALD to produce conformal metallization layers on the ferroelectric, as well as on the nanowire semiconductor cores for subsequent patterning for electrical contact. ALD is used to produce conformal multilayer ferroelectric/dielectric shells in order to design shell systems with enhanced permittivity and charge storage capacity. Specifically, metallorganic precursors are used, such as bis(methylcyclopentadienyl)nickel(II) for Ni Ohmic contact metallization directly to Si cores followed by several monolayers of capping with Pt using, e.g. cyclopentadienyl(trimethyl)platnium(IV). Dielectric and ferroelectric coatings of ZrO₂, OfBaTiO₃ and Of SrTiO₃ are realized by self- limiting depositions of alternating layers of different metal oxides (e.g. BaO and TiO₂) using other precursors known for metallorganic chemical vapor deposition. While the growth rate is moderately slow, the surface-controlled growth provides the needed environment to produce coatings with control of the chemistry and hierarchal complexity.

While the process route described above will result in nanostructured materials which can be used for nanoscale, non-volatile memories, tunable devices, logic elements and sensors, it may be advantageous to produce hybrid nanostructures with single-crystalline shell components having epitaxial interfaces with the nanowire core. The ALD process route may be employed to achieve conformal and epitaxial deposition on nanostructures and within templates; thereby further extending the state-of-the-art in the integration of elemental semiconductors with functional binary and oxide perovskite transition metal oxides. ALD can also be used to control the surface chemistry of these nanostructures, and monitor the response of their ferroelectric and semiconductor components ex situ and, where possible, in situ with electrical feed-throughs.

There have been a number of efforts to model the effects of finite size on FE properties of thin films and nanostructures. Briefly, each of the various descriptions can be classified to within one of three approaches. These include (1) applications of the Landau- Ginzburg-Devonshire phenomenological theory, transverse field Ising models, and (3) ab- initio and ab-initio-derxved methods.

The present invention directly probes ferroelectricity in individual nanostructures using scanning probe microscopy (SPM) in ultrahigh vacuum to selectively induce and manipulate individual FE polarizations normal to the axis of ferroelectric nanowires. In this method, the nanostructures were dispersed on a conductive substrate, and a metallic AFM tip was fixed just above the nanowire while DC voltages of different polarity are applied across the nanowire to induce and manipulate ferroelectric domains perpendicular to the long axis of the nanowire. The state of polarization was subsequently "read" by collecting electrostatic force microscopy (EFM) images in constant height planes above the nanowire with the application of smaller DC voltages to the tip, as shown in Fig. 4(b)-(d). Contrast as seen in the images in Fig. 4(b)-(d) corresponds to a spatial map of the polarizations in the nanowire, and multiple polarizations pointing perpendicular to the nanowire can be selectively induced and manipulated. This demonstrates that these nanowires are indeed ferroelectric, with ferroelectric hysteresis observed in nanowires as narrow as 10 ran in diameter, as shown in Fig. 4(a); furthermore the estimate of the coercive field in a 18-nm diameter nanowire (EQ about 7 kV/cm) is not unlike that of bulk single-crystalline BaTiO₃, and found to be independent of nanowire diameter for 10 nm < d_nw < 50 ran. Finally, the stability of these nanowire polarizations is retained for more than one week, the longest timescale of the measurement, as shown in Fig. 4(b). SPM techniques have been used to investigate the ferroelectricity in these individual ferroelectric shell nanostructures and may be used to investigate the size and shape dependence of the switching field, the size dependence in the character of switching, the scaling of the dielectric permittivity in individual nanostructures, and the piezoelectric response. SPM was used to investigate the temperature- and size-dependent ferroelectric properties of individual BaTiO₃ nanostructures in ultrahigh vacuum, as shown in Figs. 5(a)- 5(b). This shows evidence of the evolution of the ferroelectric phase transition temperature Tc with finite size as probed in individual, chemically produced nanostructures — without the complications of ensemble averaging. The finding of ferroelectric stability in a 3-nm diameter nanowire segment at room temperature represents the smallest volume switchable ferroelectric domain reported to date in a perovskite ferroelectric (Figs. 6(a)-6(b)). By using infrared spectroscopy of the nano wires and the results of both thermodynamic modeling and density functional theoretical simulations, the PI showed that adsorbates account for the observed ferroelectricity in these nanostructures and in thin films, and that adsorbates are measurably superior to metals in screening uncompensated surface charges which destabilize polarizations and ferroelectricity (Figs. 7(a)-7(b)), and that the polarity of their end groups influences the polarization direction. The sample was prepared in pellet form after baking nanowire ensemble sample at 430K in ultrahigh vacuum for about 24 hours. The lower lattice diagram is the result of a density functional theoretical simulation, confirming that molecular adsorbates (OH^") stabilize the ferroelectric distortions.

The ferroelectric, piezoelectric and dielectric properties of the semiconductor- ferroelectric core-shell nanostructures shown in Fig. 10 were characterized. Both scanning local probes (e.g. electrostatic force microscopy, piezoresponse force microscopy, and scanning capacitance microscopy, and nanomechanical characterizations) as well as electroded test structures were used. The ferroelectric hysteresis, imprint, fatigue properties and ferroelectric phase transition temperatures of these hybrid nanostructured devices were characterized using a ferroelectric tester and a Labview-interfaced Agilent™ LCR meter along with a Lakeshore Desert Cryotronics variable-temperature vacuum probe station. The local ferroelectric and dielectric properties were characterized using electrostatic force microscopy. Piezoresponse force microscopy, second harmonic electrostatic force microscopy, scanning conductance microscopy and scanning gate microscopy were also used to evaluate the local properties. The scanning probe capability enables simultaneous monochromatic or broadband optical excitation with these local probes, allowing investigation of how photoreduction of molecular species and other optically-induced charging processes can be used to study and manipulate the local ferroelectric properties. The effects of molecular adsorbates on electronic transport in the semiconductor core nanostructures in electrically addressed form were also investigated in a variety of available environments, including our N₂/Ar-purged glove box and in an ALD chamber. The orientation of chemisorbed molecules may be important in the sensing by the manipulation of FE polarization and electronic transport. The up to one thousand-fold increase in the optical scattering response of individual Si nano wires also presents opportunities for local field enhancement and sensing of molecular species via spectroscopic methods. For example, enhancements in the Raman scattering from functionalized and Au- coated cones are on the order of 10¹⁰ times that due to the same molecules on an Au-coated Si substrate with the same concentration probed (Figs. 9(a)-9(c)). The basic mechanism for the enhancement may be related to finding of shell thickness- and size-dependent tuning of the surface plasmon frequency to longer wavelengths in dielectric core-metallic shell nanostructures. In the present nanocones, however, shape tunability and the significant enhancement at the tip may be achieved by a slowing of the plasmon-polariton in tapered metal nanostructures for engineering local electric field enhancements. These nanocones can be developed as scanning probes or other platforms (e.g. substrates for matrix-assisted laser desorption spectroscopy) to provide tunability of optical and electromagnetic properties, and for applications in sensing and photonics. Organic ligands are important for surfactant-controlled solution-based synthesis of nanocrystals. Molecules with polar end groups chemisorbed onto ferroelectric surfaces influence the ferroelectric stability and polarization. In both solution-based syntheses as well as metal-catalyst vapor phase growth, quantitative knowledge of selected surface energies and energy-minimized surface reconstructions provides further insight into rational synthesis of nanostructures. For semiconductor nanocones of metastable structural polymorphs, understanding the structural, thermodynamic, electronic and optical properties of the DH phase facilitates understanding the DH SiNC and GeNC growth, thermodynamic stability, and properties. For example, the expected direct μ-point energy gap in DH Ge may be useful for photonic applications; the enhancements of local electric fields in the vicinity of these nanostructures may enable application of their functional properties in photonic and/or electronic devices, and as platforms for laser desorption-induced time-of-flight mass spectroscopy.

Two methods for the simulation of features that influence the growth, of the energies of surfaces and structures, and of properties are used: density functional theoretical (DFT) simulation tools (e.g. the Vienna ab initio simulation package (VASP) and other codes) and ab initio thermodynamics approaches to modeling the binding energies of selected ligands, surface energies, lattice dynamics and ferroelectric stability. The latter permits extrapolation of zero K DFT calculations to experimentally accessible temperatures. For the DFT simulations showing the influence of adsorbates on ferroelectric stability, energy-minimized relaxed structures are calculated with paraelectric structures as initial configurations, and we consider three distinct geometries, using the BaTiO₃ material system as a model for simplicity. The ultra-thin film geometry is a reasonable approximation of the behavior of the nanowire cross-section and its surface. The simulation configurations are electrode/BaTiO₃/electrode, electrode/BaTiO₃/adsorbate, and adsorbate/BaTiO₃/adsorbate. Periodic copies separated by vacuum are employed to facilitate the calculations. In all systems, each metal electrode will consist of several atomic layers of Au(IOO) or Pt(IOO), or four (100) planes of SrRuO₃ (a metallic and oxide electrode, for comparison). Different surface terminations (TiO₂ or BaO(IOO)) and of increasing the metal electrode thickness are also considered.

Thermodynamic analyses are applied to investigate whether selected adsorbates can be expected to stabilize ferroelectricity. In particular, the analyses include all of the abundant species present in equilibrium. Since the experiments are conducted under fixed temperature T and pressure p, the Gibbs free energy is calculated. Finally, Landau theory fitting of DFT data to establish the evoluation of the ferroelectric phase transition temperature is used to compare the experimental results and calculations. For this the total free energy is taken as the sum of the free energy of the bulk of the film and that of the surface. The obtained depolarizing field allows determination of the effectiveness of the molecular screening in terms of the screening length parameter λ = εoE_dd_nJP, where εo is the permittivity of vacuum, E_d is the depolarization field, d_ΩVI is the nanowire diameter and P is the polarization. Although currently there is no rigorously correct way of computing polarization of an individual unit cell, P(z) is estimated by assuming that unit cell polarization is proportional to the displacement of the ferroelectrically active Ti cation from the center of its oxygen cage. This approach has been shown to be successful in a variety of bulk and thin film studies.

A representative calculation for OH^" molecules showing the evolution of ferroelectric stability in the nanowire for different diameters (thicknesses), along with the results of a calculation of the sum of contributions to the free energy are shown in Fig. 11. It is clear from these calculations that the molecular adsorbate strongly influences the ferroelectric stability and it acts to pin the value of polarization at the ferroelectric surface onto which it is chemisorbed.

Two device structures based on semiconductor nanowire core-ferroelectric shell architectures will now be discussed. One device structure demonstrates successful integration of one or more ferroelectric non- volatile memory device elements with the capabilities of silicon-nanowire-(SiNW) based transistors- within individual nanowires. The other device structure demonstrates the integration of nanoelectromechanical sensing and actuation with the SiNW based transistors.

The semiconductor core-FE shell nanowire architecture is used to fabricate nanoscale ferroelectric non- volatile memories. A schematic diagram of a series of the individually addressable, multiple non-volatile, two-terminal memory elements situated along a single nanowire is shown in Fig. 10. Core A is a degenerately doped semiconductor and shell C is FE.

Ferroelectric shells of PbTiO3 and PZT are grown on degenerately doped Si and SiGe nanowire cores. Evaporated and patterned electrical contacts (Au with Cr as an adhesion layer) to the ends of the nanowire cores and shells are achieved using a combination of focused ion beam, reactive ion etching, and wet etching. Selective etching and electrical contact to the core and shell layers are also established. Metallic contact to the shell layers is established using electron beam lithography and a lift-off process. These structures can be fabricated with a range of selected FE shell layer thicknesses, nanowire core diameters, and with thermal oxide or thermal oxide-free core surfaces. Though the smallest semi-circular capacitor electrode areas are dictated by lower size limits of electron beam lithography, another technique recently developed may also be useful in facilitating the assembly of electrical contacts of smaller area. This technique utilizes the reactivity of ferroelectric surfaces along with scanning probe microscopy and electron and ion beams to facilitate the controlled assembly of metal colloidal structures.

The resulting two-terminal, non-volatile ferroelectric memory devices are characterized using measurements of ferroelectric hysteresis, of dielectric permittivity, of dielectric loss and of leakage current. These measurements of PbTiO₃ and PZT structures are performed on shells of selected diameter and thickness, and as functions of frequency and temperature. The device geometry is altered to optimize device performance, and selected data collected as a function of size will be also analyzed within the framework of the LDG theory as well as compared with the results of recent and ongoing first-principles calculations. One of the attractive features of this device platform is that one or more other nanoelectronic device elements and types to exist along an individual nanowire. To date, individual single bipolar junctions or field effect transistors (FETs) have been fabricated within individual nanowires.

The bipolar junction devices are fabricated by modulating the doping along the nanowire axis during its growth, and establishing Ohmic contact to the ends of each of the nanowires. The nanowire field effect transistor device structure shown in Fig. 8 consists of a doped semiconducting core, an intrinsic shell of lower energy gap, a grown gate oxide shell, and an external electrode. For SPM-based studies, the gate electrodes will be absent and the tip and/or molecular adsorbates will serve as the local gate to control the carrier transport in the semiconductor nanowire core. Another variation of this layout for a nanoelectromechanical resonator includes only pairs of contacts across the shell at each end with the test structure traversing a trench. The structure envisioned above could serve as a multiple bit non- volatile memory, or a logic element, or even as a basic element in an encoder or an address decoder.

2.3 Multiple bipolar junctions or FETs (or a mixture of types) are formed within individual nanowires. Required electrical isolation between devices is realized by introducing potential barriers via modulation of doping and composition along the nanowires; control of this underlying composition during growth along with discrete electrical contact to core segments and shell layers enable the fabrication of multiple devices within individual nanowires. This concept can be extended further, however, by replacing the conventional oxide shell (gate) with a functional material- a ferroelectric. The device concepts involve combining the non- volatile memory element with (1) a bipolar junction device, and alternatively (2) with a nanowire FET. The fabrication of these structures represents an important step toward achieving multifunctional nanowire devices with extremely high functional densities. Among these are reproducibility of fabrication and performance, device stability, and crosstalk between device elements. As discussed above, the architecture and processing may enable these device structures to be transferred to solution and to other substrates during an intermediate stage in their processing.

It is anticipated that the semiconductor core-FE shell nanowire structures will have potential impact in the following additional areas: semiconductor nanowire-FE shell structures for "moletronics"; nanoscale ferroelectric nondestructive read-out transistor memory devices; and semiconductor core-shell structures for nanoelectromechanical devices based on piezoresistivity. Also, the strong curvature presented by nanowire (or nanocone) cores of fixed (or varying) nano-scale curvature offers an opportunity for extending ferroelectric stability and performance in nanostructured materials, and for performing systematic studies on the interplay of nanoscale curvature, strain and FE stability. The potential advantages of hybrid nanostructures formed can be realized by using steps involving different synthetic strategies. The synthetic methods can be applied to a wide array of combinations of materials systems for nano-scaled applications including, but not limited to, non-volatile, radiation-hard memories, nano-scaled transistors and logic elements, high- frequency (GHz) resonators, and high-sensitivity detectors of biomolecules and pathogens. Solution phase-based and vapor phase-based synthetic approaches may be combined to fuse different materials systems to within individual nanostructures. The hybrid nanostructures may each be composed of different domains of various materials assembled by different routes: these hybrid nanostructures can be fabricated by combining solution-based synthesis methods and vapor-phase processes. A synthesis route which combines of sol-gel alkoxide wet chemistry, electrochemistry and chemical vapor deposition results in semiconductor core-shell and core-multishell nanostructures.

Semiconductor-ferroelectric core-shell nanowires may be produced with core materials including, but not limited to, Si, Ge and SiGe, Au, Ag and Ni, and shell materials including, but not limited to PZT, BaTiO₃ and SrTiO₃. The growth of semiconducting nanowire cores may be accomplished: (a) with and without dopants, and (b) with and without axial modulation of composition and/or doping. The shell thickness may be controlled by adjusting the role of process conditions, including, but not limited to, sol-gel concentration, solvent, sintering and/or calcinations temperature and temperature ramp profile and time. Concentric shell hierarchy may be added to the process by preparing shell layers sequentially. Examples of these shell materials include, but are not limited to BaTiO₃,

SrTiO₃, PZT, SrRuO₃, ZrO₂. In particular a metallic and oxide perovskite such as SrRuO₃ is of particular interest here not only because it is well lattice-matched to other perovskites, but also because sequential layering of the pore walls (e.g. SrRuO₃ followed by BaTiO₃) can result a conformal metallic sheath on the finished nanostructures for subsequent patterning and facilitating electrical contact. Concentric shells and core-multilayer shells may also provide enhancements in the dielectric permittivity for high-κ capacitor applications in which the shell layers consist of, e.g. a ferroelectric such as BaTiO₃ sandwiched between two dielectric layers, such as SrTiO₃. Also, anodic aluminum oxide templates of smaller diameter may be produced The techniques that can be used to characterize these structures include, but are not limited to scanning electron microscopy, energy-dispersive X-ray analysis, transmission electron microscopy, variable temperature and polarized resonant, infrared spectroscopy following chemical functionalization and non-resonant Raman scattering spectroscopy. In order to characterize the functional properties of these hybrid nanostructures, they should be electrically addressable. The core-shell and core-multishell nanostructures possessing n-type and/Mype semiconductor cores may be addressed using two different methods: (1) electron beam lithography for a three, four or five-layer PMMA resist, and selective etching of the perovskite oxide shell(s) followed by metallization and lift-off, and (2) dielectrophoresis, in which a series of pairs of contacts are used to manipulate and position the hybrid nanostructures onto the electrodes. In the first method, metallizations may include, but not be limited to, Ni adhesion layers followed by Au or Pt capping for Ohmic contacts, and Cr adhesion layers followed by Au capping for Schottky contacts. Method (1) may be employed to facilitate contact to the one or both ends of each nanowire core. These structures can be used for scanning probe microscopy characterization of local ferroelectric, piezoelectric and dielectric properties, including also scanning gate microscopy. In addition, structures may be further processed to introduce one or more metal contacts on the outside of each nanostructure shell. The number and spacing of these contacts may be adjusted on the basis of results obtained from electronic transport characterizations of the test structures. Those hybrid nanostructures which have been positioned using method (2) do not have metal contacts in direct contact with the nanowire core. Thus, these devices may be processed to introduce additional, separate metal contacts on each end which are contacted to the core, as well as an additional contact or contacts on the exterior of the shell.

The atomic layer deposition (ALD) system may also be used for producing flat and then conformal coatings of layers of several materials, including but not limited to, binary oxides leading to oxide perovskites and noble metals.

The hybrid nanostructures possessing p-type and, alternatively, n-type semiconducting cores which were contacted using method (7) and which posses metal contacts on their shells can be tested using current-voltage (IV) measurements, with the core-shell hybrid nanostructures considered as a nanowire ferroelectric field effect transistor. For each test structure, conductance may be collected as a function of bias voltage applied between the source and drain electrodes at the ends of the semiconducting core, and as a function of gate voltage applied to one or more of the available metallic electrodes on the shell. These measurements may be carried out at atmospheric and vacuum pressure, and as a function of temperature, and in the absence of light, and in the presence of white light and selected wavelengths of monochromatic laser radiation. The influence of a remanent field from the ferroelectric on the electronic transport in the nanowire core can be characterized, and used to evaluate the robustness of the test structure as a ferroelectric field effect transistor. For test structures which possess multiple electrodes on the shell, a series of voltage pulses may be applied to create a pattern of local polarizations. These structures can act individually and/or collectively as logic elements, including, but not limited to logic gates and other components.

Test structures from method (2) with shell metallizations demonstrate that large numbers of these nanostructures may be assembled in organized arrays using dielectrophoresis with relative ease and in high number density for a variety of applications. In order to optimize the frequency of dielectrophoresis for these structures, the test structures which are positioned using method (2) above with additional metal contacts may be characterized using frequency-dependent impedance analysis in air, in vacuum and in a solvent medium surrounding the nanowires. With a pair of contacts across each end of the ferroelectric, and with the test structure traversing a shallow trench, the response of the core- shell hybrid nanostructure system as a high-frequency nano-scaled nanoelectromechanical circular beam resonator via piezoelectric coupling can be determined.

Structures can also be prepared using both the grown-core-in shell and the ALD methods discussed above, but without additional metal contacts on their shells. These structures may be studied using scanning and static local probe microscopy, in which the fixed metal electrodes are replaced by a scanning, metallic-coated AFM tip. Using SPM, the local FE properties will be characterized using electrostatic force microscopy (EFM) and piezoresponse force microscopy. SPM will be used to characterize the mechanical properties of these nanostructures — in particular using dynamic force microscopy, which measures the local storage and loss modulus. In addition the local internal (core) electronic landscape may be mapped using scanning conductance microscopy, EFM, and scanning gate microscopy under different source-drain bias configurations, and with and without illumination.

Stable functional groups can be introduced and/or exchanged on the ferroelectric shell surfaces with selected molecules using local reduction or oxidation with the test structures immersed in solution. These adsorbates can be used to influence the polarization orientation and ferroelectric stability.

An alternate synthesis route allows a broader range of nanostructure shapes to be conformally and epitaxially coated by functional materials such as ferroelectrics, high-κ paraelectrics, binary oxides and metals. Enhancement in performance afforded by an epitaxial interface may be useful in some applications in which the high-frequency response time of the device may be limited by mobile defects (e.g. oxygen vacancies) at or near the interface. Hybrid nanostructures based on solution-phase synthesis of nanocrystals, and their subsequent application in CVD and ALD may also be made. For some applications, the approach of growing the semiconductor nanowire cores through the ferroelectric shells is expected to be effective for achieving the desired hetero structures with unique properties. However, for some applications, heteroepitaxy may be required so that the interfaces possess fewer defects which can limit device performance. Additionally, the possibility of growing ferroelectric shells directly on nanowire cores can be adapted for a variety of other nanostructures, namely, nanocones and nanohelices. Here, an additional, alternate synthesis route for producing semiconductor-ferroelectric core-shell nanostructures via combination of chemical vapor deposition (CVD) and atomic layer deposition (ALD) may be employed. An important challenge is the handling of the native oxide which forms on the Si and Ge nanowires following exposure to moderate vapor pressures of oxygen. In one scheme nanowire surfaces are hydrogen passivated in situ following nanowire or other nanostructure growths, and subsequently desorbed just prior to ALD. Alternatively, the native oxide coatings on grown nanowire surfaces may be selectively etched using a buffered HF in a N₂ or Ar-gas purged environment, and then the nanowire surfaces can be functionalized, suppressing the oxidation. The nanowires can then be transferred to the ALD system. In the ALD process, conformal coatings of binary oxides and noble metals can produce ferroelectric and paraelectric shell layers, and conformal metallizations for subsequent processing and testing. The shell layers may include, but are not limited to BaTiO₃, SrTiO₃, PZT, ZrO₂, and selected noble metals.

The coating by functional materials onto nanostructure topologies other than nanowires will enable conformal coatings of these materials onto nanocones and nanohelices. Depending upon composition of the coating and of the core, these structures may represent a new class of inorganic chiral and inductive functional nanostructures.

In the same manner as the nanostructures produced using the core-grown-in-shell method, the nanostructures can be assembled into test structures and addressed for characterization and testing using a variety of fabrication techniques, including, but not limited to, photolithography, electron beam lithography, thermal and electron-beam evaporation for metallization, and a programmable CMOS-based dielectrophoresis platform. The semiconductor-ferroelectric core-shell and core-multi-shell paradigm may be extended to include other materials systems as components, including, but not limited to semiconductor-ferromagnetic core-shell and core-multishell nanostructures, where the ferromagnetic component here is a magnetic perovskite, charged ordered material. Multiferroism may also be incorporated within the shell component. This can be accomplished using two different approaches, using either the sol-gel/electrochemistry/CVD route or the CVD-ALD route: (1) shell materials will be made of a multiferroic perovskite compound such as BiFeO₃ or BiMnO₃; and (2) shell layers will consist of alternating layers of ferroelectric and ferromagnetic material, scaling the engineered multifunctional nanocomposite to within individual nanostructures.

In order to address the need for a scalable applications, a CMOS-based programmable dielectrophoresis platform (Fig. 12) can be used to systematically assemble and address large arrays of these hybrid nanostructures. Here a large number (64 in the prototype) of addressable elements allows statistical analysis on materials and device properties of the hybrid nanostructures. This system is particularly useful with semiconductor nanowires. The up-scaling implied by this CMOS systems approach will greatly facilitate the integration, application and overall impact of the devices based on nanoscale intergration of dissimilar materials in a variety of areas.

The system of Fig. 12 consists of a CMOS layout and a prototype board housing our power supplies for the CMOS chip as well as the PIC microcontroller device to be used to interface between a computer and the device. The CMOS chip houses the array of pads as well as signal amplifiers to ensure the integrity of the data. The board houses the PIC microcontroller and various other devices that are needed. The PIC provides an interface from the user's computer to the CMOS chip using a universal serial bus (USB) interface. It provides row and column coded addresses in order to select and poll individual sites on the sensor array. The PIC also contains Analog-to-Digital Converters used in gathering data from the CMOS and passing it on to the user's workstation. The CMOS chip takes power from the sources on the board; these sources include an oscillating source for dielectrophoresis (DEP), a DC or AC test voltage for interrogating the wires and a second DC voltage to bias the CMOS amplifiers. The user can control the board via their computer, using a graphical user interface (GUI). The GUI allows the user to select which pads to use in contacting the nanowires and, when finished contacting the wires, will be able to obtain information from the nanowires. This information is then displayed on a new screen which showcases the obtained data in an easy manner for the user to interpret.

The present invention will have a significant impact on future generation system/device technologies, in particular the development of a family of highly efficient, practical, cost-effective antennas and subordinate products covering the 30 MHz to 44 GHz frequency range. This work has application in the area of antenna technology, particularly in more ubiquitous platforms such as body-borne antennas. The process routes employed in this work can be applied to Micro-Electro-Mechanical devices (MEMS) which integrate semiconductor and ferroelectric components. In addition, the combination of a non- volatile memory element with a bipolar junction device or with a nanowire FFET which are value- added by enhancements such as logic elements within these nanostructures can be made.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms.

Claims

What is claimed is:

1. A method for the production of a structure including a semiconductor component and a transition metal oxide component, said method comprising the steps of: providing a semiconductor component containing substrate; and depositing a transition metal oxide component on a surface of said substrate by metal organic chemical vapor deposition.

2. A method as claimed in claim 1, wherein the step of providing a semiconductor component containing substrate comprises a metal organic chemical vapor deposition step.

3. A method as claimed in claim 1, further comprising the step of annealing the structure after said deposition step.

4. A method as claimed in claim 1, wherein said step of providing a semiconductor component containing substrate comprises the steps of: providing a semiconductor core; and depositing a doped semiconductor shell on said core.

5. A method as claimed in claim 4, further comprising the step of removing at least a portion of said semiconductor core to provide an at least partially hollow structure.

6. A method as claimed in claim 5, wherein said step of providing a semiconductor core comprises the step of fabricating said semiconductor core in regions of different composition, doping or both that can serve as an etch stop during said step of removing at least a portion of said semiconductor core.

7. A method as claimed in claim 5, further comprising the step of removing at least a portion of said doped semiconductor shell in a hollow portion of said structure.

8. A method as claimed in claim 5, further comprising the step of providing electrical contacts in contact with said transition metal oxide component on a hollow portion of said structure.

9. A method as claimed in claim 1, further comprising the step of functionalizing the structure with at least one molecular receptor.

10. A method as claimed in claim 1, further comprising the step of removing a portion of said semiconductor component on at least one end of said structure to form a partially hollow structure at said at least one end.

11. A method as claimed in claim 10, wherein said step of removing a portion of said semiconductor component is carried out on both ends of said structure to form a partially hollow structure at both ends.

12. A method as claimed in claim 1, wherein said step of providing a semiconductor component comprises the step of fabricating said semiconductor component in regions of different composition, doping or both that can serve as at least one etch stop; and said method further comprises the step of removing a portion of said semiconductor component.

13. A method as claimed in claim 1, wherein said structures are nanostructures.

14. A method for the production of one or more core-shell nanostructures comprising the steps of: growing at least one ferroelectric nanotube using an alkoxide precursor in an anodic aluminum oxide template; evaporating metal from said at least one nanotube; electrodepositing silver and gold segments onto said at least one nanotube; at least partially etching said silver to expose at least some gold; growing a semiconductor material containing nanowire through said at least one ferroelectric nanotube; and selectively etching the anodic aluminum oxide template to provide one or more core- shell nano structures.

15. A method as claimed in any one of claims 1-14, further comprising the step of depositing one or more layers on said structure by atomic layer deposition.

16. A method as claimed in claim 15, wherein at least two different layers are deposited on said structure by atomic layer deposition.

17. A method as claimed in claim 15, wherein metallorganic precursors are employed in said atomic layer deposition.

18. A method as claimed in claim 15, wherein said step of depositing one or more layers on said structure by atomic layer deposition produces a conformal layer.

19. A method as claimed in claim 15, wherein said step of depositing one or more layers on said structure by atomic layer deposition produces an epitaxial layer.

20. A method as claimed in claim 15, further comprising the step of providing electrical contacts on said structure.