WO2008050398A1 - Mémoire à changement de résistance - Google Patents

Mémoire à changement de résistance Download PDF

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Publication number
WO2008050398A1
WO2008050398A1 PCT/JP2006/321140 JP2006321140W WO2008050398A1 WO 2008050398 A1 WO2008050398 A1 WO 2008050398A1 JP 2006321140 W JP2006321140 W JP 2006321140W WO 2008050398 A1 WO2008050398 A1 WO 2008050398A1
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WIPO (PCT)
Prior art keywords
change memory
resistance change
transistor
potential
resistance
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Application number
PCT/JP2006/321140
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English (en)
Japanese (ja)
Inventor
Hiroshi Iwasa
Masaki Aoki
Original Assignee
Fujitsu Limited
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Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/321140 priority Critical patent/WO2008050398A1/fr
Publication of WO2008050398A1 publication Critical patent/WO2008050398A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to a resistance change memory that stores information using a plurality of resistance states having different resistance values.
  • ReRAM resistance random access memory
  • This resistance change memory is expected because it can be read at high speed and can operate at high temperatures, and can be manufactured at a low price for mixed applications.
  • a resistance change memory element (unipolar resistance change memory element) whose resistance value is changed by electrical stimulation of a single sign is composed of a single-layer film of an inexpensive material having a good affinity with a silicon process. It is suitable as an embedded nonvolatile memory.
  • Such a resistance change memory element has different resistance states, for example, a high resistance state and a low resistance state, for example, the high resistance state and the low resistance state correspond to information “0” and “1”. Information can be stored.
  • a resistance change memory element changes its resistance value by applying a voltage higher than a set voltage (eg, 1.6V), and is in a high resistance state (eg, this resistance value is 1.6V when applied). 80k Q) to a low resistance state (this resistance is 4k ⁇ when 1.6V is applied, for example) (this is called a set).
  • the resistance change memory element is lower than the set voltage and higher than the reset voltage (for example, 0.75 V), and the resistance value is changed by applying the voltage, and the resistance change state is changed from the low resistance state to the high resistance state. (This is called reset). Therefore, information can be written by setting or resetting the resistance change memory element.
  • Patent Document 1 As for the resistance change memory, there are Patent Document 1 and Non-Patent Documents 1 and 2 as follows.
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-025914
  • Non-Patent Literature 1 1.G. Baek et al., Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses, Tech.Dige st IEDM 2004, p.587
  • Non-Patent Document 2 S. Seo et al., "Conductivity switching characteristics and reset curren ts in NiO films", APPLIED PHYSICS LETTERS 86, 093509, 2005
  • control when writing to and reading from the resistance change memory element is simple and short. I was able to go on time.
  • the present invention was devised in view of such a problem, so that writing to and reading from the resistance change memory element can be performed normally, and writing to the resistance change memory element and It is an object of the present invention to provide a resistance change memory that can perform control in reading easily and in a short time.
  • the resistance change memory includes a plurality of memory blocks and a word line connecting the plurality of selected transistors.
  • the plurality of memory blocks are provided in each of the plurality of bit lines, the transistor having one current limiting function provided between the plurality of bit lines and the power source, and the plurality of bit lines.
  • a plurality of column switches including a clamp transistor having a function of clamping a potential to a predetermined value or less, and a plurality of resistors connected to each of a plurality of bit lines and capable of storing information according to a change in resistance value due to electrical stimulation.
  • the memory device includes a change memory device and a plurality of select transistors connected to each of the plurality of resistance change memory devices.
  • the word line is configured to connect select transistors included in each of the plurality of memory blocks.
  • the resistance change memory of the present invention writing to and reading from the resistance change memory element are normally performed, and the control at the time of writing to and reading from the resistance change memory element is simple, In addition, there is an advantage that it can be performed in a short time.
  • FIG. 1 is a diagram showing a circuit configuration of a memory block of a resistance change memory according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing an overall circuit configuration of a resistance change memory according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing current-voltage characteristics of a resistance change memory element constituting the resistance change memory according to the first embodiment of the present invention.
  • FIG. 4 (A) is a circuit diagram of the resistance change memory according to the first embodiment of the present invention.
  • FIG. 4B is a diagram showing the range of the set voltage and the reset voltage obtained from this simulation result.
  • FIG. 5 is a schematic plan view showing the structure of the resistance change memory according to the first embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view showing the structure of the resistance change memory according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a circuit configuration of a memory block of a resistance change memory according to a second embodiment of the present invention.
  • FIG. 8 is a diagram showing an entire circuit configuration of a resistance change memory according to the second embodiment of the present invention.
  • FIG. 9 (A) is a diagram showing the result of simulation in the circuit configuration of the resistance change memory according to the second embodiment of the present invention
  • FIG. 9 (B) is the result of this simulation. It is a figure which shows the range of the set voltage and reset voltage which were obtained from (2).
  • FIG. 10 is a diagram showing a circuit configuration of a memory block of the resistance change memory according to the third embodiment of the present invention.
  • FIG. 11 is a diagram showing an overall circuit configuration of a resistance change memory according to a third embodiment of the present invention.
  • FIG. 12 is a diagram showing a configuration of a column switch control circuit of the resistance change memory according to the third embodiment of the present invention.
  • FIG. 13 is a diagram showing a DC-DC converter used in the resistance change memory according to the third embodiment of the present invention.
  • FIG. 14 is a diagram showing a configuration of a control circuit for a multi-function pMOS transistor of a resistance change memory according to a third embodiment of the present invention.
  • FIG. 15 (A) is a diagram showing the result of simulation in the circuit configuration of the resistance change memory according to the third embodiment of the present invention
  • FIG. 15 (B) is the result of this simulation.
  • FIG. 6 is a diagram showing ranges of a set voltage and a reset voltage obtained from the above.
  • FIG. 16 (A) is a diagram showing the dependency of the gate width conversion coefficient on the reset switching current in the resistance change memory according to the embodiment of the present invention
  • FIG. FIG. 10 is a diagram showing the reset switching current dependence of the gate width of the multi-function pMOS transistor.
  • FIG. 17 is a diagram showing a configuration including a drive circuit as a modified example of the resistance change memory according to the embodiment of the present invention.
  • FIG. 18 is a diagram showing a configuration including an output sofa as a modification of the resistance change memory according to the embodiment of the present invention.
  • FIG. 1 the resistance change memory according to the first embodiment of the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 3, FIG. 4 (A), FIG. 4 (B), FIG.
  • the resistance change memory (ReRAM: Resistance Random Access Memory) according to the present embodiment has, for example, a plurality (eight in this case) of memory blocks (memory memory blocks) 1701 to 1701 as shown in the overall circuit configuration diagram of FIG. 1708.
  • a configuration example of a resistance change memory including eight memory blocks 1701 to 1708 is shown.
  • the figure shows an example of the configuration of an 8-bit input / output interface resistance change memory (low-priced product) that has 8 input / output external interfaces and can write or read in 8-bit units.
  • the configuration of the resistance change memory is not limited to this.
  • the resistance change memory may be configured as a resistance change memory (high performance product) of a 32-bit input / output interface.
  • Each memory block 1701 to 1708 has the same circuit configuration.
  • a plurality of (here, two) column switches 1301, 1311 are provided on one master bit line 1205 (2205). (2301, 2311) to multiple (here two) bit lines 1 302, 1312 (2302, 2312) and multiple bit lines 1302, 1312 (2302, 2312) respectively
  • a plurality of (six in this case) memory memories 1403, 1406, 1409, 1413, 1 416, 1419 (2403, 2406, 2409, 2413, 2416, 2419) are provided.
  • reference numerals 1101 and 2101 indicate write pMOS transistors
  • reference numerals 1 204 and 2204 indicate read circuits. Details of these will be described later.
  • FIG. 2 for convenience of explanation, only three memory cells connected to one bit line are shown. However, in reality, a large number of memory cells, for example, 512 or 1024 memory cells are provided. ing.
  • a plurality (three in this case) of common word lines WL0 to WL2 are connected to each of the memory blocks 1701 to 1708, for example, as shown in FIG. That is, word line WL0 ⁇ WL2 is provided to pass through all the memory blocks 1701 to 1708.
  • the word line WLO constitutes memory cells 1403 and 1413 of the memory block 1701, memory cells 2403 and 2413 of the memory block 1702, and memory cells (not shown) of the other memory blocks 1703 to 1708.
  • the word line WL1 is a selection transistor that forms memory cells 1406 and 1416 of the memory block 1701, memory cells 2406 and 2416 of the memory block 1702, and memory cells (not shown) of the other memory blocks 1703 to 1708.
  • the gate is connected.
  • Sarakuko word line WL2 is selected to configure memory cells 1409 and 1419 of memory block 1701, memory cells 2409 and 2419 of memory block 1702, and memory cells (not shown) of other memory blocks 1703 to 1708 Connect the gate of the transistor.
  • the memory block 1701 will be described as a representative of the plurality of memory blocks 1701 to 1708 having the same circuit configuration.
  • the memory block 1701 includes one master bit line 1205, a plurality (two in this case) of bit lines 1302, 1312, and one pMOS transistor (write transistor) used for writing. ) 1101 and a plurality of (two here) column switches 1301 and 1311 provided on each of a plurality of bit lines 1302 and 1312 and a plurality of bit lines 1302 and 1312 connected here (here Then, two memory cells 1403 and 1413, a readout circuit 1204, and a ⁇ 1 ”control circuit 1351, 1352, 1353, and 1356 are omitted.
  • FIG. 1 for convenience of explanation, only one memory cell connected to one bit line is shown.
  • the memory cell 1403 includes a resistance change memory element (here, a single memory cell) that can store information (data) by a change in resistance value due to an electrical stimulus (here, a single sign electrical stimulus).
  • a resistance change memory element here, a single memory cell
  • Polarity resistance change memory element 1401
  • this resistance change memory element 1401 1401
  • a selection transistor 1402 142
  • the resistance change memory element 1401 is an element in which a resistance value is changed by voltage application to be in a high resistance state or a low resistance state. The specific configuration will be described later.
  • FIG. 3 shows voltage-current characteristics of the resistance variable memory element.
  • the resistance change memory element 1401 (1411) is in a low resistance state in addition to a high resistance state when a voltage exceeding the set voltage is applied, and a voltage exceeding the reset voltage is applied.
  • the low resistance state force also becomes a high resistance state.
  • information (data) can be written by setting or resetting the resistance change memory element 1401 (1411).
  • reading of information from the resistance change memory element 1401 (1411) is performed by applying a voltage (a voltage that is not reset) that is even smaller than the reset voltage.
  • a high voltage (a voltage necessary for this forming is called a forming voltage) is first applied to the resistance change memory element in the initial state to cause a phenomenon such as dielectric breakdown.
  • Use force (this is called forming).
  • the forming may be performed once for one resistance variable memory element. Forming may or may not be necessary depending on the material and film thickness of the resistance change memory element.
  • one of these resistance change memory elements 1401 is connected to the bit line 1302 (1312), and the other is connected to the drain of the selection transistor 1402 (1412). It is connected to the.
  • the source of the selection transistor 1402 (1412) is connected to the ground line (GND), and the gate is connected to the word line WLO.
  • the word line WLO constitutes the gate of the select transistor 1402 (1412).
  • the substrate potential of the selection transistors (nMOS transistors) 1402 and 1412 is set to 0.0. v (vss potential).
  • the pMOS transistor 1101 is a transistor having a current limiting function. This pMOS transistor 1101 constitutes a writing circuit.
  • the pMOS transistor 1101 is provided on a line connecting a plurality of (here, two) bit lines 1302, 1312 and a power source (here, 3.3V-VDD power source). .
  • the source of the pMOS transistor 1101 is connected to the 3.3V—VDD power supply, and the drain is connected to a plurality of (here, two) bit lines 1302 and 1312 via the master bit line 1205.
  • the gate is connected to the node XWE0 of the control circuit (pMOS transistor control circuit) 1351.
  • the substrate potential of the pMOS transistor 1101 is 3.3 V (VDD potential).
  • the column switches 1301 and 1311 are used to select one specific bit line from a plurality of bit lines.
  • column switch 1301 is controlled when selected (set, reset, and read), and bit line 1302 is selected, while column switch 1311 is controlled when it is not selected.
  • bit line 1312 is selected.
  • the column switches 1301 and 1311 are nMOS transistors as shown in FIG. 1, for example.
  • the nMOS transistor 1301 (1311) has a function of clamping the potential of the bit line 1302 (1312) to which the nMOS transistor 1301 (1311) is connected to a predetermined value (a predetermined value for writing) or less. Therefore, the nMOS transistors 1301 and 1311 as column switches are also called clamp transistors.
  • the source of the nMOS transistor 1301 (1311) is connected to the bit line 1302 (1312) to which the memory cell 1403 (1413) is connected, and the drain is the master.
  • the bit line 1205 is connected to the drain of the pMOS transistor 1101, and the gate is connected to a node CL0 0 (CL01) of the control circuit (column switch control circuit) 1352.
  • the writing transistor 1101, the clamp transistors 1301, and 1311 are higher in breakdown voltage than other transistors (such as a selection transistor).
  • the write transistor 1101 and the clamp transistors 1301 and 1311 have a gate oxide film thicker than other transistors (such as a selection transistor) to have a high breakdown voltage.
  • the gate oxide film thickness of the write transistor 1101, the clamp transistors 1301, 1311 is set to 8. Onm, and the gate oxide film thickness of the other transistors (select transistor, etc.) is set to 4. Onm.
  • the breakdown voltage of the write transistor 1101, clamp transistor 1301, 1311 is 3.3V or higher, and the breakdown voltage of other transistors (such as selected transistors) is 1.8V or higher.
  • the writing transistor 1101, the clamp transistors 1301, and 1311 are referred to as thick film transistors, and the other transistors (such as selection transistors) are referred to as thin film transistors.
  • the clamp transistors 1301 and 1311 are configured to have a gate oxide film that is a predetermined thickness or more (for example, twice or more) thicker than the gate oxide films of the selection transistors 1402 and 1412. ing.
  • the predetermined value is set as a value that exceeds the range of variation due to the process.
  • the gate length of the writing transistor 1101, the clamp transistors 1301, 1311 is 0.34 / zm, and the other transistors (selection transistors, etc .; thin film transistors) Is 0.18 m.
  • the gate width of the write transistor 1101, clamp transistor 1301, 1311 is 12. O / zm, and the gate width of other transistors (selection transistors, etc.) is 1. O / zm! .
  • the gate width required for the write transistor 1101 and the clamp transistors 1301 and 1311 is determined by the current flowing through these transistors when the resistance change memory element 1401 is reset.
  • the thick film transistor and the thin film transistor are arranged.
  • a high voltage can be applied to the resistance change memory elements 1401 and 1411 while achieving high integration of the memory cells 1403 and 1413. Note that the above numerical values are given as examples only, and are not limited to these numerical values.
  • the read circuit 1204 includes a pMOS transistor (read transistor) 1202 and an nMOS transistor 1203, for example, as shown in FIG. Note that the configuration of the reading circuit 1204 is not limited to this, and any circuit configuration capable of reading information (data) stored in the resistance change memory elements 1401 and 1411 may be used.
  • the read circuit 1204 is connected to the memory cells 1403 and 1413 via the master bit line 1205, the plurality of clamp transistors 1301, 1311 and the plurality of bit lines 1302, 1312.
  • the read pMOS transistor 1202 is a transistor having a current limiting function. Therefore, the read pMOS transistor 1202 can also be regarded as a read current source.
  • the nMOS transistor 1203 has a function of clamping the potential of the bit lines 1302 and 1312 to which the nMOS transistor 1203 is connected to a predetermined value for reading. Therefore, the nMOS transistor 12 03 is also referred to as a read clamp transistor.
  • the read clamp transistor 1203 is important for preventing writing to the resistance change memory elements 1401 and 1411 during reading.
  • the source of the pMOS transistor 1202 is connected to the power supply (here, 1.8 V—VDD power supply), and the drain is connected to the drain of the nMOS transistor 1203.
  • the gate is connected to the node VRCS of the control circuit 1353.
  • a node 1 206 connecting the pMOS transistor 1202 and the nMOS transistor 1203 is a primary output node of the readout circuit 1204.
  • the substrate potential of the pMOS transistor 1202 (thin film transistor) is assumed to be 1.8 V (VDD potential).
  • the source of the nMOS transistor 1203 is connected to the drains of the plurality of clamp transistors 1301 and 1311 via the master bit line 1205, and the gate is connected to the control circuit 1353.
  • the read circuit 1204 includes the drains of the plurality of clamp transistors 1301 and 1311 and the write transistor 11. It is connected to the contact that connects the 01 drain, and this contact is the input node of the readout circuit 1204.
  • the reading transistor 1202 and the reading clamp transistor 1203 are thin film transistors. That is, the read transistor 1202 and the read clamp transistor 1203 have a gate oxide film thickness of 4. Onm and a breakdown voltage of 1.8 V or more.
  • the gate length of the reading transistor 1202 and the reading clamp transistor 1203 is set to 0.18 / zm.
  • the gate width of the read transistor 1202 is 2. O / zm
  • the gate width of the read clamp transistor 1203 is 1. O / zm.
  • these read transistor 1202 and read clamp transistor 1203 may be configured as thick film transistors.
  • the source of the reading transistor 1202 must be connected to the 3.3V—VDD power supply, and the potentials (voltages) of the nodes VRCS and VRC of the control circuit 1353 must be adjusted.
  • Control circuit 1351, 1352 writes the selected resistance change memory element (here, resistance change memory element 1401) out of a plurality of resistance change memory elements 1401, 1411 in a high resistance state or a low resistance state. Therefore, for example, as shown in FIG. 1, the gate potential of the selected clamp transistor (here, clamp transistor 13 01) and the gate potential of the write transistor 1101 are controlled among the plurality of clamp transistors 1301 and 1311. It is configured to
  • the control circuits 1351 and 1352 set the gate potential of the clamp transistor 1301 and the gate potential of the write transistor 1101, respectively, at the time of setting (the resistance change memory element 1401 is in a high resistance state state and a low resistance state state). In the case where the resistance change memory element 1401 is changed from the low resistance state to the high resistance state). Therefore, the clamp transistor 1301 and the write transistor 1101 have a set function and a reset function.
  • the control circuit 1352 includes a gate of the clamp transistor 1301 connected to the selected bit line (here, the bit line 1302) so that the potential at the time of setting is higher than that at the time of reset. Control the potential.
  • the control circuit 1352 controls the potential of the node CLOO to 3.3V at the time of setting and to 2.4V at the time of reset (control at the time of selection).
  • the column switch 1301 functions as a clamp transistor at reset. Note that, since the column switch 1301 is in a switch-on state when set, the column switch 1301 does not substantially function as a clamp transistor that clamps the potential of the bit line 1302 below a predetermined value.
  • control circuit 1352 uses the gate potential of the clamp transistor (here, the clamp transistor 1311) connected to the unselected bit line (here, the bit line 1312) as the ground potential (GND potential; 0. OV; VSS ) To control.
  • control circuit 1352 controls the potential of the node CL01 connected to the gate of the unselected clamp transistor 1311 to 0.OV (control when not selected).
  • control circuit 1351 controls the gate potential of the writing transistor 1101 so that the potential at the time of setting is higher than that at the time of resetting.
  • control circuit 1351 controls the potential of the node XWEO to 2.5 V at the time of setting and to 0.OV at the time of reset (control at the time of selection).
  • the current supplied from the power source (3.3V-VD D power source) to the selected resistance change memory element 1401 is limited. That is, the write transistor 1101 provided between the bit line 1302 connected to the selected resistance change memory element 1401 and the power supply (3.3V—VDD power supply) has a current limiting function when set. Note that the writing transistor 1101 is in a switch-on state at the time of resetting, and thus has substantially no current limiting function.
  • a write mode (set mode and reset mode), a read mode, and a power saving mode are provided as control modes. There is no power saving mode.
  • the control circuit 1351 includes the write transistor 11 Control 01 to switch off (fully closed). That is, the control circuit 1351 controls the gate potential of the writing transistor 1101 to 3.3 V (VDD), for example, as shown in FIG.
  • the control circuit 1351 controls the potential of the node XWEO to 3.3 V (VDD) in the read mode and the power saving mode (OFF).
  • the control circuit 1352 controls a selected clamp transistor (here, the clamp transistor 1 301) among the plurality of clamp transistors 1301 and 1311 to be in a switch-on state. (Control during selection). That is, the control circuit 1352 controls the gate potential of the selected clamp transistor 1301 to 3.3 V (V DD), for example, as shown in FIG. Here, at the time of reading, the control circuit 1352 controls the potential of the node CLOO to 3.3 V (VDD).
  • the potential of the node CLOO is controlled to 3.3V / 2.4V / 3.3V at the time of set Z reset, Z reset, respectively. In either case, however, the potential at node CL01 is controlled to 0.OV.
  • the resistance change memory can select the necessary voltage and current at the time of setting, resetting and reading.
  • Device 1401 can be supplied.
  • the control circuit (read circuit control circuit) 1353 reads out the resistance state of the selected resistance change memory element (here, the resistance change memory element 1401) among the plurality of resistance change memory elements 1401 and 14 11.
  • the gate potential of the reading transistor 1202 and the gate potential of the reading clamp transistor 1203 are controlled.
  • control circuit 1353 controls the potential of the node VRCS to 1.2 V (—constant voltage) and the potential of the node VRC to 0.9 V (—constant) as shown in FIG. Voltage).
  • the bit line connected to the selected resistance change memory element 1401 is read. 1302 is clamped below a predetermined value for reading. At the time of reading, the current supplied from the power supply (1.8V—VDD power supply) to the selected resistance change memory element 1401 is limited.
  • the control circuit (word line control circuit) 1356 has a selection transistor (in this case, the memory cell 1403) of the selected memory cell even when there is a deviation at the time of reset, set and read.
  • the gate potential of the selection transistor 1402) is controlled to the same potential (constant potential; here, 1.8 V).
  • the control circuit 1356 sets the potential of the word line WL0 connected to the gate of the selected selection transistor 1402 to 1.8 V (—constant potential). Control.
  • the control circuit 1356 controls the selection transistors 1402 and 1412 to be in a switch-off state (fully closed state). (Control when not selected) That is, the control circuit 1356 sets the gate potential of the unselected selection transistors 1402 and 1412 (that is, the potential of the word line WL0 connected to the gates of the unselected selection transistors 1402 and 1412) to 0. OV (VSS). To control.
  • the selected word line WL0 is always controlled to 1.8V (when selected), and the unselected word line WL1.
  • WL2 is always controlled at 0.0V (when not selected).
  • the control is performed to set the selected word line to 1.0 V at the time of setting and the selected word line to 1.8 V at the time of resetting, it is connected to the selected word line, and This means that some of the 8 memory cells connected to the selected bit line are set and some are reset (i.e., write ⁇ 0 '' in part and ⁇ 1 '' in part). I can't do it at the same time.
  • a common word line WL0 to WL2 is used by a plurality (eight in this case) of memory cells 1701 to 1708, and the selected word line is set and reset. Therefore, the selected word line is always set to the same potential. To set a part and reset a part at the same time.
  • the reset time is very long compared to the set time at present, so the effect is small. However, if the reset time is short and a resistance change memory element is found, the write time is shortened.
  • FF 135 control circuit 1351, 1352, 1356 If the power is not connected, as shown in Fig. 1, the potential of NO ⁇ WEO is controlled to 2.5V (write current limit control potential) CLOO potential is controlled to 3.3V, node CL01 potential is controlled to 0.OV, word line WLO potential is controlled to 1.8V, and word line WL1, WL2 potential is controlled to 0.OV. .
  • 2.5V write current limit control potential
  • CLOO potential is controlled to 3.3V
  • node CL01 potential is controlled to 0.OV
  • word line WLO potential is controlled to 1.8V
  • word line WL1, WL2 potential is controlled to 0.OV.
  • the gate potential of the write pMOS transistor 1101 is controlled to 2.5 V via the node XWEO of the control circuit 1351.
  • the source-gate voltage of the write pMOS transistor 1101 becomes 0.8V. This voltage value is slightly higher than the threshold voltage.
  • the writing pMOS transistor 1101 behaves like a current source. That is, the write pMOS transistor 1101 allows a constant current to flow relatively independently of the resistance value of the resistance serving as a load (mainly the resistance value of the resistance change memory element).
  • the resistance value of the load that is not the ideal current source is large, a voltage exceeding a certain level cannot be applied to the load resistance.
  • the write pMOS transistor 1101 functions as a voltage source with a voltage limiting function or a voltage source with a current limiting function.
  • a write pMOS transistor 1101 is provided, and the potential of the node X WE0 connected to the gate thereof is controlled to a desired set value (2.5 V in this case), thereby limiting the current limit, that is, the resistance
  • the upper limit of the current flowing through the memory element 1401 is determined. As the potential of the node XW E0 is lowered, a larger current flows through the resistance change memory element 1401.
  • the gate potential of the column switch 1301 is controlled to 3.3 V via the node CL00 of the control circuit 1352, and the column switch 1301 is switched on ( Fully open). As a result, the bit line 1302 is selected.
  • the gate potential of the column switch 1311 is controlled to 0.OV via the node CL01 of the control circuit 1352, the column switch 1311 is turned off (fully closed), and the bit line 1312 is not selected.
  • the selection transistor of the memory cell 1403 The gate potential of 1402 is controlled at 1.8V.
  • the path through which the current flows is 3.3V—VDD power supply ⁇ pMOS transistor 1101 for writing ⁇ column switch 1301 ⁇ resistance memory element 1401 ⁇ selection transistor 1402 ⁇ GND.
  • the resistance change memory element 1401 is set in a low resistance state while being in a high resistance state force.
  • the load becomes low resistance, and there is a possibility that an excessive current may flow through the resistance change memory element 1401.
  • the current flowing through the resistance change memory element 1401 does not increase so much.
  • the current flowing through the resistance change memory element 1401 is about 28 A before setting (high resistance state) and about 100 A after setting (low resistance state). In this case, the voltage applied to the resistance change memory element 1401 is greatly reduced.
  • the current limiting function of the write pMOS transistor 1101 can prevent an excessive current from flowing through the resistance change memory element 1401 and being destroyed.
  • the current flowing to the resistance change memory element 1401 is limited by the write pMOS transistor 1101 provided between the 3.3V-VDD power supply and the master bit line 1205. ing.
  • control circuit 1351, 1352, 1356 controls the potential of the node XWE0 to 0.0V and the potential of the node CL00 to 2.4V (write clamp control potential) as shown in Figure 1, for example. Then, the potential of the node CL01 is controlled to 0.0 V, and the potential of the word line WL0 is set to 1. Control to 8V and control the potential of word lines WL1 and WL2 to 0.OV.
  • the gate potential of the write pMOS transistor 1101 is controlled to 0.0 V via the node XWEO of the control circuit 1351.
  • the write pMOS transistor 1101 is switched on (fully opened).
  • the gate potential of the column switch 1301 is controlled to 2.4 V via the node CL00 of the control circuit 1352, and the bit line 1302 is selected.
  • the column switch 1301 functions as a clamp transistor, and the potential of the selected bit line 1302 is clamped to a predetermined value or less.
  • the threshold voltage of the clamp transistor 1301 is about 0.7V
  • the source potential of the clamp transistor 1301 is the gate potential (here 2.4V)
  • the potential (predetermined value) at which the source potential of the clamp transistor 1301 is clamped depends on the threshold voltage of the clamp transistor 1301 and the current flowing through the clamp transistor 1301.
  • the limit potential that is, the voltage applied to the resistance change memory element 1401 is reduced.
  • the upper limit is decided. Note that the higher the potential at the node CL00, the higher the voltage applied to the resistance change memory element 1401.
  • the gate potential of the column switch 1311 is controlled to 0.0 V via the node CL01 of the control circuit 1352, and the column switch 1311 is in the switch-off state (fully closed state). And bit line 1312 is not selected.
  • the potential of the word line WL0 is controlled by the control circuit 1356.
  • select transistor 1402 of memory cell 1403 is controlled to 1.8V.
  • the path through which current flows (current path at the time of writing) is the same as in the above-described setting.
  • the resistance change memory element 1401 is reset to a low resistance state force and a high resistance state.
  • the function of the column switch 1301 as a clamp transistor limits the potential of the bit line 1302 to which the resistance change memory element 1401 is connected to a predetermined value or less, and the voltage applied to the resistance change memory element 1401. Does not increase so much.
  • the voltage applied to the resistance change memory element 1401 is about 1.OV before reset (low resistance state) and about 1.5 V after reset (high resistance state).
  • the column switch 1301 by causing the column switch 1301 to function as a clamp transistor, a voltage exceeding the set voltage is applied to the resistance change memory element 1401 immediately after reset, and the column switch 1301 is set again. (That is, a low resistance state) is prevented.
  • the reading operation of the resistance change memory element 1401 will be described.
  • control circuits 1351, 1352, 1353, and 1356 control the potential of the node XWEO to 3.3V and the potential of the node CLOO to 3.3V, for example, as shown in FIG. CL01 potential is controlled to 0.OV, word line WLO potential is controlled to 1.8V, wordline WL1, WL2 potential is controlled to 0.OV, node VRCS potential is 1.2V (for reading) Current limit control potential), and control the potential of node VRC to 0.9V (reading clamp control potential).
  • the gate potential of the write pMOS transistor 1101 is controlled to 3.3 V via the node XWEO of the control circuit 1351. As a result, the write pMOS transistor 1101 is switched off (fully closed).
  • the gate potential of the column switch 1301 is controlled to 3.3 V via the node CL00 of the control circuit 1352, and the column switch 1301 is switched on (fully opened). As a result, the bit line 1302 is selected.
  • the gate potential of the column switch 1311 is controlled to 0.0 V via the node CL01 of the control circuit 1352, and the column switch 1311 is in the switch-off state (fully closed state). And bit line 1312 is not selected.
  • the potential of the word line WLO is controlled to 1.8 V by the control circuit 1356 (that is, when the word line WLO is selected)
  • the gate potential of the selection transistor 1402 of the memory cell 1403 is 1.8 V. Controlled.
  • the current flow path (current path at the time of reading) is: 1. 8V—VDD power supply ⁇ Reading pMOS transistor 1202 ⁇ Reading clamp transistor 1203 ⁇ Column switch 130 1 ⁇ Resistance-change memory element 1401 ⁇ Selection Transistor 1402 ⁇ GND.
  • the resistance state of the resistance change memory element 1401 is read by passing a current through the resistance change memory element 1401 through such a path.
  • the resistance value difference between the high resistance state and the low resistance state of the resistance change memory element 1401 is output from the primary output node 1206 of the readout circuit 1204 as a large potential difference.
  • the gate potential of the read p MOS transistor (read current source) 1202 is controlled to about 1.2 V via the node VRCS of the control circuit 1353.
  • the source-gate voltage of the read pMOS transistor 1202 becomes 0.6 V, and the read pMOS transistor 1202 functions as a current source for supplying a constant current to the current path during reading.
  • the current limiting function of the read pMOS transistor 1202 prevents a current exceeding a certain level from flowing in the current path during reading.
  • the potential of the node VRCS connected to the gate of the reading pMOS transistor 1202 is controlled to a desired setting value (1.2 V in this case), thereby limiting the current, that is, the current flowing in the current path during reading.
  • the upper limit is decided.
  • the gate potential of the read clamp transistor 1203 is controlled to 0.9 V via the node VRC of the control circuit 1353.
  • the potential of the master bit line 1205 is clamped to 0.4 V or less, for example.
  • the potential of the bit line 1302 is clamped below a predetermined value for reading.
  • the limit potential that is, the potential of the master bit line 1205, and thus Determines the upper limit of the potential of the bit line 1302 [0080]
  • the resistance between the source and the drain of the read clamp transistor 1203 is the voltage between the source and the gate. It is very different by slight difference. That is, the resistance between the source and the drain of the read clamp transistor 1203 varies greatly depending on the potential difference of the master bit line 1205 to which the source of the read clamp transistor 1203 is connected.
  • the resistance change memory element 1401 Since the pMOS transistor 1202 for reading tries to flow a constant current through the current path during reading, the resistance change memory element 1401 has a resistance change depending on whether it is in a low resistance state or in a high resistance state.
  • the difference in the resistance value of the memory element 1401 becomes the potential difference of the master bit line 1205 (that is, the potential difference between the source and the gate of the read clamp transistor 1203).
  • the potential difference (voltage) between the drains is very different.
  • the potential of the master bit line 1205 is, for example, about 50 mV when the resistance change memory element 1401 is in the low resistance state (eg, 4 k ⁇ ).
  • a high resistance state for example, 80 k ⁇
  • the potential difference between the source and the drain of the read clamp transistor 1203 is, for example, about 200 mV when the resistance change memory element 1401 is in the low resistance state (for example, 4 kQ), for example, in the high resistance state (for example, For example, 80k ⁇ is about 1.7V.
  • the difference in resistance value between the high resistance state and the low resistance state of the resistance change memory element 1401 is output from the primary output node 1206 of the read circuit 1204 as a large potential difference.
  • the resistance change memory According to the resistance change memory according to the present embodiment, there is an advantage that writing (set and reset) and reading to the resistance change memory element 1401 can be performed normally. That is, according to the present resistance change memory, there is an advantage that it is possible to provide a circuit configuration for generating a voltage / current signal that can be normally set, reset and read.
  • FIGS. 4 (A) and 4 (B) show simulation results in the circuit configuration of the resistance change memory as described above.
  • the resistance change memory element 1401 uses a pure resistance having a resistance value of 80 k ⁇ in the high resistance state and a resistance value of 4 k ⁇ in the low resistance state.
  • Fig. 4 (A) shows a resistance change memory element when off (during power saving), before setting (resistance change memory element 1401 is in a high resistance state), after setting (resistance change memory element 1401 is in a low resistance state).
  • resistance change When reading when 401 is in low resistance state (when reading low resistance), before resetting (resistance change memory element 1401 is in low resistance state), after reset (resistance change memory element 1401 is in high resistance state), resistance change
  • the current flowing through the resistance change memory element 1401 after setting is suppressed to about 100 A, and the voltage applied to both ends of the resistance change memory element 1401 after reset is 1. It is suppressed to 5V or less.
  • a voltage of about 2.2 V can be applied to the resistance change memory element 1401 before setting.
  • FIG. 4B shows the range of the set voltage and the reset voltage of the resistance change memory element 1401 for which the simulation capability is also obtained!
  • the set voltage of the resistance change memory element 1401 is 1.498 V or more and 2.249 V or less, and the reset voltage is 0. 408V or more 1. 039V or less is required.
  • writing can be performed with the circuit configuration of the resistance change memory as described above. For example, when the reset voltage of the resistance change memory element 1401 is 0.75 V and the set voltage is 1.6 V, writing can be performed with the above-described circuit configuration.
  • forming voltage of the resistance change memory element 1401 is 1.498V or more and 2.249V or less, forming is performed by the setting operation in the above circuit configuration.
  • the resistance change memory element 1401 is required to have a set voltage of 1.600V or more and 2. OOOV or less, and a reset voltage of 0.5 to 500V or more and 0.90V or less.
  • FIGS. 5 and 6 cross-sectional views taken along arrows A—A ′ in FIG. 5). To do.
  • an element isolation film 32 that defines an element region is formed on a silicon substrate 30.
  • each element region has a rectangular shape that is long in the X direction.
  • the plurality of element regions (active regions) are arranged in a staggered pattern.
  • a plurality of word lines WL extending in the Y direction are formed on the silicon substrate 30 on which the element isolation film 32 is formed.
  • two word lines WL are extended in each element region.
  • source Z drain regions 36 and 38 are formed in the active regions on both sides of the word line WL.
  • two selection transistors ST each having the gate electrode 34 also serving as the word line WL and the source Z drain regions 36 and 38 are formed.
  • Two selection transistors ST formed in one element region share a source Z drain region 36.
  • An interlayer insulating film 40 is formed on the silicon substrate 30 on which the selection transistor ST is formed.
  • a contact plug 46 connected to the source / drain region 36 and a contact plug 48 connected to the source Z drain region 38 are embedded.
  • ground line 50 electrically connected to the source / drain region 36 (source terminal) via the contact plug 46 and a source Z drain region 38 ( A relay wiring 52 electrically connected to the drain terminal) is formed.
  • the ground line 50 extends in the Y direction.
  • an interlayer insulating film 54 is formed on the interlayer insulating film 40 on which the ground line 50 and the relay wiring 52 are formed.
  • a contact plug 58 connected to the relay wiring 52 is embedded in the interlayer insulating film 54.
  • a resistance change memory element RMD is formed on the interlayer insulating film 54 in which the contact plug 58 is embedded.
  • the resistance change memory element RMD is formed on the lower electrode 60 and the lower electrode 60 electrically connected to the source Z drain region 38 via the contact plug 58, the relay wiring 52, and the contact plug 48.
  • the resistance change memory material constituting the resistance change memory layer 62 in addition to TiO, for example, NiO, YO, CeO, MgO, ZnO, ZrO, HfO, WO, NbO, TaO, Cr O, MnO, AIO, VO, SiO, etc. can be applied.
  • An acidic material can also be applied. It is to be noted that such a resistance change memory material can be used alone, and a resistance change memory layer having a single layer structure can be formed, or any combination thereof can be used to form a resistance change memory layer having a stacked structure. Also good.
  • an electrode material constituting the lower electrode 60 and the upper electrode 64 in addition to platinum, for example, Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, and the like.
  • the electrode material constituting the lower electrode 60 and the electrode material constituting the upper electrode 64 may be the same or different.
  • An interlayer insulating film 68 is formed on the interlayer insulating film 54 on which such a resistance change memory element RMD is formed, for example, as shown in FIG.
  • a contact plug 72 connected to the upper electrode 64 of the resistance change memory element RMD is embedded in the interlayer insulating film 68.
  • a bit line BL electrically connected to the upper electrode 64 of the resistance change memory element RMD through the contact plug 72 is formed. As shown in FIG. 5, the bit line BL extends in the X direction.
  • the resistance change memory according to the present embodiment is different from the first embodiment in the configuration of the column switch.
  • the column switch 1304 (1314) is connected to the nMOS ⁇ transistor 1301 (1311) and the nMOS ⁇ transistor 1301 (1311) in parallel with IJ. Powered by 1303 (1313), nMOS transistor 1301 (131 1) and pMOS transistor 1303 (1313) share the source and drain! /
  • the pMOS transistor 1303 (1313) is used when the resistance change memory element 1401 is set (that is, when the resistance change memory element 1401 is in a high resistance state state and a low resistance state).
  • the line 1302 is set to a high potential so as to apply a larger voltage to the resistance change memory element 1401 before setting (high resistance state).
  • a pMOS transistor 1303 is provided so that a larger voltage can be applied to the resistance variable memory element 1401 before setting.
  • the gate oxide film thickness of the pMOS transistors 1303 and 1313 is set to 8. Onm. From this point, the pMOS transistors 1303 and 1313 have a pressure of 3. 3 V or more.
  • the ⁇ MOS transistors 1303 and 1313 are called thick film transistors.
  • the pMOS transistors 1303 and 1313 are configured to have a gate oxide film that is a predetermined thickness or more (for example, twice or more) thicker than the gate oxide films of the selection transistors 1402 and 1412. ing.
  • the predetermined value is set as a value that exceeds the range of variation due to the process.
  • the pMOS transistors 1303 and 1313 have a gate length of 0.34 ⁇ m and a gate width of 6.! Note that the pMOS transistors 1303 and 1313 only need to allow current to flow when the resistance change memory element 1401 at the time of setting is in a high resistance state (before setting), so the gate width is the pMOS transistor for writing 1101 or the nMOS transistor 1301. It may be smaller.
  • the nMOS transistor 1301 (1311) has the potential of the bit line 1302 (1312) to which the nMOS transistor 1301 (1311) is connected not more than a predetermined value (predetermined value for writing), as in the first embodiment. It has a function to clamp to. Therefore, the nMOS transistors 1301 and 1311 constituting the column switches 1304 and 1314 are also referred to as clamp transistors.
  • the source of the nMOS transistor 1301 (1311) and the drain of the pMOS transistor 1303 (1313) are connected to the bit line 1302 (to which the memory cell 1401 (1411) is connected)
  • the drain of the nMOS transistor 1301 (1311) and the source of the pMOS transistor 1303 (1313) are connected to the drain of the pMOS transistor 1101 via the master bit line 1205, and the nMOS transistor , Connected to node CLOO (CLOl) and node CPLOO (CPLOl) of control circuit 1355.
  • the control circuit (column switch control circuit) 1355 has a pMOS transistor (here, pMOS transistor 1303) selected out of the pMOS transistors 1303 and 1313, and the resistance change memory element 1401 has a high resistance state power. It is configured to control the switch state when the resistance change state is set and to control the switch-off state when resetting the resistance change memory element 1401 from the low resistance state to the high resistance state.
  • pMOS transistor 1303 selected out of the pMOS transistors 1303 and 1313
  • the resistance change memory element 1401 has a high resistance state power. It is configured to control the switch state when the resistance change state is set and to control the switch-off state when resetting the resistance change memory element 1401 from the low resistance state to the high resistance state.
  • the pMOS transistor 1303 is switched on, and a large voltage is applied to the resistance change memory element 1401 before setting (high resistance state).
  • the pMOS transistor 1303 is switched off, and potential / current is transmitted by the nMOS transistor 1301.
  • control circuit 1355 controls the potential of the node CPL00 to 0.0 V (VSS potential) at the time of setting and 3.3 V (VDD potential) at the time of resetting.
  • Control read 3.
  • Control to 3V (VDD potential) control when selected).
  • control circuit 1355 controls the gate potential of the unselected pMOS transistor (here, the pMOS transistor 1313) of the pMOS transistors 1303 and 1313 to 3.3 V (VDD potential).
  • control circuit 1355 controls the potential of the node CPL01 connected to the gate of the unselected pMOS transistor 1313 to 3.3 V (VDD potential) (when not selected). Control).
  • the resistance change memory according to this embodiment has a plurality of identical circuit configurations (here, 8) as shown in the overall circuit configuration diagram of FIG. 8, for example.
  • a configuration example of a resistance change memory having eight memory blocks 1701 to 1708 is shown. is doing.
  • the figure shows an example of the configuration of an 8-bit input / output interface resistance change memory (low-priced product) that has 8 input / output external interfaces and can write or read in 8-bit units.
  • the configuration of the resistance change memory is not limited to this.
  • the resistance change memory may be configured as a resistance change memory (high performance product) of a 32-bit input / output interface.
  • a plurality (three in this case) of common word lines WL0 to WL2 are connected to the memory blocks 1701 to 1708. That is, the word lines WL0 to WL2 are provided so as to pass through all the memory blocks 1701 to 1708.
  • bit lines connected to one master bit line are shown, and the force of connecting 16 memory cells to one word line is actually 1 Eight bit lines are connected to one master bit line via a column switch, and one word line is connected to 64 memory cells. In many cases, 4 to 16 bit lines are provided.
  • the resistance change memory according to the present embodiment has the same effect as that of the first embodiment described above.
  • FIGS. 9A and 9B show simulation results in the circuit configuration of the resistance change memory as described above.
  • the resistance change memory element 1401 uses a pure resistance having a resistance value of 80 k ⁇ in the high resistance state and a resistance value of 4 k ⁇ in the low resistance state.
  • Fig. 9 (A) shows a resistance change memory element when off (during power saving), before setting (resistance change memory element 1401 is in a high resistance state), after setting (resistance change memory element 1401 is in a low resistance state).
  • the current flowing through the resistance change memory element 1401 after setting is suppressed to about 100 A, and the voltage applied to both ends of the resistance change memory element 1401 after reset is 1. It is suppressed to 5V or less.
  • a voltage of about 3. IV can be applied to the resistance change memory element 1401 before setting.
  • the column switch 1304 to include the pMOS transistor 1303, a larger voltage than that in the first embodiment is applied to the resistance change memory element 1401, and the resistance change memory element It can be seen that the applied voltage to 1401 can be improved.
  • the potential of the primary output node 1206 when reading when the resistance change memory element 1401 is in the low resistance state (during low resistance reading), the potential of the primary output node 1206 is 0.105V, and the resistance change memory element 1401 has a high resistance. At the time of reading in the state (high resistance reading), the potential of the primary output node 1206 is 1.763 V, and the resistance change memory element 1401 is in the low resistance state and in the high resistance state, It can be seen that the potential of the primary output node 1206 has a difference of 1.6 V or more.
  • FIG. 9 (B) shows the range of the set voltage and the reset voltage of the resistance change memory element 1401 for which the simulation capability is also obtained!
  • the set voltage of the resistance change memory element 1401 is 1.498V or more and 3.135V or less, and the reset voltage is 0. 408V or more 1. 039V or less is required.
  • the set voltage and reset voltage of the resistance change memory element 1401 are within these ranges. If it exists, writing can be performed with the circuit configuration of the resistance change memory as described above. For example, when the reset voltage of the resistance change memory element 1401 is 0.75 V and the set voltage is 1.6 V, writing can be performed with the above-described circuit configuration.
  • the forming voltage of the resistance change memory element 1401 is 1.498V or more and 3.135V or less, the forming can be performed by the setting operation in the above circuit configuration. If the column switch 1304 is configured to include the pMOS transistor 1303 as in the present embodiment, there is an effect that forming is easier than in the first embodiment.
  • the resistance change memory according to this embodiment is different from that of the above-described second embodiment in that the pMOS transistor 1101 and the column switch 1304 used for writing without providing a separate reading circuit are used as a reading circuit. The point is different.
  • the read circuit is configured by the read pMOS transistor 1202 and the read clamp transistor (nMOS transistor) 12 03 that serve as a current source.
  • the configuration and connection relationship (combination) of the pMOS transistor 1202 and the nMOS transistor 1203 constituting the read circuit are the same as the configuration and connection relationship (combination) of the pMOS transistor 1101 and the nMOS transistor 1301 used for writing.
  • the reading circuit is composed of a pMOS transistor 1101 and a column switch 1304 used for writing.
  • the drain of the multi-function pMOS transistor 1101, the drain of the nMOS transistors 1301 and 1311 and the sources of the pMOS transistors 1303 and 1313 constituting the power switch 1304 are the primary output nodes. Connected to 1206.
  • the node 1206 to which the master bit line 1205 is connected is the next output node. During reading, the node 1206 passes through this node 1206. Therefore, the pMOS transistor (multi-function pMOS transistor) 1101 and the column switch 1304 that constitute the readout circuit have a potential of a large difference between the high resistance state and the low resistance state (here, amplified by the column switch 1304). Output potential).
  • control circuits 1357 and 1358 read out the resistance state of the selected resistance change memory element (here, the resistance change memory element 1401) among the plurality of resistance change memory elements 1401 and 1411.
  • the selected resistance change memory element here, the resistance change memory element 1401
  • the gate potential of the transistors constituting the selected column switch here, the transistors 1301 and 1303 constituting the column switch 1304.
  • the multi-function transistor 1101 is configured to control the gate potential.
  • the control circuits 1357 and 1358 determine the gate potential of the transistors 1301 and 1303 constituting the selected column switch 1304 and the gate potential of the multi-function transistor 1101 (transistor having a current limiting function).
  • the column switch and the multi-function transistor have a set function, a reset function, and a read function.
  • control circuit 1358 has a higher potential at the time of setting than at the time of reset, and at the time of resetting than at the time of reading. Are controlled so that the gate potentials of the transistors 1301 and 1303 constituting the column switch 1304 connected to the selected bit line (here, the bit line 1302) are controlled.
  • control circuit 1358 sets the potential of the node CL00 as shown in FIG. 10, for example. Control to 3.3V at reset, control to 2.4V at reset, and control to 0.9V at read (control when selected).
  • the potential of the selected bit line 1302 is clamped to a predetermined value or less during reset. That is, the nMOS transistor 1301 constituting the column switch 1301 functions as a clamp transistor at reset.
  • the potential of the selected bit line 1302 is clamped to a predetermined value for reading or less during reading. That is, the nMOS transistor 1301 constituting the column switch 1304 functions as a clamp transistor during reading.
  • nMOS transistor 1301 that constitutes the column switch 1301 is in the switch-on state (fully open state) when set, so it effectively functions as a clamp transistor that clamps the potential of the bit line 1302 below a predetermined value for reading. do not do.
  • the potential of the node CL00 at the time of reading is not written to the resistance change memory element 1401, and the potential of the bit line 1302 is set to the high resistance state and the low resistance state. From the standpoint of being able to output to the primary output node 1206, the difference is set to be lower than the potential of the node CL00 at the time of reset.
  • the potential of node CL00 at the time of reading is set to 0.9V.
  • the control circuit 1358 sets the gate potential of the nMOS transistor 1311 constituting the column switch 1314 connected to the unselected bit line (here, the bit line 1312) to the ground. Control to potential (GND potential; 0.0V; VSS).
  • the control circuit 1358 controls the potential of the node CL01 connected to the gate of the nMOS transistor 1311 constituting the unselected column switch 1314 to 0.0 V (when not selected). control).
  • the control circuit 1358 controls the gate potential of the pMOS transistor 1313 constituting the column switch 1314 connected to the unselected bit line 1312 to 3.3 V (VDD potential).
  • control circuit 1358 controls the potential of the node CPL01 connected to the gate of the pMOS transistor 1313 constituting the unselected column switch 1314 to 3.3 V (VDD potential) (non-voltage). Control during selection).
  • control circuit 1358 controls the potential of the node CPL00 to 0.0 V (VSS potential) at the time of setting and 3.3 V (VDD potential) at the time of resetting. ) And 3.3V (VDD potential) during reading (control during selection; see Figure 10).
  • the pMOS transistor 1303 is switched on, and a large voltage is applied to the resistance change memory element 1401 before setting (high resistance state).
  • the pMOS transistor 1303 is switched off, and potential / current is transmitted by the nMOS transistor 1301.
  • the control circuit 1358 is controlled by a first selector (potentials of transistors 1321 to 1324 as shown in FIG. 12, for example).
  • Selector potentials of transistors 1321 to 1324 as shown in FIG. 12, for example.
  • Selector 1365
  • second selector potential selector
  • third selector potential selector
  • a DC-DC converter 1359 as shown in FIG. 13 [a constant potential generated by this (here, 3.3V, 2.4V, 0.9V, 0. (0V) may be selected and supplied to control the potential of the nodes CL00, CL01, CPL00, and CPL01.
  • WDATA0 is a node to which data to be written is supplied.
  • XWDA TA0 is a node to which an inverted signal of WDATA0 is supplied.
  • WC is a node to which a write control signal is supplied, and is “H” (High) in the write mode and “L” (Low) in the read mode.
  • XWC is a node to which an inversion signal of WC is supplied.
  • CSL0 and CSL1 are nodes to which an address decoded column address signal is supplied.
  • the DC-DC converter 1359 receives 3.3V-VDD potential (3.3V) and 0.OV-VSS potential (0.OV). 2.74V, 2.5V, 2.4V, 1.8V (VDD), 0.9V are configured to output each potential.
  • the first selector 1365 is a circuit that selects a potential supplied to the gate of the nMOS transistor 1301 of the column switch 1304 to be selected.
  • the potential of node 1361 is selected by the circuit on the left side of FIG. 12 of second selector 1366 and supplied to node CLOO.
  • the potential of the node 1362 is selected and supplied to the node CPLOO by the circuit on the right side of the second selector 1366 in FIG.
  • the gate potential of the nMOS transistor 1301 constituting the column switch 1304 is controlled to the potential of the node 1361 (3.3V at the time of setting, 2.4V at the time of resetting, 0.9V at the time of reading), and the column switch 1304 is constituted.
  • the gate potential of the pMOS transistor 1303 is controlled to the potential of 1362.
  • the potential of the node 1362 becomes “L” (here, 0.0 V) when XWDATAO is “H” and WC is “H” (when set), and XWDATAO is “L”. ”And when WC is“ H ”(at reset), it becomes“ H ”(3.3 V here), and when WC is“ L ”(when reading), it is“ H ”(here 3. 3V).
  • the potential of the node 1361 is selected by the circuit on the left side of FIG. 12 of the third selector 1367 and supplied to the node CL01.
  • the potential of the node 1362 is selected by the circuit on the right side of the third selector 1367 in FIG. 12 and supplied to the node CPL01.
  • the gate potential of the nMOS transistor 1311 constituting the column switch 1314 is controlled to the potential of the node 1361 (3.3V at the time of setting, 2.4V at the time of resetting, 0.9V at the time of reading), and the column switch 1314 is constituted.
  • the gate potential of the pMOS transistor 1313 is controlled to the potential of 1362 (0.0V at set, 3.3V at reset, 3.3V at read).
  • control circuit 1357 has a higher potential at the time of setting than at the time of resetting as shown in FIG. 10, for example.
  • the gate potential of the multi-function transistor 1101 is controlled so that the potential during reading is higher than that during reset.
  • control circuit 1357 controls the potential of the node XWE0 to 2.5 V at the time of setting (when selected) and to 0.0 V at the time of reset (when selecting) When reading (selected), control to 2.74V, and when saving power (not selected), control to 3.3V (VDD). Note that the power saving mode may not be provided.
  • the multi-function transistor 1101 provided between the bit line 1302 connected to the selected resistance change memory element 1401 and the power supply (3.3V—VDD power supply) has a current limiting function at the time of setting and reading. Yes. Note that the multi-function transistor 1101 does not actually have a current limiting function because it is in a switch-on state upon reset. [0141]
  • the potential of node XWEO at the time of reading is set to a voltage slightly lower than the potential of 3.3V—VDD power supply potential and the threshold value of pMOS transistor 1101 at bow IV. Yes.
  • the potential of the node XWEO at the time of reading is preferably set higher than the potential of the node XWEO at the time of setting.
  • the pMOS transistor 1101 is used as a current source for passing a small current, and when the resistance change memory element 1401 is in the low resistance state, the resistance change memory element 1401 While the voltage applied to both ends is kept low so that the potential of the bit line 1302 is lowered, the voltage applied to both ends of the resistance change memory element 1401 is high when the resistance change memory element 1401 is in a high resistance state. This is because the potential of the bit line 1302 is increased so that the potential of the bit line 1302 varies greatly depending on the resistance state of the resistance change memory element 1401.
  • the potential of node XWE0 at the time of reading is set to 2.74V, for example.
  • the control circuit 1357 includes a first selector (potential selector) 1165 composed of transistors 1158 and 1159, and a transistor 1155 as shown in FIG.
  • the second selector (potential selector) 1166 consisting of ⁇ 1157
  • the third selector (potential selector) 1167 consisting of transistors 1151 to 1153 and an inverter 1154, and these selectors 1165 to 1167
  • a constant potential 3.3V, 2.74V, 2.5V, 0.0V in this case
  • WDATA0 is a node to which data to be written is supplied.
  • WC is a node to which a write control signal is supplied, and is “H” (High) in the write mode and “L” (Low) in the read mode.
  • XWC is a node that is supplied with the WC inversion signal. It is.
  • CE is a node to which a chip enable signal is supplied, and is “LJ (Low)” in the power saving mode, and “H” (High) otherwise.
  • the second selector 1166 selects the potential of the node 1162 (2.5 V at the time of setting, 0.OV at the time of resetting) and is supplied to the node 1161.
  • WC is “H” (during writing)
  • the second selector 1166 selects the potential of the node 1162 (2.5 V at the time of setting, 0.OV at the time of resetting) and is supplied to the node 1161.
  • WC is “L” (during reading)
  • 2.74V is selected by the second selector 1166 and supplied to the node 1161.
  • the third selector 1167 causes the potential of the node 1161 (2.5V at set, 0.0V at reset, 2. at read). 74V) is selected and supplied to node XWE0. That is, the gate potential of the multi-function transistor 1101 is controlled to the potential of the node 1161 (2.5 V at the time of setting, 0.0 V at the time of resetting, 2.74 V at the time of reading).
  • CE is “L” (in power saving mode)
  • 3.3V is selected by the third selector 1167 and supplied to the node XWE0. That is, the gate potential of the multi-function transistor 1101 is controlled to 3.3V.
  • control circuit (word line control circuit) 1356 can be reset, set, or read (selected) in the same manner as in the first and second embodiments described above.
  • the gate potential of the selection transistor of the selected memory cell here, the selection transistor 1402 of the memory cell 1403 is controlled to the same potential (constant potential; here, 1.8 V) (see, for example, FIG. 10).
  • the control circuit 135 6 sets the potential of the word line WL0 connected to the gate of the selected selection transistor 1402 to 1.8 V (—constant potential). To control.
  • the control circuit 1356 controls the selection transistors 1402 and 1412 to be in a switch-off state (not selected). Control of time). That is, the control circuit 1356 controls the gate potential of the non-selected transistor 1402, 1412 (that is, the non-selected selection transistor 1402, 1). The potential of the word line WLO connected to the gate of 412 is controlled to 0. OV (VSS) (see Figure 10 for example).
  • the potential of the node CLOO is controlled to 3.3V / 2.4V / 0.9V at the time of set Z reset, Z off, respectively, and the node CPLOO Is set to 0. OV / 3. 3V / 3. 3V when Z is reset, and Z is off. In both cases, the potential of node CL01 is controlled to 0.0V.
  • CPL01 will be controlled to 3.3V.
  • the resistance change memory according to this embodiment has the same circuit configuration as shown in, for example, the overall circuit configuration diagram of FIG.
  • a plurality of (here, eight) memory blocks (memory cell blocks) 1701 to 1708 are provided.
  • a configuration example of a resistance change memory including eight memory blocks 1701 to 1708 is shown.
  • the figure shows an example of the configuration of an 8-bit input / output interface resistance change memory (low-priced product) that has 8 input / output external interfaces and can write or read in 8-bit units.
  • the configuration of the resistance change memory is not limited to this.
  • the resistance change memory may be configured as a resistance change memory (high performance product) of a 32-bit input / output interface.
  • a plurality (three in this case) of common word lines WL0 to WL2 are connected to the memory blocks 1701 to 1708.
  • the drains WL0 to WL2 are provided to pass through all the memory blocks 1701 to 1708.
  • bit lines connected to one master bit line are shown, and the force of connecting 16 memory cells to one word line is actually 1 Eight bit lines are connected to one master bit line via a column switch, and one word line is connected to 64 memory cells. In many cases, 4 to 16 bit lines are provided.
  • control circuits 1357, 1358, 1356 control the potential of the node X WEO to 2.74V (reading current limit control potential) and the potential of the node CLOO to 0.9V ( Control the potential of node CL01 to 0.OV, control the potential of word line WLO to 1.8V, and control the potential of word lines WL1, WL2 to 0.OV.
  • the gate potential of the multi-function pMOS transistor 1101 is controlled to 2.74 V via the node XWEO of the control circuit 1357.
  • the current supplied from the power source (3.3V—VDD power source) to the selected resistance change memory element 1401 is limited by the multi-function pMOS transistor 1101.
  • the gate potential of the nMOS transistor 1301 constituting the column switch 1304 is controlled to 0.9 V via the node CL00 of the control circuit 1358, and thereby the bit line 1302 is selected.
  • the nMOS transistor 1301 clamps the potential of the selected bit line 1302 below a predetermined value for reading.
  • the gate potential of the pMOS transistor 1303 constituting the column switch 1304 is controlled to 3.3 V, and the pMOS transistor 1303 is switched on (fully opened).
  • the gate potential of the nMOS transistor 1311 constituting the column switch 1314 is controlled to 0.0 V via the node CL01 of the control circuit 1358, and the column switch 1311 is in the switch-off state. (Fully closed state). As a result, the bit line 1312 is not selected. Note that the gate potential of the pMOS transistor 1313 constituting the column switch 1314 is controlled to 3.3 V, and the pMOS transistor 1313 is switched on (all Open state).
  • the path through which the current flows (current path at the time of reading) is 3.3V—VDD power supply ⁇ multifunctional pMOS transistor 1101 ⁇ column switch 1304 ⁇ resistance memory element 1401 ⁇ selection transistor 1402 ⁇ GND.
  • the resistance state of the resistance change memory element 1401 is read by passing a current through the resistance change memory element 1401 through such a path.
  • the resistance value difference between the high resistance state and the low resistance state of the resistance change memory element 1401 is a large potential difference.
  • the multifunction p is connected via the node XWE0 of the control circuit 1357.
  • the gate potential of the MOS transistor (readout current source) 1101 is controlled to about 2.74V.
  • the multi-function pMOS transistor 1101 functions as a current source that allows a constant current to flow in the current path during reading.
  • the current limiting function of the multi-function pMOS transistor 1101 prevents a current exceeding a certain level from flowing in the current path during reading.
  • the limiting current that is, the current at the time of reading is set.
  • the upper limit of the current flowing through the path is determined.
  • the gate potential of the nMOS transistor (reading clamp transistor) 1301 constituting the column switch 1304 is controlled to 0.9 V via the node CL00 of the control circuit 1358.
  • the potential of the bit line 1302 is clamped below a predetermined value for reading.
  • the limit potential that is, the bit line
  • the upper limit of the potential of 1302 is determined.
  • the resistance between the source and gate of the nMOS transistor 1301 constituting the column switch 1304 In a region where the voltage of the nMOS transistor 1301 constituting the column switch 1304 is slightly higher than the threshold voltage, the resistance between the source and the drain of the nMOS transistor 1301 varies greatly depending on a slight difference in the voltage between the source and the gate. In other words, the resistance between the source and drain of the nMOS transistor 1301 constituting the column switch 1304 differs greatly depending on the potential difference of the bit line 1302 to which the source of the nMOS transistor 1301 constituting the column switch 1304 is connected. .
  • the multi-function pMOS transistor 1101 tries to pass a constant current through the current path during reading. Therefore, the resistance change between the resistance change memory element 1401 in the low resistance state and in the high resistance state The difference in resistance value of the memory element 1401 becomes the potential difference of the bit line 1302 (that is, the potential difference between the source and gate of the nMOS transistor 1301 constituting the column switch 1304), and this difference constitutes the column switch 1304.
  • the potential difference (voltage) between the source and drain of the nMOS transistor 1301 differs greatly.
  • the resistance value difference between the high resistance state and the low resistance state of the resistance change memory element 1401 is output as a primary potential node 1206 (master bit line) as a large potential difference.
  • the resistance change memory according to this embodiment, there are the same effects as those of the first embodiment and the second embodiment described above.
  • the occupied area can be saved as compared with the case where the writing circuit and the reading circuit are provided separately.
  • FIGS. 15A and 15B show the simulation results in the circuit configuration of the resistance change memory as described above.
  • the resistance change memory element 1401 uses a pure resistance having a resistance value of 80 k ⁇ in the high resistance state and a resistance value of 4 k ⁇ in the low resistance state.
  • Fig. 15 (A) shows a resistance change memory element when off (during power saving), before setting (resistance change memory element 1401 is in a high resistance state), after setting (resistance change memory element 1401 is in a low resistance state).
  • the current flowing through the resistance change memory element 1401 after setting is suppressed to about 100 ⁇ , and the voltage applied to both ends of the resistance change memory element 1401 after reset Is kept below 1.5V.
  • a voltage of about 3. IV can be applied to the resistance change memory element 1401 before setting.
  • the column switch 1304 to include the pMOS transistor 1303, a larger voltage than that in the first embodiment is applied to the resistance change memory element 1401, and the resistance change memory element It can be seen that the applied voltage to 1401 can be improved.
  • FIG. 15B shows the range of the set voltage and the reset voltage of the resistance change memory element 1401 in which the simulation capability is also obtained!
  • the set voltage of the resistance change memory element 1401 is 1.498V or more and 3.135V or less, and the reset voltage is 0. 408V or more 1. 039V or less is required.
  • the set voltage and reset voltage of the resistance change memory element 1401 are within these ranges. If it exists, writing can be performed with the circuit configuration of the resistance change memory as described above. For example, when the reset voltage of the resistance change memory element 1401 is 0.75 V and the set voltage is 1.6 V, writing can be performed with the above-described circuit configuration.
  • the forming voltage of the resistance change memory element 1401 is 1.498V or more and 3.135V or less, the forming can be performed by the setting operation in the above circuit configuration. If the column switch 1304 is configured to include the pMOS transistor 1303 as in the present embodiment, there is an effect that forming is easier than in the first embodiment.
  • the set voltage range is wider than that of the first embodiment. Therefore, the resistance change memory is larger than that of the first embodiment.
  • the set voltage of element 1401 may vary!
  • the present embodiment has been described as a modification of the above-described second embodiment, the present embodiment is not limited to this.
  • the present embodiment is applied to the above-described first embodiment. It ’s all right.
  • the gate width required for each transistor may be set so as to increase in proportion to the reset switching current.
  • the gate width of all transistors can be set to increase at the same rate in proportion to the reset switching current.
  • Fig. 16 (A) shows the reset switching current created based on this concept.
  • the gate width conversion coefficient a can also be regarded as the gate width of the selection transistors 1402 and 1412. This relationship can be expressed by the following equation.
  • Gate width conversion coefficient a 4.00 (/ mA) X reset switching current
  • FIG. 16B shows the relationship between the reset switching current (mA) and the gate width of the nMOS transistors 1301 and 1311 constituting the write or multi-function pMOS transistor 1101 and the column switches 1304 and 1314 (pMOS transistor 1101 and The reset switching current dependence of the gate width of the nMOS transistors 1301 and 1311 constituting the column switches 1304 and 1314 is shown. This relationship can be expressed by the following equation.
  • nMOS transistor gate width for writing or multi-function pMOS transistor and column switch 48.0 ( ⁇ m / mA) X reset switching current
  • the data (information) stored in the resistance change memory elements 1401 and 1411 is read from the primary output node 1206 via the plurality of bit lines 1302 and 1312.
  • the primary output node 1206 For example, when configuring as a large-capacity memory, read It is preferable to provide a drive circuit outside the primary output node 1206 in order to increase the protruding speed.
  • each of the memory blocks 1701 to 1708 is divided into a multi-function pMOS transistor 1101, one or a plurality of bit lines, one or a plurality of column switches, and a plurality of sub-blocks including a plurality of memory cells.
  • the driver circuit may be provided so as to be connected to the primary output nodes 1206-1 to 1206-4 of the sub-blocks 1701-1 to 1701-4.
  • the nodes connected to control the gate potential of the transistors constituting the column switch are common to the column switches provided in one sub-block.
  • the drive circuit includes a plurality of inverters connected to each of the primary output nodes 1206-1 to 1206-4 of each of the sub-blocks 1701-1 to 170 1-4. 1801 to 1804 and a plurality of transmission gates 1851 to 1854 connected to each of the inverters 1801 to 1804, and the primary output nodes 1206 to 1 of each of the sub blocks 1701-1 to 1701-4 1206-4 forces Connected to one output node 1841 through each inverter 1801 to 1804 and each transmission gate 1851 to 1854.
  • the outputs from the primary output nodes 1206-1 to 4 are amplified by the inverters 1801 to 1804 and output from the output node 1841.
  • the parasitic capacitance of the output node 1841 is driven by each of the inverters 1801 to 1804, for writing or reading included in each of the sub-blocks 1701-1 to 1701-4. This is not the circuit (see Figure 10).
  • the transmission gates 1851 to 1854 are composed of nM OS transistors 1811 to 1814 and pMOS transistors 1821 to 1824, respectively, and each of the nodes GCL0 to GCL0 to Connected to GCL3.
  • the nodes GCL0 to GCL3 are connected to the pMOS transistors 1821 to 1824 via the inverters 1831 to 1834, and the control signals from the nodes GCL0 to GCL3 are logically inverted and input.
  • any one of the nodes GCL0 to GCL3 of the control circuit becomes "H", and any one of the plurality of transmission gates 1841 to 1844 is selected, Any one of the paths connecting the primary output nodes 1206-1 to 1206-4 and the output node 1841 is conducted.
  • one bit line included in the sub-blocks 1701-1 to 1701-4 is selected by the transmission gates 1851 to 1854 and the column switches 1304 and 1314.
  • one of the multi-function pMOS transistors 1101 included in each of the sub-blocks 1701-1-1 to 1701-4 is in the read mode (that is, the potential of the node XWE0 becomes the set potential at the time of reading) Otherwise, the power saving mode is set (that is, the potential of the node XWE0 is controlled to the set potential at the time of power saving). As a result, any one of the sub-blocks 1701-1 to 1701-4 is selected.
  • the force that causes data (information) to be read from the primary output nodes 1206 to 8206 of the memory blocks 1701 to 1708 for example, as shown in FIG.
  • Output buffers (read buffers) 1901 to 1908 may be provided so as to be connected to the primary output nodes 1206 to 8206 of the memory block.
  • the data read from each of the memory blocks 1701 to 1708 is temporarily stored in the reading output 1901 to 1908 from the primary output node 1206 to 8206, and is referred to from the outside when necessary. Can be.
  • FIG. 18 Note that a configuration in which such a read buffer is provided (see FIG. 18) can be combined with a configuration in which the above-described driving circuit is provided (see FIG. 17).
  • the primary output node 1206 of the memory block 1701 is replaced with the output node 1841 of FIG. 17, and similarly, the primary output nodes 2206 to 8206 of the other memory blocks 1702 to 1708 are also shown in FIG. It replaces the output node corresponding to 17 output nodes 1841.
  • control circuit 1357 that controls the gate potential of the multi-function pMOS transistor 1101 and the control circuit 1358 that controls the gate potential of the column switches 1304 and 1314
  • control circuit in the first and second embodiments described above may be configured similarly.
  • the present invention is applied to ReRAM as an example.
  • the resistance change memory using resistance change is not limited to this, for example, a phase change memory (PRAM)
  • PRAM phase change memory
  • MRAM magnetoresistive memory

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Abstract

L'invention concerne une mémoire à changement de résistance qui comporte une pluralité de blocs de mémoire (1701) et une ligne de mots (WL0). Les blocs de mémoire (1701) comprennent une pluralité de lignes de bits (1302, 1312); un seul transistor (1101) ayant une fonction de limitation du courant; une pluralité de commutateurs de colonnes (1301, 1311); une pluralité d'éléments de mémoire à changement de résistance (1401, 1411); et une pluralité de transistors de sélection (1402, 1412). Le transistor ayant la fonction de limitation du courant est placé entre une ligne de bits et une alimentation. Chacun des commutateurs de colonnes est placé sur une ligne de bits respective et comprend un transistor de blocage respectif ayant pour fonction de fixer le potentiel de la ligne de bits à une valeur prédéterminée ou une valeur inférieure à cette dernière. Les éléments de mémoire à changement de résistance sont reliés aux lignes de bits respectives, tandis que les transistors de sélection sont reliés à ces éléments de mémoire à changement de résistance respectifs. La ligne de mots relie les transistors de sélection qui sont intégrés dans les blocs de mémoire respectifs.
PCT/JP2006/321140 2006-10-24 2006-10-24 Mémoire à changement de résistance WO2008050398A1 (fr)

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JP2011523488A (ja) * 2008-05-09 2011-08-11 マイクロン テクノロジー， インク． 逆バイアス漏れを緩和するシステム及び方法
JP2012502401A (ja) * 2008-09-09 2012-01-26 クゥアルコム・インコーポレイテッド 抵抗に基づいたメモリアプリケーションのためのメモリデバイス
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011523488A (ja) * 2008-05-09 2011-08-11 マイクロン テクノロジー， インク． 逆バイアス漏れを緩和するシステム及び方法
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TWI421866B (zh) * 2008-05-09 2014-01-01 Micron Technology Inc 減輕反向偏壓漏電之系統和方法
JP2012502401A (ja) * 2008-09-09 2012-01-26 クゥアルコム・インコーポレイテッド 抵抗に基づいたメモリアプリケーションのためのメモリデバイス
JP2013178869A (ja) * 2008-09-09 2013-09-09 Qualcomm Inc 抵抗に基づいたメモリアプリケーションのためのメモリデバイス
US11077037B2 (en) 2013-06-28 2021-08-03 L'oreal Stable cosmetic composition containing a monoglyceride, a tartaric ester of monoglyceride, and a coated filler

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