WO2008029361A1

WO2008029361A1 - Integrated circuit and use thereof

Info

Publication number: WO2008029361A1
Application number: PCT/IB2007/053579
Authority: WO
Inventors: Aarnoud Roest; Mareike Klee; Ruediger Mauczok; Michael Joehren
Original assignee: Nxp B.V.
Priority date: 2006-09-06
Filing date: 2007-09-05
Publication date: 2008-03-13
Also published as: WO2008028660A2; WO2008028660A3

Abstract

The integrated circuit comprises an input structure and an output structure, which input structure comprises an input for receiving said an analog signal with an input voltage, an ESD protection element and a passband filter and which output structure comprises a first and second parallel channel so as to be differential, each channel comprising a coupling capacitor and an output for transmitting the filtered analog signal with an output voltage lower than a prescribed limit. The coupling capacitors are ferroelectric capacitors with a capacitance dependent on a bias voltage, said voltage dependence being substantially symmetric around a maximum capacitance, and being substantially independent of application of transient peak bias voltages and wherein the input voltage as amended by the input structure acts as the bias voltage.

Description

INTEGRATED CIRCUIT AND USE THEREOF

FIELD OF THE INVENTION

The invention relates to an integrated circuit for protection of an external component, that is in use coupled to at least one output, and for filtering of analog signals of certain input voltages, which circuit comprises an input for receiving said an analog signal with an input voltage, an ESD protection element and a passband filter and an output for transmitting the filtered analog signal with an output voltage lower than a prescribed limit.

BACKGROUND OF THE INVENTION

Such an integrated circuit is known from WO-A 2006/008680. As explained in the known document, ESD protection is needed for a variety of components within a mobile phone. A second application class of the integrated circuits involves the connection to a voice band codec in particular, and to analog signals more in general. Specific audio interfaces include the interface to a speaker, from a microphone and to system connectors. Specific filtering is desired here in order to remove induced signals from long cables, demodulate induced signals by non- linear elements, provide channel resistance in order to match differential channels and allow biasing. Some of these filtering tasks are met in that the filter is specifically a filter with a π-type topology. Additionally, the integrated circuit suitably comprises resistors. The protection elements are herein preferably diodes and more preferably Zener diodes. They are designed to withstand very high ESD pulses of 8 kV or more as measured in accordance with the Human Body Model. These high requirements form a barrier to commercially attractive and technologically achievable integration with other circuits, such as memories, amplifiers, transceivers, microprocessors and the like as conventionally made in CMOS technology.

For the use of such circuits for analog signals, and for audio and video signals in particular, requirements are gradually increasing. Such higher requirements are for instance that the allowable third order harmonic distortion is reduced, to for instance at most 0.1%. The Hifϊ-norm prescribes - 60 dBr for stereo and the GSM standard requires - 74 dBr for a microphone. Similar norms are set for other standards. The higher requirements are either needed for better performance or for using cheaper external components. Additionally, the increasing number of components in for instance a mobile phone requires that neither the components, nor any signals to or from the components interfere with each other.

However, it is not evident that integrated circuits can meet such requirements. Minor deviations or variations in the design or technology may already generate noise or distortion. Moreover, this requirement has to be met over a fairly large temperature range from between approximately minus 30 degrees up to 80 degrees Celsius. As a skilled person is well aware, filters comprise capacitors and resistors of which the values are dependent on temperature. Besides, manufacture without spread is virtually impossible. And this variation tends to become more problematic for meeting higher requirements, particularly if standard engineering constraints such as cost and size are taken into consideration.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an integrated circuit of the kind mentioned in the opening paragraph that is able to meet such higher requirements at least to acceptable levels.

This object is met in that the integrated circuit comprises an input structure and an output structure. The input structure comprises an input for receiving said an analog signal with an input voltage, an ESD protection element and a passband filter. The output structure comprises a first and second parallel channel so as to be differential, each channel comprising a coupling capacitor and an output for transmitting the filtered analog signal with an output voltage lower than a prescribed limit. The coupling capacitors are ferroelectric capacitors with a capacitance dependent on a bias voltage, said voltage dependence being substantially independent of the application of a transient peak bias voltage, and wherein the input voltage as amended by the input structure acts as the bias voltage. The required property will also be referred to as a symmetry requirement. In fact, one may distinguish several types of symmetry. First of all, there may be a symmetry of the voltage dependence of the capacitance around the maximum capacitance. This kind of symmetry is highly preferred, but not strictly necessary for the invention, as will be explained in the following. Secondly, there may be a symmetry of the voltage dependence of the capacitance around zero bias voltage. Suitably, this is combined with the first kind of symmetry. However, this kind of symmetry is not strictly needed in which the circuit carries a (modulated) DC voltage (e.g. a DC voltage with certain AC voltage on top of it), which has always the same polarity (e.g. is always larger or smaller than 0 volt). And else, because it can be measured, lack of symmetry of this kind may be compensated through design measures.

Thirdly - and this is the important kind of symmetry - there is a symmetry as a consequence of the application of transient peak bias voltages. These voltages are short peaks of large voltage, for instance larger than 15 V or smaller than -15 V. In the context of the present application, they are assumed to the ESD pulses. If there is no symmetry, poling of the ferroelectric capacitor will occur that leads to a permanent change in the capacity. For instance, if a voltage peak of 20 V is applied, the capacitance at 0 V bias voltage may thereafter be reduced with 20%. A voltage peak of - 20 V however may have the opposite effect of increasing the capacitance at 0 V bias voltage. If this kind of symmetry is present, a voltage peak of negative voltage will have the same effect as a voltage peak of positive voltage. Hence, after a first initialisation with a large voltage peak, the voltage dependence of the capacitance will not change anymore in use due to such voltage peaks.

According to the invention, the circuit is provided with a differential output structure having at least two channels in which capacitors are provided. The use of a differential output structure allows an output with a higher quality, in that the signals from the first and the second channel can be compared in for instance a differential amplifier. Such amplifier is conventionally part of the external component, i.e. another integrated circuit, to be protected. Evidently, the use of such differential structure requires that corresponding elements within the parallel channels have been matched to each other, so as to prevent generation of unexpected noise. If not, then the problem of common mode rejection may turn up at low frequencies, such as frequencies that can be heard by a human ear. The third order harmonic distortion is particularly relevant for higher frequencies. Here, it is observed that this distortion may be amplified due to particularly non-linear signal processing in the external component. This distortion is particularly problematic in as far as it cannot be predicted. Due to this subsequent signal processing third order harmonic distortion may even be a problem for noise in the output structure of relatively low frequencies.

Such risk of distortion may be decreased by designing the coupling capacitors with a large capacitance, for instance of several nF. In order to design such capacitors cost- effectively, use may be made of capacitor shapes or dielectric materials that allow a large capacitance density. These capacitors nevertheless need to have a sufficiently high breakdown voltage to withstand voltages transmitted by an ESD pulse. Although protection elements take away a larger portion of an ESD pulse, the voltage flowing through the integrated circuit is nevertheless high. Additionally, it has to be a Metal-insulator-metal (MIM) type capacitor in order to design it as a floating capacitor with two metallic contacts. The implementation according to the invention resides in the use of ferroelectric capacitors. It has been observed, however, in experiments leading to the invention, that the voltages flowing through the integrated circuit after an ESD pulse, may have dramatic and hardly predictable impact on the capacitance of standard ferroelectric capacitors, such as currently commercially available (Al electrode with barrier layer or Irθ₂-electrode), and are thus asymmetric. ESD pulses may be of different polarity, i.e. either have a negative voltage or a positive voltage. The resulting voltage in the circuit may rise to levels of 15 V or even higher, or -15V or even lower. This then brings the ferroelectric capacitor in another state and induces changes in the capacity in the order of up to 50%. Since the first and the second channel are usually not identical - they have for instance a different resistance -, the effect on an ESD pulse on the capacitor in the first channel may be different than the effect on the capacitor in the second channel. And then, there is still distortion that is unpredictable. Now, in the invention, this problem has been solved in that the ferroelectric capacitors have a capacitance with a voltage dependence that is substantially symmetric around a bias voltage of zero volt. The actual voltage, which is the input voltage as amended by the input structure, and possibly further amended, is herein the bias voltage.

Suitably, the voltage dependence is such that the variation of the capacitance at a bias voltage of 0 volt is at most 10% after passing of a transient peak bias voltage of 10 V or- 10 V. The term 'transient peak bias voltage' is herein used to describe the voltage flowing through the integrated circuit after an ESD pulse.

More suitably, the variation of the capacitance at a bias voltage of 0 volt is at most 10% after passing of a transient bias voltage of 20 V or- 20 V. Even more suitably, the variation is less than 5 % or even less than 1% after passing of such transient bias voltage of 20 V or -20V.

Advantageously, the capacitor is a stacked capacitor, in which an intermediate electrode is embedded in a dielectric between a bottom and top electrode. The intermediate electrode will herein be input and the top and the bottom electrode together form output of the capacitor, or vice versa. It has been found that such a stacked capacitor fulfils such symmetry requirements better than non- stacked capacitors. Even though the bottom and top electrode of a non-stacked capacitor may be made of the same material, interface charges, processing steps and the material of the underlying substrate tend to give a certain asymmetry. Apparently, the charge flow in opposite directions within a stacked capacitor cancels such asymmetry to a substantial extent. This cancelling effect is found to extend relatively far. Even a stacked capacitor, in which the bottom electrode is made from another material than the top electrode, shows nevertheless an adequately symmetric behaviour in the bias voltage dependence of its capacitance. It is herein preferable that the intermediate electrode has a workfunction between that of the bottom electrode and the top electrode. Particularly, herein, the bottom and center electrode comprise a noble metal, whereas the top electrode comprises another material. An examples is the use of platinum (Pt) for the bottom and center electrode and TiW or TiWN for the top electrode.

It is preferable that any capacitors that form part of the passband filter in the input structure, and in any passband type filter that may be present in the output structure, are also ferroelectric capacitors. This enables better process integration, e.g. one layer of dielectric material may be used in several capacitors. It is herein a possibility to design such capacitors with a higher breakdown voltage. This can be achieved in that a stacked capacitor is provided with a first branch and a second branch. The first branch is herein designed with a floating electrode or without intermediate electrode and with a shorter RC time constant than the second branch. Therefore, a pulsed voltage peak will substantially follow the first branch. The second branch will here be provided as a stacked capacitor. Evidently, the second branch can be left out, but this is rather disadvantageous for the capacitance density. It is observed here for clarity that the voltage dependence is not so much a problem for such passband capacitors. These have to filter out signals above a certain cut-off frequency. If the capacitance changes as a consequence of a transient bias voltage, the cut-off frequency might change slightly. However, generally, there is a plurality of filters to improve the filtering.

In a further embodiment, the ferroelectric capacitors comprise a lead- containing dielectric between a bottom and a top electrode, while a lead-donating layer is present on a reverse side of said bottom and/or said top electrode. Such dielectrics are for instance PbZr^_xTi_xO₃ and Pbi__yLa_y Zr^_xTi_xO₃ with 0.00 < y < 0.20 and 0.00 < x < 1.0. Other materials include PbMgo.33Nbo.67O3 as mixed with any of the above mentioned materials or optionally any other ferroelectric material. The materials are suitably applied with sol-gel processing. Further materials will be apparent to the skilled person in the field. It has been found that the presence of a lead-donating layer on or under the ferroelectric capacitor strongly increases the capacitance density. An increase of about 30% was achieved with the application of a lead-donating layer below the ferroelectric capacitor. Optionally, the bottom electrode is patterned such that the lead-donating layer and the dielectric have a mutual interface on more than one side of the bottom electrode. This may further improve the mechanical stability of the materials stack, particularly under the influence of thermal, mechanical or thermomechanical stress. Such stress may be due to the presence of solder balls on top of the capacitor.

In another embodiment of the integrated circuit according to the invention, it further comprises a voltage supply line coupled to the input structure for provision of an operating voltage to a second external component that is in use coupled to the input of the integrated circuit, which voltage supply line is connected to the channels of the differential output structure. Suitably, the external component is designed such that a calibration of the ferroelectric coupling capacitors is enabled, when in use the - first - external component is coupled to the outputs of the output structure. This embodiment allows a further control of the coupling capacitors with a calibration step.

Advantageously, switches and additional capacitors are provided within the integrated circuit so as to tune the coupling capacitors prior to use or even during use. Varactors or even MEMS capacitors may be used alternatively, if made with appropriate breakdown voltages. As long as not connected, such capacitors are not facing any high voltage. Thus even ferroelectric capacitors could be used, although capacitors with a non- ferroelectric dielectric such as silicon oxide, silicon nitride, titanium oxide or the like appear suitable as well. In one suitable embodiment, such further capacitor can be embodied directly on top of the ferroelectric capacitor, such that the top electrode forms one of the electrodes of the additional capacitor. Switches can achieve that this additional capacitor is either not connected or connected in parallel or connected in series to the ferroelectric capacitor.

An alternative advantage of the embodiment of the invention with the additional supply line is the option of differential operation. The symmetric behaviour of the coupling capacitors of the invention are very beneficial for common mode suppression, and enable the use of amplifiers with variable amplifier voltage. Such amplifiers are particularly part of an external component coupled to the output. A variable amplifier voltage is desired to improve gain control. However, therewith there is no knowledge beforehand, whether a positive or a negative voltage is applied on the coupling capacitor. However, due to the symmetric behaviour, this lack of knowledge is not relevant anymore. Suitably, the integrated circuit comprises a second input structure and a second output structure, which are substantially identical to the - first - input structure and output structure respectively, so as to enable transmission of stereo analog signals. Actually, this constitutes a second circuit within the same integrated circuit that is usually isolated from the first circuit. BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be further explained with reference to the Figures, in which: Fig. 1 shows an electrical diagram of the integrated circuit, and

Fig. 2 shows a cross-sectional drawing of the integrated circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Fig. 1 shows an electrical diagram of the integrated circuit in one embodiment. This embodiment is designed for a microphone. The circuit comprises an input structure 50 and an output structure 70. The input structure 50 is provided with an input (MiCin), a protection element D and a pass band filter 52. The protection element D is in this example a diode. A Zener diode is a suitable embodiment, particularly in combination with a connection to a good-conducting substrate zone. This enables a rapid removal of large voltage peaks and the associated heat. Most suitable is the use of a back-to-back diode as the protection element D. The pass band filter, in this case a low pass filter, is a π-type filter comprising a first and a second capacitor Cl, C2 and a resistor Rl. The capacitors Cl, C2 are connected between the supply line and the ground.

The output structure 70 is differential and comprises a first channel 71 and a second channel 72. The first channel 71 comprises a coupling capacitor C6, an output MicP and further a filter 73. This filter is a π-type filter comprising capacitors C2, C4 and a resistor R3. The second channel 72 comprises a coupling capacitor C7, an output MicN and another filter. This filter is a π-type filter comprising capacitors C3, C5 and a resistor R4. These capacitors have for instance a capacitance of 1 nF, while the capacitors C6, C7 have a capacitance of 6 nF. These values are however open to optimisation and dependent on a specific application. It however appears suitable that the coupling capacitors C6, C7 have a larger capacitance than the filtering capacitors C1-C5. The second channel 72 further comprises a resistor R2, which acts as a delay line and/or current divider.

The circuit further comprises a voltage supply line 80. This voltage supply line is provided with an input (Bias), and extends to the input structure 50 while passing the resistor R2 in the second channel 72 of the output structure 70. The channels 71, 72 of the output structure and the voltage supply line 80 are all provided with protection elements D2. These are needed to protect the circuit against ESD pulses entering from the side of the output, for instance during assembly. The protection elements D2 are furthermore desired to take away any voltage peaks that have been flowing through the integrated circuit. Even though the integrated circuit may reduce the ESD pulse from 100 V to 10 V and take away 99% of its intensity, the 10V peak may still be higher than acceptable in the external component. Such additional protection D2 may however not be needed everywhere. The voltage supply line 80 supplies a voltage to the microphone. This microphone is an external component (not shown) that is coupled to the input MiCin. The voltage supply line is driven through its input Bias from another external component. This external component is suitably an integrated circuit with driver functionality. The external component is further suitable to process the signals transmitted by the differential output structure. In this embodiment the voltage supply line supplies a DC signal while the line from input to output transmits an AC signal.

In the present invention, the coupling capacitors C6, C7 are ferroelectric capacitors with a capacitance dependent on a bias voltage, said voltage dependence being substantially symmetric around a bias voltage of 0 volt, and wherein the input voltage as amended by the input structure acts as the bias voltage.

Fig. 2 shows an example device of the invention. It is not in any case meant to be limiting, and it is purely diagrammatical. For the manufacture of an electronic component as shown in Fig. 1, a semiconductor substrate 1 was provided with first semiconductor regions 2 and second semiconductor regions 3. The substrate 1 was doped with B as the dopant of a first doping type. The first semiconductor regions 2 were doped with B in a lower doping density. The second semiconductor regions 3 were doped with P as the dopant of the second doping type. An insulating layer 4 of for instance SiO₂ , Si3N4 or a combination of Si3N4 and SiO2 is provided on the semiconductor substrate 1. The insulating layer 4 can be covered by a barrier layer 5 of TiO₂ or ZrO₂ or Al₂θ3 or MgO or a combination of Si3N4 and TiO₂. Particularly TiO₂ is suitable.

Preferably, although not shown, a lead-donating layer is provided thereon. Such lead-donating layer suitably comprises a material such as leadoxide, leadcarbonate, leadtitanate, leadzirconate-titanate, leadlanthanate-zirconate-titanate, leadzirconate. Preferably, use is made of the same material as for the first dielectric layer. The ferroelectric capacitor with such lead-donating layer is found to have a substantially higher capacity, for instance 30% higher. This comparison is made such that the thickness of the dielectric between the top and bottom electrodes was equal in both ferroelectric capacitors. This enables the provision of integrated circuits with protection elements, such as diodes, and filters, include filters with π-type topology, that fulfil several apparently conflicting requirements: first of all, a sufficiently high capacitance density, and thus a product with proper functionality in limited size; secondly, an adequate breakdown voltage against ESD pulses; thirdly, a capacitor that may be used in circuits carrying a higher DC voltage than the common 3 V, for instance 6 V. Thereon, a patterned, first electrically conductive layer 6 is provided, for instance comprising Pt with a layer thickness of 50 nm to 1 μm. Other metals may be used alternatively. Additional layers, for instance of Ti, may be present for improvement of adhesion. Other metals and metal stacks may be used alternatively such as , TiW/Pt, Ta/Pt, W, Ni, Mo, Au, Cu, Ir, IrO2/Ir, Ti/Pt/Al, Ti/Ag, Ti/Ag/Ti, Ti/Ag/Ir, Ti/Ir, Ti/Pd, Ti/Agi__xPt_x (0 < x < 1), Ti/Agi__xPd_x (0 < x < 1), A_gl._xPt_x (0 < x < 1), Ti/Pti__xAl_x (0 < x < 1), Pt₁^Al_x (0 < x < 1), Ti/Ag/Pti__xAl_x (0 < x < 1), Ti/Ag/Ru, Ru, Ru/RuO₂, Ti/Ru, Ti/Ir, Ti/Ir/IrO₂, Ti/Ru/Ru_xPti__x (0 < x < 1), Ti/Ag/Ir/IrO_x (0 < x < 2), Ti/Ag/Ru/RuO_x (0 < x < 2), Ti/Ag/Ru/Ru_xPti__x (0 < x < 1), Ti/Ag/Ru/Ru_xPWRuO_y (0 < x < 1, 0 < y < 2), Ti/Ag/Ru/RuO_x/Ru_yPti__y (0 < x < 2, 0 < y < 1), Ti/Ag/Ru_xPti__x (0 < x < 1), Ti/Ag/Pt_xAli__x (0 < x < 1), PtxAWAg/PtyAli-y (0 < x < 1, 0 < y < 1), Ti/Ag/Pty(RhO_x)i__y (0 < x < 2, 0 < y < 1), Ti/Ag/Rh/RhO_x (0 < x < 2), Rh, Rh/RhO₂, Ti/Ag/Pt_xRhi__x (0 < x < 1), Ti/Ag/Pt_y(RhO_x)i_ _y/Pt_zRhi__z (0 < x < 2, 0 < y < 1, 0 < z < 1), Ti/Ag_xPWIr (0 < x < 1), Ti/Ag_xPti__x/Ir/IrO_y (0 < x < 1, 0 < y < 2), Ti/AgxPti-x/PtyAli-y (0 < x < 1, 0 < y < 1), TiZAg_xPt₁. _X/Ru (0 < x < 1), Ti/A_gxPti__x/Ru/RuO_y (0 < x < 1, 0 < y < 2), Ti/Ag/Cr, Ti/Ag/Ti/ITO, Ti/Ag/Cr/ITO, Ti/Ag/ITO, Ti/Ni/ITO, Ti/Rh, Ti/Rh/RhO₂. The first electrically conductive layer 6 comprises first electrodes of a first and a second capacitor, as will be shown and explained in more detailed with reference to the Figures 2-4. A top view corresponding to the Fig. 2 is shown in Fig. 5. A top view of a device similar to that of Fig. 4 is shown in Fig. 6. Electrical diagrams corresponding to Fig. 1 are shown in Figs. 7-9. A first dielectric layer 7 is present on the first electrically conductive layer 6, as well as on the barrier layer 5, where the first conductive layer 6 is absent. . A preferred example is a complex oxide layer 7, for instance a ferroelectric layer of Pbi__yLa_yZri__xTi_xθ3, with 0.00 < y < 0.20 and 0.0 < x < 1.0. Other complex oxide layers having a relatively high dielectric constant are known to the skilled person and include materials such as bariumstrontiumtitanate, leadtitanate-leadmanganese-niobium. Other materials such as tantalumoxide, hafniumoxide or silicon nitride could be used alternatively. A list of suitable materials has been disclosed in WO-A 02/75780. A nucleation layer with another composition that the first dielectric layer 7 may be applied on the first conductive layer 6 so as to improve adhesion. A suitable nucleation layer is for instance a layer of titanium oxide, PbZri__xTi_xθ3 or Pbi__yLa_yZri__xTi_xθ3, with x and y in the same range as mentioned above.

An intermediate electrode layer 16 is provided on the first dielectric layer 7 and covered with a second dielectric layer 17. The patterns in this intermediate electrode 16 include an intermediate electrode of the second capacitor, and optionally a floating electrode in the first capacitor. Suitably, also the second dielectric layer 17 comprises a complex oxide layer, and more suitably, this is - at least for the major part - the same as the material as that of the first dielectric layer 7. Use of the same material is understood to provide a most regular structure of the dielectric and therefore preferred. The structure of the dielectric influences both the breakdown and dielectric properties positively. Use of another nucleation layer is not excluded. The material of this intermediate electrode layer 16 is preferably the same as that of the first conductive layer 6. Adhesion layers for the intermediate electrode are most likely not be used but could be used, if necessary. The growth of the (poly)crystalline ferroelectric layers is dependent on the substrate structure. A floating electrode would therefore be undesired, in that adjacent portions of the dielectric have a different support. However, it is believed that with the use of the same material for first conductive layer and intermediate layer, the structure of the dielectric on the floating electrode and adjacent to the floating electrode will be the very similar or even identical.

With the use of a complex oxide layer as the dielectric layers 7,17, use of Pt as electrode material is preferred. With alternative sintering techniques, particularly with post- treatments under reducing atmosphere, other metals such as Cu, Ag or Ni can be applied as for the conducting layers 6,16. Conducting oxides such as RuOx or IrO2 or conductive oxides with perovskite lattice such as La,SrRuO3 constitute another suitable alternative. Particularly, when the complex oxide layers are provided in a wet-chemical manner, such as with sol-gel technology, the structure of the layers has been found to be very good, and also the adhesion is excellent.

Contact holes reaching down to the semiconductor substrate 1 were made after the etching of the first and the second dielectric layers 7, 17, with conventional etchant that are specific for the layers. The contact holes were filled with a conductive material, such as Al, Cu, Pt or an alloy of Al and Cu or of Al and Si or combinations of Ti and Al or Ti and Cu or Ti and an alloy of Al and Cu or of Ti and Al and Si or combinations of TiW and Al or TiW and Cu or TiW and an alloy of Al and Cu or of Al and Si or combinations of TiW or TiWN - both also referred to as TiW(N) - and Al or TiW(N) and Cu or TiW(N) and an alloy of Al and Cu or Al and Si or combinations of TiN and Al or TiN and Cu or TiN an alloy of Al and Cu or of Al and Si to provide first, second and third supply leads 8,9,19. In this embodiment, use is made of TiW(N) and Al.

The conductive material was also provided on top of the complex oxide layer 17 to form a second electrically conductive layer 10, in which the second electrode of the capacitor is defined. Particularly in case that Cu is used as the conductive material, an additional barrier layer, for instance of TaN or TiN, may be provided between the complex oxide layer 17 and the second electrically conductive layer 10. The use of TiW(N) and Al was found to have an appropriate symmetry behaviour. If desired, an additional Pt electrode can be provided between the complex oxide layer 17 and the TiW(N) layer. It is further possible to apply another lead-containing layer on top of the top electrode. This lead- containing layer may function both as a hydrogen-barrier for the improvement of the stability of the electrode, in case Pt is used as electrode material, as well as to counteract degradation of the lead-containing complex oxide layer.

Hereon, a passivation layer 11 , in this case of silicon nitride is present. The passivation layer 11 is provided with contact holes 12, 13 defining in 12, out 13 and the ground contact 15 of the circuit. Metal or solder bumps are provided to the contact in known manner.

Claims

CLAIMS:

1. An integrated circuit for protection of an external component, that is in use coupled to at least one output, and for filtering of analog signals of certain input voltages, which circuit comprises an input structure and an output structure, which input structure comprises an input for receiving said an analog signal with an input voltage, an ESD protection element and a passband filter and which output structure comprises a first and second parallel channel so as to be differential, each channel comprising a coupling capacitor and an output for transmitting the filtered analog signal with an output voltage lower than a prescribed limit, which coupling capacitors are ferroelectric capacitors with a capacitance dependent on a bias voltage, said voltage dependence being substantially independent of application of transient peak bias voltages and wherein the input voltage as amended by the input structure acts as the bias voltage.

2. The integrated circuit as claimed in claim 1, wherein the variation of the capacitance at a bias voltage of 0 volt is at most 10% after passing of a transient bias peak voltage of 10 V or - 10 V.

3. The integrated circuit as claimed in claim 2, wherein the variation of the capacitance at a bias voltage of 0 volt is at most 10% after passing of a transient bias voltage of20 V or- 20 V.

4. The integrated circuit as claimed in claim 1, wherein the capacitor is a stacked capacitor, in which an intermediate electrode is embedded in a dielectric between a bottom and top electrode.

5. The integrated circuit as claimed in claim 4, wherein the passband filter comprises ferroelectric capacitors.

6. The integrated circuit as claimed in claim 1, wherein the ferroelectric capacitors comprise a lead-containing dielectric between a bottom and a top electrode, while a lead-donating layer is present on a reverse side of said bottom and/or said top electrode.

7. The integrated circuit as claimed in claim 6, wherein the lead-donating layer is present on the reverse side of the bottom electrode.

8. The integrated circuit as claimed in claim 7, wherein the bottom electrode is patterned so as to be embedded in a body of the lead-donating layer and the lead-containing dielectric.

9. The integrated circuit as claimed in claim 1, further comprising a voltage supply line coupled to the input structure for provision of an operating voltage to a second external component that is in use coupled to the input of the integrated circuit, which voltage supply line is connected to the channels of the differential output structure, therewith enabling a calibration of the ferroelectric coupling capacitors, when in use the - first - external component is coupled to the outputs of the output structure.

10. The integrated circuit as claimed in claim 1, wherein the circuit comprises a second input structure and a second output structure, which are substantially identical to the - first - input structure and output structure respectively, so as to enable transmission of stereo analog signals.

11. Use of the integrated circuit as claimed in any of the preceding claims as a protecting and filtering circuit between a second and a first external component.

12. A method of manufacturing the integrated circuit as claimed in any of the preceding Claims, wherein the coupling capacitors are provided simultaneously by application and subsequent patterning of conducting and dielectric layers