WO2008021024A3 - Multiprocessor architecture with hierarchical processor organization - Google Patents

Multiprocessor architecture with hierarchical processor organization Download PDF

Info

Publication number
WO2008021024A3
WO2008021024A3 PCT/US2007/017347 US2007017347W WO2008021024A3 WO 2008021024 A3 WO2008021024 A3 WO 2008021024A3 US 2007017347 W US2007017347 W US 2007017347W WO 2008021024 A3 WO2008021024 A3 WO 2008021024A3
Authority
WO
WIPO (PCT)
Prior art keywords
hierarchical level
junior
senior
operations
slave processors
Prior art date
Application number
PCT/US2007/017347
Other languages
French (fr)
Other versions
WO2008021024A2 (en
Inventor
Dragos Dudau
Eugene Miloslavsky
Nicolas Cobb
Original Assignee
Mentor Graphics Corp
Dragos Dudau
Eugene Miloslavsky
Nicolas Cobb
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp, Dragos Dudau, Eugene Miloslavsky, Nicolas Cobb filed Critical Mentor Graphics Corp
Priority to EP07811051A priority Critical patent/EP2069958A2/en
Priority to JP2009524613A priority patent/JP2010500692A/en
Publication of WO2008021024A2 publication Critical patent/WO2008021024A2/en
Publication of WO2008021024A3 publication Critical patent/WO2008021024A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Multi Processors (AREA)

Abstract

A computing system is provided that has a multiprocessor architecture. The processors are hierarchically organized so that one or more slave processors at a senior hierarchical level provide tasks to one or more slave processors at a junior hierarchical level. Further, the slave processors at the junior hierarchical level will have a different functional capability than the slave processors at the senior hierarchical level, such that the junior slave processors can perform some types of operations better than the senior slave processors. A master computing process distributes operation sets among one or more computing processes running on a processor at the senior hierarchical level, which will begin executing operations in the operation set. When a process running at the senior hierarchical level identifies one or more operations of the type better performed by a processor at the junior hierarchical level, it provides this operation or operations to a process running on a processor at the junior hierarchical level. After the process running at the junior hierarchical level executes its assigned operation or operations, it returns the results to the process running at the senior hierarchical level to complete the execution of the operation set.
PCT/US2007/017347 2006-08-13 2007-08-03 Multiprocessor architecture with hierarchical processor organization WO2008021024A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07811051A EP2069958A2 (en) 2006-08-13 2007-08-03 Multiprocessor architecture with hierarchical processor organization
JP2009524613A JP2010500692A (en) 2006-08-13 2007-08-03 Multiprocessor architecture with hierarchical processor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82224706P 2006-08-13 2006-08-13
US60/822,247 2006-08-13

Publications (2)

Publication Number Publication Date
WO2008021024A2 WO2008021024A2 (en) 2008-02-21
WO2008021024A3 true WO2008021024A3 (en) 2008-05-15

Family

ID=39082534

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/017347 WO2008021024A2 (en) 2006-08-13 2007-08-03 Multiprocessor architecture with hierarchical processor organization

Country Status (4)

Country Link
EP (1) EP2069958A2 (en)
JP (1) JP2010500692A (en)
CN (1) CN101523381A (en)
WO (1) WO2008021024A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7003758B2 (en) 2003-10-07 2006-02-21 Brion Technologies, Inc. System and method for lithography simulation
JP5326308B2 (en) * 2008-03-13 2013-10-30 日本電気株式会社 Computer link method and system
FR2984557B1 (en) * 2011-12-20 2014-07-25 IFP Energies Nouvelles SYSTEM AND METHOD FOR PREDICTING EMISSIONS OF POLLUTANTS OF A VEHICLE WITH SIMULTANEOUS CALCULATIONS OF CHEMICAL KINETICS AND EMISSIONS
US8959522B2 (en) * 2012-01-30 2015-02-17 International Business Machines Corporation Full exploitation of parallel processors for data processing
US9141631B2 (en) 2012-04-16 2015-09-22 International Business Machines Corporation Table boundary detection in data blocks for compression

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0627682A1 (en) * 1993-06-04 1994-12-07 Sun Microsystems, Inc. Floating-point processor for a high performance three dimensional graphics accelerator
EP0715257A1 (en) * 1994-11-30 1996-06-05 Bull S.A. Tool for assisting the load balancing of a distributed application

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2704663B1 (en) * 1993-04-29 1995-06-23 Sgs Thomson Microelectronics Method and device for determining the composition of an integrated circuit.
US5682323A (en) * 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
JP3981238B2 (en) * 1999-12-27 2007-09-26 富士通株式会社 Information processing device
US6703167B2 (en) * 2001-04-18 2004-03-09 Lacour Patrick Joseph Prioritizing the application of resolution enhancement techniques
US20040083475A1 (en) * 2002-10-25 2004-04-29 Mentor Graphics Corp. Distribution of operations to remote computers
JP2006155187A (en) * 2004-11-29 2006-06-15 Sony Corp Information processing system, information processor and processing method, storage medium and program

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0627682A1 (en) * 1993-06-04 1994-12-07 Sun Microsystems, Inc. Floating-point processor for a high performance three dimensional graphics accelerator
EP0715257A1 (en) * 1994-11-30 1996-06-05 Bull S.A. Tool for assisting the load balancing of a distributed application

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
FRANCOIS CHAROT ET AL: "Toward Hardware Building Blocks for Software-Only Real-Time Video Processing: The MOVIE Approach", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 9, no. 6, September 1999 (1999-09-01), XP011014605, ISSN: 1051-8215 *
S. CHOI ET AL: "Hierarchical heterogeneous multiprocessor system for real-time motion picture coding", VISUAL COMMUNICATIONS AND IMAGE PROCESSING '94, September 1994 (1994-09-01), pages 1777 - 1787, XP002472128, Retrieved from the Internet <URL:http://spiedl.aip.org/getpdf/servlet/GetPDFServlet?filetype=pdf&id=PSISDG002308000001001777000001&idtype=cvips&prog=normal GetPDFServlet (application/pdf Object)> [retrieved on 20080203] *
SHU D B ET AL: "A multiple-level heterogeneous architecture for image understanding", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PATTERN RECOGNITION. ATLANTIC CITY, JUNE 16 - 21, 1990. CONFERENCE A : COMPUTER VISION AND CONFERENCE B : PATTERN RECOGNITION SYSTEMS AND APPLICATIONS, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. VOL. 1 CONF. 10, 16 June 1990 (1990-06-16), pages 629 - 634, XP010020506, ISBN: 0-8186-2062-5 *

Also Published As

Publication number Publication date
WO2008021024A2 (en) 2008-02-21
CN101523381A (en) 2009-09-02
EP2069958A2 (en) 2009-06-17
JP2010500692A (en) 2010-01-07

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