WO2008020266A1

WO2008020266A1 - Method and apparatus for designing an integrated circuit

Info

Publication number: WO2008020266A1
Application number: PCT/IB2006/003067
Authority: WO
Inventors: Kevin Dean Lucas; Robert Elliott Boone; Kyle Patterson
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2006-08-16
Filing date: 2006-08-16
Publication date: 2008-02-21

Abstract

Method and apparatus for designing an integrated circuit by routing connections (210) between features of a first subset of a plurality of features forming an IC layout design of the IC. Performing optical proximity correction, OPC, simulation (220) on the first subset of features and connections such that defects are identified. Routing connections between features of a second subset of the plurality of features.

Description

METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT

Field of the Invention

The present invention relates to a method and apparatus for designing an integrated circuit.

Background of the Invention

When making an integrated circuit (which may also be referred to as an IC, chip or device) , a design layout of the IC is made using, for example, CAD tools. A reticle or mask is then produced for the IC design layout and then photolithography is used to transfer features from the reticle or mask to a die (integrated circuit semiconductor wafer) .

Typically, the designer will build an IC layout design by adding and arranging cells, comprising multiple features, to the IC layout design. Once, the cells have been arranged paths or tracks that will form the electrical connections on the wafer are defined to link the cells together. This process is known as place and route and various software packages dedicated to assisting the IC designer with these specific tasks are available. US 7,069,530 describes the place and route procedures and electronic design automation (EDA) software applications used to automate these processes .

The addition of electrical connection paths is typically achieved by applying a rule based procedure to the IC layout design. As electrical connections have many dependencies on each other it is difficult to process these rules using parallel processing means. As this process is carried out using computer resources the majority of the processing will be carried out on a single processor or a small number of processors even if the computer system has a larger number of processors available. Therefore, in order to manage the processing time it is desirable to restrict the amount of work performed by the place and route software to that necessary to complete the complex tasks of creating the many millions of electrical connections.

Various techniques are used to reduce the level of defects in the resultant die. For instance, prior to the production of the reticle, the IC design layout may be optimised using optical proximity correction (OPC) to create an optimised reticle layout design. OPC is described in more detail in US 5,705,301. Typically, the OPC process involves identification of features that require optimisation. For instance, a rule based approach may be used to find features exhibiting particular properties, e.g. properties that may result in defects when the feature is transferred to the IC wafer. The distortion of features caused by the subsequent manufacturing process, including optical effects, may be simulated by the OPC process. This could include simulating the optical distortions and diffraction effects occurring when transferring the IC layout design on to an IC wafer. These are typically simulated using convolution kernel methods or fast Fourier transform methods. Defects may be identified in the IC layout design should the simulated result fall outside any predetermined tolerances or fail comparison with any other particular criteria. This identification of features requiring optimisation incorporating the use of optical simulations shall be referred. to as OPC simulation and may additionally include the rule based tests and/or the manufacturing simulation steps, which are may also be performed in OPC processes.

After OPC simulation any features containing defects may be optimised in order to ensure that defects are removed or their effects minimised. As discussed in US 5,705,301 the OPC optimisation stage may use various techniques and amends the physical design layout in order to avoid optical or process distortions, also known as patterning defects, when features are transferred from the reticle or mask that may cause failures of the final device. Where distortions are found that are likely to cause failures the OPC optimisation process discretizes the design layout into moveable segments and manipulates these segments until the distortions are minimised so that the risk of failures in the resultant chip is reduced.

The success of the optimisation of a particular feature may be tested by a further OPC simulation step and the process may iterate until the defects are corrected or minimised. These OPC simulation and OPC optimisation processes occur after the place and route stage has been completed.

The OPC process requires significant amounts of computing resources due to the large numbers of features present in the IC layout design which are simulated and optimised in the OPC process. Full OPC of an IC layout design may require tens of hours ^■ or even days to complete. Even after an IC layout design has been optimised and the IC wafer has been manufactured defects may be found when analysing the IC that require repetition of the earlier design, for example, the place and route stage and optimisation stages. Therefore, there is required a method to improve the efficiency of IC design and optimisation. Summary of the Invention

The present invention provides a method and apparatus for designing an integrated circuit as described in the accompanying claims .

Brief description of the Figures

The present invention may be put into practice in a number of ways and an embodiment will now be described by way of example only and with reference to the accompanying drawings, in which:

FIG. 1 shows a scanning electron microscope (SEM) image of part of a wafer including metal electrical connections, given by way of example;

FIG. 2 shows a schematic diagram of a metal connection on an IC layout design, given by way of example;

FIG. 3 shows a flowchart of a method for designing an integrated circuit according to an embodiment of the present invention, given by way of example;

FIG. 4A shows a cross sectional view through an oxide layer on an IC wafer including a trench for receiving metal of an electrical connection, given by way of example; and

FIG. 4B shows a cross sectional view through the oxide layer shown in FIG. 4A additionally including an opening for forming a via, given by way of example. It should be noted that the figures are illustrated for simplicity and are not necessarily drawn to scale.

Detailed description of an embodiment

FIG. 1 shows an SEM image of a portion of an IC wafer 10. The portion shown includes trenches 30 formed in an oxide layer 20 that may be filled with a metal to produce an electrical connection. Trench 30 also has a via 40 located on it that may be used to provide an electrical connection between the trench 30 (after filling with metal) and another layer (not shown) of the IC.

FIG. 2 shows a portion of an IC layout design 100 having an electrical connection point 130 connecting two tracks 110, 115. This electrical connection 130 was generated during a place and route procedure . In order to avoid a weak connection caused by a shortened track a jog 120 has been used to extend the length of track 110. This ensures that any track shortening caused by optical effects, for instance, when the wafer is manufactured does not lead to a weak or missing connection. However, this resultant structure may lead to a line breakage occurring at point 140. This potential failure point will only be detectable after OPC simulation of the feature, which in prior art methods, is only carried out once all of the cells have been placed and the connection routing completed.

FIG. 3 shows an embodiment of the method according to the present invention. This method commences after cells or features have been placed in the IC layout design, i.e. the first stage of the place and route procedure. First, a subset of features within the IC layout design are considered and desired connections relating to this subset of features are defined and routed 210 and added to the IC layout design. The routing step may be carried out by routing software.

The connections may be represented only in an internal data format of the routing software. A typical memory efficient internal data format may be used to store the connection in memory as the vertices of a fixed width path (or track) between two endpoints on a course grid of allowed path placements. Many thousands of connections between pairs of endpoints are typically required in a routing step. The routing process may start with a pair of two endpoints which are desired to be connected. A path between this first pair of endpoints may be routed and then the router proceeds to the next pair of endpoints, etc., until all endpoint pairs are suitably connected or the routing step otherwise terminates. Routing software typically uses complex heuristics to determine the sequential order in which the endpoint pairs should be connected and also the method by which a connection between two endpoints is attempted.

During or after this routing step OPC simulation of the features associated with these connections is performed 220. OPC software typically has a different internal data format than is used in routing software. For example, the OPC software may use a more flexible (but memory intensive) internal format which does not limit the layout features to be on a course grid. Therefore, before OPC simulation or optimisation of the routed features can be performed, a layout data format translation step may need to be performed. Any defects identified by the OPC simulation process may be corrected, for example, during the subsequent OPC optimisation step 230 including the placing and manipulation of segments including serifs. Defects which are found to not be correctable during OPC may be corrected by modifying the routed path containing the defect. For example, the path containing the defect may be removed and a different path connecting the endpoints may be routed. In another example, the path containing the defect may be modified (e.g., widened) to make it more, manufacturable. OPC simulations may be performed on the final path to ensure it will pattern acceptably on the wafer. After the initial first group of connections have been processed by the OPC processes further connections may be routed 240. The first group of connections may be associated with a small portion of the IC layout design or alternatively, form a greater number of connections associated with a larger portion of the IC layout design.

The method 200 is repeated until all of the routing has been completed.

As much of the OPC optimisation has been performed already (or at least an initial guess has been made) further OPC processing of the full IC layout design may be minimised or eliminated.

In an alternative embodiment the OPC optimisation step 230 may be left out and instead any features determined by the OPC simulation step 220 to be a likely cause of defects, i.e. requiring OPC optimisation, are flagged or recorded in some way, for later analysis. This could be, for instance, after the IC layout design has been fully routed or during an additional full OPC optimisation of the complete IC 1ayout design . US 4,615,011 describes the serial nature of the routing problem. As the routing step is predominantly a serial operation this may be limited to the use of a single processor (CPU) in a computer system leaving any remaining CPUs in the computer system mostly idle. The OPC steps may be executed using parallel processing techniques (see "Parallel Processing Machine", Lithography Review, Semiconductor Equipment and Materials International, Volume 4, Issue 9, May 2002) and therefore may be carried out by a selection of the remaining idle CPUs. Therefore, the additional OPC processing should not significantly increase the total actual time required to carry out the complete routing stage of the IC design.

A particular type of defect that may be identified during the execution of method 200 is the shortening of connection tracks causing weak or missing electrical connections. The formation of electrical connections is illustrated in FIG. 4A and 4B, which show schematic cross- sections through the oxide layer 20 shown in FIG. 1.

An electrical connection is intended between point A and point B through an insulating oxide layer 320 shown in FIG. 4A. Building the connection is a two-part process. Firstly, a trench 310 is etched partially through the oxide layer 320. Then the trench is filled with a metal (not shown), which may be copper, for instance. However, when the trench does not extend far enough (this is shown in FIG. 4A by the trench falling short of point B) a faulty or incomplete electrical connection results. Such a defect may be identified during OPC simulation if the shortened connection is due to diffraction or other manufacturing effects. During OPC optimisation, additional segments or serifs may be added to compensate for the distortions. However, these correcting measures may be insufficient or may themselves cause other defects to occur. Vias (as shown in FIG. 1 as 40, for example) are electrical connections that extend through insulting layers. Vias extend more deeply through an oxide layer than the trenches that form surface based electrical connections. It is known to provide additional redundant vias to prevent single points of failure, when for instance, a random defect introduced at the via patterning step results in a faulty via connection. The redundant vias are typically placed randomly along metal connections. Vias may be formed by etching a deep opening in an oxide layer as illustrated in

FIG. 4B shown by opening 350. The deep opening 350 may then be filled with metal in a similar way to surface based connections are formed.

In a further aspect of the present invention a. via may be placed at an end of a surface based electrical connection such that during subsequent manufacture of the connection a defect due to the connection being too short is corrected by the presence of the via. One embodiment of this further aspect of the present invention is shown in FIG. 4B, whereby the shortened trench is extended during the etching step by the etching of a via. The via may be one that is redundant in the sense that it duplicates the connection made by one or more existing vias or it may be the only single via used to make a particular electrical connection. However, where the via is redundant it provides the dual purpose of redundancy for the primary via as well as ensuring that the surface connection is made.

Additionally, a via may be placed in a region of the layout which has been identified to be a risk for the width of the trench to pattern too narrow. For example, at point

140 in FIG. 2. The placement of a via in the layout at point 140 will ensure good patterning of the trench at that location. Obviously, a via can only be placed in a layout location where it will not cause an undesired connection between two metal features on neighboring layers .

This further aspect may be implemented to fix defects identified during the OPC simulation method step 220 or at any other time during the design or testing phase of IC wafer development .

The method described above may be carried out in an automated manner using suitable apparatus or a computer programmed to perform each of the method steps.

As will be appreciated by the skilled person, details of the above embodiment may be varied without departing from the scope of the present invention, as defined by the appended claims . For example, the OPC simulation step 220 may instead be replaced by a simplified optical simulation step that simulates the optical distortions, such as diffraction for instance, caused when transferring the IC layout design to an IC wafer. In any case as described above, this optical simulation may be carried out as part of the OPC simulation step 220.

When the method 200 described above is carried out using software running on a computer system having multiple processors individual processors may be allocated to particular tasks in order to evenly balance the processing load. For instance, the routing steps may be carried out on a single dedicated processor (at a particular time) , whilst simultaneously the OPC processes may be carried out on one or more other processors. The ratio of processors dedicated to routing to processors dedicated to OPC may be 1:2, 1:3,

1:4 or any other suitable ratio.

Claims

CLAIMS :

1. A method of designing an integrated circuit, IC, comprising the steps of: routing connections (210) between features of a first subset of a plurality of features forming an IC layout design of the IC; performing optical proximity correction, OPC, simulation (220) on the first subset of features and connections such that defects are identified; and routing connections between features of a second subset of the plurality of features.

2. The method of claim 1, further comprising performing OPC optimisation (230) after the OPC simulation step to correct the identified defects.

3. The method of claim 2, wherein the optimising step (230) further comprises placing segments proximal to features containing identified defects.

4. The method of claim 1 further comprising the step of storing the routed connections in a first computer data format .

5. The method of claim 4 further comprising translating the first computer data format into a second computer data format such that the second computer data format may be used by OPC simulation and optimisation software.

6. The method of any previous claim further comprising the step of flagging identified defects.

7. The method of any previous claim further comprising the step of fixing identified defects.

8. The method of claim 7, wherein the fixing step further comprises adding vias (350) to the connections having identified defects.

9. The method of claim 8, wherein the vias (350) are placed such that misalignment defects of the connections are corrected.

10. The method of claim 8, wherein the vias (350) are placed at the ends of connections such that during subsequent manufacture of the connections defects due to the connections being too short are corrected by the presence of the vias .

11. A computer program comprising program instructions that, when executed on a computer cause the computer to perform the method of any of the previous claims.

12. A computer-readable medium carrying a computer program according to claim 11.

13. A computer programmed to perform the method of any of claims 1 to 10.

14. An integrated circuit manufactured according to the method of any of claims 1 to 10.

15. Apparatus for designing an integrated circuit comprising: means for routing connections (210) between features of a first subset of a plurality of features forming an IC layout design of the IC; means for performing optical proximity correction, OPC, simulation (220) on the first subset of features and connections such that defects are identified; and means for routing connections between features of a second subset of the plurality of features.

16. The apparatus of claim 15 further comprising: a plurality of computer processors, wherein each means for routing connections comprises at least one of the plurality of computer processors, and wherein the means for performing OPC simulation comprises at least one further different computer processor of the plurality of computer processors.