WO2008012481A1 - Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit - Google Patents

Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit Download PDF

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Publication number
WO2008012481A1
WO2008012481A1 PCT/FR2007/051746 FR2007051746W WO2008012481A1 WO 2008012481 A1 WO2008012481 A1 WO 2008012481A1 FR 2007051746 W FR2007051746 W FR 2007051746W WO 2008012481 A1 WO2008012481 A1 WO 2008012481A1
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WO
WIPO (PCT)
Prior art keywords
support
integrated circuit
layer
pads
tracks
Prior art date
Application number
PCT/FR2007/051746
Other languages
French (fr)
Inventor
Alain Charpentier
Dominique Bocquene
Joseph Tregret
Pierre Tauzinat
Original Assignee
Microcomposants De Haute Sécurité Mhs
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Application filed by Microcomposants De Haute Sécurité Mhs filed Critical Microcomposants De Haute Sécurité Mhs
Publication of WO2008012481A1 publication Critical patent/WO2008012481A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
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    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the invention relates to a method of manufacturing an encapsulated integrated circuit and an encapsulated integrated circuit obtained by this method.
  • the invention particularly aims to make reliable the manufacture of connections connecting pads of the integrated circuit to the conductive pins of a housing for receiving this circuit.
  • the invention finds an advantageous application in the field of "packaging" of integrated circuits.
  • the integrated circuits comprise small pads connected to their inputs / outputs. These pads allow the connection of the integrated circuit with external circuits. However, these pads are difficult to access and can not be directly welded to a printed circuit board with electronic circuits.
  • the integrated circuit To facilitate the connection of the integrated circuit with other circuits, it is known to interface the integrated circuit with a housing having pins large enough to be soldered on a printed circuit.
  • the integrated circuit is fixed on the housing, and the pads are connected to the housing pins, by welding wire connections on the one hand to the pads of the integrated circuit and on the other hand to the pins of the housing (Wire operation -Bonding).
  • connections are sufficiently robust to withstand the high accelerations present and that the assembly of the integrated circuit with the housing is hermetic.
  • the active face of the integrated circuit (the one carrying the pads) to be accessible as long as possible during the manufacturing phase, in order to be able to check the manufacturing quality of the integrated circuit as well as that of the connections up to in the last stages of encapsulation.
  • this accessibility of the integrated circuit and connections is not possible today by using the techniques for making connections by a technique other than Wire-Bonding (BUMPS or TAB for example), techniques that require positioning the active face of the integrated circuit facing a printed circuit or do not allow hermetic encapsulation of the integrated circuit.
  • the invention proposes to solve the aforementioned problems.
  • the pads of the integrated circuit are connected to conductive tracks of a support by means of thin conductive layers.
  • the ground integrated circuits having a thickness between
  • connection lines by a photo-lithography operation on high form factor topologies, while avoiding problems of residues that can cause short circuits or leaks;
  • planarize the connection surfaces between the pads of the integrated circuit and the conductive tracks of the support on which the integrated circuits are implanted is intended to facilitate the deposition of the thin layers between the pads and the tracks, as well as the photo-lithography operations.
  • the maximum number of steps is treated at pseudo-platelets grouping many cut ICs, in order to be able to use conventional equipment of the microelectronics industry and minimize production costs. More specifically, there is provided a disc-shaped ceramic support having a plurality of through cavities and conductive tracks extending around the cavities.
  • the different surfaces to be connected to each other are leveled so as to facilitate the deposition steps of the thin layers and the photo-lithography operations.
  • the cavities between the support and the integrated circuits are filled with resin and a layer of photoresensitive polymer resin (type BCB for example) is deposited on the entire support.
  • the electrical connections are made by thin film deposition between the integrated circuits and the tracks of the support.
  • vias are opened on the metallization pads of the integrated circuits and on the conductive tracks of the support.
  • a thin layer of copper is deposited by electrolytic deposition. After deposition, this layer is covered with a thin layer of dielectric for its protection.
  • the copper thin film is produced by means of a conventional "Lift-off" deposition technique for which the integrated circuit pseudo-chip is not polarized.
  • the support is then cut around each cavity so as to obtain circuits with remote connections.
  • These circuits with remote connections each comprise an integrated circuit fixed on an individual support, the integrated circuit having its pads connected to the tracks of the support.
  • each pad of the integrated circuit is split so that each pad has a first and a second connection surface.
  • the first connection surface is used to perform functional tests of the integrated circuit.
  • the second connection surface is used for the connection of the integrated circuit with the pins of the housing carrying the integrated circuit.
  • FIG. 4-7 schematic representations of steps of the method according to the invention making it possible to planarize the rear face of the support and to planarize between the connection zones of the conductive tracks of the support and the connection zones of the integrated circuits. ;
  • FIGS. 8-13 schematic representations of steps of the method according to the invention making it possible to produce connection lines between the pads of the integrated circuits and the tracks of the support;
  • FIGS. 14-20 schematic representations of steps of the method according to the invention for hermetically sealing the integrated circuits and connecting the tracks of the support to contact pins for interfacing the integrated circuit with a printed circuit
  • FIGS. 21-22 schematic representations of a conventional single-chip integrated circuit and an integrated circuit with split-pins according to the invention.
  • Figure 1 shows a plate 1 of substantially circular glass which has the shape of a pseudo-silicon wafer.
  • An adhesive film 2 which is for example a thin layer of wax, a polyvinyl film, or a layer of polyimide resin, is deposited on the plate 1.
  • FIG. 2 shows a step in which a circular ceramic support 5 is positioned and aligned against the glass plate 1. This support
  • the film 5 is positioned against the film 2 with the aid of equipment allowing, for example, wafer-bonding or the assembly of integrated circuits on a glass or silicon substrate.
  • the support 5 comprises through cavities 6 and conductive tracks 7 extending around the cavities 6. These cavities 6 and these tracks 7 are distributed on the support 5 so as to form a real matrix of cavities 6 and conductive tracks 7.
  • the size of the support 5 is identical to that of the glass plate 1.
  • the technique of producing this support 5 is similar to that used for the production of traditional multilevel BGA-type housings.
  • the tracks 7 comprise connection pads 7.1, 7.2 which extend on the surface of the ceramic support 5. These connection pads 7.1, 7.2 are connected to each other via a conductive portion 7.3 located under the surface of the support 5.
  • the first connection pad 7.1 opens in the vicinity of the cavity, while the second pad 7.2 opens in the support 5 is offset with respect to the first connection pad.
  • the support 5 is positioned against the plate 1, so that the connection pads 7.1, 7.2 are positioned on the side of the glass plate 1.
  • integrated circuits 11 are placed inside the cavities 6 using a Flip-Chip type tool.
  • Bonder the support 5 being provided for this purpose alignment marks. More specifically, these integrated circuits 11 are arranged so that their active face 12 is positioned against the plate 1. These active faces 12 bear the conductive pads of the integrated circuits 11 connected to the inputs / outputs of these circuits. Thus, each of the circuits 11 is inside a cavity 6 corresponding thereto. This step makes it possible to position the active faces 12 of the circuits 11 substantially at the same level as the connection pads 7.1 and 7.2 of the support 5.
  • FIG. 4 shows a step in which the spaces between the outer walls of the integrated circuits 11 and the walls of the cavities 6 of the support 5 are filled with a resin 14 made of epoxy or silicone.
  • the resin 14 is injected into the cavities 6, so that the integrated circuits 11 are covered with resin, the resin height 14 being substantially the same as that of the cavities 6.
  • This resin 14 is cured by low temperature annealing. , film 2 being such that it supports the temperature of this annealing.
  • the resin 14 has a coefficient of thermal expansion, a Young's modulus, and a transition temperature compatible with the materials and thermal budgets used in this assembly process.
  • the thickness tolerances resulting from the manufacturing process of the support 5, the thickness tolerances of the integrated circuit 11, the film 2 and the resin 14 can induce a difference in level between the surfaces of these elements after assembly.
  • the assembly obtained is leveled so as to position the face of the integrated circuit 11 opposite to the active face 11, the resin layer 14 and the ceramic support 5 in the same plan.
  • This upgrade is performed by conventional lapping techniques of silicon wafers.
  • the asperities 13 have disappeared and all the elements 5,14, and rear face of the integrated circuit 11 is level.
  • This break-in operation aims to eliminate ten microns of the entire rear face to ensure the flatness of the assembly and facilitate subsequent technological operations, including operations requiring high-speed rotation.
  • the adhesive film 2 is removed to facilitate the separation of the support 5 from the plate 1.
  • a withdrawal technique chosen from the following techniques: UV exposure, thermal annealing, laser or wet chemical shrinkage.
  • a wet chemical cleaning with a posterior solvent, such as acetone, may be useful for removing residues from the active faces 4 of the integrated circuits 1.
  • the support 5 is separated from the plate 1 and it is turned back along the arrow 17.
  • a structure is obtained comprising the circular ceramic support inside which are 11.
  • this structure may undergo subsequent technological operations similar to those performed on silicon wafers in the microelectronics industry.
  • the active faces 12 of the integrated circuits 11 are not at the same level as the connection pads 7.1, as shown by the enlargement of the joint area between the integrated circuits 11 and the support 5 of FIG. 7.
  • the entire support 5 is covered with a layer 18 of photosensitive polymer dielectric of the BCB type, polyimide or any other photosensitive polymer of low dielectric constant (k ⁇ 3.5).
  • This polymer layer should preferably also have characteristics compatible with the other materials present and the subsequent steps of the process, ie a low Young's modulus, a thermal expansion coefficient compatible with silicon and ceramics, a temperature high transition and low permittivity.
  • FIGS. 8 to 13 show steps enabling the realization of electrical connections between the connection pads 7.1 of the support 5 and the pads.
  • FIG. 8 shows a step in which openings (vias) 16 are made on the metallization pads 15 of the integrated circuits 11 and on the connection pads 7.1 of the support 5.
  • a conventional photo-lithography tool is used to define the openings 16. The use of this tool may involve the definition of alignment marks on the integrated circuits 11 and the support 5.
  • pads 15 are made through the passivation layer 19 insulating and protecting the entire integrated circuit 11. These pads 15 are made during the manufacturing process of the integrated circuit.
  • FIG. 9 shows a step in which a thin metal sub-layer 21 of a titanium-tungsten alloy (TiW layer) is deposited on the entire support 5.
  • This sub-layer 21 is thus deposited on the layer 18 and in the vias 16.
  • This sub-layer 21 acts as a diffusion barrier for the copper connections to be made to prevent this copper from entering the silicon circuits 11 through the metallization used to make the pads 15.
  • Figure 10 shows a step in which a layer is deposited
  • FIG. 11 shows a step in which an electrolytic selective deposition of a copper layer 27 preferably having a thickness of at least 5 microns is carried out.
  • the underlayer 21 acts as a polarized conduction layer for the whole of the support 5, the deposition of the layer 27 being effected only in the openings 28 where is present the metal underlayer 21 not covered of resin.
  • the openings defining the electrical connections are made in a photosensitive resin layer and, after firing and development, the bonds are made by evaporation of the copper.
  • the metal deposited on the resin layer around the connections is removed with a solvent at the same time as the resin.
  • the copper deposit is replaced by a gold deposit produced by evaporation.
  • Figure 12 shows a step in which the resin layer 25 that was used to define the connection paths was removed by an oxygen plasma etching technique.
  • the metal sublayer 21 of TiW is etched by a RIE technique, in order to remove it in the zones other than those where the electrical connections are made. Electrical connections are thus obtained between the pads 15 of the circuit 11 and the connection pads 7.1 of the support 5.
  • FIG. 13 shows a step in which a thin layer 29 of photosensitive dielectric polymer of the BCB type (similar to the layer 18) is deposited on the surface of the support 5 in order to mechanically and thermally protect the electrical links 27.
  • All the operations described in FIGS. 8 to 13 may be repeated several times to integrate several levels of connections, in a manner comparable to the multilevel integration practiced in the manufacturing process of an integrated circuit.
  • FIGS. 14 to 17 make it possible to fix welding rings 31, 32 on the front and rear faces of the support 5, around the faces of the circuits 11 opening on the outside. As will be seen, these rings 31, 32 allow the welding of covers ensuring the hermetic integrity of each integrated circuit 11 of the support 5.
  • the dielectric deposits 29 present on the connections 7.2 are first removed.
  • a conventional photo-lithography step is carried out by depositing and defining a photoresist layer 35 on the dielectric zones to be preserved.
  • the dielectric 29 not covered with resin 35 is removed by plasma etching of the RIE type.
  • a solder ring 31 is made around the active face of each integrated circuit 11.
  • This ring 31 is positioned around the remaining dielectric layer 29, between the connections 7.1 and 7.2 which extend on the surface of the support 5.
  • This ring 31 is preferably composed of a layer of nickel and a layer of gold.
  • the resin layer 35 may also serve as a resin of the lift-off sequence for producing the ring 31, the nickel / gold layer being in this case also deposited on the connection pad 7.2.
  • a layer 39 of resin is deposited on the front face of the support 5 carrying the rings 31 so as to protect these rings 31.
  • a conventional lift-off sequence is performed to make the ring 32.
  • the rings 31 and 32 are substantially symmetrical with respect to a plane perpendicular to the plane of the sheet which separates the support 5 into two identical parts.
  • the layer 39 is then removed in a step shown in FIG. 17.
  • the creation of the ring 32 and the elimination of the layer 39 are performed simultaneously during the lift-off sequence.
  • Figure 18 shows a wafer 41 obtained at the end of the previous steps.
  • This plate 41 comprises the integrated circuits 1 1 implanted inside the cavities 6 of the support 5.
  • Each circuit 43 comprises an integrated circuit 11 implanted inside an individual support 45, the pads 15 connected to the tracks
  • connection pads 7.2 being deported to the connection pads 7.2.
  • FIG. 19 represents a step in which two attached hoods 47 and 48 are welded, presenting in section a shape of
  • each cover 47, 48 comprises a solder ring 49, 50 composed of a layer of nickel and a layer of gold. These rings 49, 50 are respectively plated against the rings 31 and 32 of the individual circuit 43 encapsulated.
  • the attachment between the covers 47 and 48 and the support 45, or more precisely the fixing between their welding ring, is conventionally made in a passage oven for example.
  • the individual support 45 thus constitutes the body of the final housing.
  • a connector 55 of the SCI type Solid Column Interposer, FIG. NTK
  • connection columns 56 is positioned against the individual support 45 around the cover 47 positioned on the side of the connection pads 7.2 of the individual support.
  • the columns 56 of the SCI 55 are welded to the connection pads 7.2. This produces a final BGA type package.
  • the columns 56 of the SCI 55 allow the interface of the individual circuit 43 with a printed circuit.
  • FIG. 21 shows a schematic representation of an integrated circuit 1 comprising conventional single pads.
  • Each stud 15 consists of a metal zone 135 covered with a passivation layer 136 in which a window has been defined via a conventional photo lithography operation.
  • the metal zone 135 made of aluminum or using a stack of layers of titanium, titanium nitride, titanium-tungsten, tantalum, tantalum nitride, molybdenum, ruthenium, aluminum or aluminum-copper alloy and aluminum silicon copper has the shape of a square of 80 micrometers side, the window defined in the passivation having a square opening of 70 micrometers side.
  • the tools used to establish the connections with the measuring devices can damage the pad 15. Or a damaged stud can reduce the reliability of the electrical connection made between the pads 15 of Figure 8 and the connection pads 7.1 of the support 5.
  • the pad 15 is split to ensure the reliability of the metal connection 11 between the pads and an outer member.
  • the stud 15 has two surfaces 139, 140 interconnected connections, these two surfaces 139, 140 each having a sufficient area to establish a connection with a measuring tool or an electrical connection with a connection outside the circuit.
  • the first connection surface 139 is used to test the operation of the integrated circuits.
  • the second connection surface 140 is used for the connection between the integrated circuit 1 and the tracks of the support 5.
  • the use of a connection surface dedicated to the connector allows a better adhesion of the metal deposits on the stud and reliability thus the connection between the studs and the tracks.
  • the copper layer covers the two connection surfaces 139, 140.
  • two apertures 142 and 143 are made by conventional photolithography operation in a passivation layer 141 deposited on a rectangular conductor zone 144 of 135 micrometers by 80 micrometers. This conducting zone 144 is connected to an input or an output of the circuit.
  • connection surfaces 139, 140 thus defined have substantially the shape of a 60-micrometer square.
  • the conductive zone 144 may be made of the same material as the zone 135.
  • the invention also extends to the integrated circuit obtained with the method described above.

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Abstract

The invention relates to a process for fabricating an integrated circuit (11) encapsulated in an individual support (45). In the process, a support (5) having a matrix of through-cavities (6) and conducting tracks (7) is positioned against a plate (1) and integrated circuits (11) are deposited in the cavities (6). Next, resin (14) is injected into the cavities (6) between the walls of the cavities (6) and the walls of the integrated circuits (11). Electrical connections (27) between the tracks of the cavities (6) and the pads (15) are then produced by thin-film deposition. After the deposition, the support around each cavity (6) is cut away so as to obtain individual circuits (43), each comprising an integrated circuit (11) implanted on an individual support (45).

Description

Procédé de fabrication d'un circuit intégré encapsulé et circuit intégré encapsulé associé Method of manufacturing an encapsulated integrated circuit and associated encapsulated integrated circuit
L'invention concerne un procédé de fabrication d'un circuit intégré encapsulé et un circuit intégré encapsulé obtenu par ce procédé. L'invention a notamment pour but de fiabiliser la fabrication des connexions reliant des plots du circuit intégré à des broches conductrices d'un boîtier destiné à recevoir ce circuit. L'invention trouve une application avantageuse dans le domaine du « packaging » des circuits intégrés.The invention relates to a method of manufacturing an encapsulated integrated circuit and an encapsulated integrated circuit obtained by this method. The invention particularly aims to make reliable the manufacture of connections connecting pads of the integrated circuit to the conductive pins of a housing for receiving this circuit. The invention finds an advantageous application in the field of "packaging" of integrated circuits.
De manière générale, les circuits intégrés comportent des plots de petite taille reliés à leurs entrées / sorties. Ces plots permettent la connexion du circuit intégré avec des circuits extérieurs. Toutefois, ces plots sont difficilement accessibles et ne peuvent pas être directement soudés sur un circuit imprimé portant des circuits électroniques.In general, the integrated circuits comprise small pads connected to their inputs / outputs. These pads allow the connection of the integrated circuit with external circuits. However, these pads are difficult to access and can not be directly welded to a printed circuit board with electronic circuits.
Pour faciliter la connexion du circuit intégré avec d'autres circuits, il est connu d'interfacer le circuit intégré avec un boîtier comportant des broches de taille suffisamment importante pour être soudées sur un circuit imprimé. A cette fin, on fixe le circuit intégré sur le boîtier, et on relie les plots aux broches du boîtier, en soudant des connexions filaires d'une part aux plots du circuit intégré et d'autre part aux broches du boîtier (opération de Wire-Bonding).To facilitate the connection of the integrated circuit with other circuits, it is known to interface the integrated circuit with a housing having pins large enough to be soldered on a printed circuit. For this purpose, the integrated circuit is fixed on the housing, and the pads are connected to the housing pins, by welding wire connections on the one hand to the pads of the integrated circuit and on the other hand to the pins of the housing (Wire operation -Bonding).
Toutefois, de telles connexions filaires sont fragiles et leur réalisation est techniquement délicate, puisqu'elles doivent être soudées individuellement à un plot et à une borne.However, such wire connections are fragile and their realization is technically delicate, since they must be individually welded to a pad and a terminal.
Par ailleurs, dans le domaine des applications militaires, il est important que les connexions soient suffisamment robustes pour résister aux fortes accélérations présentes et que l'assemblage du circuit intégré avec le boîtier soit hermétique. En outre, il est important que la face active du circuit intégré (celle portant les plots) soit accessible le plus longtemps possible lors de la phase de fabrication, afin de pouvoir vérifier la qualité de fabrication du circuit intégré ainsi que celle des connexions jusqu'aux dernières étapes de l'encapsulation. Or cette accessibilité du circuit intégré et des connexions n'est pas possible aujourd'hui en utilisant les techniques permettant de réaliser des connexions par une technique autre que le Wire-Bonding (BUMPS ou TAB par exemple), techniques qui imposent de positionner la face active du circuit intégré en regard d'un circuit imprimé ou ne permettent pas une encapsulation hermétique du circuit intégré.Furthermore, in the field of military applications, it is important that the connections are sufficiently robust to withstand the high accelerations present and that the assembly of the integrated circuit with the housing is hermetic. In addition, it is important for the active face of the integrated circuit (the one carrying the pads) to be accessible as long as possible during the manufacturing phase, in order to be able to check the manufacturing quality of the integrated circuit as well as that of the connections up to in the last stages of encapsulation. However, this accessibility of the integrated circuit and connections is not possible today by using the techniques for making connections by a technique other than Wire-Bonding (BUMPS or TAB for example), techniques that require positioning the active face of the integrated circuit facing a printed circuit or do not allow hermetic encapsulation of the integrated circuit.
L'invention se propose de résoudre les problèmes précités.The invention proposes to solve the aforementioned problems.
A cette fin, on relie les plots du circuit intégré à des pistes conductrices d'un support par l'intermédiaire de couches minces conductrices.To this end, the pads of the integrated circuit are connected to conductive tracks of a support by means of thin conductive layers.
Le dépôt d'une couche mince conductrice impose de nombreuses contraintes, à savoir :The deposition of a conductive thin layer imposes numerous constraints, namely:
- déposer une épaisseur importante sur des topologies de facteur de forme élevé, les circuits intégrés rodés ayant une épaisseur comprise entredepositing a large thickness on high form factor topologies, the ground integrated circuits having a thickness between
150 et 400 micromètres, ce qui peut induire localement des amincissements de ces mêmes couches conductrices ;150 and 400 micrometers, which can locally induce thinning of these same conductive layers;
- définir des lignes de connexions par une opération de photo- litographie sur les topologies de facteur de forme élevées, tout en évitant les problèmes de résidus pouvant provoquer des courts circuits ou des fuites ;- define connection lines by a photo-lithography operation on high form factor topologies, while avoiding problems of residues that can cause short circuits or leaks;
- réaliser plusieurs niveaux d'interconnexions pour adresser le cas de boîtiers multi-niveaux ;- realize several levels of interconnections to address the case of multi-level boxes;
- tenir compte de différences de tenue mécanique entre les différents composants en présence, tels que le silicium, les dépôts métalliques et les éléments du boîtier.- Take into account differences in mechanical strength between the various components in the presence, such as silicon, metal deposits and housing elements.
Pour surmonter ces contraintes, dans une mise en oeuvre, on planarise les surfaces de connexions entre les plots du circuit intégré et les pistes conductrices du support sur lequel sont implantés les circuits intégrés. Cette étape de planarisation a pour but de faciliter le dépôt des couches minces entre les plots et les pistes, ainsi que les opérations de photo- litographie. En outre, on traite le maximum d'étapes possibles au niveau de pseudo-plaquettes regroupant de nombreux circuits intégrés découpés, afin de pouvoir utiliser des équipements classiques de l'industrie microélectronique et minimiser les coûts de production. Plus précisément, on réalise un support en céramique en forme de disque comportant une multitude de cavités traversantes et des pistes conductrices s'étendant autour des cavités. Des circuits intégrés individualisés (résultat de l'opération de découpe de tranches de silicium) sont positionnés à l'intérieur de ces cavités, de sorte qu'un circuit intégré entre en coopération avec une cavité lui correspondant. On crée ainsi des pseudo-plaquettes de circuits intégrés qui facilitent l'industrialisation du procédé selon l'invention.To overcome these constraints, in an implementation, planarize the connection surfaces between the pads of the integrated circuit and the conductive tracks of the support on which the integrated circuits are implanted. This planarization step is intended to facilitate the deposition of the thin layers between the pads and the tracks, as well as the photo-lithography operations. In addition, the maximum number of steps is treated at pseudo-platelets grouping many cut ICs, in order to be able to use conventional equipment of the microelectronics industry and minimize production costs. More specifically, there is provided a disc-shaped ceramic support having a plurality of through cavities and conductive tracks extending around the cavities. Individualized integrated circuits (result of the operation of cutting silicon wafers) are positioned inside these cavities, so that an integrated circuit cooperates with a cavity corresponding thereto. We thus create pseudo-integrated circuit boards that facilitate the industrialization of the method according to the invention.
Ensuite, on met à niveau les différentes surfaces à connecter entre elles de manière à faciliter les étapes de dépôt des couches minces et les opérations de photo-lithographie. A cette fin, les cavités entre le support et les circuits intégrés sont remplies de résine et une couche de résine polymère photo-sensible (type BCB par exemple) est déposée sur l'ensemble du support.Next, the different surfaces to be connected to each other are leveled so as to facilitate the deposition steps of the thin layers and the photo-lithography operations. To this end, the cavities between the support and the integrated circuits are filled with resin and a layer of photoresensitive polymer resin (type BCB for example) is deposited on the entire support.
Dans une autre étape du procédé, on réalise les connexions électriques par un dépôt de couche mince entre les circuits intégrés et les pistes du support. A cet effet, on ouvre des vias sur les plots de métallisation des circuits intégrés et sur les pistes conductrices du support. Puis, après avoir recouvert les plots et les pistes d'un conducteur jouant le rôle de barrière de diffusion pour les connexions, on réalise un dépôt d'une couche mince de cuivre par dépôt électrolytique. Après dépôt, cette couche est recouverte d'une fine couche de diélectrique pour sa protection.In another step of the method, the electrical connections are made by thin film deposition between the integrated circuits and the tracks of the support. For this purpose, vias are opened on the metallization pads of the integrated circuits and on the conductive tracks of the support. Then, after having covered the pads and the tracks of a conductor acting as a diffusion barrier for the connections, a thin layer of copper is deposited by electrolytic deposition. After deposition, this layer is covered with a thin layer of dielectric for its protection.
En variante, la couche mince de cuivre est réalisée via une technique classique de dépôt dite « Lift -off » pour lequel on ne polarise pas la pseudoplaquette de circuits intégrés. On découpe ensuite le support autour de chaque cavité de manière à obtenir des circuits à connexions déportées. Ces circuits à connexions déportées comportent chacun un circuit intégré fixé sur un support individuel, le circuit intégré ayant ses plots reliés aux pistes du support.In a variant, the copper thin film is produced by means of a conventional "Lift-off" deposition technique for which the integrated circuit pseudo-chip is not polarized. The support is then cut around each cavity so as to obtain circuits with remote connections. These circuits with remote connections each comprise an integrated circuit fixed on an individual support, the integrated circuit having its pads connected to the tracks of the support.
Ces circuits à connexions déportées sont alors fermés hermétiquement à l'aide de capots rapportés soudés sur des faces de ces circuits. A cette fin, les capots comportent des anneaux qui sont soudés sur des anneaux de soudure des circuits à connexions déportés. Les anneaux de soudure des circuits sont réalisés préalablement pour l'ensemble des circuits de la plaque, avant leur découpe. En outre, dans une mise en œuvre, on dédouble chaque plot du circuit intégré de manière que chaque plot possède une première et une deuxième surface de connexion. La première surface de connexion est utilisée pour réaliser des tests de fonctionnement du circuit intégré. La deuxième surface de connexion est utilisée pour la connectique du circuit intégré avec les broches du boîtier portant le circuit intégré. L'invention concerne donc un procédé de fabrication d'un circuit intégré encapsulé dans un support individuel, le circuit intégré comportant des plots conducteurs sur sa face active, les plots étant connectés à des entrées/sorties du circuit intégré, caractérisé en ce qu'il comporte les étapes suivantes :These circuits with remote connections are then hermetically sealed using attached covers welded to the faces of these circuits. For this purpose, the covers comprise rings which are welded to solder rings of the remote connection circuits. The solder rings of the circuits are made beforehand for all the circuits of the plate, before their cutting. In addition, in one implementation, each pad of the integrated circuit is split so that each pad has a first and a second connection surface. The first connection surface is used to perform functional tests of the integrated circuit. The second connection surface is used for the connection of the integrated circuit with the pins of the housing carrying the integrated circuit. The invention therefore relates to a method of manufacturing an integrated circuit encapsulated in an individual support, the integrated circuit comprising conductive pads on its active face, the pads being connected to inputs / outputs of the integrated circuit, characterized in that it comprises the following steps:
- positionner contre une plaque de verre un support comportant une matrice de cavités traversantes et de pistes conductrices,positioning a support comprising a matrix of through cavities and conductive tracks against a glass plate,
- déposer des circuits intégrés dans les cavités du support, de sorte que chaque circuit intégré se trouve à l'intérieur d'une cavité, - injecter de la résine dans les cavités entre les parois des cavités et les parois extérieures des circuits intégrés,depositing integrated circuits in the cavities of the support, so that each integrated circuit is located inside a cavity, injecting resin into the cavities between the walls of the cavities and the outer walls of the integrated circuits,
- réaliser, par dépôt de couches minces, des liaisons électriques entre les pistes des cavités et les plots pour l'ensemble des circuits intégrés implantés dans le support, et - découper autour de chaque cavité de manière à obtenir des circuits individuels comportant chacun un circuit intégré implanté sur un support individuel.- Making, by deposition of thin layers, electrical connections between the tracks of the cavities and the pads for all the integrated circuits implanted in the support, and - cut around each cavity so as to obtain individual circuits each having a circuit integrated on an individual support.
L'invention sera mieux comprise à la lecture de la description qui suit et à l'examen des figures qui l'accompagnent. Celles-ci ne sont données qu'à titre illustratif mais nullement limitatif de l'invention. Ces figures montrent :The invention will be better understood on reading the description which follows and on examining the figures which accompany it. These are given for illustrative purposes only but not limiting of the invention. These figures show:
- figures 1-3 : une représentation schématique d'une étape du procédé selon l'invention permettant la réalisation d'une pseudo-plaquette de circuits intégrés en positionnant des circuits dans des cavités d'un support céramique en forme de plaquette de silicium ; - figure 4-7 : des représentations schématiques d'étapes du procédé selon l'invention permettant de réaliser une planarisation de la face arrière du support et une planarisation entre les zones de connexions des pistes conductrices du support et les zones de connexions des circuits intégrés ;- Figures 1-3: a schematic representation of a step of the method according to the invention for the realization of a pseudo-integrated circuit board by positioning circuits in cavities of a ceramic support in the form of silicon wafer; FIG. 4-7: schematic representations of steps of the method according to the invention making it possible to planarize the rear face of the support and to planarize between the connection zones of the conductive tracks of the support and the connection zones of the integrated circuits. ;
- figures 8-13 : des représentations schématiques d'étapes du procédé selon l'invention permettant de réaliser des lignes de connexions entre les plots des circuits intégrés et les pistes du support ;FIGS. 8-13: schematic representations of steps of the method according to the invention making it possible to produce connection lines between the pads of the integrated circuits and the tracks of the support;
- figures 14-20 : des représentations schématiques d'étapes du procédé selon l'invention permettant la fermeture hermétique des circuits intégrés et la connexion des pistes du support à des broches de contact pour l'interfaçage du circuit intégré avec un circuit imprimé ; - figures 21-22 : des représentations schématiques d'un circuit intégré à plot simple classique et d'un circuit intégré à plots dédoublés selon l'invention.FIGS. 14-20: schematic representations of steps of the method according to the invention for hermetically sealing the integrated circuits and connecting the tracks of the support to contact pins for interfacing the integrated circuit with a printed circuit; FIGS. 21-22: schematic representations of a conventional single-chip integrated circuit and an integrated circuit with split-pins according to the invention.
Les éléments identiques conservent la même référence d'une figure à l'autre. Par ailleurs, sur les figures, les zones pour lesquelles un grandissement est représenté sont entourées.Identical elements retain the same reference from one figure to another. On the other hand, in the figures, the areas for which magnification is shown are surrounded.
La figure 1 montre une plaque 1 de verre sensiblement circulaire qui présente la forme d'une pseudo-plaquette de silicium. Un film adhésif 2, qui est par exemple une couche mince de cire, un film polyvinyle, ou une couche de résine polyimide, est déposé sur la plaque 1.Figure 1 shows a plate 1 of substantially circular glass which has the shape of a pseudo-silicon wafer. An adhesive film 2, which is for example a thin layer of wax, a polyvinyl film, or a layer of polyimide resin, is deposited on the plate 1.
La figure 2 montre une étape dans laquelle on positionne et on aligne un support 5 en céramique circulaire contre la plaque 1 en verre. Ce supportFIG. 2 shows a step in which a circular ceramic support 5 is positioned and aligned against the glass plate 1. This support
5 est positionné contre le film 2 à l'aide d'un équipement permettant par exemple le wafer-bonding ou l'assemblage de circuits intégrés sur substrat de verre ou de silicium.5 is positioned against the film 2 with the aid of equipment allowing, for example, wafer-bonding or the assembly of integrated circuits on a glass or silicon substrate.
Le support 5 comporte des cavités 6 traversantes et des pistes 7 conductrices s'étendant autour des cavités 6. Ces cavités 6 et ces pistes 7 sont réparties sur le support 5 de manière à former une véritable matrice de cavités 6 et de pistes conductrices 7. La dimension du support 5 est identique à celle de la plaque 1 de verre. La technique de réalisation de ce support 5 est similaire à celle utilisée pour la réalisation de boîtiers multi-niveaux traditionnels de type BGA.The support 5 comprises through cavities 6 and conductive tracks 7 extending around the cavities 6. These cavities 6 and these tracks 7 are distributed on the support 5 so as to form a real matrix of cavities 6 and conductive tracks 7. The size of the support 5 is identical to that of the glass plate 1. The technique of producing this support 5 is similar to that used for the production of traditional multilevel BGA-type housings.
Par ailleurs, les pistes 7 comportent des plots de connexions 7.1 , 7.2 qui s'étendent en surface du support 5 en céramique. Ces plots de connexions 7.1 , 7.2 sont reliées entre eux par l'intermédiaire d'une partie conductrice 7.3 située sous la surface du support 5. Le premier plot de connexion 7.1 débouche à proximité de la cavité, tandis que le deuxième plot 7.2 débouche dans le support 5 de manière décalée par rapport au premier plot de connexion. Le support 5 est positionné contre la plaque 1 , de sorte que les plots de connexions 7.1 , 7.2 sont positionnés du coté de la plaque 1 en verre.Moreover, the tracks 7 comprise connection pads 7.1, 7.2 which extend on the surface of the ceramic support 5. These connection pads 7.1, 7.2 are connected to each other via a conductive portion 7.3 located under the surface of the support 5. The first connection pad 7.1 opens in the vicinity of the cavity, while the second pad 7.2 opens in the support 5 is offset with respect to the first connection pad. The support 5 is positioned against the plate 1, so that the connection pads 7.1, 7.2 are positioned on the side of the glass plate 1.
Ensuite, dans l'étape de la figure 3, des circuits intégrés 11 sont disposés à l'intérieur des cavités 6 à l'aide d'un outil de type Flip-ChipThen, in the step of FIG. 3, integrated circuits 11 are placed inside the cavities 6 using a Flip-Chip type tool.
Bonder, le support 5 étant pourvu à cet effet de marques d'alignement. Plus précisément, ces circuits intégrés 11 sont disposés de sorte que leur face active 12 est positionnée contre la plaque 1. Ces faces actives 12 portent les plots conducteurs des circuits intégrés 11 reliés aux entrées/sorties de ces circuits. Ainsi, chacun des circuits 11 se trouve à l'intérieur d'une cavité 6 lui correspondant. Cette étape permet de positionner les faces actives 12 des circuits 11 sensiblement au même niveau que les plots de connexion 7.1 et 7.2 du support 5.Bonder, the support 5 being provided for this purpose alignment marks. More specifically, these integrated circuits 11 are arranged so that their active face 12 is positioned against the plate 1. These active faces 12 bear the conductive pads of the integrated circuits 11 connected to the inputs / outputs of these circuits. Thus, each of the circuits 11 is inside a cavity 6 corresponding thereto. This step makes it possible to position the active faces 12 of the circuits 11 substantially at the same level as the connection pads 7.1 and 7.2 of the support 5.
Dans le cas où le film 2 est une résine ou une cire, l'ensemble formé par la plaque 1 , le film 2, les circuits intégrés 11 et le support 5 est maintenu en température pour en assurer la cohésion, de préférence à une température inférieure à 100 degrés. La figure 4 montre une étape dans laquelle on remplit d'une résine 14 en époxy ou en silicone les espaces entre les parois externes des circuits intégrés 11 et les parois des cavités 6 du support 5.In the case where the film 2 is a resin or a wax, the assembly formed by the plate 1, the film 2, the integrated circuits 11 and the support 5 is maintained in temperature to ensure cohesion, preferably at a temperature less than 100 degrees. FIG. 4 shows a step in which the spaces between the outer walls of the integrated circuits 11 and the walls of the cavities 6 of the support 5 are filled with a resin 14 made of epoxy or silicone.
Plus précisément, la résine 14 est injectée dans les cavités 6, de sorte que les circuits intégrés 11 sont recouverts de résine, la hauteur de résine 14 étant sensiblement la même que celle des cavités 6. Cette résine 14 est durcie par recuit à basse température, le film 2 étant tel qu'il supporte la température de ce recuit.More specifically, the resin 14 is injected into the cavities 6, so that the integrated circuits 11 are covered with resin, the resin height 14 being substantially the same as that of the cavities 6. This resin 14 is cured by low temperature annealing. , film 2 being such that it supports the temperature of this annealing.
De préférence, la résine 14 présente un coefficient d'expansion thermique, un module de Young, et une température de transition compatibles avec les matériaux et budgets thermiques utilisés dans ce processus d'assemblage.Preferably, the resin 14 has a coefficient of thermal expansion, a Young's modulus, and a transition temperature compatible with the materials and thermal budgets used in this assembly process.
Comme montré dans l'agrandissement de la zone de jointure entre le circuit intégré 11 , la couche de résine 14, et le support 5, il peut exister des différences de niveaux entre les surfaces de ces éléments. En effet, ces éléments peuvent présenter à leur surface de petites aspérités 13.As shown in the enlargement of the joint area between the integrated circuit 11, the resin layer 14, and the support 5, there may be differences in levels between the surfaces of these elements. Indeed, these elements may have on their surface small asperities 13.
De même, les tolérances d'épaisseur résultant du processus de fabrication du support 5, les tolérances d'épaisseur du circuit intégré 11 , du film 2 et de la résine 14 peuvent induire une différence de niveau entre les surfaces de ces éléments après assemblage. Dans une étape représentée à la figure 5, on réalise une mise à niveau de l'ensemble obtenu, de manière à positionner la face du circuit intégré 11 opposée à la face active 11 , la couche de résine 14 et le support 5 céramique dans le même plan. Cette mise à niveau est réalisée par des techniques de rodage classique de plaquettes de silicium. Ainsi, comme montré sur l'agrandissement de la figure 5, les aspérités 13 ont disparu et l'ensemble des éléments 5,14, et face arrière du circuit intégré 11 est à niveau.Similarly, the thickness tolerances resulting from the manufacturing process of the support 5, the thickness tolerances of the integrated circuit 11, the film 2 and the resin 14 can induce a difference in level between the surfaces of these elements after assembly. In a step shown in FIG. 5, the assembly obtained is leveled so as to position the face of the integrated circuit 11 opposite to the active face 11, the resin layer 14 and the ceramic support 5 in the same plan. This upgrade is performed by conventional lapping techniques of silicon wafers. Thus, as shown in the enlargement of FIG. 5, the asperities 13 have disappeared and all the elements 5,14, and rear face of the integrated circuit 11 is level.
Cette opération de rodage a pour but d'éliminer une dizaine de microns de l'ensemble de la face arrière pour garantir la planéité de l'ensemble et faciliter les opérations technologiques ultérieures, notamment des opérations nécessitant une rotation à grande vitesse.This break-in operation aims to eliminate ten microns of the entire rear face to ensure the flatness of the assembly and facilitate subsequent technological operations, including operations requiring high-speed rotation.
Ensuite, on élimine le film 2 adhésif pour faciliter la séparation du support 5 de la plaque 1. A cet effet, en fonction du film 2 utilisé (cire, résine polyimide ou époxy), on met en œuvre une technique de retrait choisie parmi les techniques suivantes : exposition UV, recuit thermique, laser ou retrait chimique humide. Un nettoyage chimique en voie humide par un solvant postérieur, tel que l'acétone, peut être utile pour éliminer des résidus des faces actives 4 des circuits intégrés 1.Subsequently, the adhesive film 2 is removed to facilitate the separation of the support 5 from the plate 1. For this purpose, depending on the film 2 used (wax, polyimide resin or epoxy), a withdrawal technique chosen from the following techniques: UV exposure, thermal annealing, laser or wet chemical shrinkage. A wet chemical cleaning with a posterior solvent, such as acetone, may be useful for removing residues from the active faces 4 of the integrated circuits 1.
Une fois le film 2 éliminé, on sépare le support 5 de la plaque 1 et on le retourne suivant la flèche 17. On obtient alors, comme représenté à la figure 6, une structure comportant le support 5 céramique circulaire à l'intérieur duquel sont implantés les circuits intégrés 11. Comme montré ci- après, cette structure pourra subir des opérations technologiques ultérieures assimilables à celles effectuées sur tranches de silicium dans l'industrie micro-électronique.Once the film 2 has been removed, the support 5 is separated from the plate 1 and it is turned back along the arrow 17. Thus, as shown in FIG. 6, a structure is obtained comprising the circular ceramic support inside which are 11. As shown below, this structure may undergo subsequent technological operations similar to those performed on silicon wafers in the microelectronics industry.
Il se peut que les faces actives 12 des circuits intégrés 11 ne soient pas au même niveau que les plots de connexions 7.1 , comme le montre l'agrandissement de la zone de jointure entre les circuits intégrés 11 et le support 5 de la figure 7. Dans ce cas, on recouvre l'ensemble du support 5 d'une couche 18 de diélectrique polymère photo-sensible de type BCB, polyimide ou tout autre polymère photo-sensible de faible constante diélectrique (k < 3.5). Cette couche de polymère doit préférentiellement présenter également des caractéristiques compatibles avec les autres matériaux présents et les étapes ultérieures du procédé, c'est à dire un faible module de Young, un coefficient d'expansion thermique compatible avec le silicium et la céramique, une température de transition élevée et une faible permittivité.It is possible that the active faces 12 of the integrated circuits 11 are not at the same level as the connection pads 7.1, as shown by the enlargement of the joint area between the integrated circuits 11 and the support 5 of FIG. 7. In this case, the entire support 5 is covered with a layer 18 of photosensitive polymer dielectric of the BCB type, polyimide or any other photosensitive polymer of low dielectric constant (k <3.5). This polymer layer should preferably also have characteristics compatible with the other materials present and the subsequent steps of the process, ie a low Young's modulus, a thermal expansion coefficient compatible with silicon and ceramics, a temperature high transition and low permittivity.
Cette étape a ainsi pour but de parfaire la planarisation entre les faces actives 12 des circuits imprimés 11 et les plots de connexion 7.1 , 7.2 du support 5, en les mettant à niveau. Les figures 8 à 13 montrent des étapes permettant la réalisation de liaisons électriques entre les plots de connexion 7.1 du support 5 et les plotsThis step is thus intended to perfect the planarization between the active faces 12 of the printed circuits 11 and the connection pads 7.1, 7.2 of the support 5, by leveling them. FIGS. 8 to 13 show steps enabling the realization of electrical connections between the connection pads 7.1 of the support 5 and the pads.
15 de métallisation des circuits intégrés 11. Ces étapes sont bien entendu réalisées pour l'ensemble des circuits intégrés 11 situés à l'intérieur du support 5.These steps are of course carried out for all the integrated circuits 11 located inside the support 5.
Plus précisément, la figure 8 montre une étape dans laquelle on réalise des ouvertures (vias) 16 sur les plots 15 de métallisation des circuits intégrés 11 et sur les plots de connexion 7.1 du support 5.More precisely, FIG. 8 shows a step in which openings (vias) 16 are made on the metallization pads 15 of the integrated circuits 11 and on the connection pads 7.1 of the support 5.
Comme la couche 18 est un polymère diélectrique photo-sensible, on utilise un outil de photo-lithographie classique pour définir les ouvertures 16. L'utilisation de cet outil peut impliquer la définition de marques d'alignement sur les circuits intégrés 11 et le support 5.Since the layer 18 is a photo-sensitive dielectric polymer, a conventional photo-lithography tool is used to define the openings 16. The use of this tool may involve the definition of alignment marks on the integrated circuits 11 and the support 5.
Il est à noter que les plots 15 sont réalisés à travers la couche de passivation 19 isolant et protégeant l'ensemble du circuit intégré 11. Ces plots 15 sont réalisés durant le processus de fabrication du circuit intégré.It should be noted that the pads 15 are made through the passivation layer 19 insulating and protecting the entire integrated circuit 11. These pads 15 are made during the manufacturing process of the integrated circuit.
La figure 9 montre une étape dans laquelle on dépose une sous- couche 21 mince métallique d'un alliage de titane et de tungstène (couche de TiW) sur l'ensemble du support 5. Cette sous-couche 21 est ainsi déposée sur la couche 18 et dans les vias 16. Cette sous-couche 21 joue le rôle de barrière de diffusion pour le cuivre des liaisons à réaliser afin d'éviter que ce cuivre ne pénètre dans le silicium des circuits 11 à travers la métallisation utilisée pour réaliser les plots 15.FIG. 9 shows a step in which a thin metal sub-layer 21 of a titanium-tungsten alloy (TiW layer) is deposited on the entire support 5. This sub-layer 21 is thus deposited on the layer 18 and in the vias 16. This sub-layer 21 acts as a diffusion barrier for the copper connections to be made to prevent this copper from entering the silicon circuits 11 through the metallization used to make the pads 15.
La figure 10 montre une étape dans laquelle on dépose une coucheFigure 10 shows a step in which a layer is deposited
25 de résine photo-sensible. Des ouvertures 28, qui définissent les chemins des liaisons électriques entre les plots 15 des circuits intégrés 11 et les plots de connexion 7.1 du support 5, sont réalisées dans la couche 25. Ces ouvertures 28 sont définies par une opération de photo-lithographie.25 of photosensitive resin. Apertures 28, which define the paths of the electrical connections between the pads 15 of the integrated circuits 11 and the connection pads 7.1 of the support 5, are formed in the layer 25. These openings 28 are defined by a photo-lithography operation.
La figure 11 montre une étape dans laquelle on réalise un dépôt sélectif électrolytique d'une couche 27 de cuivre présentant de préférence une épaisseur d'au moins 5 micromètres. A cet effet, la sous-couche 21 fait office de couche de conduction polarisée pour l'ensemble du support 5, le dépôt de la couche 27 ne s'effectuant que dans les ouvertures 28 où est présente la sous-couche métallique 21 non recouverte de résine.FIG. 11 shows a step in which an electrolytic selective deposition of a copper layer 27 preferably having a thickness of at least 5 microns is carried out. For this purpose, the underlayer 21 acts as a polarized conduction layer for the whole of the support 5, the deposition of the layer 27 being effected only in the openings 28 where is present the metal underlayer 21 not covered of resin.
En variante, pour réaliser les connexions entre les plots 15 et les plots de connexion 7.2, on met en œuvre une technique dite de « lift off ». Dans cette technique, on réalise les ouvertures définissant les liaisons électriques dans une couche de résine photosensible et, après cuisson et développement, on réalise les liaisons par évaporation du cuivre. Le métal déposé sur la couche de résine situé autour des connexions est éliminé à l'aide d'un solvant en même temps que la résine. En variante, le dépôt de cuivre est remplacé par un dépôt d'or réalisé par évaporation.Alternatively, to make the connections between the pads 15 and the connection pads 7.2, it implements a so-called "lift off" technique. In this technique, the openings defining the electrical connections are made in a photosensitive resin layer and, after firing and development, the bonds are made by evaporation of the copper. The metal deposited on the resin layer around the connections is removed with a solvent at the same time as the resin. In a variant, the copper deposit is replaced by a gold deposit produced by evaporation.
La figure 12 montre une étape dans laquelle on retire la couche 25 de résine qui avait été utilisée pour définir les chemins de connexions par une technique de gravure plasma d'oxygène. En outre, on grave la sous-couche métallique 21 de TiW par une technique RIE, afin de la retirer dans les zones autres que celles où sont réalisées les liaisons électriques. On obtient ainsi des liaisons électriques entre les plots 15 du circuit 11 et les plots de connexion 7.1 du support 5.Figure 12 shows a step in which the resin layer 25 that was used to define the connection paths was removed by an oxygen plasma etching technique. In addition, the metal sublayer 21 of TiW is etched by a RIE technique, in order to remove it in the zones other than those where the electrical connections are made. Electrical connections are thus obtained between the pads 15 of the circuit 11 and the connection pads 7.1 of the support 5.
La figure 13 montre une étape dans laquelle on dépose une fine couche 29 de polymère diélectrique photosensible de type BCB (semblable à la couche 18) sur la surface du support 5 afin de protéger mécaniquement et thermiquement les liaisons 27 électriques.FIG. 13 shows a step in which a thin layer 29 of photosensitive dielectric polymer of the BCB type (similar to the layer 18) is deposited on the surface of the support 5 in order to mechanically and thermally protect the electrical links 27.
L'ensemble des opérations décrites dans les figures 8 à 13 peuvent être répétées plusieurs fois pour intégrer plusieurs niveaux de connexions, de manière comparable à l'intégration multi-niveaux pratiquée dans le processus de fabrication d'un circuit intégré.All the operations described in FIGS. 8 to 13 may be repeated several times to integrate several levels of connections, in a manner comparable to the multilevel integration practiced in the manufacturing process of an integrated circuit.
Les étapes des figures 14 à 17 permettent de fixer des anneaux 31 , 32 de soudure sur les faces avant et arrière du support 5, autour des faces des circuits 11 débouchant sur l'extérieur. Comme on va le voir, ces anneaux 31 , 32 permettent la soudure de capots assurant l'herméticité de chaque circuit intégré 11 du support 5.The steps of FIGS. 14 to 17 make it possible to fix welding rings 31, 32 on the front and rear faces of the support 5, around the faces of the circuits 11 opening on the outside. As will be seen, these rings 31, 32 allow the welding of covers ensuring the hermetic integrity of each integrated circuit 11 of the support 5.
Plus précisément, dans l'étape de la figure 14, on élimine tout d'abord les dépôts de diélectrique 29 présents sur les connexions 7.2. A cet effet, on réalise une étape de photo-lithographie classique en déposant et définissant une couche 35 de résine photosensible sur les zones de diélectrique à conserver. Le diélectrique 29 non recouvert de résine 35 est éliminé par gravure plasma de type RIE.More precisely, in the step of FIG. 14, the dielectric deposits 29 present on the connections 7.2 are first removed. For this purpose, a conventional photo-lithography step is carried out by depositing and defining a photoresist layer 35 on the dielectric zones to be preserved. The dielectric 29 not covered with resin 35 is removed by plasma etching of the RIE type.
Dans une étape représentée à la figure 15, par une séquence de lift- off classique, l'on réalise un anneau 31 de soudure autour de la face active de chaque circuit intégré 11. Cet anneau 31 est positionné autour de la couche restante de diélectrique 29, entre les connexions 7.1 et 7.2 qui s'étendent en surface du support 5. Cet anneau 31 est de préférence composé d'une couche de nickel et d'une couche d'or.In a step shown in FIG. 15, by a conventional lift-off sequence, a solder ring 31 is made around the active face of each integrated circuit 11. This ring 31 is positioned around the remaining dielectric layer 29, between the connections 7.1 and 7.2 which extend on the surface of the support 5. This ring 31 is preferably composed of a layer of nickel and a layer of gold.
Dans la pratique, la couche de résine 35 peut également servir de résine de la séquence de lift-off de réalisation de l'anneau 31 , la couche de nickel/or étant dans ce cas déposée également sur le plot de connexion 7.2. Dans une étape représentée à la figure 16, on dépose une couche 39 de résine sur la face avant du support 5 portant les anneaux 31 de manière à protéger ces anneaux 31 . Et on réalise une séquence de lift-off classique pour réaliser l'anneau 32. Les anneaux 31 et 32 sont sensiblement symétriques par rapport à un plan perpendiculaire au plan de la feuille qui sépare le support 5 en deux parties identiques.In practice, the resin layer 35 may also serve as a resin of the lift-off sequence for producing the ring 31, the nickel / gold layer being in this case also deposited on the connection pad 7.2. In a step shown in FIG. 16, a layer 39 of resin is deposited on the front face of the support 5 carrying the rings 31 so as to protect these rings 31. And a conventional lift-off sequence is performed to make the ring 32. The rings 31 and 32 are substantially symmetrical with respect to a plane perpendicular to the plane of the sheet which separates the support 5 into two identical parts.
On élimine ensuite la couche 39 dans une étape représentée à la figure 17. Dans la pratique, la création de l'anneau 32 et l'élimination de la couche 39 sont effectuées simultanément lors de la séquence de lift-off. La figure 18 montre une plaquette 41 obtenue à l'issue des étapes précédentes. Cette plaquette 41 comporte les circuits intégrés 1 1 implantés à l'intérieur des cavités 6 du support 5.The layer 39 is then removed in a step shown in FIG. 17. In practice, the creation of the ring 32 and the elimination of the layer 39 are performed simultaneously during the lift-off sequence. Figure 18 shows a wafer 41 obtained at the end of the previous steps. This plate 41 comprises the integrated circuits 1 1 implanted inside the cavities 6 of the support 5.
En découpant le support 5 autour de chaque cavité 6 suivant les chemins 42 de découpe de forme globalement carrée, on obtient des circuits 43 individuels encapsulés. Chaque circuit 43 comporte un circuit intégré 11 implanté à l'intérieur d'un support individuel 45, les plots 15 reliés aux pistesBy cutting the support 5 around each cavity 6 along the cutting paths 42 of generally square shape, individual circuits 43 are obtained encapsulated. Each circuit 43 comprises an integrated circuit 11 implanted inside an individual support 45, the pads 15 connected to the tracks
7 étant déportés vers les plots de connexions 7.2.7 being deported to the connection pads 7.2.
Les figures 19 et 20 montrent les étapes à réaliser sur chaque circuit individuel 43 pour fermer hermétiquement ces circuits et réaliser le réseau de connexion final. A cet effet, la figure 19 représente une étape dans laquelle on soude deux capots rapportés 47 et 48, présentant en coupe une forme deFigures 19 and 20 show the steps to be performed on each individual circuit 43 to seal these circuits and achieve the final connection network. For this purpose, FIG. 19 represents a step in which two attached hoods 47 and 48 are welded, presenting in section a shape of
C, respectivement sur les faces avant et arrière de chaque circuit 43.C, respectively on the front and rear faces of each circuit 43.
Plus précisément, chaque capot 47, 48 comporte un anneau de soudure 49, 50 composé d'une couche de nickel et d'une couche d'or. Ces anneaux 49, 50 sont plaqués respectivement contre les anneaux 31 et 32 du circuit 43 individuel encapsulé. La fixation entre les capots 47 et 48 et le support 45, ou plus précisément la fixation entre leur anneau de soudure, se fait de manière classique dans un four à passage par exemple. Le support individuel 45 constitue ainsi le corps du boîtier final. Dans une dernière étape représentée à la figure 20, on reporte par soudure un élément 55 de connexion de type SCI (Solid Column Interposer, de la société NTK) comportant des colonnes 56 de connexion. Ce SCI est positionné contre le support 45 individuel, autour du capot 47 positionné du côté des plots de connexion 7.2 du support individuel. Les colonnes 56 du SCI 55 sont soudées aux plots de connexion 7.2. On obtient ainsi un boîtier final de type BGA. Les colonnes 56 du SCI 55 permettent l'interfaçage du circuit 43 individuel avec un circuit imprimé.More specifically, each cover 47, 48 comprises a solder ring 49, 50 composed of a layer of nickel and a layer of gold. These rings 49, 50 are respectively plated against the rings 31 and 32 of the individual circuit 43 encapsulated. The attachment between the covers 47 and 48 and the support 45, or more precisely the fixing between their welding ring, is conventionally made in a passage oven for example. The individual support 45 thus constitutes the body of the final housing. In a last step shown in FIG. 20, a connector 55 of the SCI type (Solid Column Interposer, FIG. NTK) with connection columns 56. This SCI is positioned against the individual support 45 around the cover 47 positioned on the side of the connection pads 7.2 of the individual support. The columns 56 of the SCI 55 are welded to the connection pads 7.2. This produces a final BGA type package. The columns 56 of the SCI 55 allow the interface of the individual circuit 43 with a printed circuit.
Par ailleurs, il est à noter que les plots 15 des circuits intégrés peuvent prendre deux formes différentes représentées sur les figures 21 et 22. La figure 21 montre une représentation schématique d'un circuit intégré 1 comportant des plots 15 simples classiques.Furthermore, it should be noted that the pads 15 of the integrated circuits can take two different forms represented in FIGS. 21 and 22. FIG. 21 shows a schematic representation of an integrated circuit 1 comprising conventional single pads.
Chaque plot 15 est constitué d'une zone 135 de métal recouverte d'une couche de passivation 136 dans laquelle une fenêtre a été définie via une opération de photo lithographie classique. La zone de métal 135 réalisée en aluminium ou à l'aide d'un empilement de couches de titane, nitrure de titane, titane-tungstène, tantale, nitrure de tantale, molybdène, ruthénium, aluminium ou alliage aluminium-cuivre et aluminium silicium cuivre présente la forme d'un carré de 80 micromètres de côté, la fenêtre définie dans la passivation comportant une ouverture carrée de 70 micromètres de côté.Each stud 15 consists of a metal zone 135 covered with a passivation layer 136 in which a window has been defined via a conventional photo lithography operation. The metal zone 135 made of aluminum or using a stack of layers of titanium, titanium nitride, titanium-tungsten, tantalum, tantalum nitride, molybdenum, ruthenium, aluminum or aluminum-copper alloy and aluminum silicon copper has the shape of a square of 80 micrometers side, the window defined in the passivation having a square opening of 70 micrometers side.
Toutefois, une telle réalisation peut engendrer des problèmes lors du test de fonctionnement des circuits intégrés, les outils utilisés pour établir les connexions avec les appareils de mesure pouvant endommager le plot 15. Or un plot endommagé peut diminuer la fiabilité de la connexion électrique réalisée entre les plots 15 de la figure 8 et les plots de connexion 7.1 du support 5. Dans la réalisation selon la figure 22, le plot 15 est dédoublé pour garantir la fiabilité de la connexion 11 métallique entre les plots et un élément extérieur. Ainsi, le plot 15 comporte deux surfaces 139, 140 de connexions reliées entre elles, ces deux surfaces 139, 140 possédant chacune une aire suffisante pour établir une connexion avec un outil de mesure ou une liaison électrique avec une connexion extérieure au circuit.However, such an embodiment can cause problems during the test of operation of the integrated circuits, the tools used to establish the connections with the measuring devices can damage the pad 15. Or a damaged stud can reduce the reliability of the electrical connection made between the pads 15 of Figure 8 and the connection pads 7.1 of the support 5. In the embodiment according to Figure 22, the pad 15 is split to ensure the reliability of the metal connection 11 between the pads and an outer member. Thus, the stud 15 has two surfaces 139, 140 interconnected connections, these two surfaces 139, 140 each having a sufficient area to establish a connection with a measuring tool or an electrical connection with a connection outside the circuit.
La première surface de connexion 139 est utilisée pour tester le fonctionnement des circuits intégrés. La deuxième surface de connexion 140 est utilisée pour la connectique entre le circuit intégré 1 et les pistes du support 5. L'utilisation d'une surface de connexion dédiée à la connectique permet une meilleure adhérence des dépôts métalliques sur le plot et fiabilise ainsi la connexion entre les plots et les pistes. En variante, la couche de cuivre recouvre les deux surfaces de connexion 139, 140.The first connection surface 139 is used to test the operation of the integrated circuits. The second connection surface 140 is used for the connection between the integrated circuit 1 and the tracks of the support 5. The use of a connection surface dedicated to the connector allows a better adhesion of the metal deposits on the stud and reliability thus the connection between the studs and the tracks. In a variant, the copper layer covers the two connection surfaces 139, 140.
Dans un exemple, pour réaliser les deux surfaces de connexion 139,In one example, to make the two connection surfaces 139,
140, on réalise par opération de photolithographie classique deux ouvertures 142 et 143 dans une couche 141 de passivation déposée sur une zone conductrice 144 rectangulaire de 135 micromètres sur 80 micromètres. Cette zone conductrice 144 est reliée à une entrée ou à une sortie du circuit.140, two apertures 142 and 143 are made by conventional photolithography operation in a passivation layer 141 deposited on a rectangular conductor zone 144 of 135 micrometers by 80 micrometers. This conducting zone 144 is connected to an input or an output of the circuit.
Les deux surfaces de connexion 139, 140 ainsi définies présentent sensiblement la forme d'un carré de 60 micromètres de côté. La zone conductrice 144 peut être réalisée dans le même matériau que la zone 135.The two connection surfaces 139, 140 thus defined have substantially the shape of a 60-micrometer square. The conductive zone 144 may be made of the same material as the zone 135.
L'invention s'étend également au circuit intégré obtenu avec le procédé décrit ci-dessus. The invention also extends to the integrated circuit obtained with the method described above.

Claims

REVENDICATIONS
1 - Procédé de fabrication d'un circuit intégré (11 ) encapsulé dans un support (45) individuel, le circuit intégré (11 ) comportant des plots (15) conducteurs sur sa face (12) active, les plots (15) étant connectés à des entrées/sorties du circuit intégré (11 ), caractérisé en ce qu'il comporte les étapes suivantes :1 - A method of manufacturing an integrated circuit (11) encapsulated in a support (45) individual, the integrated circuit (11) having pads (15) conductive on its face (12) active, the pads (15) being connected to inputs / outputs of the integrated circuit (11), characterized in that it comprises the following steps:
- positionner contre une plaque (1 ) de verre un support (5) comportant une matrice de cavités (6) traversantes et de pistes (7) conductrices, - déposer des circuits intégrés (11 ) dans les cavités (6) du support (5), de sorte que chaque circuit intégré (11 ) se trouve à l'intérieur d'une cavité,positioning a support (5) with a matrix of cavities (6) through and conducting tracks (7) against a plate (1) of glass; - depositing integrated circuits (11) in the cavities (6) of the support (5); ), so that each integrated circuit (11) is inside a cavity,
- injecter de la résine (14) dans les cavités (6) entre les parois des cavités (6) et les parois extérieures des circuits intégrés (11 ),injecting resin (14) into the cavities (6) between the walls of the cavities (6) and the outer walls of the integrated circuits (11),
- réaliser, par dépôt de couches minces, des liaisons (27) électriques entre les pistes des cavités (6) et les plots (15) pour l'ensemble des circuits intégrés (11 ) implantés dans le support (5), et- Making, by deposition of thin layers, electrical connections (27) between the tracks of the cavities (6) and the pads (15) for all the integrated circuits (11) implanted in the support (5), and
- découper autour de chaque cavité (6) de manière à obtenir des circuits (43) individuels comportant chacun un circuit intégré (11 ) implanté sur un support (45) individuel. 2 - Procédé selon la revendication 1 , caractérisé en ce que :- Cut around each cavity (6) so as to obtain individual circuits (43) each comprising an integrated circuit (11) implanted on a support (45) individual. 2 - Process according to claim 1, characterized in that:
- la plaque (1 ) de verre et le support (5) présentent la forme d'une pseudo-plaquette de silicium.the glass plate (1) and the support (5) are in the form of a pseudo-silicon wafer.
3 - Procédé selon la revendication 1 ou 2, caractérisé en ce que :3 - Process according to claim 1 or 2, characterized in that:
- les pistes (7) du support et les faces (12) actives des circuits intégrés (11 ) sont positionnés du côté de la plaque (1 ).the tracks (7) of the support and the active faces (12) of the integrated circuits (11) are positioned on the side of the plate (1).
4 - Procédé selon l'une des revendications 1 à 3, caractérisé en ce qu'il comporte l'étape suivante :4 - Process according to one of claims 1 to 3, characterized in that it comprises the following step:
- positionner entre le support (5) et la plaque (1 ) de verre un film (2) adhésif, tel qu'une couche de résine de type polyimide, un film polyvinyle ou une couche de cire, pour fixer le support (5) et les circuits (11 ) intégrés sur cette plaque (1 ).positioning between the support (5) and the glass plate (1) an adhesive film (2), such as a layer of polyimide resin, a polyvinyl film or a layer of wax, for fixing the support (5) and the circuits (11) integrated on this plate (1).
5 - Procédé selon l'une des revendications 1 à 4, caractérisé en ce que, après l'injection de résine (14), il comporte l'étape suivante :5 - Process according to one of claims 1 to 4, characterized in that, after the injection of resin (14), it comprises the following step:
- effectuer le rodage du support (5) de manière à positionner une face des circuits intégrés, la couche de résine (14) entre le circuit et le support, et le support (5) dans un même plan. 6 - Procédé selon l'une des revendications 1 à 5, caractérisé en ce que, avant de réaliser les liaisons (27) électriques entre les pistes (7) et les plots (15), il comporte l'étape suivante :- Run-in the support (5) so as to position one face of the integrated circuits, the resin layer (14) between the circuit and the support, and the support (5) in the same plane. 6 - Method according to one of claims 1 to 5, characterized in that, before making the connections (27) between electric tracks (7) and the pads (15), it comprises the following step:
- déposer une couche (18) de résine BCB ou tout autre polymère photo-sensible de faible constante diélectrique (k < 3.5) sur l'ensemble du support (5), de manière à mettre à niveau les faces (12) actives des circuits intégrés (11 ) et les pistes (7) du support.depositing a layer (18) of BCB resin or any other photosensitive polymer of low dielectric constant (k <3.5) on the entire support (5), so as to level the active faces (12) of the circuits integrated (11) and the tracks (7) of the support.
7 - Procédé selon l'une des revendications 1 à 6, caractérisé en ce que, pour réaliser les liaisons (27) électriques entre les pistes (7) et les plots (15), il comporte les étapes suivantes :7 - Method according to one of claims 1 to 6, characterized in that, to achieve the connections (27) between electrical tracks (7) and the pads (15), it comprises the following steps:
- réaliser des vias (16) sur les plots (15) des circuits intégrés et sur les pistes (7) du support,- Making vias (16) on the pads (15) of the integrated circuits and on the tracks (7) of the support,
- déposer sur l'ensemble du support (5) une sous-couche (21 ) de matériau conducteur jouant un rôle de barrière de diffusion pour le dépôt de matériau conducteur à réaliser,depositing on the entire support (5) an underlayer (21) of conductive material acting as a diffusion barrier for the deposition of conductive material to be produced,
- déposer une couche (25) de résine dans laquelle sont réalisées par photo-lithographie classique des ouvertures (28) définissant les chemins des liaisons électriques entre les pistes (11) du support et les plots (15) des circuits intégrés, - réaliser un dépôt sélectif électrolytique d'une couche (27) de matériau conducteur à l'intérieur des ouvertures (28) sur le métal de la sous- couche (21 ),- Depositing a layer (25) of resin in which are made by conventional photo-lithography openings (28) defining the paths of the electrical connections between the tracks (11) of the support and the pads (15) of the integrated circuits, - achieve a selective electrolytic deposition of a layer (27) of conductive material inside the openings (28) on the metal of the underlayer (21),
- retirer la couche (25) de résine utilisée pour définir les chemins des liaisons, et - graver la sous-couche (21) de matériau conducteur excédentaire pour la retirer.removing the layer (25) of resin used to define the paths of the bonds, and - etching the underlayer (21) of excess conductive material to remove it.
8 - Procédé selon la revendication 7, caractérisé en ce que :8 - Process according to claim 7, characterized in that:
- on dépose la couche (27) de matériau conducteur de manière qu'elle présente une épaisseur d'au moins 5 micromètres. 9 - Procédé selon la revendication 7 ou 8, caractérisé en ce qu'il comporte l'étape suivante :the layer (27) of conductive material is deposited so that it has a thickness of at least 5 microns. 9 - Process according to claim 7 or 8, characterized in that it comprises the following step:
- déposer une couche (29) de diélectrique photosensible sur les liaisons (27) électriques réalisées pour les protéger.depositing a layer (29) of photosensitive dielectric on the links (27) made to protect them.
10 - Procédé selon l'une des revendications 1 à 9, caractérisé en ce qu'il comporte l'étape suivante : - fermer hermétiquement le circuit (43) individuel par deux capots (47, 48) rapportés.10 - Method according to one of claims 1 to 9, characterized in that it comprises the following step: - Close the circuit (43) individually by two covers (47, 48) reported.
11 - Procédé selon la revendication 10, caractérisé en ce que pour fermer le circuit (43) individuel, il comporte les étapes suivantes : - réaliser deux anneaux (31 , 32) de soudure autour des faces débouchantes des circuits intégrés (11 ) de la plaque (5),11 - Process according to claim 10, characterized in that to close the circuit (43) individual, it comprises the following steps: - achieve two rings (31, 32) of solder around the open faces of the integrated circuits (11) of the plate (5),
- fixer un capot (47, 48) sur chacun de ces anneaux (31 , 32) de soudure,- Fix a cover (47, 48) on each of these rings (31, 32) of welding,
- chaque capot (47, 48) comportant également un anneau (49, 50) de soudure, les anneaux (49, 50) de soudure du capot étant fixés aux anneauxeach cover (47, 48) also comprising a ring (49, 50) for welding, the rings (49, 50) for welding the cover being attached to the rings
(31 , 32) de soudure réalisés autour de chaque circuit (11 ) intégré.(31, 32) formed around each integrated circuit (11).
12 - Procédé selon la revendication 11 , caractérisé en ce que pour réaliser les anneaux (31 , 32) autour des circuits intégrés, il comporte les étapes suivantes : - réaliser un premier anneau (31) sur le support autour de la face active (12) de chaque circuit intégré par une technique de lift-off,12 - Process according to claim 11, characterized in that to make the rings (31, 32) around the integrated circuits, it comprises the following steps: - to make a first ring (31) on the support around the active face (12 ) of each integrated circuit by a lift-off technique,
- déposer une couche (39) de résine sur la face du support portant le premier anneau (31 ) de manière à protéger ce premier anneau (31 ),depositing a layer (39) of resin on the face of the support carrying the first ring (31) so as to protect this first ring (31),
- réaliser le deuxième anneau (32) sur le support autour de la face du circuit intégré opposée à la face active (12) par une technique de lift-off, et- Making the second ring (32) on the support around the face of the integrated circuit opposite to the active face (12) by a lift-off technique, and
- éliminer la couche (39) de protection.- Remove the layer (39) of protection.
13 - Procédé selon l'une des revendications 1 à 12, caractérisé en ce qu'il comporte les étapes suivantes :13 - Method according to one of claims 1 to 12, characterized in that it comprises the following steps:
- reporter par soudure un SCI (Solid Column Interposer) (55) contre le support individuel, ce SCI comportant des colonnes (56) de connexion soudées aux pistes (7.2) du support individuel.- Postpone by welding a SCI (Solid Column Interposer) (55) against the individual support, this SCI having connection columns (56) soldered to the tracks (7.2) of the individual support.
14 - Procédé selon l'une des revendications précédentes, caractérisé en ce qu'il comporte l'étape suivante :14 - Method according to one of the preceding claims, characterized in that it comprises the following step:
- dédoubler chaque plot (15) du circuit intégré de manière que chaque plot possède une première (139) et une deuxième (140) surface de connexion,- Split each pad (15) of the integrated circuit so that each pad has a first (139) and a second (140) connection surface,
- la première surface (139) de connexion étant utilisée pour réaliser des tests de fonctionnement du circuit intégré (1 ),the first connection surface (139) being used to carry out functional tests of the integrated circuit (1),
- la deuxième surface (140) de connexion étant utilisée pour la connectique du circuit intégré (1 ) avec un autre élément,the second connection surface (140) being used for the connection of the integrated circuit (1) with another element,
- les surfaces de connexions (139, 140) étant reliées entre elles. 15 - Procédé selon la revendication 14, caractérisé en ce que pour réaliser les deux surfaces de connexion (139, 140), il comporte les étapes suivantes :- The connection surfaces (139, 140) being interconnected. 15 - Process according to claim 14, characterized in that to achieve the two connection surfaces (139, 140), it comprises the following steps:
- réaliser deux ouvertures (142, 143) dans une couche de passivation (141 ) déposée au dessus d'une zone conductrice (144) rectangulaire reliée à une entrée ou une sortie du circuit intégré.- Making two openings (142, 143) in a passivation layer (141) deposited above a rectangular conductive zone (144) connected to an input or an output of the integrated circuit.
16 - Procédé selon la revendication 15, caractérisé en ce que :16 - Process according to claim 15, characterized in that:
- la zone conductrice (144) présente une dimension de 135 micromètres sur 80 micromètres, - les deux surfaces de connexion (139, 140) réalisées présentant sensiblement la forme d'un carré de 60 micromètres de côté.- The conductive zone (144) has a size of 135 micrometers by 80 micrometers, - the two connection surfaces (139, 140) made substantially having the shape of a square of 60 micrometers side.
17 - Circuit intégré encapsulé obtenu avec le procédé selon l'une des revendications 1 à 16. 17 - encapsulated integrated circuit obtained with the method according to one of claims 1 to 16.
PCT/FR2007/051746 2006-07-28 2007-07-27 Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit WO2008012481A1 (en)

Applications Claiming Priority (2)

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FR06/53190 2006-07-28
FR0653190A FR2904472B1 (en) 2006-07-28 2006-07-28 METHOD FOR MANUFACTURING ENCAPSULE INTEGRATED CIRCUIT AND INTEGRATED ENCAPSULE INTEGRATED CIRCUIT

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