WO2007146859A1 - Integrated transistor devices - Google Patents

Integrated transistor devices Download PDF

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Publication number
WO2007146859A1
WO2007146859A1 PCT/US2007/070843 US2007070843W WO2007146859A1 WO 2007146859 A1 WO2007146859 A1 WO 2007146859A1 US 2007070843 W US2007070843 W US 2007070843W WO 2007146859 A1 WO2007146859 A1 WO 2007146859A1
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Prior art keywords
layer
oxygen
gallium
aluminum
compound semiconductor
Prior art date
Application number
PCT/US2007/070843
Other languages
French (fr)
Inventor
Walter David Braddock
Original Assignee
Osemi, Inc.
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Publication date
Application filed by Osemi, Inc. filed Critical Osemi, Inc.
Publication of WO2007146859A1 publication Critical patent/WO2007146859A1/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

Definitions

  • the present invention pertains to low power and high speed integrated circuits in the
  • V2 circuit technology exhibits faster and more optimized speed/power performance
  • IH-V compound semiconductors include GaAt, AiAs, InAx. GaN, AlN, ffiN. InP, (k ⁇ AW. s and (MN, InN, AiN ' , GaSb, InSb. and AiSb and ternary and quaternary and arbitrary mixtures
  • SK >0 may ide an effective gate insulator on TTl-V compound semiconductor
  • an effective gate insulator on that surface may be formed by s s a Sl rst layer containing substantial amounts of aluminum and oxygen, and a second layer that
  • the first layer preferably comprises at least Hi percent atoms of
  • 2 i alummum preferably more than 30 percent atoms of aluminum, preferably about 4» percent 22 atoms of aluminum ⁇ for an A12O3 ratio? and up to about filly percent atoms of alummum.
  • the first layer may comprise for example either or both of A12O3 and A12O (Aluminum sub-
  • the second laser comprises, substantia! amounts of at least three elements.
  • the second ias er forn ⁇ s a teniasy compound Preferably, the second ias er forn ⁇ s a teniasy compound.
  • 26 preferably includes lemar> ⁇ compo ⁇ jids.
  • the preferred ternary compounds include aluminum
  • the ternary compound is insulating,
  • the metallic 2 « third element of the ternary compound preferably is one of C i ) any rare earth including but 2 ! > not limited io ( 3d (Gadolinium), (2) 4d transition elements Y (Yttrium) and Zr (Zirconium), 30 and (3) 5d transition elements Hf (Hafnium).
  • Ta Teantalum.
  • W Tungsten
  • Rc Rhenium
  • the ternary compound may also include a mixture of more 1 than one of the metallic third element, the ternary element, of the ternary compound.
  • semiconductor including Aluminum (such as AiAs, AiN, mixtures of AiAs and Ci&As, and
  • an effective gate insulator on thai surface may be formed by
  • the temars compound includes
  • the ternary compound is insulating.
  • TTse ternary s element of the le-mary compound preferably includes at least one of ( I ) any rare earth
  • the ternary compound may also include a
  • the ternary metal element is Gd or Bf.
  • Alternatives preferred for the si ternary metal element are Jr and Y.
  • the structures include at least one of GaAs, AlAs, InAs, GaN, AlN, InN. s 7 iiiSb. GaSb and mixtures thereof These compound semiconductors provide the most
  • the u ⁇ eiuson provides a metal-oxide-conipo ⁇ nd semiconductor UeM
  • a gate insulator structure comprising a first layer and a second laye ⁇ . said gate z 5 insulator on said upper surface, said first Sa> er hi contact with said upper surface;
  • said first las er comprises substantia! amounts of at least one of (1 > aluminum
  • the jtn enti ⁇ n pros ides a metal-oxide-compound semiconductor
  • M comprises; 1 a compound semiconductor wafer structure bax ing an upper surface;
  • a gate insulator str ucture comprising a ft rst layer and a second e?, said gate ? insulator on said upper surface, said first layer in contact with said upper surface:
  • said first layer comprises substantial amounts of at least one of ( 11 aluminum
  • said second layer comprises at least one compound of gallium, oxygen and at
  • At least one metallic third element comprises at least one of (U am rare
  • H elements Rf (Hafnium). Ta (Tantalum). W (Tungsten). Re (Rhenium). Os (Osmium), and Ir
  • ⁇ ( > HO ! is simplified cross sectional view of a self-aligned enhancement mode s 7 compound semiconductor MOSF EI " in accordance with a preferred embodi meat of the s a present
  • the present invention provides, among other things, a self-aligned enhancement mode
  • the FBT includes, a gallium oxygen insulating
  • the first layer is most preferabk
  • insulating layer in the gallium oxide insulating structure is composed of an insulator that does
  • This upper layer roust possess excellent insulating qualities, and is most typically composed ( ⁇ > of gallium oxygen and a third rare earth element that together form a tertian ' insulating
  • the FET includes a aluminum cm gen so insulating structure that Ls composed of at least two distinct layers. The first layer is most
  • S i preferable more that 1 o angstroms thick but less thai 25 angstroms m thickness and
  • V2 composed substantially of gallium oxygen compounds including but not limited to
  • the upper insulating layer in the gallium oxide insulating structure is composed s 5 of an insulator that does not intermix.
  • This upper layer must possess excellent insulating qualities, and is s 7 most typicMK composed of Aluminum owgen and a third rare earth element that together i s form a ternary insulating materia ⁇ .
  • the e ⁇ t ⁇ e gate insulato* structuje is composed of at l «a.st wo hy ers, a first 20 layer and a second layer, which may or may not have a composition gradient therein.
  • 2 i may be a composition gradient where the first layer blends into the second layer. Additional 22 la. ⁇ ers ma> be included on top of the fust and second ia> ers. Together the gallium oxygen.
  • This region may be used for the gale insulators of a compound
  • the first layer ⁇ gallium and o ⁇ > gen. aluminum and o ⁇ vgen. or mixture of gallium 2 « and aluminum and oxygen) forms an atomically abrupt interlace with the top las er of ihe ,? ! > compound semiconductor wafer ⁇ mtchire, and »t does not introduce mid-gap surface states 30 into the compound semiconductor material.
  • a refractor metal gate is positioned on the
  • r ⁇ uiti-kryer gale insulator .structure has the multi-layer gate insulator structure being s preferably 3D- 25s ) angstroms in thickness and positioned on the upper surface of the
  • the Preferred so initial metal layer of lhe gate metal stack is the- rare earth element used in the ternary upper
  • V2 gate insulator structure is Ga x Gd v ⁇ X
  • one preferred initial layer in the gate metal is iC ⁇ ) ⁇ Gadolinium
  • iridium is also a preferred initial metal in the gate metal stack because fr oxide s ⁇ is a refractory oxide and also a cond ⁇ cth e oxide, facilitating a low gate resistance s 5
  • Some embodiment also comprise compound semiconductor het ⁇ ro-sfcructures
  • Some preferred embodiments comprise the compound semiconductor hetero-str ⁇ cture 22 b «inu irivGaj- j As. AlJfii.xAs with or without ⁇ -type and ' or p « charge supph ing !a> eis
  • Some preferred embodiments comprise the compound semiconductor hetero-structure
  • FIG I is simplified cross sectional view of a self-aligned e ⁇ ha ⁇ cemerU mode
  • Deuce IO includes a compound semiconductor materia!, such as any iff-
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor so deposition
  • top layer ! 5 may simply be the
  • ⁇ Device IO further comprises a gate insulator structures (30) that includes at least two i 4 or more la> ers.
  • the first layer of the gate insulator structure ( 31 ⁇ is composed entirely of si gallium ovide compounds, aluminum oxide compounds, or gallium and aluminum oxygen
  • the first layer is in contact with and deposited upon the upper surface of the s 7 compound semiconductor st ruciure.
  • the second layer of the gate insul ator structure C 32 ) is s s composed of a compounds of gallium, oxygen, and one or more of ⁇ 1) rare earth elements
  • the initial gallium/aluminum oxygen layer Q] forms an
  • top insulating triatrial at elevated temperature is positioned on upper surface IS
  • Dielectric spacers 26 are positioned to cover the side-wails of
  • Source and drain contacts 1 ⁇ ) and 20 are deposited on self-aligned
  • T op GaAs layer (15) is used to form an aiomtcaii v abrupt layer with 1 the gale insulator structure an abrupi interface with iov. defect demiu
  • the ? top GaAs layer (15) may be replaced with a OaAiAs or AlAs top layer
  • S i oxide layer including the deposition of both gall turn oxygen and aluminum oxygen
  • V2 compounds In particular, it is possible Io deposit the suboxide compound, (such as G ⁇ £) or
  • the present invention i 5 includes methods of fab ⁇ eati m> the proper suboxide source material in-siat in the appropriate
  • indium suboxide (l ⁇ 2O) are use ⁇ in the deposition of the initial layer of the ⁇ gate insulator structure.
  • deposition of the second layer is initialed.
  • the second layer is
  • the deposition of die second layer starts by detecting the flux from a low power
  • the substrate temperature required to deposit a galls um* ⁇ > gen* rare earth !a>er is
  • S t layer of the gate insulator structure at ated temperature such as VVSi or WN is deposited ⁇ 2 on upper surface 18 of oxide layer 32 and subsequent! ⁇ patterned using standard lithography
  • ovide la> er 31 functions as cm etch stop
  • step 103 a layer consisting of galliu ⁇ valuroin ⁇ rn oxygen compounds including but
  • step 1 SM . an insulating layer of gallium/a! ummum oxygen and one of the
  • ⁇ > insulator structure is formed in steps. 104 and 105. so In step 106, a stable refractory gate metal is positioned on upper surface of said gate
  • step 1 UL source and drain ohrnic contacts are positioned on ion implanted source si and drain areas.
  • step 100 provides a compound semiconductor s 7 substrate such as GaAs, GaN. GaSb. InSb, or TnP.
  • s s Step I (»2 includes tbe preparation and epitaxial growth of an aiomically ordered and
  • Step 103 preferably comprises ihe ⁇ nai ev aporation lrom a punfied and crystalline
  • Step KM comprises the ibrmauon of a gallium and/or aluminums-oxygen- ⁇ metal
  • the 30 structure preferably functions as an etch stop layer such that the upper surface of the
  • the self-ahgned ( ⁇ > source and drain implarris are desirably annealed at approximately 700' 1 C m an ultra high
  • the self-aligned source and drain implams are desirably realized by s positioning dielectric spacers on the s ⁇ iewalls of the refractor ⁇ ' gate metal ⁇ > Fig S shows distinct regions of N IVIOSFET and P MOSFET on the same so semiconductor compound semiconductor wafer These distinct regions may be defined by
  • the new and improved self-aligned enhancement mode metal- s ⁇ oxide-compound semiconductor hetero-structure field effect transistors enable stable ami s 5 reliable device operation, provide optimum compound semi conductor device performance for
  • Another Preferred embodiment of the invention is to use Chemical Beam Epttaxy Io
  • the semiconductor wafer is transported in UHV to an oxide i deposition chamber where the b ⁇ -Sayer or multilayer gate insulator materia! is z deposited either selectively or n ⁇ n-seieciiveiy onto the wafer forming a j compound semiconductor structure with a gate insulator structure deposited on the

Abstract

A metal-oxide-compourtd semiconductor.field effect transistor structure (10) includes a first layer in contact with an upper surface (13) of a III-V compound semiconductor wafer structure and that contains Al Ga, and Oxygen, such as a mixture aluminum oxides and gallium oxides, and a second layer (14) that is insulating, that may contain substantial amounts of three elements, that may comprise a ternary- compound including a transition metal, aluminum or gallium, and oxygen, or a rare- earth, aluminum or gallium, and oxygen. Together the first layer and the second insulating las er form a gate insulating structure for a field effect transistor The initial essentially gallium/aluminum/oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer

Description

2 i TfFLE
4 INTeGRATKD TRANSISTOR DEVICES
A C ROSS REFERENCE TO RELATED AFPiJCA OONS
? This apphαnion claims priority to US provisional application having attorney docket s number OSHM-DB6f*P~US. application number ήo/812,61 K. filing date 6/ i 2/2«X)f\ and title o "INTEGRATED TRANSI STOR DEVICES" , and the content of that application is
H) incorporated herein by reference,
S i BACKGROUND OF TOE INVEN TION
V2 FIELD OF THE INVENTION
51 The present invention pertains to low power and high speed integrated circuits in the
M compound semiconductor field utilizing field effect transistors and more specifkalK si complementary field effect transistors used in concert including enhancement mode self-
}(> aligned metai-oxtde-compound semiconductor transistors and depletion mode self-aligned s 7 raetaj-oxide-cornpound semiconductor transistors and methods of materials growth and
S s fabrication of said structures and the integration of said transistors including small scale
S '> integration through ultra large- scale integration of said transistors.
20
21 DISCUSSION OF TME BACKGROUND
22 The gallium arsynide, gallium nitride, indium antimonide and iridium phosphide
2 * integrated circuit industry has been limited without a technology that simultaneously allows
24 the integration of complementary field effect transistor devices and transistors with low gate
25 leakage currents, In contrast io silicon technology thai has a very mature and useful
26 complementary raetaJ oxide semiconductor (("MOS) technology including low voltage
27 silicon CMOS for digital circuits and high voltage silicon CMOS used in Power Electronics 2« and high voltage electronics. Field effect transistor (FE-Ts) widely used m the IfI-V
2!> semiconductor industry employ metal gates and Scliotik} gate contacts, tb&t are have
30 quiescent-slate leakage currents exceeding mam microamps. The use of metal gates m
3 ϊ compound semiconductor technology further results in individual transistors and integrated i 1 circuits that
Figure imgf000003_0001
e excessiveh high power dissipation, reduced transconductance. reduced
2 logic swing and she inability to operate on a single power supply, and generally limited
? performance characteristics. The high magnitude of the quiescent leakage current limits the
4 maximum integration of GaAs
Figure imgf000003_0002
ices io circuits of several hundred thousand transistors for
5 tho.se skilled in the art ϊn contrast, the simultaneous integration of nwiy millions of
(■> transistors n possible at high integration densities using silicon CMOS technology These
? ultra high integration densities find levels cannot be obtained using metal, Scholtky-style s gates that are not insulated in compound semiconductor FETs Thus Si CMOS technoJog>
<> offers Significant advantages in terms of individual gate leal age. circuit integration level and so cos!
S t HoΛvever when compared to sil icon, complementary OaAs, InSb. GaN, and InP
V2 circuit technology exhibits faster and more optimized speed/power performance and
51 efficiency at a low supply voltage of IV and below. The market acceptance of these GaAs, s ■} InSI). GaN. and InP integrated circuit technologies remains low because of the lack of ability si to demonstrate high integration densities vviih low amounts of operating power Thus.
}(> silicon CMOS dominates the tick! of digital integrated circuitry and neither OaAs nor InP s 7 technologies can successfully penetrate this market i s WIi at is needed are new and improved compound semiconductor field effect
1 '> transistors (F ET ). What is also needed cue new and tmpro\ ed compound semi com! octof
20 FETs ussng meuti-oxule-seniieoriduetor junctions (MOSFET). What is also needed are new
2 i and improved compound semiconductor MOSFETs using a self-aligned gate structure. What 22 is also needed ai« new and
Figure imgf000003_0003
«d self-aligned compound semiconductor MOSFETs using
2 * enhancement mode and depletion mode operation. What is also needed are new and
24 improved self-aligned compound semiconductor MOSFETs with stable and reliable
Figure imgf000003_0004
tee
25 operation. What is also needed are new and improved self-aligned compound semiconductor
26 MOSFETs which enable optimum compound semiconductor device performance What is
27 needed is new and improved High Voltage HMOS. PMOS. and CMOS transistors in 2« Compound semiconductors including OaN and SiC What is, also needed are new and
2*> irøprox ed self-aligned compound semiconductor MOSFETs with optimum efficiency and
30 output pow cf for RF and microwave applications,. What is also needed are new and
3 ϊ improved seif-al igned compound semiconductor MOSFETs for use in complementary 1 circuits and architect arcs. What is also needed are new and improved self-aligned compound
2 semiconductor MOSFETs for Sow pcmer/high performance complementary circuits and ? architectures. What is also needed are new and imprcn ed sel f-al igned compound
4 semiconductor MOSFETs which offer the design flexibility of eomplemem&ry architectures.
5 What is also needed are new and. improved seif-ahgned compound semiconductor MOSf El s (■> which keep interconnection delays in ultra large scale integration under control. Whal is
? needed are new and useful complementary integrated circuits where each individual s transistor has a leakage current approaching H)" i J amp. What is needed is a truly useful
<> integrated circuit technology for GaAs. InSb, GaN. Si(\ and TnP that allows for the issefui so and economical operation of hosh srnaii scale integration and U LSf digital integrated circuits
S i in compound semiconductors. What is needed are new and improved compound
12 semiconductor MOSFET integrated circuits with very Sow net power dissipation What is 51 nseά&d are new and improved compound semiconductor MOSFET devices with low gate M leakage currents that may be integrated together to form ultra large scale integrated circuits si that include millions of transistors. What is needed are new and improved complementary
}(> MOSfET devices and circuits in compound semiconductors that allow the direct use, transfer s 7 and appl ication of si lieon CMOS design that already exits in the art s s What is also needed are new and improved methods of fabrication of se! f- aligned i o compound semioooduetoi MC)SFETs, What is also needed is new and improved methods of
20 fabrication of seif-ahgned compound semiconductor MOSfEiTs which are compatible w ith
2 i established complementary GaM InSb. SiC. and GaAs heterosirueiυre FETs technologies. 22 What is also needed are new ami improv ed compound semiconductor MOSFETs w hich are
2 * relatively easy to fabricate and use.
24 The present inventor's US patent 6.936.900 addresses the foregoing problems by
25 providing in contact with a IH-V compound semiconductor's surface a first layer of gal limn
26 oxides and m contact w ith the first layer a second layer of gallium rare earth ON ides. The
27 aforementioned first and second layers provide an effects \ e gate insulator for H)-V 2« compound semiconductors
20 OBJECT OF THE INVENTION
30 It is an object of the invention to provide meial-oxide-compound semiconductor field
3 ϊ effect transistor structure m winch the Hl-V semiconductor surface- at the gate region is i passivated and the yate provides a suitable insulating barrier for transistor behavior
2 i SUMMARY OF THE INVENTION
4 The present in\ enter achieves that aspect by conceh ing of alternative bM&yer
5 structures on Hl-V compound semiconductors that provides an effective gate insulator on the (■> compound semiconductor, and also the transistors and eireuury obtainable {here from. The
? IH-V compound semiconductors include GaAt, AiAs, InAx. GaN, AlN, ffiN. InP, (kά\ AW. s and (MN, InN, AiN', GaSb, InSb. and AiSb and ternary and quaternary and arbitrary mixtures
<> thereof so Additional bi -layer structures on compound semiconductors, other than just the
S i gallium o\>gen first layer and the gallium oxygen rare earth second layer disclosed in IJS i 2 patent 6.936. SK >0 may
Figure imgf000005_0001
ide an effective gate insulator on TTl-V compound semiconductor
51 surfaces. Herein. "b>laver structures" includes
Figure imgf000005_0002
ers m which a compositional component s ■} in the second layer may he graded. i 5 When the TTl-V compound semiconductor's surface contains a compound
}(> semiconductor including Aluminum (such as AiAs, AiN, mixtures of AlAs and CaAs.. and s 7 mixtures of AlN and GaN. etc), an effective gate insulator on that surface may be formed by s s a Sl rst layer containing substantial amounts of aluminum and oxygen, and a second layer that
1 '> is insulating. Me-! ein, a substantial amaun t in the fuM or second layer means greater than 20 two atomic percent. The first layer preferably comprises at least Hi percent atoms of
2 i alummum, preferably more than 30 percent atoms of aluminum, preferably about 4» percent 22 atoms of aluminum {for an A12O3 ratio? and up to about filly percent atoms of alummum.
2 * The first layer may comprise for example either or both of A12O3 and A12O (Aluminum sub-
24 oxide). Preferably, the second laser comprises, substantia! amounts of at least three elements.
25 Preferably, the second ias er forn^s a teniasy compound. The insulating second layei
26 preferably includes lemar>~ compoυjids. The preferred ternary compounds include aluminum
27 and oxygen and a metallic third element. The ternary compound is insulating, The metallic 2« third element of the ternary compound preferably is one of C i ) any rare earth including but 2!> not limited io (3d (Gadolinium), (2) 4d transition elements Y (Yttrium) and Zr (Zirconium), 30 and (3) 5d transition elements Hf (Hafnium). Ta (Tantalum). W (Tungsten), Rc (Rhenium).
3 ϊ Os (Osmumi). and U (Iridium). The ternary compound may also include a mixture of more 1 than one of the metallic third element, the ternary element, of the ternary compound.
2 When the I I I- V compound semiconductor's surface contains a compound
? semiconductor including Aluminum, (such as AiAs, AiN, mixtures of AiAs and Ci&As, and
4 mixtures of AlN and GaN, etc), an effective gate insulator on thai surface may be formed by
5 a first layer containing OaUium. Aluminum, and Oxygen, and a second layer on the first (■> layer, the second layer including a ternary compound The temars compound includes
? aluminum and oxygen and a rnetai element. The ternary compound is insulating. TTse ternary s element of the le-mary compound preferably includes at least one of ( I ) any rare earth
<> including but not limited So Od < Gadolinium). (2) Λά transition elements; Y (Yttrium) and Zr so (Zirconium), and ( 3} 5d iπιn»iuon clcxπcnls MfCMafπium). Ta (Tantalum K W (Tungsten), Re
S t (Rheni υm), Os tOsuji um\ and Ir (Iridium) The ternary compound may also include a
V2 mixture of more than one of She ternary element, the metal third element, of the ternary
51 compound. s ■} Pref erabh\ the ternary metal element is Gd or Bf. Alternatives preferred for the si ternary metal element are Jr and Y.
}(> Preferably, the structures include at least one of GaAs, AlAs, InAs, GaN, AlN, InN. s 7 iiiSb. GaSb and mixtures thereof These compound semiconductors provide the most
S S promising opportunities for commercial devices,
S <> ASPECTS OF THE 1 N V ENTlON
20 In one aspect, the uπ eiuson provides a metal-oxide-conipoυnd semiconductor UeM
2 ϊ effect transistor structure, and methods of making and using ii, in vshicb the structure
22 comprises,
2 * a compound semiconductor wafer structure having an upper surface;
24 a gate insulator structure comprising a first layer and a second laye∑. said gate z 5 insulator on said upper surface, said first Sa> er hi contact with said upper surface;
26 wherein said first las er comprises substantia! amounts of at least one of (1 > aluminum
:? and oxygen and (2) gallium aisd aluminum and oxygen; and
28 wherein said second layer is iasuiatsmj.
2*> Jn another aspect, the jtn entiøn pros ides a metal-oxide-compound semiconductor
30 field effect transistor structure, and methods of making and using \l w herein the structure
M comprises; 1 a compound semiconductor wafer structure bax ing an upper surface;
2 a gate insulator str ucture comprising a ft rst layer and a second
Figure imgf000007_0001
e?, said gate ? insulator on said upper surface, said first layer in contact with said upper surface:
4 \\ heresn said first layer comprises substantial amounts of at least one of ( 11 aluminum
5 and oxygen^ {2} gallium and oxygen, and <3j gallium and aluminum and oxygen,
A uherem said second layer comprises at least one compound of gallium, oxygen and at
? least one metallic third element; and s wherein said at least one metal he third element comprises at least one of (U am rare
<> earth. (2) 4ά transition elements Y (Yttrium) and Zr (Zirconium), and (3) 5d transition
H) elements Rf (Hafnium). Ta (Tantalum). W (Tungsten). Re (Rhenium). Os (Osmium), and Ir
S i (Indium).
S 2 BRfEF DESCRJ PTION OF THE DRAWINGS
51 A more complete understanding of the present invention may be dem ed by referring
M to the detailed description and claims when considered in connection with the figures, si therein like reference numbers refer to Similar items throughout the %ures, and: }(> HO ! is simplified cross sectional view of a self-aligned enhancement mode s 7 compound semiconductor MOSF EI" in accordance with a preferred embodi meat of the s a present
S'> FIO 2 ts a simplified flow chart illυstratmg a method of n«tnufacU«3»g a self-aligned
20 enhancement mode compound semiconductor MOSFET in xvifh reference to IH-V compound
2 i semiconductor OaAs (easily translated to GaN or OaSb) in tks chart 22 is a schematic Uι> out of a
Figure imgf000007_0002
integrated circuit (IC) meocpoiaϋπg
2 \ N MOSFET and P MOSFET regions on the same substrate.
24 The exemplillcati on set out herein illustrates, a preferred embodi ment of the invention
25 in one form thereof, and such exemplification is not intended to be construed as limiting in
26 am manner.
27 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
2« The present invention provides, among other things, a self-aligned enhancement mode
2!> metai-co-kle-compcaind semiconductor FBT. The FBT includes, a gallium oxygen insulating
30 structure that is composed of at least two distinct 1 av ers. The first layer is most preferabk
3 ϊ more that 10 angstroms thick but less that 25 angstroms in thickness and composed 1 substantially of gallium oxygen compounds including but not limited to stoichiometric Oa.;O*
2 and Ga2CX and possibly a lesser fraction of other gaUujm oxygen compounds The upper
? insulating layer in the gallium oxide insulating structure is composed of an insulator that does
4 not intermix with the underlying gallium oxygen first layer of the gate insulating structure.
5 This upper layer roust possess excellent insulating qualities, and is most typically composed (■> of gallium oxygen and a third rare earth element that together form a tertian' insulating
? materia} s Another preferred embodiment of the present i tn ersiion pro A ides, a seif-ahgned enhancement
<> mode rnetai-oxide-eompound semiconductor FET. The FET includes a aluminum cm gen so insulating structure that Ls composed of at least two distinct layers. The first layer is most
S i preferable more that 1 o angstroms thick but less thai 25 angstroms m thickness and
V2 composed substantially of gallium oxygen compounds including but not limited to
51 stoichiometric AbO., and AIjO. and possibly a lesser fraction of other aluminum oxygen s ■} compounds The upper insulating layer in the gallium oxide insulating structure is composed s 5 of an insulator that does not intermix.
Figure imgf000008_0001
the underk ing gallium ox> gen first layer of the
}(> gate insulating structure. This upper layer must possess excellent insulating qualities, and is s 7 most typicMK composed of Aluminum owgen and a third rare earth element that together i s form a ternary insulating materia}.
1 '> Therefore the eπtπe gate insulato* structuje is composed of at l«a.st wo hy ers, a first 20 layer and a second layer, which may or may not have a composition gradient therein. There
2 i may be a composition gradient where the first layer blends into the second layer. Additional 22 la.\ ers ma> be included on top of the fust and second ia> ers. Together the gallium oxygen.
2 * akϊTninum oxygen, or mixture of gallium, aluminum, and oxygen, first layer, am- intermediate
24 gradation to the second layer including the ternary compound, form both ail effective gate
25 insulator region. This region may be used for the gale insulators of a compound
26 semiconductor field effect transistor.
27 The first layer {gallium and o\> gen. aluminum and o\vgen. or mixture of gallium 2« and aluminum and oxygen) forms an atomically abrupt interlace with the top las er of ihe ,?!> compound semiconductor wafer ϋmtchire, and »t does not introduce mid-gap surface states 30 into the compound semiconductor material.
3 ϊ The second Saver, the insulating ternary oxide on the first laver. eiectπcaih insulates 1 the surface of she compound semiconductor.
2 Preferably, when forming MOSFETs, a refractor) metal gate is positioned on the
? upper surface of the gate insulator structure layer. The refractors, metal ss stable on lbs gate
4 insulator structure layer at elevated temperature. Self-aligned source and dram areas, and
5 source arid drain contacts are positioned on the source and drain areas f> Preferably, any røetal-oxide-coropound semiconductor transistor that includes the
? røuiti-kryer gale insulator .structure has the multi-layer gate insulator structure being s preferably 3D- 25s) angstroms in thickness and positioned on the upper surface of the
<> compound semiconductor heterø-struetore fo form the gate insulator structure The Preferred so initial metal layer of lhe gate metal stack is the- rare earth element used in the ternary upper
S i layer of the gate insulator structure. So for example, in the case ■where the top layer of the
V2 gate insulator structure is GaxGdv<X, one preferred initial layer in the gate metal is iCά) π Gadolinium, iridium is also a preferred initial metal in the gate metal stack because fr oxide s ■} is a refractory oxide and also a condυcth e oxide, facilitating a low gate resistance s 5 Some embodiment also comprise compound semiconductor hetøro-sfcructures
}(> including a GaAs, Aix Gaj.xAs and iru Gaj.y As. AIxIn1.-,; Sh. GaN, Alx Ga^xN and in> Gau >N s 7 layers with or without π-type and/or p-iype charge supplying layers which are grown on a
1 s compound semiconductor substrate, a refractors- metal gate of W, WN. or WSi, self aligned S'> donor (n-ehanne! FET) o? acceptor (p-clutnαel FET) implants, atϊd source and drain ohnik
20 contacts,
2 i Some preferred embodiments comprise the compound semiconductor hetero-strυcture 22 b«inu irivGaj-jAs. AlJfii.xAs with or without π-type and'or
Figure imgf000009_0001
p« charge supph ing !a> eis
21 which are grown on a compound semiconductor substrate, a refractory metal gate of W. VVN.
24 or WSi, sel f aligned donor (n-channe! FET) or acceptor fp-channel FET) implants, and
25 source and drain ohmic contacts
26 Some preferred embodiments comprise the compound semiconductor hetero-structure
27 beirjy InP compound semiconductor hetero-structure and n-t>-pe anά/or p-i>'pe charge
2« supplying layers which are grown on an InP substrate, and a refractory meial gate of ϊr. Gd,
,?!> Hf- Pt, W. WN- or WSi, and multilayer stacks of such gate metais that possess the desired
30 work function, self aligned donor (π-channel FET) or acceptor fp-ehamiel FET) implants, and
3 ϊ source &nd dram ohrøic contacts. 1 FIG I is simplified cross sectional view of a self-aligned eπhaπcemerU mode
2 compound semiconductor MOSFEl" in accordance with a preferred embods mem of the
? present invention Deuce IO includes a compound semiconductor materia!, such as any iff-
4 V material emplov ed in am semiconductor device, represented herein by a IH-V
5 semiconductor substrate 1 1 and a compound semiconductor epitaxial las er structure 12. For A the purpose of this disclosure, the substrate 1 1 and any epitaxial Saver structure i 2 formed
? thereon will be referred to simply as a compound semiconductor wafer structure which in s FIG 1 is designated 13 Methods of fabricating semiconductor wafer structure 13 mciude.
<> hut are not limited to, molecular beam epitaxy (MBE) and metal organic chemical vapor so deposition (MOCVD). Ti will of course be understood that in some- specific applications,
S i there ma}' be no epitaxial layers present and upper surface of top layer ! 5 may simply be the
12 upper surface of substrate 1 1. π Device IO further comprises a gate insulator structures (30) that includes at least two i 4 or more la> ers. The first layer of the gate insulator structure ( 31 } is composed entirely of si gallium ovide compounds, aluminum oxide compounds, or gallium and aluminum oxygen
}(> compounds The first layer is in contact with and deposited upon the upper surface of the s 7 compound semiconductor st ruciure. The second layer of the gate insul ator structure C 32 ) is s s composed of a compounds of gallium, oxygen, and one or more of { 1) rare earth elements
S'> from the periodic table, (2) 4d transition elements Y and Zr, ar\d Q) 54 transition elements
20 Hf, Ta, W, RE. Os. and Ir. The initial gallium/aluminum oxygen layer Q] ) forms an
2 i atomtcairy abrupt interface 14 with She upper surface of top las δr 15. the top layer of the 22 compound semjconduclot structure,
2 * When forming MOSFETs, a refractory metal gate electrode 17 which is stable in the
24 presence of top insulating triatrial at elevated temperature is positioned on upper surface IS
25 of the gate insulator structure. Dielectric spacers 26 are positioned to cover the side-wails of
26 metal gate electrode 17. Source and drain contacts 1<) and 20 are deposited on self-aligned
27 source and drain areas 21 arid 22, respective! > .
28 In & specific embodiment, the compound semiconductor epitaxial layer structure 2!> con«s.ts of a <! ! angstrom GaAs top layer ( 15). a < 103 angstrom AlxOa^As spacer Saver 30 {23}, a -;251 angstrom l%Gaj-, As channel layer (24), and a GaAs buiϊer layer (25.) grown on
3 ϊ a GaAs substrate H I ). T op GaAs layer (15) is used to form an aiomtcaii v abrupt layer with 1 the gale insulator structure
Figure imgf000011_0001
an abrupi interface with iov. defect demiu
2 In embodiments using aluminum in the first layer of the gate insulator structure, the ? top GaAs layer (15) may be replaced with a OaAiAs or AlAs top layer
4 As a simplified prophetic example of fabricating a seif-aligned enhancement mode
5 compound semiconductor MOSFET in accordance with a preferred propheuc embodiment of (■> the present invention, a Ϊϊϊ-V compound semiconductor wafer structure 13 with an atomically ? ordered and chemically clean upper surface of Sop layer 15 is prepared in an ultra-high s vacuum semiconductor grow th chamber and transferred via a ultra high vacuum transfer
<> chamber to a second ultra high \ acuum oxide and insulator deposition chamber so In the present invention art improved method of depositing the initial passiuiiing
S i oxide layer, including the deposition of both gall turn oxygen and aluminum oxygen
V2 compounds In particular, it is possible Io deposit the suboxide compound, (such as G<£) or
51 A12) from an effusion cell and crucible combination that contains said suboxides Since the
M suboxides of Group Ul elements are not readily a\ ailable for purchase, the present invention i 5 includes methods of fabπeati m> the proper suboxide source material in-siat in the appropriate
}(> crucible tn an effusion cell in. a UHV chamber or in an MBE or Gas Source MBE (ALi) r? capable) chamber, ss it is possώle to form Aluminum sub oxide {A120} [or analogously Gallium
? f> Suboxide (Ga2O) or Indium Suboxide (ln20) as follows]: in A Start with a Indium Crucible or with a Boron Nitride crucible or Be-oxide Crucible,
2! 8. Load the crucible with a known amount of AI2O3 chunk or powder.
Ώ C. Add the proper number of moles of pure Aluminum so that the following chemical
Ii reaction can proceed when the reagents are heat to the proper temperature:
25 AI2O3 + 4Ai — > 3AI2O.
26 O. Transfer the contents of the crucible that comprise AI2O3 into a Iridium Crucible.
27 Place the crucible loaded with the two separate substances into a IMS/ vacuum
2κ chamber, and heat the crucible and source material about the 665C melting point of
><:- Aluminum, then slow proceed to raise the temperature above 720C. Using these
?o conditions will enable the formation of A120 (aluminum suboxide) given the proper
? i time and conversion of the entire charge of source materia! requires some minimal i lime that is less than three days z E. Somewhere between 720C and 800C the chemical reaction proceeds anά i Aluminum oxide (A12O3) is converted to Aluminum sub-oxide
4 Note; this same process also applies to the formation of Ga2O from Ga2O3 and Ga
5 Metal where the oniy difference In the process is that the gallium sub-oxide forms ■;. m vacuum at approximately 700C and requires 20 minutes for completion of the reaction where Gailium Oxide (Ga2O3) is converted to Gallium Suboxide (Ga2O). a The formation of Indium suboxide for use as a source materia! is also possible with
» the reaction proceeding m a manner similar to Gallium suboxide. n> Mote that oxygen is not produced in decomposition and deposition of the source s i materials,
\ 2 Please consider trie Thermal decomposition reactions of AI2O3 and Ga2O3 that are
S3 used in W)BE when evaporating these oxide m SViBE from an Ir crucible-
M Ga2O3 (heat) --> Ga2O + 02 s <> A12O3 [heat] ---> AI2O + O2 ϊo So in each case, when the stoichiometric oxsdes am used in MBE, residual 02 is r released, and this free 02 has some probability of Oxidizing the GaAs, SnGaAs, InP, s^ GaN, InSb (compound Semiconductor) surface
H Note that if the Suboxide is thermally evaporated directly, there should be no free 02
.v that would accidentally oxidize the compound semiconductor surface.
: s Specifically, when the suboxide compounds Al-suboxide (AS20), Ga- suboxide
:2 {Ga2O}, indium suboxide (lπ2O) are useύ in the deposition of the initial layer of the ϋϊ gate insulator structure. The advantage of using the suboxide material as source
2 s material tn the WBE of compound semiconductor gate insulator structures, [either A!~
::s suboxide or Ga-suboxsde or indium-suboxidej in the MBE of the Gate Insulator
>■» Structure' No Oxygen is present when evaporating a coating from either AI2O r (Aluminum Suboxide) or Ga2O {Gallium Suboxide) or in2O {Indium Suboxide)
2>> in contrast, when Aiummum Oxide (AI2O3) is evaporated in an 1V1BE system or
.-.' under Ultra High vacuum Conditions, A12O3 (heat) — > A|2O + O2(gas) . in prsor
?ι art, Ai2O3 and Ga2O3 have been used by OSEM! and others for forming two layer
■L' or multilayer gate insulator structures on compound semiconductors that are both i i 1 passivating and insulating and facilitate the formation of Compound Semiconductor
2 MGSFETs. One novel anύ subtle concept of this patent Is that the sub-oxide can be j formed with high purity in a separate vacuum chamber, and that this sub-oxide
4 materia! can be used to provide a 1-2 monolayer oxide passivation layer, and that a s second layer that composes Aluminum Oxygen and a Rare Earth or Transition fvleta!
■5 (ternary or quaternary layer) to form the gate insulator structure, Ustng the suboxide
? source materia! in UHV deposition (Le. MBE) allows the initial oxide layers to be
8 deposited where a much lower partial pressure of free oxygen is present in the
« deposition chamber, improving the quality of the semiconductor oxide interface, and n> lowering the interface recombination velocity at the interface, and also lowenπg the s i interface state trap density at the interface. i 2 The initial gallium oxygen or aluminum oxygen or mixture thereof layer, the first
13 layer (31} is deposited on upper compound semiconductor surface lav er 15 using thermal or N e-beam evaporation from a high purity Ga.jCh source, a AI^CK source, an hώ03 source.
S s from Oasth and AhCh sources eoncuirentiw from crystalline sadohumm gallium garnet
Sf- G;nCκk(>;:>. of concurrently from both a Ga.xGdjOis source and an AMD.= source.
S "J This first layer of gallium/aluminum oxygen layer ι% deposited while holdmg the i K substrate temperature of the compound semi conductor structure at <S8Θ"C and moss
\ 9 preferably at a substrate temperature <4V5"C. After the deposition of approximately I S
20 angstroms of gallium/aluminum oxygen compounds in the insulator deposition chamber over
2Ϊ $ 5 to H minute period of time, deposition of the second layer is initialed. The second layer is
1? msulating.
2? The deposition of die second layer starts by detecting the flux from a low power
14 oxygen plasma source mto the ultra high vacuum system such that the oxygen plasma 25 effluent and species are largely directed toward and impinging upon said compound
."!& semiconductor structure with initial gallium oxygen layer The flux from the oxxgers pi&sma
2" source should be directed at the surface for between 2-5 seconds, subsequently followed by
;s the CO- evaporation of gallium o\> gen compounds from Ga^CK and a second thermal
.VΪ SΛ adoration sotirce that contain? the other rneial element ( rare-earth elemeiit. Y. 2r. Hf. Ta. w W, Re. Os. or Ir) The flux beams from the oxygen source. Ga/.h, A^Ch, and ternary metal
?t ev aporations are carefully balanced to provide a ternary insulator layer on top of the initial 1 gallium layer on said compound semiconductor structure, As the deposition of the
2 second ternar> insulator la> er is initialed, the substrate temperature is simultaneously
< adjusted to pro\ κle an optimized substrate temperature for the deposition of this ias er For
4 example, the substrate temperature required to deposit a galls um*α\> gen* rare earth !a>er is
*> <55o"C The deposition of this second insulator layer proceeds until the total insulator ft thickness of 200-250 angstroms is
Figure imgf000014_0001
ed Shutters and valves are utilised to stop the
■? deposition of lhe ternary gallium-K>xygen÷rare earth las er upon the deposition of lhe required s thickness of the insulator
Figure imgf000014_0002
er.
<> The s»h<;trak» temperature is cooled in- vacuum to approximate^ 2Ot)T, and the so deposition of a refractory metal which ss stable and does not inter-diffuse with on the Sop
S t layer of the gate insulator structure at
Figure imgf000014_0003
ated temperature such as VVSi or WN is deposited ϊ2 on upper surface 18 of oxide layer 32 and subsequent!} patterned using standard lithography
51 The refractorx metal la> er is etched until oxide S aver J 1 ss exposed using a refractory metal
M etching technique such as a fluorine based drv etching process The refractory metal etching
\ 5 procedure does not etch the ovide lay er 31 , thus, ovide la> er 31 functions as cm etch stop
S <> layer such that upper surface of top layer 15 remains protected by oxide la> er 31. Ail s "> processing steps are performed using low damage plasma processing. Self-aligned source i s and drain areas 2 ! and 22. respeetneiy axe realized by ion implantation of Si (n-channe!
1 ° de\ ice J and Be? F w C/F <p-chan«el de^< ice) using the lyfraeiorv metal gate electrode S 7 and :o the dielectric spacers 20 as implantation masks. Such ion implantation schemes are
2 i compatible
Figure imgf000014_0004
standard processing of complementary compound semiconductor hetero- 22 structure FET technologies and are
Figure imgf000014_0005
known to those skilled in the art. The implants are
2 * activated at 700-^WC using rapid thermal annealing in an ultra high \ actJtsnt en\ ironmem
24 such that degradation of the interface 16 established
Figure imgf000014_0006
top layer 15 and
Figure imgf000014_0007
la> er 31
25 is completely excluded. Finally, ohmk source and drain contacts 19 and 20 are deposited on 2o the self-aligned source and drain areas 21 ami 22, r
Figure imgf000014_0008
especti\ The de\ sees
Figure imgf000014_0009
then !>e j? interconnected using the standard methods to those siil led in the art of integrated
2« microelectronics and integrated circuit manufacture.
2!> FIG 2 }$. a simplified llou chart illustrating a method of mamifactunng a self-ahgoβi:!
30 enhancement mode compound icmtcondxicior MOSFET in accordance ^ ith a preferred
3 ϊ prophetic embodiment or the present 1 Sii step K>2_ a compound semiconductor wafer structure is produced ostru* standard
2 epitaxial growth methods m the art. t In step 103. a layer consisting of galliuπvaluroinυrn oxygen compounds including but
4 not limited to Ga^O? and GajO. AΪ.$CK and AM,), In^Q* and in;O and mixtures thereof, is
5 deposited on the upper .surface of said compound semiconductor wafer structure. f> In step 1 SM . an insulating layer of gallium/a! ummum oxygen and one of the
? aforementioned ternary or tbtrd metal elements is deposited on the upper surface of the initial s gallium/aluminum oxygen compound layer The galhunVa!um»?u?rj/ternaty metal/oxide gate
<> insulator structure is formed in steps. 104 and 105. so In step 106, a stable refractory gate metal is positioned on upper surface of said gate
S i insulator structure
S? hi step IHH, source and drain ion. implants are proxided self-aligned to the gate π electrode.
M In step 1 UL source and drain ohrnic contacts are positioned on ion implanted source si and drain areas.
}(> in tx preferred prophetic embodiment, step 100 provides a compound semiconductor s 7 substrate such as GaAs, GaN. GaSb. InSb, or TnP. s s Step I (»2 includes tbe preparation and epitaxial growth of an aiomically ordered and
S '> chemically cksao uppes surface of the compound semiconductor wafer structure.
20 Step 103 preferably comprises iheπnai ev aporation lrom a punfied and crystalline
2 i gadolinium gallium garnet or Ga^O? source on an atornieafiy ordered and chemically cleat)
22 yμpei surface of the compound semiconductor wafer structure,
2 * Step KM comprises the ibrmauon of a gallium and/or aluminums-oxygen-^ metal
24 element insulating ljι> er formed through the simultaneous \ acuum «\ aporanon of gal Hum
25 ox> gerr m aluminum ox> gers species and at least one mεtailic element such as Gadolinium or
26 Iridium \\ iih the simuStaneotB oxidation u&ing the effluent of an oxygen yas plasma source
27 directed in simultaneous combination with other thεirnal e\aporatton sources toward 2« substrate K X).
2!> The gaJliyro/alumJnum oxx en coropourvd of the first .layer of the gate tmulator
30 structure preferably functions as an etch stop layer such that the upper surface of the
3 ϊ compound semiconductor w afer structure remains protected b> tbe gate oxide during and 1 after gate metal etching. The refractory gate metal desirably docs not react \\ ith or diffuse
2 into the gale oxide layer during high temperature arirsealing of the self-ai igned source and
? drain JOO implants. The quality of the interface formed by the gate
Figure imgf000016_0001
layer and the upper
4 surface of the compound semiconductor structure is desirab!) preserved during high
5 temperature annealing of the self-aligned source and drain ion implants. The self-ahgned (■> source and drain implarris are desirably annealed at approximately 700'1C m an ultra high
? vacuum environment. The self-aligned source and drain implams are desirably realized by s positioning dielectric spacers on the sπiewalls of the refractor}' gate metal <> Fig S shows distinct regions of N IVIOSFET and P MOSFET on the same so semiconductor compound semiconductor wafer These distinct regions may be defined by
S t various steps of depositing, implanting, and lithography i 2 Thus, new and improved compound semi conductor devices and methods of
51 fabrication are disclosed. The new and improved self-aligned enhancement mode metal- s ■} oxide-compound semiconductor hetero-structure field effect transistors enable stable ami s 5 reliable device operation, provide optimum compound semi conductor device performance for
}(> low power/high performance complementary circuits and architectures, keep interconnection s 7 dela^ in ULSl under control and provide optimum efficiency and output power for RF and
1 s microwave applications as v^eli as for digital integrated circuits that require very high S'> integration densities.
20 Another Preferred embodiment of the invention is to use Chemical Beam Epttaxy Io
2 s selectively grown either P-type or N-type regions on the wafer that would be
2: arranged in pairs for use as Drain and Source regions of an FET transistors, then to
25 deposit the ohmic contact metai selectively on top of said N-type or P-type Drain
M source regions, and anneal said ohmic contact regions in a manner that facilitates
1-5 the formation of ohmic contact regions in the locally regrown regions, fonnad by
26 CBE or UHV-CVD that are similar techniques. After the drain-source regions are
2i formed, Selective Epitaxy using Chemical Beam Epitaxy or similar technique is used
28 to deposit crystalline compound semiconductor material between the drain and
2>> source regions in such a manner that a channel region is formed between the n-type Drains Source contacts, and/or the P-ϊype Drains source contacts. After deposition
■! i of the channel material the semiconductor wafer is transported in UHV to an oxide i deposition chamber where the bι-Sayer or multilayer gate insulator materia! is z deposited either selectively or nαn-seieciiveiy onto the wafer forming a j compound semiconductor structure with a gate insulator structure deposited on the
4 top of said compound semiconductor structure. Finally then the proper gate metal or s gate metal stack ss deposited on top of the gate oxide. The gate region is defined
■;. using ifte. standard techniques of lithography Known in the art of semiconductor
"! processing, and a properly designed metal etch and oxide etch Is used to remove
8 the oxide and gate metal over the drain source regions of the newly formed
« Compound Semiconductor MOSFET structure,
\o ThtHβ improvements mats essentially *olv* or overcome the problem* of the prior art i i and e&peαaih the border trap issues caused by deposition on interfaced in the presence of
12 residual owgen generated when source materials such as 08:0«, irυϋ.:- and AhO,ι are
! ϊ deposited such as high gale leakage in compound semiconductor FET
Figure imgf000017_0001
ices. Sow
! 4 integration densities, dc elecincal msiabiliij . aid electrical In steresis, and therefore ρro\ ide
15 a highly useful im ention. While we have shown and described specific prophetic
U÷ embodiments of the present ind ent ton. further modificaltoαs and improx emente wilt occur Jo f those skiϊied in the art. We desire it io be understood, therefore, that this
Figure imgf000017_0002
em.n>n is not i s limned to the particular forms shown and w e intend ni the- appended claims to co\ er all
S ι> modifiC-tSionsj that do not depart from the spirit and scope of ύ\ι$ im eαύon
i ?>

Claims

1 What is claimed.
2 1. A metal-oxide-compound semiconductor field effect transistor structure. ? comprising:
4 a compound semiconductor wafer structure ha\ mg an upper surface;
5 a gate insulator structure comprising a first layer and a second layer, said gate (■> insulator on said upper surface, said first layer in comae! with said upper surface;
? wherein said fust layer comprises substantia! amounts of at least one of (I ) aluminum s and oxygen and (2) gallium and aluminum and oxygen; and
<> n herein said second layer i.s insulating so 2. The structure of claim 1 wherein said second layer comprises at least one
S t insulating oxide compound including (I) at least one of gallium and aluminum, (2) oxygen.
V2 and (3) at least one metallic third element π 3. The structure of clai m 2 wherein said at least one metallic third element
M comprises at least one of { I) am rare earth. (2) 4ύ transition elements Y {Yttrium} arid Zr si (Zirconium), and O) 5d transition elements Hf (Hafnium). Ta ('Tantalum), W (Tungsten), Re
}(> (Rhenium), Oa (Osmium), and ir (Iridium) s 7 4. The structure of clai m 2 w herein said at least one metallic third element
S s comprises at least one of Gadolinium and Iridium
S '> 5. The structure of clai m I \s herein said compound semiconductor ^ afer
20 structure comprises at least one of As and N.
2 { (\ The structure of clai m I wherein said compound semiconductor wafer
22 structure comprises at least one of Ga and AL
2 * ?. The structure of claim 1 further comprising a gate electrode above said second
24 layer.
25 8. An integrated circuit comprising the transistor including the structure of elairn
26 L
27 <?. The structure of clai rn I wherein said first layer comprises at least one of
28 AI2O3 and Ai20.
2*> 10. A
Figure imgf000018_0001
ιdό~compouod semiconductor Held effect transistor structure,
30 comprising;
3 ϊ a compound semiconductor u afer siascture ha\ im> an upper surface: π 1 a gate insulator structure comprising a H KJ lav er aitd a second layer, said gate
2 insulator on said upper surface, said first iayer in contact with said upper surface;
? v. herein said Rrst layer comprises substantial amounts of at leas! one of (!) aluminum
4 and oxygen, {2} gallium atκ1 OHJ gers. and β) gallium and aluminum and
Figure imgf000019_0001
gen,
5 therein said second layer comprises at least one compound of gallium, oxygen and at f> leasi one metallic third element; and
? wherein said at least one metallic third element comprises ai least one of (i ) any rare s earth, {2) 4ύ transition elements Y (Yttrium) and Zr (Zirconium), and (3) 5d transition
<> elements Mf {Hafnium}, Ta (Tantalum), W (Tungsten). Re (Rhenium), Os (Osmium), and Ir so (iridium). ϊ i I i The structure of claim 10 wherein said at least one metallic third element i 2 comprises at least one of Gadolinium and Iridium π 1 2, The structure of clai m 10 wherein said compound semiconductor wafer s ■} structure comprises at least one of As and N . si 13. The structure of clai m 1 G wherein said compound semiconductor w afer
S 6 structure comprises as least one of Oa and Ai. s 7 S 4. The structure of clai m i O further comprising a gate electrode above said i s second layer.
1 '> S 5. An integrated circuit comprising the transistor including lite structure of claim 20 H),
2 i Kx A method of making a metsi-oxids-compound semiconductor field effect 22 transistor structure, comprising:
2 * providing a compound semiconductor wafer structure having an upper surface.
24 providing a tjate insulator structure comprising a first la> er and a second layer, said
25 gate insulator on said upper surface, said first lay er in contact with said upper surface;
26 wherein said first las er comprises substantial amounts of at least one of (1 > aluminum
27 and oxygen and (2) gallium and aluminum and oxygen; and
28 wherein said second layer is insulating.
2!> 1 7. A method of using a meusl-oxide-compoυnd semiconductor field effect
30 transistor structure, comprising, said structure comprising;
3 ϊ a compound semiconductor u afer siatcture ha\ im> an upper surface; is 1 a gate insulator structure comprising a H KJ lav er and a second layer, said gate
2 insulator on said upper surface, said first iayer m contact with said upper surface;
? v. herein said first layer comprises substantial amounts of at leas! one of (!) aluminum
4 and oxygen and (2) gallium and aluminum and oxygen;
5 therein said second layer is insulating; and
A saui method comprising applying a voltage to said gate insulator structure.
? 18 A method of making a metaJ-oxide-compound semiconductor He-id effect s transistor structure, comprising1
<> iding a compound semiconductor wafer structure
Figure imgf000020_0001
ing an upper surface: so prm iding a gate insulator structure comprising a first layer wd a second layer, said
S i gaie insulator on said upper surface, said first layer in contact with said upper surface; i 2 wherein said fust layer comprises substantia! amounts of at least one of ( 1 } aluminum π and oxygen, Q) gallium and oxygen, and VS) gallium and aluminum and oxygen: M wherein said second layer comprises at least one compound of gallium, oxygen and at si least one metallic third element: and
}(> wherein said at least one metallic third element comprises at least one of (1 } am rare s 7 earth. i2) 4ά transition elements Y (Yttrium) and Zr (Zirconium), and O) Sd transition
1 s elements Hf {Hafnium}. Ta (Tantalum}. W (Tungsten), Re (Rhenium}. Os (Osmium}, and Ir S '> (Iridium).
20 19, A method of using a metal-oxide-eompound semiconductor field effect
2 { transistor structure, said structure comprising;
22 a compound semiconductor wafer structure having an upper surface;
2 * a gate insulator structure comprising a first layer and a second layer, said gate 24 insulator on said upper surface, said Arsi las er in contact with said upper surface: z 5 tt herein said first ia> er comprises substantial amounts of at least one of ( 1 ) aluminum
26 and oλs gen, (2) gallium and oxygen, and B) gallium and aluminum and oxygen:
;? wherein said second layer comprises at least: one compound of gallium, oxygen and at
2« least one metallic third element;
2!> uhereϊo saa1 at least one metallic third element comprises aϊ least one of i U any rare
30 earth, (2) 4d transition elements Y (Yttrium) and Zr (Zirconium), and O ) Sd transition
3 ϊ elements Hf (Hafnium). Ta. (Tantalum). W (Tungsten). Re (Rhemum). Os (Osinnim). and Ir i 9 (Iridium); and said method comprising applying a \ oliage to said gate insulator structure.
PCT/US2007/070843 2006-06-12 2007-06-11 Integrated transistor devices WO2007146859A1 (en)

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EP2830096A1 (en) * 2013-07-25 2015-01-28 IMEC vzw III-V semiconductor device with interfacial layer
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