WO2007130973A1 - Semiconductor device including a dopant blocking superlattice and associated methods - Google Patents
Semiconductor device including a dopant blocking superlattice and associated methods Download PDFInfo
- Publication number
- WO2007130973A1 WO2007130973A1 PCT/US2007/067926 US2007067926W WO2007130973A1 WO 2007130973 A1 WO2007130973 A1 WO 2007130973A1 US 2007067926 W US2007067926 W US 2007067926W WO 2007130973 A1 WO2007130973 A1 WO 2007130973A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor
- semiconductor device
- superlattice
- channel layer
- layers
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 137
- 239000002019 doping agent Substances 0.000 title claims abstract description 52
- 230000000903 blocking effect Effects 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 34
- 239000010410 layer Substances 0.000 claims abstract description 128
- 239000002356 single layer Substances 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 5
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- 239000001301 oxygen Substances 0.000 claims description 19
- 229910052760 oxygen Inorganic materials 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 46
- 239000000463 material Substances 0.000 description 30
- 230000037230 mobility Effects 0.000 description 18
- 239000002800 charge carrier Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 239000007943 implant Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 206010010144 Completed suicide Diseases 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000003775 Density Functional Theory Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002099 adlayer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 201000005206 focal segmental glomerulosclerosis Diseases 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000007734 materials engineering Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- the present invention relates to the field of semiconductors, and, more particularly, to semiconductors having enhanced properties such as based upon energy band engineering and associated methods.
- U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.
- U.S. Patent No. 4,937,204 to lshibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.
- U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice.
- U.S. Patent No. 5,683,934 to Candeiaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutional ⁇ present in the silicon lattice at a percentage that places the channel layer under tensile stress.
- U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxialiy grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiOj/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
- An article entitled "Phenomena in silicon nanostructure devices" also to Tsu and published online September 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor- atomic superiattice (SAS) of silicon and oxygen.
- the Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices.
- a green eiectromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
- the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules.
- the application discloses that material parameters, for example, the location of band minima, effective mass, etc, can be tailored to yieid new aperiodic materials with desirable band-structure characteristics.
- Other parameters such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.
- a semiconductor device which may include at least one metal oxide field-effect transistor (MOSFET). More particularly, the at least one MOSFET may include a body, a channel layer adjacent the body, and a dopant blocking superlattice between the body and the channel layer.
- the dopant blocking superlattice may include a plurality of stacked groups of layers.
- Each group of layers of the dopant blocking superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
- the superlattice advantageously blocks unwanted diffusion of dopants between the body and the channel layer.
- the dopant blocking superlattice may have a relatively small thickness, in addition, the superlattice also enjoys enhanced mobility properties which may also be utilized in certain applications in addition to its dopant blocking ability, such as if a portion of the MOSFET channel is formed in the dopant blocking superlattice.
- the body may have at least one doped region therein.
- the body may have a dopant concentration of greater than about 1x10 18 cm "3 .
- the channel layer may be substantially undoped, i.e., having a dopant concentration of less than about 1x10 15 cm "3 , for example.
- At least one group of layers of the dopant blocking superlattice may also be substantially undoped.
- the at least one MOSFET may further include a gate overlying the channel layer including a gate insulating layer adjacent the channel layer, and a gate electrode adjacent the gate insulating layer and opposite the channel layer. Additionally, source and drain regions may be lateraiiy adjacent the channel layer.
- the at least one non-semiconductor monolayer may be a single monolayer thick, and the base semiconductor portion may be less than eight monolayers thick. All of the base semiconductor portions may be a same number of monolayers thick, for example. Alternately, at least some of the base semiconductor portions may be a different number of monolayers thick. Also, opposing base semiconductor monolayers in adjacent groups of layers of the superlattice may be chemically bound together. [0018] Another aspect of the invention is directed to a method for making a semiconductor device.
- the method may include forming at least one metal oxide field-effect transistor (MOSFET) by forming a body, forming a dopant blocking superlattice adjacent the body, and forming a channel layer adjacent the dopant blocking superiattice and opposite the body.
- MOSFET metal oxide field-effect transistor
- the dopant blocking superlattice may include a plurality of stacked groups of layers. Each group of layers of the dopant blocking superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
- the superlattice advantageously blocks unwanted diffusion of dopants between the body and the channel layer.
- the dopant blocking superlattice may have a relatively small thickness.
- the superlattice also enjoys enhanced mobility properties which may also be utilized in certain applications in addition to its dopant blocking ability, such as if a portion of the MOSFET channel is formed in the dopant blocking superlattice.
- FIG. 1 is schematic cross-sectional diagram of a semiconductor device in accordance with the present invention including a dopant blocking superlattice.
- FIG. 2 is a greatly enlarged schematic cross-sectional view of the superlattice as shown in FIG. 1.
- FlG. 3 is a perspective schematic atomic diagram of a portion of the superiattice shown in FlG. 1.
- FiG. 4 is a greatly enlarged schematic cross-sectional view of another embodiment of a superiattice that may be used in the device of FIG. 1.
- FIG. 5A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superiattice as shown in FIGS. 1-3.
- FIG. 5C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superiattice as shown in FIG. 4.
- FSGS. 6A-6D are a series of schematic cross-sectional diagrams illustrating a method for making the semiconductor device of FIG. 1.
- Detailed Description of the Preferred Embodiments The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in alternate embodiments.
- the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices.
- f is the Fermi-Dirac distribution
- EF is the Fermi energy
- T is the temperature
- E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
- the indices i and ] refer to Cartesian coordinates x, y and z
- the integrals are taken over the Briiiouin zone (B.Z.)
- the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
- the illustrated MOSFET 20 includes a substrate 21 with one or more body implants 29 therein.
- one or more body implants 29 may be used for setting a voltage threshold (VT) of the MOSFET 20, and/or for reducing punch through effect, as will be appreciated by those skilled in the art.
- VT voltage threshold
- such body implants may have a dopant concentration of greater than about 1x10 18 cm "3 .
- substantially undoped it is meant that no dopants are intentionally added, although it will be appreciated by those skilled in the art that impurities may still be present from semiconductor processing.
- the dopant concentration in the substantially undoped channel layer 24 may preferably be !ess than about 1x10 15 cm "3 , and, more preferably, less than about 5x10 14 cm “3 , for example.
- the superlattice 25 advantageously blocks unwanted diffusion of dopants between the body and the channel layer 24, as will be discussed further below.
- a gate dielectric layer 37 (which is shown with stippling for clarity of illustration in F!G. 1) is on the channel layer 24, and a gate electrode layer 36 is on the gate dielectric layer and opposite the channel layer. Sidewall spacers 40, 41 are also provided in the illustrated MOSFET 20, as well as suicide layers 30, 31 and respective source/drain contacts 32, 33 on the lightly doped source and drain regions 22, 23. A suicide layer 34 is also on the gate electrode layer 36.
- the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or moiecular layer deposition.
- the superiattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 2.
- Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a»46n and an energy band- modifying layer 50 thereon.
- the energy band-modifying layers 50 are indicated by stippling in F!G. 2 for clarity of illustration.
- the energy-band modifying layer 50 illustratively includes one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. That is, opposing base semiconductor monolayers 46 in adjacent groups of layers 45a-45n are chemicaliy bound together.
- silicon monolayers 46 some of the silicon atoms in the upper or top semiconductor monolayer of the group of monolayers 46a will be covalently bonded with silicon atoms in the lower or bottom monolayer of the group 46b. This allows the crystal lattice to continue through the groups of layers despite the presence of the non-semiconductor monolayer(s) (e.g., oxygen monolayer(s)).
- the non-semiconductor monolayer(s) e.g., oxygen monolayer(s)
- non-semiconductor or semiconductor monolayer means that the materia! used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as semiconductor, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
- energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present.
- this parallel direction is orthogonal to the stacking direction.
- the band modifying layers 50 may also cause the superiatttce 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.
- this structure aiso advantageously provides a barrier to dopant and/or materia! bleed or diffusion between layers vertically above and crizow the superlattice 25.
- a semiconductor device such as the illustrated MOSFET 20, will enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than wouid otherwise be present.
- the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example, as described in further detail below.
- a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example, as described in further detail below.
- all of the above-described properties of the superlattice 25 need not be utilized in every application.
- the superlattice 25 may only be used for its dopant biocking/insulation properties or its enhanced mobility, or it may be used for both in other applications, as will be appreciated by those skilled in the art.
- the superlattice 25 may also advantageously be used to provide the channel layer 24. More particularly, in the illustrated embodiment the channel layer 24 of the MOSFET 20 is a cap layer 52 of the superlattice 25. Yet, in some embodiments the superlattice 25 may be made sufficiently thick so that portions of the channel are defined in the upper group(s) of layers 45 of the superlattice. In other embodiments, a second channel superlattice layer may be grown on the dopant blocking superlattice 25, for example. Further details on using such a superlattice as a channel in a semiconductor device are provided in U.S. application serial no. 10/647,069, which is assigned to the present Assignee and is hereby incorporated in its entirety by reference, for example.
- the cap layer 52 is on an upper iayer group 45n of the superiattice 25.
- the cap Iayer 52 may comprise a plurality of base semiconductor monolayers 46.
- the cap iayer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers. Other thicknesses may be used as well.
- Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group IH-V semiconductors, and Group H-Vl semiconductors.
- Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
- the base semiconductor may comprise at least one of silicon and germanium, for example.
- Each energy band-modifying layer 50 may comprise a non- semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example.
- the non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
- the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing, as will be appreciated by those skilled in the art.
- the term "monolayer” is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied. For example, with particular reference to the atomic diagram of FIG. 3, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied. [005O]In other embodiments and/or with different materials this one half occupation would not necessarily be the case as will be appreciated by those skiiied in the art.
- the lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
- the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
- the superlattice 25 it may be especially appropriate to dope some portion of the superlattice 25 if the superlattice is to provide a portion of the channel, for example. In other embodiments, it may be preferably to have one or more groups of layers 45 of the superlattice 25 substantially undoped.
- FIG. 4 another embodiment of a superlattice 25' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'.
- the energy band-modifying layers 50' may each include a single monolayer.
- all of the base semiconductor portions 46a-46n of a superlattice 25 may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions 46a- 46n may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions 46a-46n may be a different number of monolayers thick.
- FIGS. 5A-5C band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate "scissors correction.” However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.
- DFT Density Functional Theory
- FIG. 5A shows the calculated band structure from the gamma point (G) for both buik silicon (represented by continuous lines) and for the 4/1 Si/O superiattice 25 as shown in FIGS. 1-3 (represented by dotted lines).
- the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventionai unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum.
- the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventionai Si unit cell.
- FIG. 5B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superiattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.
- F!G. 5C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superiattice 25' of FIG. 4 (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
- the substrate may be an eight-inch wafer 21 of lightly doped P-type or N-type single crystal silicon with ⁇ 100> orientation, although other suitable substrates may also be used.
- a trench 60 is formed in the substrate and the body implant(s) 29 is formed in the trench.
- the body implants may be performed before the trench 60 is formed.
- a layer of the superlattice 25 material is formed in the trench 60. More particularly, the superiattice 25 material is deposited in the trench 60 using atomic layer deposition, and the epitaxial silicon cap layer 52 is formed thereon to provide the channel layer 24 of the MOSFET 20, as discussed previously above, and the surface is planarized.
- the superlattice 25 material may be selectively deposited in desired areas, rather than across the entire substrate 21 , as will be appreciated by those skilled in the art. That is, the superlattice may be formed on the upper surface of the substrate 21 in some embodiments without a trench 60, and the source/drain regions 22, 26 and 23, 27 may be epttaxially formed laterally adjacent thereto.
- the epitaxial silicon cap layer 52 may have a preferred thickness to prevent channel consumption during gate oxide growth, or any other subsequent oxidations. According to the well-known relationship of consuming approximately 45% of the underlying silicon for a given oxide grown, the silicon cap layer may be sized accordingly as would be known to those skilled in the art.
- the gate dieiectric layer 37 and the gate electrode layer 36 are formed. More particularly, the dielectric materia! is deposited, and steps of poly deposition, patterning, and etching are performed to provide the gate stack illustrated in FIG. 6B.
- Poly deposition refers to low-pressure chemical vapor deposition (LPCVD) of silicon onto an oxide (hence it forms a polycrystalline material). The step includes doping with P+ or As- to make it conducting, and the layer may be around 250 nm thick, for example.
- the pattern step may include performing a spinning photoresist, baking, exposure to light (i.e., a photolithography step), and developing the resist.
- the pattern is then transferred to another layer (oxide or nitride) which acts as an etch mask during the etch step.
- the etch step typically is a plasma etch (anisotropic, dry etch) that is material selective (e.g., etches silicon ten times faster than oxide) and transfers the lithography pattern into the material of interest.
- the superlattice 25 material may be etched using known semiconductor processing techniques. However, it should be noted that with the non- semiconductor present in the superlattice 25, e.g., oxygen, the superlattice may be more easily etched using an etchant formulated for oxides rather than silicon. Of course, the appropriate etch for a given implementation will vary based upon the structure and materials used for the superlattice 25 and substrate 21, as will be appreciated by those of skill in the art. [007O] In FiG.
- LDD lightly doped source and drain
- These regions are formed using n-type or p-type LDD implantation, annealing, and cleaning.
- An anneal step may be used after the LDD implantation, but depending on the specific process, it may be omitted.
- the clean step is a chemical etch to remove metals and organics prior to depositing an oxide layer.
- FIG. 6D shows the formation of the sidewall spacers 40, 41 and the source and drain 26, 27 implants.
- An Si ⁇ 2 mask may be deposited and etched back for this purpose.
- N-type or p-type ion implantation is used to form the source and drain regions 26, 27, depending upon the given impiementation.
- the structure is then annealed and cleaned.
- Self-aligned suicide formation may then be performed to form the silicide layers 30, 31 , and 34, and the source/drain contacts 32, 33, are formed to provide the final semiconductor device 20 illustrated in FIG. 1.
- the suicide formation is also known as salicidation.
- the salicidation process includes metal deposition (e.g., Ti), nitrogen annealing, metai etching, and a second annealing.
- the foregoing is, of course, but one example of a process and device in which the present invention may be used, and those of skill in the art will understand its application and use in many other processes and devices.
- the structures of the present invention may be formed on a portion of a wafer or across substantially ail of a wafer.
- the use of an atomic layer deposition tool may also not be needed for forming the superlattice 25 in some embodiments.
- the monolayers may be formed using a CVD tool with process conditions compatible with control of monolayers, as will be appreciated by those skilled in the art. Further details regarding fabrication of semiconductor devices in accordance with the present invention may be found in the above-noted U.S. application no. 10/467,069, for example.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Nanotechnology (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07761675A EP2020035A1 (en) | 2006-05-01 | 2007-05-01 | Semiconductor device including a dopant blocking superlattice and associated methods |
AU2007248171A AU2007248171A1 (en) | 2006-05-01 | 2007-05-01 | Semiconductor device including a dopant blocking superlattice and associated methods |
JP2009510026A JP2009535861A (en) | 2006-05-01 | 2007-05-01 | Semiconductor device having superlattice to block dopants and related method |
CA002650965A CA2650965A1 (en) | 2006-05-01 | 2007-05-01 | Semiconductor device including a dopant blocking superlattice and associated methods |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/380,987 US20060220118A1 (en) | 2003-06-26 | 2006-05-01 | Semiconductor device including a dopant blocking superlattice |
US11/380,992 US20060273299A1 (en) | 2003-06-26 | 2006-05-01 | Method for making a semiconductor device including a dopant blocking superlattice |
US11/380,987 | 2006-05-01 | ||
US11/380,992 | 2006-05-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007130973A1 true WO2007130973A1 (en) | 2007-11-15 |
Family
ID=38542004
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/067926 WO2007130973A1 (en) | 2006-05-01 | 2007-05-01 | Semiconductor device including a dopant blocking superlattice and associated methods |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP2020035A1 (en) |
JP (1) | JP2009535861A (en) |
AU (1) | AU2007248171A1 (en) |
CA (1) | CA2650965A1 (en) |
WO (1) | WO2007130973A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011112574A1 (en) * | 2010-03-08 | 2011-09-15 | Mears Technologies, Inc | Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods |
WO2018213385A1 (en) * | 2017-05-16 | 2018-11-22 | Atomera Incorporated | Semiconductor device and method including a superlattice as a gettering layer |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014135359A (en) * | 2013-01-09 | 2014-07-24 | Tokyo Institute Of Technology | Field-effect transistor |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4594603A (en) * | 1982-04-22 | 1986-06-10 | Board Of Trustees Of The University Of Illinois | Semiconductor device with disordered active region |
US6326272B1 (en) * | 1999-11-18 | 2001-12-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming self-aligned elevated transistor |
US20040029320A1 (en) * | 2002-08-07 | 2004-02-12 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate elevated source/drain structures in mos transistors |
US20040266045A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears Llc. | Method for making semiconductor device including band-engineered superlattice |
WO2005004241A1 (en) * | 2003-07-02 | 2005-01-13 | Koninklijke Philips Electronics N.V. | Semiconductor device, method of manufacturing a quantum well structure and a semiconductor device comprising such a quantum well structure |
WO2006031601A1 (en) * | 2004-09-09 | 2006-03-23 | Rj Mears, Llc | Integrated circuit comprising an active optical device having an energy band engineered superlattice and associated fabrication methods |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0719888B2 (en) * | 1985-04-05 | 1995-03-06 | セイコーエプソン株式会社 | Field effect transistor and method of manufacturing the same |
JPS6394682A (en) * | 1986-10-08 | 1988-04-25 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated-gate field-effect semiconductor device |
JP2003174161A (en) * | 2001-12-05 | 2003-06-20 | Matsushita Electric Ind Co Ltd | Semiconductor device |
US7033437B2 (en) * | 2003-06-26 | 2006-04-25 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
-
2007
- 2007-05-01 CA CA002650965A patent/CA2650965A1/en not_active Abandoned
- 2007-05-01 EP EP07761675A patent/EP2020035A1/en not_active Withdrawn
- 2007-05-01 JP JP2009510026A patent/JP2009535861A/en active Pending
- 2007-05-01 AU AU2007248171A patent/AU2007248171A1/en not_active Abandoned
- 2007-05-01 WO PCT/US2007/067926 patent/WO2007130973A1/en active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4594603A (en) * | 1982-04-22 | 1986-06-10 | Board Of Trustees Of The University Of Illinois | Semiconductor device with disordered active region |
US6326272B1 (en) * | 1999-11-18 | 2001-12-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming self-aligned elevated transistor |
US20040029320A1 (en) * | 2002-08-07 | 2004-02-12 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate elevated source/drain structures in mos transistors |
US20040266045A1 (en) * | 2003-06-26 | 2004-12-30 | Rj Mears Llc. | Method for making semiconductor device including band-engineered superlattice |
WO2005034245A1 (en) * | 2003-06-26 | 2005-04-14 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
WO2005004241A1 (en) * | 2003-07-02 | 2005-01-13 | Koninklijke Philips Electronics N.V. | Semiconductor device, method of manufacturing a quantum well structure and a semiconductor device comprising such a quantum well structure |
WO2006031601A1 (en) * | 2004-09-09 | 2006-03-23 | Rj Mears, Llc | Integrated circuit comprising an active optical device having an energy band engineered superlattice and associated fabrication methods |
Non-Patent Citations (1)
Title |
---|
SEO YONG-JIN ET AL: "Transport through a nine period silicon/oxygen superlattice", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 79, no. 6, 6 August 2001 (2001-08-06), pages 788 - 790, XP012029987, ISSN: 0003-6951 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011112574A1 (en) * | 2010-03-08 | 2011-09-15 | Mears Technologies, Inc | Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods |
WO2018213385A1 (en) * | 2017-05-16 | 2018-11-22 | Atomera Incorporated | Semiconductor device and method including a superlattice as a gettering layer |
US10381242B2 (en) | 2017-05-16 | 2019-08-13 | Atomera Incorporated | Method for making a semiconductor device including a superlattice as a gettering layer |
US10410880B2 (en) | 2017-05-16 | 2019-09-10 | Atomera Incorporated | Semiconductor device including a superlattice as a gettering layer |
Also Published As
Publication number | Publication date |
---|---|
JP2009535861A (en) | 2009-10-01 |
AU2007248171A1 (en) | 2007-11-15 |
EP2020035A1 (en) | 2009-02-04 |
CA2650965A1 (en) | 2007-11-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7018900B2 (en) | Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions | |
CA2530067C (en) | Semiconductor device including band-engineered superlattice | |
US7033437B2 (en) | Method for making semiconductor device including band-engineered superlattice | |
US7446002B2 (en) | Method for making a semiconductor device comprising a superlattice dielectric interface layer | |
US20060220118A1 (en) | Semiconductor device including a dopant blocking superlattice | |
US20060273299A1 (en) | Method for making a semiconductor device including a dopant blocking superlattice | |
EP1902472B1 (en) | Semiconductor device comprising a superlattice dielectric interface layer | |
WO2006127291A2 (en) | Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers | |
WO2006127269A2 (en) | Semiconductor device including a superlattice having at least one group of substantially undoped layer | |
EP2020035A1 (en) | Semiconductor device including a dopant blocking superlattice and associated methods | |
CA2650809A1 (en) | Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods | |
EP2016621A1 (en) | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice and associated methods |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200780021569.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 07761675 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2650965 Country of ref document: CA Ref document number: 2009510026 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007248171 Country of ref document: AU |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007761675 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2007248171 Country of ref document: AU Date of ref document: 20070501 Kind code of ref document: A |