WO2007116362A1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
WO2007116362A1
WO2007116362A1 PCT/IB2007/051245 IB2007051245W WO2007116362A1 WO 2007116362 A1 WO2007116362 A1 WO 2007116362A1 IB 2007051245 W IB2007051245 W IB 2007051245W WO 2007116362 A1 WO2007116362 A1 WO 2007116362A1
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WO
WIPO (PCT)
Prior art keywords
layer
pattern
hard mask
photo
mask layer
Prior art date
Application number
PCT/IB2007/051245
Other languages
French (fr)
Inventor
Jerome Todeschini
Bertrand Le-Gratiet
Philippe Garnier
Veronique De-Jonghe
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2007116362A1 publication Critical patent/WO2007116362A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/203—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0277—Electrolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • the invention relates to a method of manufacturing a semiconductor device.
  • Electron Beam Direct Write (EBDW) lithography uses an electron source that produces a small diameter spot and has an arrangement for turning the beam on and off.
  • EBDW lithography generally does not have the small process window of conventional optical photolithography. Furthermore, it allows for highly precise feature sizes, that otherwise would require complex optical masks. However, EBDW lithography has the unfortunate disadvantage that it is significantly slower than conventional optical photolithography.
  • Patent application US 2005/0160383 describes a combined EBDW and optical exposure lithography for semiconductor fabrication.
  • a semiconductor design for a semiconductor wafer is separated in critical dimension (CD) areas and non-CD areas.
  • a photoresist is coated on the semiconductor wafer.
  • the method employs EBDW lithography to create the CD areas in the photoresist on the semiconductor wafer and optical exposure lithography to create the non-CD areas in the photoresist on the semiconductor wafer.
  • the combination of EBDW and optical exposure is used on the same wafer to obtain good resolution via EBDW lithography, and at the same time to obtain a high throughput by applying the optical exposure.
  • the invention provides a device as claimed in claim 1.
  • Advantageous embodiments are defined by the dependent claims.
  • the invention is based on the recognition that it is not possible to apply a photoresist optimized both for the EBDW lithography and for the optical lithography because only one photoresist per lithography step can be applied in the prior art.
  • the invention overcomes this disadvantage and enables applying different types of photoresist for the EBDW lithography and for the optical lithography.
  • the method of manufacturing a semiconductor device comprises the steps of: depositing a stack of a first hard mask layer, a capping layer and a second hard mask layer on a substrate region; forming a first pattern in the second hard mask layer with a first lithographic technique using a first photo-sensitive layer; depositing a second photo- sensitive layer at least on the capping layer; forming a second pattern in the second photo- sensitive layer and in the capping layer with a second lithographic technique, thereby also forming the second pattern in the capping layer; and removing the second photo- sensitive layer, the second hard mask layer and exposed portions of the first hard mask layer, thereby forming a third pattern, comprising the second pattern and a part of the first pattern, in the first hard mask layer.
  • the second pattern comprises at least one line or one space with a dimension that is smaller than achievable by optical lithography. This allows for the manufacturing of dimensions smaller than achievable by optical lithography with a lithographic technique different from optical lithography in combination with the manufacturing of dimensions that are obtained with optical lithography in one masking layer.
  • the first lithographic technique comprises optical lithography and the second lithographic technique comprises electron beam lithography.
  • the best properties of optical lithography are combined with the best properties of electron beam lithography, such as speed in optical lithography and feature size in electron beam lithography.
  • the removal rate of the first hard mask layer is comparable to the removal rate of the second photo-sensitive layer.
  • the second photo-sensitive layer is removed with the same removal step, such as etching, as sued for removing the first hard mask layer, thereby saving a separate removal step for the second photo-sensitive layer.
  • the first hard mask layer is of an amorphous carbon material.
  • the first photosensitive layer has a resist tone opposite to that of the second photo-sensitive layer. This allows for an optimization of the first and the second lithographic step.
  • Figs. 1-8 are diagrammatic cross-sectional views of an embodiment of a semiconductor device being fabricated in accordance with a method according to the invention.
  • Fig. 1 shows a substrate 1 on which a first hard mask layer 2, a capping layer 3 and a second hard mask layer 4 are formed.
  • the first hard mask layer 2 and the second hard mask layer 4 have approximately the same thickness and are, in this case, of amorphous carbon material.
  • the capping layer 3 prevents the etching process from affecting the first hard mask layer 2. Therefore, the capping layer 3 is of a material that is different from the material of the first and second hard mask layers 2,4 and that is not affected by the etching process of the second hard mask layer 4.
  • the capping layer 3 comprises, for example, silicon dioxide or silicon nitride.
  • a first photoresist layer 5 is deposited on the second hard mask layer 4.
  • a first lithographic step is applied to create a first pattern in the first photoresist layer 5, resulting in a patterned first photoresist layer 15, which exposes portions 24 of the second hard mask layer 4.
  • the exposed portions 24 of the second hard mask layer 4 are removed with an etching step that stops when portions 23 of the capping layer 3 are exposed.
  • the first pattern is transferred to the second hard mask layer 4 resulting in a patterned second hard mask layer 14.
  • the first photoresist layer 21 is removed using a standard stripping technique.
  • a second photoresist layer 6 is deposited on the capping layer 3 and on the patterned second hard mask layer 14.
  • a second lithographic step is applied to create a second pattern in the second photoresist layer 6, resulting in a patterned second photoresist layer 16 on the capping layer 3, which exposes the patterned second hard mask layer 14 and portions 33 of the capping layer 3.
  • the exposed portions 33 of the capping layer 3 are removed using a standard etching technique that does not affect the first hard mask layer 2, resulting in a patterned capping layer 13, which comprises a third pattern that is a combination of the first pattern and the third pattern. Portions 23 of the first hard mask layer 2 are now exposed.
  • the first lithographic step is, in this case, an optical lithography step and the second lithographic step is, in this case, an EBDW lithography step.
  • the optical lithographic step creates a first pattern with a minimum dimension that is larger than the minimum dimension of the second pattern, as is schematically illustrated in Fig. 5 by the relative large dimensions of the patterned second hard mask layer 14 and the relatively small dimensions of the patterned second photoresist layer 16.
  • an etching technique is applied that removes simultaneously the patterned second photoresist layer 16, the patterned second hard mask layer 14 and the exposed portions 23 of the first hard mask layer 2, resulting in a patterned first hard mask layer 12 comprising the third pattern, which is a combination of the first pattern and the second pattern. Portions 21 of the substrate region 1 are now exposed.
  • the patterned capping layer 13 is, in this case, removed and, as is illustrated in Fig. 8, the third pattern is transferred to the substrate region 1 by removing the exposed portions 21 of the substrate region 1 by an appropriate etching technique in which the patterned second hard mask layer 12 functions as a mask, resulting in a patterned substrate region 11.
  • the patterned second hard mask layer 12 comprises the third pattern, which combines dimensions obtained with two different lithographic techniques and, in this case, two different photoresist layers 5,6.
  • the patterned substrate region 11 comprises at least one line or one space with a dimension that is smaller than can be achieved with optical lithography that is manufactured by the second lithographic step that created the second pattern. Dimensions that can be achieved by optical lithography are manufactured by the first lithographic step that created the first pattern. Furthermore, the first pattern comprises at least one region in which the second pattern is formed.
  • the invention provides a method of manufacturing a semiconductor device in which a stack of a first hard mask layer, a capping layer and a second hard mask layer is provided on a substrate.
  • a first pattern is formed in the second hard mask layer with a first lithographic technique using a first photo-sensitive layer.
  • a second photo-sensitive layer is deposited at least on the capping layer.
  • a second pattern is formed in the second photo- sensitive layer and in the capping layer with a second lithographic technique thereby also forming the second pattern in the capping layer.
  • the second photo-sensitive layer, the second hard mask layer and exposed portions of the first hard mask layer are removed, thereby forming a third pattern, which is a combination of the second pattern and a part of the first pattern, in the first hard mask layer.

Abstract

The invention provides a method of manufacturing a semiconductor device in which a stack of a first hard mask layer (2), a capping layer (3) and a second hard mask layer (4) is provided on a substrate region (1). A first pattern is formed in the second hard mask layer (4) with a first lithographic technique using a first photo-sensitive layer (5). Thereafter, a second photo-sensitive layer (6) is deposited at least on the capping layer (3). Then a second pattern is formed in the second photo-sensitive layer (6) and in the capping layer (3) with a second lithographic technique thereby also forming the second pattern in the capping layer (3). Thereafter the second photo- sensitive layer (6,16), the second hard mask layer (4,14) and exposed portions (23) of the first hard mask layer (2) are removed, thereby forming a third pattern, which is a combination of the second pattern and a part of the first pattern, in the first hard mask layer (2,12). In this way two different photo-sensitive layers (5,6) are applied to create the third pattern in the first hard mask layer (2), which is a combination of a part of the first pattern, created by the first photo- sensitive layer (5), and the second pattern, created by the second photo- sensitive layer (6).

Description

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
The invention relates to a method of manufacturing a semiconductor device.
Feature sizes on integrated circuits (ICs) have become exponentially smaller. Improvement in overlay tolerances in optical photolithography, and the introduction of new light sources with progressively shorter wavelengths, have enabled optical steppers in semiconductor fabrication with a significantly reduced resolution limit of the feature sizes. To continue to make the features smaller, traditional optical photolithography with complicated masks for semiconductor fabrication has become difficult, even though optical photolithography is a desired process because of the short throughput time. One solution is to write on the semiconductor wafer directly, using an electron beam, or e-beam, instead of using traditional optical exposure. Electron Beam Direct Write (EBDW) lithography, as it is known, uses an electron source that produces a small diameter spot and has an arrangement for turning the beam on and off. EBDW lithography generally does not have the small process window of conventional optical photolithography. Furthermore, it allows for highly precise feature sizes, that otherwise would require complex optical masks. However, EBDW lithography has the unfortunate disadvantage that it is significantly slower than conventional optical photolithography.
Patent application US 2005/0160383 describes a combined EBDW and optical exposure lithography for semiconductor fabrication. A semiconductor design for a semiconductor wafer is separated in critical dimension (CD) areas and non-CD areas. Then a photoresist is coated on the semiconductor wafer. Subsequently, the method employs EBDW lithography to create the CD areas in the photoresist on the semiconductor wafer and optical exposure lithography to create the non-CD areas in the photoresist on the semiconductor wafer. Thus, the combination of EBDW and optical exposure is used on the same wafer to obtain good resolution via EBDW lithography, and at the same time to obtain a high throughput by applying the optical exposure.
It is therefore an object of the invention to provide an improved method of manufacturing a semiconductor device. The invention provides a device as claimed in claim 1. Advantageous embodiments are defined by the dependent claims. The invention is based on the recognition that it is not possible to apply a photoresist optimized both for the EBDW lithography and for the optical lithography because only one photoresist per lithography step can be applied in the prior art. The invention overcomes this disadvantage and enables applying different types of photoresist for the EBDW lithography and for the optical lithography.
The method of manufacturing a semiconductor device according to the invention comprises the steps of: depositing a stack of a first hard mask layer, a capping layer and a second hard mask layer on a substrate region; forming a first pattern in the second hard mask layer with a first lithographic technique using a first photo-sensitive layer; depositing a second photo- sensitive layer at least on the capping layer; forming a second pattern in the second photo- sensitive layer and in the capping layer with a second lithographic technique, thereby also forming the second pattern in the capping layer; and removing the second photo- sensitive layer, the second hard mask layer and exposed portions of the first hard mask layer, thereby forming a third pattern, comprising the second pattern and a part of the first pattern, in the first hard mask layer.
In this way two different photo-sensitive layers are applied to create the third pattern in the first hard mask layer, which is a combination of a part of the first pattern, created by the first photo-sensitive layer, and the second pattern, created by the second photosensitive layer.
In an embodiment of the method according to the invention the second pattern comprises at least one line or one space with a dimension that is smaller than achievable by optical lithography. This allows for the manufacturing of dimensions smaller than achievable by optical lithography with a lithographic technique different from optical lithography in combination with the manufacturing of dimensions that are obtained with optical lithography in one masking layer.
In another embodiment of the method according to the invention the first lithographic technique comprises optical lithography and the second lithographic technique comprises electron beam lithography. This way the best properties of optical lithography are combined with the best properties of electron beam lithography, such as speed in optical lithography and feature size in electron beam lithography. In an embodiment of the method according to the invention the removal rate of the first hard mask layer is comparable to the removal rate of the second photo-sensitive layer. As a result of this, the second photo- sensitive layer is removed with the same removal step, such as etching, as sued for removing the first hard mask layer, thereby saving a separate removal step for the second photo-sensitive layer. Preferably, the first hard mask layer is of an amorphous carbon material.
In an embodiment of the method according to the invention the first photosensitive layer has a resist tone opposite to that of the second photo-sensitive layer. This allows for an optimization of the first and the second lithographic step.
These and other aspects of the invention will be further elucidated and described with reference to the drawings, in which:
Figs. 1-8 are diagrammatic cross-sectional views of an embodiment of a semiconductor device being fabricated in accordance with a method according to the invention.
The Figures are not drawn to scale. In general, identical components are denoted by the same reference numerals in the Figures.
Fig. 1 shows a substrate 1 on which a first hard mask layer 2, a capping layer 3 and a second hard mask layer 4 are formed. The first hard mask layer 2 and the second hard mask layer 4 have approximately the same thickness and are, in this case, of amorphous carbon material. In the case of etching of the second hard mask layer 4, the capping layer 3 prevents the etching process from affecting the first hard mask layer 2. Therefore, the capping layer 3 is of a material that is different from the material of the first and second hard mask layers 2,4 and that is not affected by the etching process of the second hard mask layer 4. The capping layer 3 comprises, for example, silicon dioxide or silicon nitride. Then, a first photoresist layer 5 is deposited on the second hard mask layer 4.
As is shown in Fig. 2, a first lithographic step is applied to create a first pattern in the first photoresist layer 5, resulting in a patterned first photoresist layer 15, which exposes portions 24 of the second hard mask layer 4.
Then, as is shown in Fig. 3, the exposed portions 24 of the second hard mask layer 4 are removed with an etching step that stops when portions 23 of the capping layer 3 are exposed. At this stage the first pattern is transferred to the second hard mask layer 4 resulting in a patterned second hard mask layer 14.
Thereafter, as is shown in Fig.4, the first photoresist layer 21 is removed using a standard stripping technique. Then, a second photoresist layer 6 is deposited on the capping layer 3 and on the patterned second hard mask layer 14.
As is shown in Fig. 5, a second lithographic step is applied to create a second pattern in the second photoresist layer 6, resulting in a patterned second photoresist layer 16 on the capping layer 3, which exposes the patterned second hard mask layer 14 and portions 33 of the capping layer 3.
Thereafter, as is shown in Fig. 6, the exposed portions 33 of the capping layer 3 are removed using a standard etching technique that does not affect the first hard mask layer 2, resulting in a patterned capping layer 13, which comprises a third pattern that is a combination of the first pattern and the third pattern. Portions 23 of the first hard mask layer 2 are now exposed.
It should be noted that the first lithographic step is, in this case, an optical lithography step and the second lithographic step is, in this case, an EBDW lithography step. Hence, the optical lithographic step creates a first pattern with a minimum dimension that is larger than the minimum dimension of the second pattern, as is schematically illustrated in Fig. 5 by the relative large dimensions of the patterned second hard mask layer 14 and the relatively small dimensions of the patterned second photoresist layer 16.
Then, as is shown in Fig. 7, an etching technique is applied that removes simultaneously the patterned second photoresist layer 16, the patterned second hard mask layer 14 and the exposed portions 23 of the first hard mask layer 2, resulting in a patterned first hard mask layer 12 comprising the third pattern, which is a combination of the first pattern and the second pattern. Portions 21 of the substrate region 1 are now exposed.
Then the patterned capping layer 13 is, in this case, removed and, as is illustrated in Fig. 8, the third pattern is transferred to the substrate region 1 by removing the exposed portions 21 of the substrate region 1 by an appropriate etching technique in which the patterned second hard mask layer 12 functions as a mask, resulting in a patterned substrate region 11. The patterned second hard mask layer 12 comprises the third pattern, which combines dimensions obtained with two different lithographic techniques and, in this case, two different photoresist layers 5,6. This enables the combination of, for example, a positive tone photoresist layer for optical lithography and a negative tone photoresist layer for EBDW photolithography, thereby enabling an optimized manufacturing of, for example, active area and gate electrode patterns, and also of contact patterns or metal layer patterns.
The patterned substrate region 11 comprises at least one line or one space with a dimension that is smaller than can be achieved with optical lithography that is manufactured by the second lithographic step that created the second pattern. Dimensions that can be achieved by optical lithography are manufactured by the first lithographic step that created the first pattern. Furthermore, the first pattern comprises at least one region in which the second pattern is formed.
In summary, the invention provides a method of manufacturing a semiconductor device in which a stack of a first hard mask layer, a capping layer and a second hard mask layer is provided on a substrate. A first pattern is formed in the second hard mask layer with a first lithographic technique using a first photo-sensitive layer. Thereafter, a second photo-sensitive layer is deposited at least on the capping layer. Then a second pattern is formed in the second photo- sensitive layer and in the capping layer with a second lithographic technique thereby also forming the second pattern in the capping layer. Thereafter the second photo-sensitive layer, the second hard mask layer and exposed portions of the first hard mask layer are removed, thereby forming a third pattern, which is a combination of the second pattern and a part of the first pattern, in the first hard mask layer.
In this way two different photo-sensitive layers are applied to create the third pattern in the first hard mask layer, which is a combination of a part of the first pattern, created by the first photo-sensitive layer, and the second pattern, created by the second photosensitive layer.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Claims

CLAIMS:
1. A method of manufacturing a semiconductor device comprising the steps of: depositing a stack of a first hard mask layer (2), a capping layer (3) and a second hard mask layer (4) on a substrate region (1); forming a first pattern in the second hard mask layer (4) with a first lithographic technique using a first photo-sensitive layer (5); depositing a second photo- sensitive layer (6) at least on the capping layer (3); forming a second pattern in the second photo- sensitive layer (6) and in the capping layer (3) with a second lithographic technique, thereby also forming the second pattern in the capping layer (3); and removing the second photo- sensitive layer (6,16), the second hard mask layer (4,14) and exposed portions (23) of the first hard mask layer (2), thereby forming a third pattern, comprising the second pattern and a part of the first pattern, in the first hard mask layer (2,12).
2. A method as claimed in claim 1, in which the second pattern comprises at least one line or one space with a dimension that is smaller than achievable by optical lithography.
3. A method as claimed in claim 1, in which the first lithographic technique comprises optical lithography and the second lithographic technique comprises electron beam lithography.
4. A method as claimed in claim 1, in which the removal rate of the first hard mask layer (2) is comparable to the removal rate of the second photo-sensitive layer (6,16).
5. A method as claimed in claim 4, in which the first hard mask layer (2,12) is of an amorphous carbon material.
6. A method as claimed in claim 1, in which the first photo- sensitive layer (5,15) has a resist tone opposite to that of the second photo-sensitive layer (6,16).
PCT/IB2007/051245 2006-04-07 2007-04-06 Method of manufacturing a semiconductor device WO2007116362A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06300342 2006-04-07
FR06300342.0 2006-04-07

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012062058A1 (en) * 2010-11-10 2012-05-18 中国科学院微电子研究所 Method for improving efficiency of electron beam lithography
US8278026B2 (en) 2010-11-10 2012-10-02 Institute of Microelectronics, Chinese Academy of Sciences Method for improving electron-beam
US20140057099A1 (en) * 2012-08-21 2014-02-27 Globalfoundries Inc. Hardmask capping layer
US10918356B2 (en) 2016-11-22 2021-02-16 General Electric Company Ultrasound transducers having electrical traces on acoustic backing structures and methods of making the same

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