Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

• the present invention relates to a multi-port memory device, more specifically
• memories can be classified into volatile memories and
• Volatile memories are commonly referred to as a RAM (random access
• ROM read only memory
• the volatile memories are sub-classified into a DRAM (dynamic RAM) and an
• SRAM static RAM
• Memories can be also classified into a single-port memory and a dual-port memory, according to the number of ports that are accessible to the memory.
• Today's digital processing apparatuses have a plurality of processors, each of
• FIG. 1 shows a bank structure of a dual-port memory, among conventional
• the conventional dual-port memory has an A-port
• A-port dedicated bank 100 only an A-port may access and read or write data, and in the
• B-port dedicated banks 104 and 106 only a B-port.
• the shared bank 102 can be accessed by both the A-port and the B-port to read
• the other port was not allowed to use the shared bank, even though the shared bank 102 could be used by either of the A-port and B-port. That is, while the A-port is
• the B-port was not able to access the shared
• the present invention provides a multi-port memory device in which each of
• the ports in a multi-port memory can access a shared bank at the same time to use the
• the present invention provides a multi-port memory device that can have an
• the shared bank into a plurality of blocks while maintaining the number of banks.
• the present invention provides a multi-port memory device that includes a
• an aspect of the present invention features a
• the multi-port memory device having two or more ports.
• the multi-port memory device has
• At least one dedicated bank allowing access by a particular port only and at least one
• the shared bank allowing access by multiple ports.
• the shared bank includes a plurality of
• the multiple ports can be modified from an address part of a predetermined memory
• the modified address part can include address information of a shared bank
• the command related to use of the shared bank can include a SET command
• Each block of the shared bank prohibits access by another port if a particular
• the predetermined memory command can be an MRS (Mode Register Set)
• the modified address part can also include information for setting attributes of
• each bank, and the attributes can include information on whether the bank is a dedicated
• Another aspect of the present invention features a dual-port memory device
• the shared bank includes a
• the first port and the second port independently access and use
• the first port or the second port can be modified from an address part of a predetermined
• the modified address part can include address information of a shared bank
• the second register can deliver the command to a block corresponding to the
• the predetermined memory command can be an MRS command, and the
• command related to use of the shared bank can include a SET command requesting
• Another aspect of the present invention features a method of accessing a
• a multi-port memory device which has at least one dedicated bank and a
• the dedicated bank allows access by a particular port, and the shared bank
• the method includes:
• multiple ports is modified from an address part, wherein the modified address part
• Each of the multiple ports independently accesses each block of
• the command for use of the block of the shared bank can include a SET
• FIG. 1 shows the bank structure of a dual-port memory, among the
• FIG. 2 shows the structure of a multi-port memory device including a plurality
• FIG. 3 shows how the A-port and the B-port access each respective bank in
• FIG. 4 shows the structure of a typical combination of an MRS command
• FIG. 5 shows an example of an MRS command that is modified to utilize a
• FIG. 6 shows the operation of ports in accordance with an embodiment of the present invention
• FIG. 7 shows the structure of a modified MRS command that includes
• FIGS. 8 and 9 show the operation of ports in accordance with another
• FIG. 10 shows an example of a read command that is modified to utilize a
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• the first element can be any element used only to distinguish one element from the other.
• FIG. 2 is an illustration of the structure of a multi-port memory device that
• the multi-port memory in accordance with the present
• inventions can include an A-port dedicated bank 200, a shared bank 202, two B-port
• the shared bank 202 can include a plurality of blocks 210, 212, 214,
• FIG. 2 shows a dual-port memory device, which accesses a memory
• Multi-port memory device which accesses the memory bank via more than two ports.
• Applications 220 and 222 provide a command and address information to the
• the application 220 provides command information, such as, for example,
• the above commands are made up of combinations of /RAS, /CAS, /CS, and
• the ACT command which enables /RAS to low, enables a
• the READ command which enables /CAS to low, reads data corresponding to
• the WRITE command which enables /CAS and /WE to low, writes the data
• the Precharge command which enables /RAS and /WE to low, disables a
• the Refresh command which enables /RAS and /CAS to low, periodically runs a refresh operation such that the memory does not lose the data.
• Every register set command enables all of /RAS, /CAS, /CS, and /WE to low
• the application 220 provides the command and address,
• the first and second register 230 and 232 receives the command from the
• the bank 200, 202, 204, and 206 is a unit by which data can be read or written
• the memory device has 4 banks to carry
• the A-port dedicated bank 200 is an area in which an A-port only can
• A-port dedicated bank 200 is A-port dedicated bank 200.
• the B-port dedicated banks 202 and 204 are areas in which the B-port only can
• FIG. 2 shows that one bank is assigned to the A-port dedicated bank
• banks assigned to the A-port and B-port can be various.
• the shared bank 202 is an area in which both the A port and B port can access
• the shared bank 202 was accessible by either of the A
• the B port could not access the shared bank 202 while the A port
• the shared bank has a
• the plurality of blocks 210, 212, 214, and 216 are independently operable, and
• the A port and B port can independently access any of the plurality of blocks.
• the B port accesses a block 1 212 and reads or writes data. However, it is not possible for the B port to use the block that the A port is occupying and using while
• the A port is occupying and using the particular block.
• FIG. 2 shows that there are 4 blocks, the number of blocks can be
• the number of blocks can be any of 2, 4, 8, or 16, as
• FIG. 3 shows how the A port and the B port access each bank in accordance
• a bank 0 300 is an A-port dedicated bank
• a bank 1 302 is a
• a bank 3 is a B-port dedicated bank.
• an X decoder of each bank codes a row address
• each bank functions as a control circuit
• the bank 0 300 is accessible by the A port only, and the
• control circuit of the bank 0 processes a command signal inputted from the A port.
• control circuit functions to identify address information included in the command and read/write the data corresponding to the address information from/to a
• the bank 2 304 is accessible by the B port only, and the control circuit of the
• bank 2 processes command information inputted from the B port.
• Each block of the bank 1 302, which is the shared bank, has an X decoder, a Y
• control circuit SO, Sl, S2, or S3
• the B port can occupy
• the B port can access the block 1 and write data to be
• the B port could write data in the shared bank only after the A port completes reading
• the present invention suggests a method of using conventional memory
• the command provided from the application commonly consists of a command type
• the command type uses the conventional
• a particular port is made
• the MRS command functions to set various specs, such as
• FIG. 4 is a structure of a combination of typical MRS commands and an
• the typical MRS commands are divided into a command
• /CAS, /RAS, /CS, and /WE are all set to low in the command type setting part, and through this setting the
• the address part 402 is written with information for setting an operation spec
• the spec includes a burst length, burst type, CAS latency, operation
• 3 bits are assigned for the setting of the burst length, which is set as
• the present invention allows the A port and B port to independently use the
• modified MRS commands are used as a command for using the modified MRS commands. That the modified MRS commands are used as a command for using the modified MRS commands.
• FIG. 5 is an example of modified MRS commands for use of the shared bank
• a command type part 500 is identical to typical MRS commands, and an address
• part includes shared block command information 502 and shared block address
• the command type part is identical to typical MRS
• control logic/register determines through the information of the
• the shared block command information includes command information set for
• command set for use of the shared blocks include SET, READ, and RESET commands.
• the SET command is for occupying a particular block of the shared bank. If
• the A port or B port desires to use a particular block, the SET command is used to
• the READ command is used to check whether a particular block of the shared
• the memory device If the READ command is delivered, the memory device provides
• the RESET command is for releasing the occupation of a particular block of the shared bank. If the use of the memory block of the shared bank is finished, the
• the shared block address information 504 includes block address information
• FIG. 1, 2 bits can be assigned for the block address. If there are 8 blocks in the shared
• bits for setting the shared block commands and the shared block address are to be
• all of the remaining bits can be set to low.
• MRS commands are modified to be used as a command for using
• the present invention is not restricted to modifying the MRS commands for use of a particular block of the shared banks in the above description, the present invention is not restricted to modifying the MRS commands for use of a particular block of the shared banks in the above description, the present invention is not restricted to modifying the MRS commands for use of a particular block of the shared banks in the above description, the present invention is not restricted to modifying the MRS commands for use of a particular block of the shared banks in the above description, the present invention is not restricted to modifying the MRS commands for use of a particular block of the
• the READ command or WRITE command can be modified to be
• FIG. 10 is an example of a READ command that is modified for use of a
• the command for use of a block of the shared bank can be any command for use of a block of the shared bank.
• FIG. 10 has the same address part as FIG. 5, but the
• command type is set as a READ command. If the modified READ command is utilized
• FIG. 6 is shows the operation of ports in accordance with an embodiment of
• a bank 0 600 which is an A-port dedicated bank, is only accessible by the A port for reading or writing data
• a bank 2 604 which is a B-port
• dedicated bank is only accessible by the B port for reading or writing data.
• a bank 1 602 which is a shared bank, can be accessed by the A port and B port
• the B port can occupy another block, other than the
• FIGS. 8 and 9 shows the operation of ports in accordance with another
• number of the B port dedicated bank, and the number of the shared bank can vary.
• FIG. 8 shows that two shared banks 804 and 806 are
• FIG. 9 shows that two A-port dedicated banks 900 and 902 are used.
• the command for modifying bank attributes can be also made through
• FIG. 7 shows the structure of a modified MRS
• the modified MRS command further includes a bank
• the bank attributes setting part includes information for setting whether each bank is an A-port dedicated bank, a B-port
• multi-port memory can access a shared bank at the same time to use the memory area of

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Citations (4)

• 2006
  • 2006-03-29 KR KR1020060028297A patent/KR100754359B1/ko active IP Right Grant
• 2007
  • 2007-03-29 WO PCT/KR2007/001543 patent/WO2007111492A1/en active Application Filing

Patent Citations (4)

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