WO2007107176A1

WO2007107176A1 - Method of reducing risk of delamination of a layer of a semiconductor device

Info

Publication number: WO2007107176A1
Application number: PCT/EP2006/004034
Authority: WO
Inventors: Kevin Cooper; Srdjan Kordic; Maurice Rivoire
Original assignee: Freescale Semiconductor, Inc.; St Microelectronics (Crolles 2) Sas
Priority date: 2006-03-17
Filing date: 2006-03-17
Publication date: 2007-09-27
Also published as: TW200802574A

Abstract

A method of minimizing de lamination of a layer (14, 16, or 18), the method includes providing a semiconductor substrate (12), forming a first layer (14) over the semiconductor substrate, wherein the first layer has a first corner (20) and the first corner has a first angle of approximately 90 degrees; forming a second layer (16) over the first layer, wherein the second layer has a second corner (20) and the second corner has a second angle of approximately 90 degrees, and modifying the first and second corners to form a first slanted edge (50, 60, or 70) of the first layer and a second slanted edge (50, 60, or 70) of the second layer, wherein the first slanted edge and the second slanted edge are continuous with each other and the first slanted edge forms a third angle with respect to the semiconductor substrate, wherein the third angle is less than 30 degrees.

Description

Title; METHOD OF REDUCING RISK OF DELAMINATON OF A LAYER OF A SEMICONDUCTOR DEVICE

Description Field of the invention

This invention relates generally to semiconductor devices, and more specifically, to minimizing delamination of a layer.

Background of the invention

Figure 1 illustrates a portion of a typical semiconductor stack 10 located near an edge 19 of a semiconductor substrate or wafer 12. The stack 10 includes a semiconductor substrate 12, a first dielectric layer 14 formed over the semiconductor substrate 12, a second dielectric layer 16 formed over the first dielectric layer 14, and a first conductive layer 18 formed over the second dielectric layer 16. Near the edge 19 of the semiconductor substrate, the second dielectric layer 16 and the first conductive layer 18 each have a corner or discontinuity 20 that is exposed. These corners 20 are created because portions of the first conductive layer 18 and the first and second dielectric layers 14 and 16 that are near the edge 19 of the semiconductor substrate 12 are removed after deposition of each layer to prevent particle generation.

Particles can be generated at the edge of the semiconductor wafer 12 in two instances. First, particles can be generated during thermal or mechanical stresses during processing because the wafer edge is rough and the layers weakly adhere to the semiconductor substrate 12 at the edge. Second, particles can be generated when the photoresist that is deposited over the semiconductor stack 10 is placed in a wafer carrier (e.g., FOUP). Thus, to prevent particle generation the photoresist is removed from the wafer edge. Subsequent dielectric etch steps remove portions of the underlying first and second dielectric layers 14 and 16 creating the corner 20 in the dielectric layers 14 and 16. The corner 20 in the conductive layer 18 is created in the similar fashion, or it is created when the edge of the layer 18 is removed using a directional chemical jet.

While particle generation may be decreased by removing portions of the first and second dielectric layer 14 and 16 and the first conductive layer 18, the corners 20 that are created may cause delamination at each interface 22, shown in Figure 2, during chemical mechanical planarization (CMP). CMP is a conventional process used in the semiconductor industry to planarize or remove a layer formed on a semiconductor substrate. With current technology the maximum shear force during CMP is found at the edge 19 of the wafer 12 and more specifically, at the corners 20. As shown in Figure 2, during CMP, the polishing pad 24 is placed in contact with the first conductive layer 18 and then the polishing pad 24 rotates relative to the wafer during the CMP process. During CMP the polishing pad 24 hangs over the corners 20. Because the maximum shear force is at the edge 19 of the wafer 12, delamination of the layers 14, 16, or 18 occurs at the interfaces 22 due to the presence of forces 26 and 28 during CMP. As the polishing time increases, more delamination occurs. The delamination is undesirable because it generates particles that can negatively impact the performance of the devices on the wafer 12. For example, the particles can scratch the first conductive layer 18 which is eventually forms the interconnect layers for the semiconductor device. If the first conductive layer 18 is scratched deep enough it may break the interconnect line. However, even if the first conductive layer 18 is not scratched to break the interconnect line, the scratches can create a point for electromigration to occur, which over time will cause the metal line 18 to break and fail electrically. Thus, the delamination is undesirable. Furthermore, the delamination is prominent when using low-k material and air gaps for the first dielectric layer 14, which are the desirable materials for this layer as technology advances. Thus, a need exists for minimizing the delamination that occurs when a CMP process is used.

Summary of the invention

The present invention provides a method of reducing risk of delamination and a method of and apparatus for producing a semiconductor device with reduced risk of delamination of a layer as described in the accompanying claims.

Brief description of the drawings

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Figure 1 illustrates a cross-sectional view of a prior art portion of a semiconductor stack having sharp corners that cause delamination.

Figure 2 illustrates a prior art polishing pad in contact with the semiconductor stack of Figure 1.

Figure 3 illustrates the stack of Figure 1 being polishing in accordance with an embodiment of the present invention given by way of example.

Figure 4 illustrates the resulting structure of the stack after processing in accordance with Figure 3 according to one. embodiment of the present invention given by way of example._.

Figure 5 illustrates the stack of Figure 1 being polished in accordance with an embodiment of the present invention given by way of example.

: Figure 6 illustrates the resulting structure of the stack after processing in accordance with Figure 5 according to one embodiment of the present invention given by way of example.

FIGs. 7-10 illustrate additional examples of polishing pads that can be used to modify the corners of the stack of Figure 1 in accordance with embodiments of the present invention given by way of example.

Figure 11 illustrates one embodiment for forming a semiconductor stack that is devoid of sharp corners given by way of example.

Figure 12 illustrates a tool used in one embodiment of the present invention for modifying the sharp corners of Figure 1 given by way of example.

Figure 13 illustrates the stack of Figure 1 being polished in accordance with an embodiment of the present invention given by way of example.

Figure 14 illustrates additional processing steps to form additional stacks without corners given by way of example.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention. Detailed description of the preferred embodiments

A method for minimizing delamination is described. As used herein, minimizing includes reducing or eliminating. Thus, delamination may be decreased or eliminated when minimizing delamination. And thus, the corners may be eliminated or reduced so that they no longer have an angle that is approximately 75 degrees or more with respect to the wafer surface, or in one embodiment approximately 90 degrees after being modified. In one embodiment, edge polishing or grinding is performed using a polishing pad that spins relative to the stack 10. By modifying the corners 20 using a process described, delamination is minimized allowing for integration schemes that use low-k materials and air gaps.

The semiconductor stack 10 is modified to reduce delamination. As. previously discussed, the semiconductor stack 10 includes a semiconductor substrate or wafer 12, a first dielectric layer 14 formed over the semiconductor substrate 12, a second dielectric layer 16 formed over the first dielectric layer 14, and a first conductive layer 18 formed over the second dielectric layer 16. The semiconductor substrate 12 can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI) (e.g., fully depleted SOI (FDSOI)), silicon, monocrystalline silicon, the like, and. combinations of the above. The first dielectric layer 14 can be any insulating material, such as silicon dioxide. In a preferred embodiment, the first dielectric layer 14 is a low-k material or an insulating material, such as a low-k material, with air gaps. The second dielectric layer 16 can be any insulating material, and may be the same material as the first dielectric layer 14, but preferably is a different dielectric material than the first dielectric layer 14. The second dielectric layer 16 is a cap that in one embodiment, may be an etch stop or polishing stop dielectric layer. In one embodiment, the first dielectric layer 14 is approximately 1000 to 20000 Angstroms of SiOF or SiOC, and the second dielectric layer 16 is approximately 100 to 5000 Angstroms of SiO2, SiC, SiCN, or SiN.

The first conductive layer 18 can be any metal or metal alloy. For example, the first conductive layer 18 may include aluminum, tungsten, or copper. In one embodiment, the first conductive layer 18 is a copper layer that will undergo additional processing to become the interconnect layer for the semiconductor device. In one embodiment, the first conductive layer 18 is approximately 500 to 50000 Angstroms of copper. The first conductive layer 18 and the second dielectric layer 16 have sharp corners 20. The sharp corners 20 make an approximately 75 or greater degree angle (or in one embodiment approximately 90 degrees) with the top surface of each layer and are not covered by other layers.

In one embodiment to modify the sharp corners 20 of the stack 10, edge polishing (which includes grinding) with a spinning polisher may be performed prior to performing conventional polishing. In one embodiment, the edge polishing rounds-off the sharp corners 20, thereby decreasing delamination during subsequent conventional polishing. Figure 3 illustrates one embodiment of a spinning polisher that may be used. In this embodiment, the polishing pad 30 of the spinning polisher is hour-glass shaped so that it is thinnest in the middle and thickest at the top and bottom. The middle portion is substantially curved and is where at least a portion of the stack 10 will contact the polishing pad 30. In one embodiment, the maximum curvature 31 of the polishing pad 30 is less than approximately 0.5mm, or more preferably less than approximately 0.35 mm. The thickness of the wafer is approximately 0.5 to 1 mm and the entire thickness of the wafer must be able to fit within the curved portion of the polishing pad 30 so the polishing pad 30 should have a maximum curvature less than V. of the thickness of the wafer 12. The curvature decreases farther away from the location of the polishing pad 30 with the maximum curvature. In one embodiment, the slope of slanted portions 33 of the polishing pad 30 is approximately 2, and the slanted ^; portions 33 have a length of approximately 1 to 15 mm.

The angle of contact between the stack and the polishing pad 30 may either be constant or change. In one embodiment, the angle between the polishing pad 30 and the stack progressively decreases towards the wafer during polishing.

In one embodiment, the polishing pad 30 spins, as shown by arrows 34, around an axis 32. Although the polishing pad 30 is shown to spin counter clockwise in Figure 3, a skilled artisan recognizes that only one direction is shown for illustration and that the polishing pad 30 may spin clockwise. In one embodiment, the relative motion of the polishing pad 30 with respect to the stack 10 is parallel to the edges of the first and second dielectric layers 14 and 16 and the first conductive layer 18, which are substantially perpendicular to the semiconductor substrate 12. As described above, the polishing pad 30 shown in Figure 3 is hour-glass shaped. However, if the polishing pad 30 itself does not spin, then only the portion of the polishing pad 30 that is in contact with the semiconductor wafer may have the curvature described above. Figure 4 shows the resulting structure of the stack 10 after using the polishing pad 30 to modify the corners 20. The corners 20 and edges of the layers have been removed and instead slanting sidewalls 50 are formed. The slanting sidewalls form an angle with the flat surface of the wafer 12 and this angle is less than 30 degrees. In one embodiment, the angle is less than approximately 5 degree or more preferably, between approximately 2 to 5 degrees. The semiconductor substrate 12 is not substantially polished during this process and therefore remains substantially the same as before this polishing process. Because all of the first and second dielectric layers 14 and 16 and first conductive layer 18 are polished with an hour-glass shaped polishing pad 30 as described above, the first dielectric layer 14 extends past the flat portion of the semiconductor substrate 12 to the curved portion or edge of the semiconductor substrate 12 and covers part of the edge of the semiconductor substrate 12. However, the layers formed over the first dielectric layer 14 do not extend as far as the first dielectric layer and instead, are deposed more towards the center of the wafer 12 than the first dielectric layer 14. However, unlike the prior art there are no sharp corners 20 that will generate a force sufficient to create delamination during polishing.

Figure 5 illustrates one embodiment of a spinning polisher that may be used. In Ihis embodiment, the polishing pad 40 of the spinning polisher is sloped on all sides so that it looks like a top that spins on its point. In one embodiment, the slope of the sides is approximately 2 and the length of each slope is approximately 5 to 50 mm. The slope and length are designed so that the polishing pad 40 will contact the corners 20 and polish them. The angle of contact between the stack and the polishing pad 30 may either be constant or change. In one embodiment, the angle between the polishing pad 30 and the stack progressively decreases towards the wafer during polishing.

In one embodiment, the polishing pad 40 spins, as shown by arrows 44, around an axis 42. Although the polishing pad 40 is shown to spin counter clockwise in Figure 5, a skilled artisan recognizes that only one direction is shown for illustration and that the polishing pad 40 may spin clockwise. In one embodiment, the relative motion of the polishing pad 40 with respect to the stack 10 is parallel to the edges of the first and second dielectric layers 14 and 16 and the first conductive layer 18. As described above, the polishing pad 40 shown in Figure 5 has slanted sides in all directions as to form a top or pyramid shape. However, if the polishing pad 40 itself does not spin, then only the portion of the polishing pad 40 that is in contact with the semiconductor wafer may be slanted. Figure 6 shows the resulting structure of the stack 10 after using the polishing pad 40. The corners 20 and edges of the layers have been removed and instead slanting sidewalls 60 are formed. Because the first and second dielectric layers 14 and 16 and the first conductive layer 18 are polished with the polishing pad 40 as described above, the slopes of the slanted portions of the first dielectric layer 14, the second dielectric layer 16, and the first conductive layer 18 are substantially the same. The slanting sidewalls form an angle with the flat surface of the wafer 12 and this angle is less than 30 degrees. In one embodiment, the angle is less than approximately 5 degree or more preferably, between approximately 2 to 5 degrees. The semiconductor substrate 12 is not substantially polished during this process and therefore remains substantially the same as before this polishing process. As shown in Figure 6, each layer is disposed closer to the center of the wafer then any underlying layer. However, unlike the prior art there are no sharp corners 20 that will create a force that is sufficient to create delamination during polishing. »

Figure 7 shows another embodiment of a spinning polisher that can be used to modify the corners 20. Polishing pad 52 is similar to the polishing pad 40 of Figure 5. In this embodiment, the polishing pad 52 is sloped where it contacts the stack 10. In one embodiment, the slope of the sides is approximately 2 and the length of each slope is approximately 5 to 50 mm. In one embodiment, the angle 53 is approximately 2 degrees.

The slope and length are designed so that the polishing pad 52 will contact the corners 20 and polish them. The angle of contact between the stack and the polishing pad 52 may either be constant or change. In one embodiment, the angle between the polishing pad 52 and the stack progressively decreases towards the wafer during polishing.

In one embodiment, the polishing pad 52 spins, as shown by arrow 54, around an axis 56. The polishing pad 52 differs from the polishing pad 40 of Figure 5 is that the polishing pad 52 spins about a horizontal axis 42, wherein the polishing pad 40 spins about a vertical axis 56. Although the polishing pad 52 is shown to spin counter clockwise in Figure 7, a skilled artisan recognizes that only one direction is shown for illustration and that the polishing pad 52 may spin clockwise. In one embodiment, the relative motion of the polishing pad 52 with respect to the stack 10 is parallel to the edges of the first and second dielectric layers 14 and 16 and the first conductive layer 18. After polishing using the polishing pad 52, the stack will appear like the stack in Figure 6. Figure 8 shows another embodiment of a spinning polisher that can be used to modify the corners 20. In this embodiment, the polishing pad 62 is curved so that the polishing pad 62 has a convex shape where it contacts the stack as opposed to the concave shape of the polishing pad 30 in Figure 4. The angle of contact between the stack and the polishing pad 62 may either be constant or change. In one embodiment, the angle between the polishing pad 62 and the stack progressively decreases towards the wafer during polishing.

In one embodiment, the polishing pad 62 spins, as shown by arrow 64, around an axis 66. The polishing pad 62 spins about the horizontal axis 62. Although the polishing pad 52 is shown to spin clockwise in Figure 8, a skilled artisan recognizes that only one direction is shown for illustration and that the polishing pad 62 may spin counter clockwise. In one embodiment, the relative motion of the polishing pad 52 with respect to the stack 10 is parallel to the edges of the first and second dielectric layers 14 and 16 and the first conductive layer 18. After polishing using the polishing pad 62, the stack will appear similar to the stack in Figure 6, but the slanted edges 60 will be concave formation when viewed at the edge of the wafer 12.

Figure 9 shows another embodiment of a spinning polisher that can be used to modify the corners 20. In this embodiment, the polishing pad 72 is curved so that the polishing pad has a convex shape where it contacts the stack as opposed to the concave shape of the polishing pad 30 in Figure 4. The angle of contact between the stack and the polishing pad 72 may either be constant or change. In one embodiment, the angle between the polishing pad 72 and the stack progressively decreases towards the wafer during polishing.

In one embodiment, the polishing pad 72 spins, as shown by arrow 74, around an axis 76. The polishing pad 72 differs from the polishing pad 62 of Figure 8 is that the polishing pad 72 spins about a vertical axis 42, wherein the polishing pad 62 spins about a horizontal axis 56. Thus, the polishing pad 72 also differs from the polishing pad 62 in that the polishing pad 72 has two curved portions so that the polishing pad 72 has the same shape when it contacts the stack as it spins. Although the polishing pad 72 is shown to spin counter clockwise, a skilled artisan recognizes that only one direction is shown for illustration and that the polishing pad 72 may spin clockwise. In one embodiment, the relative motion of the polishing pad 72 with respect to the stack 10 is parallel to the edges of the first and second dielectric layers 14 and 16 and the first conductive layer 18. After polishing using the polishing pad 72, the stack will appear similar to the stack that results from using the polishing pad 62 of Figure 8.

Figure 10 shows another embodiment of a spinning polisher that can be used to modify the corners 20. In this embodiment, the polishing pad 92 is sloped where it contacts the stack 10. In one embodiment, the slope of the sides is approximately 2 and the length of each slope is approximately 5 to 50 mm. In one embodiment, the angle 93 is approximately 2 degrees. The slope and length are designed so that the polishing pad 92 will contact the corners 20 and polish them. The angle of contact between the stack and the polishing pad 92 may either be constant or change. In one embodiment, the angle between the polishing pad 92 and the stack progressively decreases towards the wafer during polishing.

In one embodiment, the polishing pad 92 spins, as shown by arrow 94, around an axis 96. The polishing pad 92 differs from the polishing pad 52 of Figure 5 is that the polishing pad 92 spins about a vertical axis 96, wherein the polishing pad 52 spins about a horizontal axis 56. Thus, the polishing pad 92 also differs from the polishing pad 52 in that the polishing pad 92 has two identical end portions so that the polishing pad 92 has the same shape when it contacts the stack as it spins. Although the polishing pad 92 is shown to spin counter clockwise, a skilled artisan recognizes that only one direction is shown for illustration and that the polishing pad 92 may spin clockwise. In one embodiment, the relative motion of the polishing pad 92 with respect to the stack 10 is parallel to the edges of the first and second dielectric layers 14 and 16 and the first conductive layer 18. After polishing using the polishing pad 92, the stack will appear like the stack in Figure 6.

Shown in Figure 11 is another embodiment for forming slanted sides of the dielectric layers 14 and 16 and the first conductive layer 18. In this embodiment, the first and second dielectric layers 14 and 16 and the first conductive layer 18 are formed by over-edge deposition. First, the wafer edge is polished before any other processing begins to smooth the edge. In subsequent processing it is desirable to use only electrostatic chucks so the edge of the wafer is not damages. For example, clamps should be avoided. Next, the dielectric layers 14 and 16 are deposited. During the depositions shields should not be used that cover a part of the wafer so that the dielectric layers 14 and 16 wrap around the edge of the semiconductor wafer. Next, the first conductive layer 18 is formed. In one embodiment, the conductive layer 18 includes a stack formed by sequential depositions of copper barrier layer, such as Ta, TaN, or TiN, and a copper seed layer. These two layers are may be deposited using physical vapor deposition (PVD) techniques, but in some cases, chemical vapor deposition (CVD) techniques can be used. The final conductive layer of copper may be deposited by electrochemical deposition (ECD). These conductive layers are deposited over the edge of the semiconductor wafer. Furthermore, in this process portions of the subsequent photoresist layers at the edge of the semiconductor wafer are not removed. Typically, the photoresist is removed to prevent particle generation when the wafer is put into the FOUP, as previously discussed. Thus, to prevent particle generation, the semiconductor wafer should not touch the edge of the FOUP. In one embodiment, this is done by putting suction cups on the bottom side of the wafer, especially near the center of the wafer. This processing results in rounded off edges of the dielectric layers 14 and 16 and the first conductive layer 18. This is desirable because sharp corners are avoided; the flatter the corners the better.

Although as described above the corners 20 are rounded using the polishing pad 30, the corners 20 may optionally be etched first and then polished using the polishing pad 30. In one embodiment, the corners 20 are removed by plasma etching or using a fluid jet as shown in Figure 12 and then subsequently polished. Alternatively, either the etching or polishing processes may be skipped. As shown in Figure 12, a semiconductor wafer 80 moves relative to the plasma or fluid 86, depending on whether an etch or fluid jet process is used, as shown by the arrow 82. Although the arrow 82 shows the semiconductor wafer 80 moving counterclockwise relative to the plasma or fluid 86, this is for illustration purposes only and the semiconductor wafer 80 may move clockwise relative to the plasma or fluid 86. The plasma or fluid, in one embodiment, is formed or dispersed, respectively by elements 84. (Although two elements 84 are shown in Figure 12 only one may be needed.)

Figure 13 illustrates another embodiment of a spining polisher where the wafer edge is polished using a rotating cylindrical pad 41. Here the rotational direction 39 of the pad is counterclockwise so that the interfaces are compressively stressed reducing the probability of delamination. The axis of rotation is in the direciton that goes in and out of the paper. The radius of the cylinder can range between 5 and 50 mm, and the cylinder can be 10 to 100 mm long. As shown in Figure 13, the length of the cyclindrical pad 41 is in the dirction that goes in and out of the paper.

In all embodiments it is also desirable to rotate the wafer during the polishing of the wafer edge. The wafer is rotated in its plane. After modifying the corners 20, which is one embodiment, occurs by removal of the corners 20 and in another embodiment occurs by slanting the corners 20, the first conductive layer 18 can be planarized. In one embodiment, the first conductive layer 18 is planarized by bringing a polishing pad in contact with the first conductive layer 18 and rotating the semiconductor wafer 12 relative to the polishing pad. Since the corners 20 are modified the maximum shear force should not occur at the edge of the wafer and cause delamination of the dielectric layers 14 and 16 and the first conductive layer 18. In one embodiment, the polishing is performed by using a soft pad, low pressure, a chemistry that reduces friction, or combinations of the above. In one embodiment, the soft pad has a Young's modulus between approximately 5 to 50 MPa. In one embodiment, the low pressure is a pressure between approximately 0.1 psi to 5 psi. In one embodiment, the chemistry is like soap because it decreases friction. The chemistry may include a surfactant, inhibitor, a long carbon chain molecule (such as PEG), the like, or a combination of the above. In one embodiment to remove the first and second dielectric layers 14 and 16, KOH, HF, or an ammonia based solution is used with silica abrasives, or polymer abrasives, or composite abrasives like polymer particles coated with silica or alumina, and for the first conductive layer 18, an acid with silica or alumina is used. In another embodiment, a nonselective slurry is used to remove the first and second dielectric layers 14 and 16, and the first conductive layer 18. For example, a nonselective slurry such as CuS 1351 from Rohm and Haas may be used.

After polishing the first conductive layer 18, a third dielectric layer, a fourth dielectric layer, and another metal layer are formed like the first dielectric layer, the second dielectric layer, and a second conductive layer, respectively. These new layers will probably form sharp corners like the underlying layers and any of the above processes can be used to modify the sharp corners of these new layers. This process is repeated until the desired number of metal layers (and underlying dielectric layers) is formed. An example is shown in Figure 14 where a third dielectric layer 100, which can have any of the characteristics of the first dielectric layer 14, the fourth dielectric layer 102, which can have any of the characteristics of the second dielectric layer 16, and a second conductive layer 104, which can have any of the characteristics of the first conductive layer 18, are formed and modified to create slanted edges 106 that are continuous with each other and the first slanted edge forms an angle with respect to the semiconductor substrate that is less than 30 degrees. The slanted edges 106 of the first and second dielectric layers 14 and 16 and the first conductive layer 18 may or may .

not be continuous with the slanted edges 50 of the third and fourth dielectric layers 100 and 102 and the second conductive layer 104.

In one embodiment, a method of minimizing delamination of a layer includes providing a semiconductor substrate, forming a first layer over the semiconductor substrate, wherein the first layer has a first corner and the first corner has a first angle of approximately 90 degrees, forming a second layer over the first layer, wherein the second layer has a second corner and the second corner has a second angle of approximately 90 degrees, and modifying the first and second corners to form a first slanted edge of the first layer and a second slanted edge of the second layer, wherein the first slanted edge and the second slanted edge are continuous with each other and the first slanted edge forms a third angle with respect to the semiconductor substrate, wherein the third angle is less than 30 degrees. In one embodiment, the third angle is less than 5 degrees. In one embodiment, the method further includes polishing the second layer to remove portions of the second layer, wherein the second layer includes a metal, to form interconnects, forming a third layer over the second layer, wherein the third layer has a third corner and the third corner has a fourth angle of approximately 90 degrees, forming a fourth layer over the third layer, wherein the fourth layer has a fourth corner and the fourth corner has a fifth angle that is approximately 90 degrees, and modifying the third and fourth corners to form a third slanted edge of the third layer and a fourth slanted edge of the fourth layer, wherein the third slanted edge and the fourth slanted edge or continuous with each other and the first slanted edge forms an angle with respect to the semiconductor substrate that is less than 30 degrees. In one embodiment, modifying includes removing the first and second corners. In some embodiments, modifying includes performing a titled plasma etch. In some embodiments, modifying includes spraying the first and second corners using a fluid chemical jet. In some embodiments, modifying the first and second corners includes polishing the first and second corners, wherein the polishing pad rotates along an axis that is perpendicular to the semiconductor substrate. In one embodiment, the polishing pad has a radius of curvature that is greater than 0.35 mm. In some embodiments, the polishing pad is at a fourth angle with respect to the semiconductor substrate when polishing begins and the polishing pad is at a fifth angle with respect to the semiconductor substrate when polishing ends, wherein the fifth angle is less than the first angle. In some embodiments, modifying further includes polishing using a parameter selected from the group consisting of:a pad having a Young's modulus between 5 to 50 Mpa, a pressure between 0.1 to 5 PSI, and a friction reducing slurry. In one embodiment, a method of minimizing delamination of a layer, the method comprising:

providing a semiconductor substrate, forming a first layer over the semiconductor substrate, wherein the first layer has a first corner and the first corner has a first angle of approximately 90 degrees, forming a second layer over the first layer, wherein the second layer has a second corner and the second corner has a second angle of approximately 90 degrees, and modifying the first and second corners to form a first slanted edge of the first layer and a second slanted edge of the second layer without modifying the semiconductor substrate.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the first conductive layer 18 may include a barrier layer. The barrier layer, for example, may be TaN, Ta, or TiN. Furthermore, although the polishing pads in FIGs. 3, 5, and 7-10 are shown to spin around an axis, in other embodiments, the polishing pads do not spin and the wafer instead spins, or both the polishing pad and the wafer spin. Regardless, the polishing pads in FIGs. 3, 5, and 7-10 spin relative to the wafer. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "a" or "an", as used herein, are defined as one or more than one. Moreover, the terms "front", "back", "top", "bottom", "over", "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orieniations than those illustrated or otherwise described herein.

Claims

1. A method of reducing risk of de lamination of a layer (14, 16, 18) of a semiconductor device, the method comprising: providing a semiconductor substrate (12); forming a first layer (14) over the semiconductor substrate, wherein the first layer has a first corner (20) and the first corner has a first angle of approximately 90 degrees; . forming a second layer (16) over the first layer, wherein the second layer has a second corner (20) and the second corner has a second angle of approximately 90 degrees; characterized by modifying the first and second corners to form a first slanted edge (50, 60, 70) of the first layer and a second slanted edge (50, 60, 70) of the second layer, wherein the first slanted edge and the second slanted edge are continuous with each other and the first slanted edge forms a third angle with respect to the semiconductor substrate (12), wherein the third angle is less than 30 degrees.

2. The method of claim 1, further comprising: polishing the second layer (16) to remove portions of the second layer, wherein the second layer comprises a metal, to form interconnects; forming a third layer (18) over the second layer (16), wherein the third layer has a third corner and the third corner has a fourth angle of approximately 90 degrees; forming a fourth layer (100) over the third layer (18), wherein the fourth layer has a fourth corner and the fourth corner has a fifth angle that is approximately 90 degrees; and modifying the third and fourth corners to form a third slanted edge of the third layer (50) and a fourth slanted edge (106) of the fourth layer, wherein the third slanted edge and the fourth slanted edge are continuous with each other and the first slanted edge (50, 60, 70) forms an angle with respect to the semiconductor substrate that is less than 30 degrees.

3. The method of claim 1 or 2, wherein modifying comprises removing the first and second corners.

4. The method of any of claims 1 to 3, wherein modifying comprises performing a titled plasma etch.

5. The method of any of claims 1 to 3, wherein modifying comprises spraying the first and second corners using a fluid chemical jet.

6. The method of any of claims 1 to 3, wherein modifying the first and second corners comprises polishing the first and second corners, wherein a polishing pad rotates along an axis that is perpendicular to the semiconductor substrate.

7. The method of claim 6, wherein the polishing pad has a radius of curvature lhat is greater than 0.35 mm.

8. The method of claim 6 or 7, wherein the polishing pad is at a fourth angle with respect to the semiconductor substrate when polishing begins and the polishing pad is at a fifth angle with respect to the semiconductor substrate when polishing ends, wherein the fifth angle is less than the first angle.

9. The method of claim 6, 7, or 8, wherein modifying further comprises polishing using a parameter selected from the group consisting of: a pad having a Young's modulus between 5 to 50 MPa; a pressure between 0.1 to 5 PSI; and a friction reducing slurry.

10. A method of reducing risk of delamination of a layer, the method comprising: providing a semiconductor substrate; forming a first layer (14) over the semiconductor substrate, wherein the first layer has a first corner (20) and the first corner has a first angle of approximately 90 degrees; forming a second layer (16) over the first layer, wherein the second layer has a second corner (20) and the second corner has a second angle of approximately 90 degrees; characterized by modifying the first and second corners to form a first slanted edge (50, 60, 70) of the first layer and a second slanted edge (50, 60, 70) of the second layer without modifying the semiconductor substrate (12).

11. A method of producing a semiconductor device including reducing risk of delamination of a layer by the method of any preceding claim.

12. Apparatus for use in producing a semiconductor device with reduced risk of delamination of a layer by the method of claim 11 and including means for performing the step of modifying the first and second corners to form a first slanted edge (50, 60, 70) of the first layer and a second slanted edge (50, 60, 70) of the second layer.