WO2007080696A1 - High-frequency power supply device - Google Patents

High-frequency power supply device Download PDF

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Publication number
WO2007080696A1
WO2007080696A1 PCT/JP2006/322256 JP2006322256W WO2007080696A1 WO 2007080696 A1 WO2007080696 A1 WO 2007080696A1 JP 2006322256 W JP2006322256 W JP 2006322256W WO 2007080696 A1 WO2007080696 A1 WO 2007080696A1
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WIPO (PCT)
Prior art keywords
signal
square wave
circuit
output
control
Prior art date
Application number
PCT/JP2006/322256
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French (fr)
Japanese (ja)
Inventor
Tadashi Honda
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Advanced Design Corp.
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Filing date
Publication date
Application filed by Advanced Design Corp. filed Critical Advanced Design Corp.
Publication of WO2007080696A1 publication Critical patent/WO2007080696A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32174—Circuits specially adapted for controlling the RF discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge

Definitions

  • the present invention relates to a high frequency power supply device for supplying high frequency power to a plasma generator or the like.
  • a square wave oscillating unit (1) has a rectangular shape with a predetermined frequency (eg, 13.56 MHz).
  • the wave train is oscillated, and the waveform shaping unit (2) generates a square wave train of the predetermined frequency and power required by the power amplification unit (3).
  • the duty 1: 1 square wave train generated in (2) the required high-frequency power is generated in the power amplification unit in (3).
  • a DC voltage corresponding to the required power is supplied from the DC power supply section (4).
  • the filter in (8) is for removing unnecessary frequency components other than the fundamental wave component in the output.
  • the present invention has been made paying attention to such problems, and an object of the present invention is to provide a high-frequency power supply device capable of performing high-speed adjustment control of output power in these high-frequency power supply devices.
  • the high frequency power supply device includes a basic drive square wave generating unit that generates a basic drive square wave having an output frequency of high frequency power to be output, and an output A signal width variable means for varying a signal width within one cycle of the basic drive square wave generated by the basic drive square wave generation means based on a control signal for controlling power, and the signal width variable means And amplifying means for amplifying the amplification source signal whose signal width is adjusted based on the control signal.
  • the basic drive square wave is generated based on the control signal by the signal width varying means.
  • a high frequency power supply device according to claim 2 of the present invention is the high frequency power supply device according to claim 1,
  • the signal width variable means generates a control square wave having a frequency and waveform substantially the same as the basic drive square wave, and the basic drive square wave of the control square wave.
  • a high-frequency power supply device is the high-frequency power supply device according to claim 2,
  • the phase shift control circuit generates a control signal for generating the control square wave and a PLL circuit including a phase comparator for synchronizing the phases of the basic drive square wave and the control square wave
  • the voltage controlled oscillator includes a noise voltage application circuit that applies a bias voltage to the control voltage applied from the PLL circuit.
  • the phase shift control circuit can be configured simply by adding a bias voltage application circuit to a PLL circuit including a phase comparator in which many devices normally exist.
  • a phase shift control circuit having a simple structure and good accuracy can be obtained.
  • a high frequency power supply device is the high frequency power supply device according to claim 1,
  • the signal width varying means is
  • a differential signal generation circuit section for generating a differential signal of a leading edge or a trailing edge of the basic driving square wave
  • the first inverter that starts the inverted output of the input signal triggered by the input of the generated differential signal, and the first inverter that inverts the output signal from the first inverter and inputs it to the first inverter. 2 and the input of the output signal output from the second inverter to the first inverter at a time determined by a time constant changed according to the control signal !,
  • a signal width control circuit having a time constant circuit part that continues inversion, and a vibrator circuit part having
  • the high frequency power supply device according to claim 5 of the present invention is the high frequency power supply device according to claim 4,
  • the first inverter is formed by a multi-input transformation logic gate circuit. It is said.
  • the first inverter can be formed by using a multi-input transformation logic gate circuit such as a NAND gate that can operate at a higher speed than a general MSI multi-noiser.
  • a multi-input transformation logic gate circuit such as a NAND gate that can operate at a higher speed than a general MSI multi-noiser.
  • a square wave signal with a short signal width can be generated, and the range of controllable output power can be increased.
  • a high frequency power supply device is the high frequency power supply device according to claim 4 or 5
  • the signal width varying means receives an output signal from the vibrator circuit unit and the basic driving square wave, and cuts out an input basic driving square wave based on the input output signal of the vibrator circuit unit force.
  • the amplification means amplifies an output signal from the logic gate circuit as the amplification source signal.
  • a high frequency power supply device is the high frequency power supply device according to claim 6,
  • It includes a delay circuit for delaying a basic driving square wave input to the logic gate circuit by a signal propagation delay time in the first inverter.
  • FIG. 1 is a circuit configuration diagram showing a configuration of a high frequency power supply circuit according to Embodiment 1 of the present invention.
  • FIG. 2 (a) and (b) are explanatory diagrams showing the state of generation of an amplification source signal in the high frequency power supply circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a circuit configuration diagram showing an embodiment of a high frequency power supply circuit according to the present invention.
  • FIG. 4 (a) to (e) are charts showing timings of various signals in the high-frequency power circuit of the embodiment of FIG.
  • FIG. 5 is a diagram showing a configuration of a high frequency power supply circuit in an example of the present invention.
  • FIG. 6 is a circuit configuration diagram showing another type of high-frequency power supply circuit.
  • FIG. 7 is a diagram showing a configuration of a conventional power supply circuit.
  • FIG. 8 is a diagram showing a configuration of a high-frequency power supply circuit in another form.
  • FIG. 9 is a diagram showing a configuration of a high-frequency power supply circuit in another form.
  • FIG. 10 is a diagram showing an oscilloscope measurement screen for measuring the control speed of the high-frequency power circuit in the embodiment of the present invention.
  • FIG. 11 is a diagram showing a measurement screen of an oscilloscope that measures the control speed of a conventional power supply circuit.
  • FIG. 1 is a circuit configuration diagram of a high frequency power supply circuit used in the high frequency power supply apparatus of the present embodiment.
  • the high-frequency power supply circuit of this embodiment is a basic drive square which is a square wave having a duty ratio of about 50% and the same frequency as the output frequency output from the high-frequency power supply circuit.
  • Basic drive square wave generating circuit unit 5 for generating a wave, and a control square wave for generating a control square wave having the same frequency and waveform as the basic drive square wave generated in the basic drive square wave generation circuit unit
  • AND gate circuit 31 which is a logic gate circuit in the present invention to which the control square wave generated by control square wave generation circuit unit 3 4 is input, and an amplification source signal output from AND gate circuit 31
  • Class E amplifier 32 which is a switching amplifier circuit.
  • the basic drive square wave generation circuit unit 5 of the present embodiment includes a basic operation signal generator 1, a double frequency generation circuit 2, a waveform shaping circuit 3, and a frequency division generation circuit. It consists of four.
  • the basic operation signal generator 1 outputs a high frequency output from a high frequency power supply circuit, for example, a 13.56MHz high frequency signal if the frequency of the high frequency output is 13.56MHz.
  • the basic drive signal which is a high-frequency signal oscillated by this basic operation signal generator 1, which is sufficient if a powerful oscillator (oscillator) is used, is set to a double frequency of 27.12 MHz by a known double-frequency circuit. .
  • the basic drive signal of 27.12 MHz which is twice the frequency, is amplified by an amplifying transistor (not shown) and then supplied to the waveform shaping circuit 3 to form a 27.12 MHz square. Shaped into waves.
  • a square wave generating circuit usually used in a digital circuit or the like, specifically, a circuit using inverters in multiple stages (for example, two stages) can be suitably used.
  • the basic drive signal converted into a square wave of 27.12 MHz, which is twice the frequency in the waveform shaping circuit 3, is supplied to, for example, the frequency dividing circuit 4 having a pulse counter equal power and divided by two. It is converted into a certain 13.56MHz square wave and a 3.39MHz square wave that is divided by 8.
  • the control square wave generation circuit unit 34 of the present embodiment includes a voltage control oscillator (VCO) 26, a waveform shaping circuit 27, and a frequency division generation circuit 28. Composed.
  • This voltage control oscillator (VCO) 26 may be any one that can oscillate a signal in a predetermined range including a 27.12 MHz signal that is twice the frequency of the basic drive signal described above according to the control voltage.
  • the amplitude of the 27.12 MHz signal oscillated by the voltage controlled oscillator (VCO) 26 was appropriately amplified by an amplifying transistor (not shown) in the same manner as the basic drive square wave generation circuit unit 5 described above. After that, it is supplied to the waveform shaping circuit 27 and shaped into a square wave.
  • these waveform shaping circuits 27 a circuit similar to the waveform shaping circuit 3 described above, specifically, an inverter used in multiple stages (for example, two stages) can be suitably used.
  • the control signal converted into a 27.12 MHz square wave in these waveform shaping circuits 27 is supplied to a frequency dividing circuit 28 such as a pulse counter, for example. It is converted into a square wave and a 3.39 MHz square wave that is divided by 8. [0025] It should be noted that these square waves are also generated based on the double-frequency square wave, and as shown in Fig. 2, a control square wave (13.56MHz) whose square duty ratio is about 50% is obtained. ) And supplied to the AND gate circuit 31. 3. A 39 MHz square wave is input to the PLL circuit 30 described later as a phase comparison square wave.
  • the phase shift control circuit unit 35 of the present embodiment includes each of the phase comparison squares from the basic drive square wave generation circuit unit 5 and the control square wave generation circuit unit 34 described above. Including a phase comparator that compares the phase of the basic driving square wave and the control square wave based on the input phase comparison square wave, and synchronizes the phase of both of them. And a bias voltage corresponding to the output control input is applied to the control voltage signal applied from the PLL circuit 30 to the voltage control oscillator (VCO) 26 of the control square wave generating circuit section 34. And a bias voltage applying circuit 29.
  • VCO voltage control oscillator
  • each phase comparison square wave from the basic drive square wave generation circuit unit 5 and the control square wave generation circuit unit 34 described above in the phase comparator in the PLL circuit 30 ( 3.39MHz) phase is compared and the control voltage signal is applied to the voltage controlled oscillator (VCO) 26 after it is amplified appropriately so that the phase is synchronized, that is, the phase is eliminated.
  • VCO voltage controlled oscillator
  • both phase comparison square waves are synchronized.
  • the basic drive square wave having these phases synchronized is synchronized. 1 and the control square wave are input to the AND gate circuit 31 as shown in FIG.
  • Amplification source signal with 13.56MHz square wave The signal is output from the AND gate circuit 31 to the class E amplifier 12, amplified, and output as a 13.56 MHz pulse output or a sine wave output by passing the pulse output through the low-pass filter 33.
  • the bias voltage application circuit 29 is output from the PLL circuit 30.
  • a circuit that increases or decreases the bias voltage applied to the control voltage signal using a variable resistor can be used.When the resistance value by these variable resistors is changed to increase the bias voltage applied to the control voltage signal, These bias voltages Control is performed so that a phase difference is generated between the basic driving square wave and the control square wave, in which the voltage necessary to cancel these bias voltages is generated. The phase of the square wave is shifted.
  • FIG. 2 (b) As shown in Fig. 2, there is no overlap between both the control square wave and the basic drive square wave, so there is no pulse output from the AND gate circuit 31, and there is no signal that is the amplification source in the class E amplifier 32. Therefore, the output is almost reduced to “0”.
  • the half cycle of the output frequency can be achieved. Since an amplification source signal having a short signal width is generated and the amplification source signal is amplified by the class E amplifier 32, even if the output frequency is high, the amplification source signal can be generated with a simple configuration.
  • the signal width can be changed according to the control signal, so the output power from the high-frequency power circuit amplified by the class E amplifier 32 can be adjusted quickly with a simple configuration. Similar to the circuit of the embodiment described later shown in FIG. 10, it can be controlled with an accuracy of about several hundred nanoseconds.
  • the phase shift control circuit includes a phase comparator for synchronizing the phases of the basic drive square wave and the control square wave. 10 and a bias voltage application circuit 9 that applies a bias voltage to the control voltage applied from the PLL circuit 10 to the voltage controlled oscillator 6 that generates a control signal for generating the control square wave.
  • a phase shift control circuit can be configured simply by adding a bias voltage application circuit to a PLL circuit including a phase comparator with a phase shifter, the degree of freedom in circuit design is improved and a phase with good accuracy with a simple configuration. A shift control circuit can be obtained.
  • the high frequency power supply circuit As shown in FIG. 3, the high frequency power supply circuit according to the second embodiment generates a basic drive square wave that is a square wave with a duty ratio of about 50% having the same frequency as the output frequency output from the high frequency power supply circuit.
  • the first inverter 10 to which the leading edge differential signal generated in Step 1 is input, and the output signals from the second inverter 11 and the second inverter 11 that invert the output signal from the first inverter 10 are the first output.
  • the basic driving square wave generated by the monostable multivibrator 15 including the time constant circuit unit 12 for variably controlling the time input to the inverter 10 and the basic driving square wave generation circuit unit 5 , Delay time delayed by the signal propagation delay time in the first inverter 10 Unit 13, AND gate circuit 14 which is a logic gate circuit in the present invention to which the basic driving square wave delayed in delay circuit unit 13 and the output signal from first inverter 10 are input, and A It comprises a class E amplifier 6 which is a switching amplifier circuit section in the present invention for amplifying the amplification source signal output from the ND gate circuit 14.
  • the basic drive square wave generation circuit unit 5 of the present embodiment is the same as the basic drive square wave generation circuit unit 5 of the first embodiment, and includes a basic operation signal generator 1 and a double frequency generation circuit 2. And a waveform shaping circuit 3 and a frequency division generation circuit 4.
  • the basic operation signal generator 1 a high-frequency output output from a high-frequency power supply circuit, specifically, an oscillator (oscillator) that outputs a 13.56 MHz high-frequency signal if the output frequency is 13.56 MHz is used.
  • the basic drive signal which is a high-frequency signal oscillated by the basic operation signal generator 1, is once set to a double frequency of 27.12 MHz by a known double-frequency circuit.
  • the basic drive signal of 27.12 MHz which is twice the frequency, is appropriately amplified by an amplifying transistor (not shown) and then supplied to the waveform shaping circuit 3, It is shaped into a 27.12MHz square wave.
  • the basic drive signal converted into a square wave of 27.12 MHz, which is twice the frequency in the waveform shaping circuit 3, is supplied to, for example, a frequency division generation circuit 4 having a pulse counter equal power, and the output frequency depends on the output frequency.
  • a 13.56 MHz square wave divided by 2 and a 3.39 MHz square wave divided by 8 are generated.
  • 13.56 MHz which is divided by two, is used to set the output frequency to 13.56 MHz.
  • the square wave generated by the basic drive square wave generation circuit unit 5 in this way is generated based on the double-frequency square wave, so that its duty ratio is approximately as shown in FIG.
  • the basic drive square wave (13.56 MHz) is a 50% square wave, one of which is supplied to the AND gate circuit 14 via the delay circuit section 13, and the other is supplied to the differentiation circuit section 9 and its leading edge derivative Used as a trigger signal for monostable multivibrator 15
  • a control signal for controlling the output power is input to the time constant circuit unit 12, and the time constant is changed according to the control signal. Therefore, when a control signal for reducing the output power is input, a signal with a short pulse width is output to the AND gate circuit 14 due to the time constant being reduced, and the output power is increased. When a control signal is input, a signal having a long pulse width is output to the AND gate circuit 14 by increasing the time constant.
  • the monostable multivibrator 15 is a force in which two inverters are AC-DC coupled.
  • the first inverter 10 used here is a half of the high frequency output frequency. If the output frequency is 13.56 MHz, as shown in Figure 4, one period is 7 3.7 nanoseconds, so the pulse width (signal) is shorter than the half period, which is about 36.8 nanoseconds.
  • the first inverter 10 is an NAND circuit circuit IC as shown in FIG. 5 in an embodiment to be described later as an actual circuit. Is used as an inverter.
  • a square wave with a shorter and more accurate pulse width can be output and formed by the NAND gate circuit IC.
  • the basic drive square wave is cut out in the AND gate circuit 14 (IC in FIG. 5) by the pulse width (signal width) output from the first inverter 10 and used as the amplification source signal.
  • a NAND gate circuit IC is used as the first inverter 10.
  • the present invention is not limited to this, and an inverter capable of high-speed operation with other configurations may be used.
  • the second inverter 11 only inverts the output of the first inverter 10, so that the second inverter 11 can operate at an output frequency level with a small relative propagation delay. Good.
  • the time constant circuit section 12 constituting the monostable multivibrator 15 is a time constant composed of a capacitor (C) and a variable resistor (R) that are normally used as a time constant circuit section.
  • C capacitor
  • R variable resistor
  • the time constant circuit using these capacitors (C) and variable resistors (R) is difficult to implement stable continuous control in which the time constant easily changes over time.
  • FET field effect transistor
  • the grounding of R in Fig. 3 is a high-frequency grounding.
  • FIG. 3 As shown in (a), a basic drive square wave (13.56 MHz) with a duty ratio of about 50% is generated.
  • the generated basic driving square wave is input to the differentiating circuit unit 9 to be converted into a leading edge differential signal in which only the leading edge is extracted as shown in FIG. 4 (b).
  • the leading edge differential signal is input to the first inverter 10 as a trigger signal.
  • the first inverter 10 starts signal output triggered by the input of the leading edge differential signal from the differentiation circuit unit 9, and the inverted output of the signal output by the second inverter 11 is the time constant circuit unit 12 When the signal is input to the first inverter 10 after the period based on the time constant set in The signal output is terminated at.
  • the first inverter 10 is triggered by the input time of the leading edge differential signal, and according to the period based on the time constant set in the time constant circuit unit 12. Outputs a pulse width (signal width) signal.
  • the signal propagation delay time in the first inverter 10 is close to one cycle time of the output frequency or longer (larger) than one cycle time
  • the length (size) of the minimum pulse width (signal width) that can be output is close to one cycle time of the output frequency, it depends on the signal width within the same cycle of the basic drive square wave. Since the output control becomes difficult, these first inverters 10 serving as the square wave signal generator in the present invention have the signal propagation delay time of at least two logic gates of one cycle time of the output frequency, and the one cycle. It is preferable to output a square wave signal with a signal width of at least half the time.
  • the AND gate circuit 14 by using the AND gate circuit 14 to cut out from the basic drive square wave, an excessive time constant (reverse duty ratio) as shown by the wavy line in FIG. 4 is prevented.
  • This is preferable because it is possible to avoid the occurrence of inconveniences such as equipment damage due to the reverse of the control force due to the reverse of the signal width.
  • the output signal from the first inverter 10 using the AND gate circuit 14 is not limited to this, and the output signal from the first inverter 10 may be directly input to the class E amplifier 6 as an amplification source signal. In this case, the delay circuit unit 13 can be omitted.
  • FIG. 5 is a circuit diagram showing a circuit actually manufactured.
  • the NAND circuit IC is used as the first inverter 10 and the time constant circuit unit 12 is as follows.
  • capacitor C1 With capacitor C1
  • the inverting circuit IC is for reshaping the input basic drive square wave, and the basic drive square wave has an adverse effect on the propagation path of the input basic drive square wave. Do not take it if you want.
  • the differentiation circuit unit 9 is composed of R, R, and C, and the R side is Vd.
  • leading edge differential signal is actually set to ⁇ 0 '' when the input 1 of the NAND gate circuit IC is in the LOW state.
  • a time constant is needed to keep “0” in the LOW state until it becomes.
  • IC to IC are delay devices, and the delay circuit section 13 is formed by the IC to IC.
  • the IC corresponds to the second inverter 11 and the IC is an AND gate circuit 14.
  • the leading edge differential signal is NAND gate circuit with the voltage signal applied to the gate of FETQ as the control signal.
  • FET field effect transistor
  • a NAND gate circuit IC is used as the first inverter 10.
  • Input 2 connected to the differential circuit section 9 consisting of R, R and C is the leading edge differential signal.
  • the signal is not output, “1” which is in the HIGH state is input, and the other input 1 is also in the HIGH state by being connected to Vd via the field effect transistor (FET ⁇ i ⁇ ). Since “1” is input, the output of the NAND gate circuit IC is in the LOW state.
  • the NAND gate circuit IC power is also slightly less than the leading edge
  • a square wave signal having a signal width within a period corresponding to a half cycle of 13.56 MHz, which is the output frequency, set in the time constant circuit unit 12 is output.
  • the first inverter 10 formed by the NAND gate circuit IC is
  • the time constant circuit unit 12 of the monostable multivibrator 15 configured by a field effect transistor (FET) Q or the like constitutes the first inverter 10 which is a square wave signal generator in the present invention.
  • NAND gate circuit that outputs the power of the pulse width (signal width) that is also output
  • the time constant circuit unit 12 corresponds to the signal width control circuit in the present invention.
  • the NAND gate circuit IC power that is variable according to the control signal is also output.
  • the pulse width is half the pulse width (signal width)
  • an amplification source signal having a pulse width that is approximately half (50%) the pulse width (signal width) of the basic drive square wave is transferred from the AND gate circuit 14 to the class E amplifier 6
  • the output is narrowed down and amplified, and the NAND gate circuit IC power is also output.
  • the pulse width (signal width) is also 1% of the pulse width (signal width) of the basic driving square wave.
  • an amplification source signal having a pulse width of approximately 1Z3 (33%) of the pulse width (signal width) of the basic drive square wave is output to the E-class amplifier 6 and amplified by 14 AND gate circuits. As a result, the output force S is reduced.
  • the control square wave generating circuit unit 34, the phase shift control circuit unit 35, and the AND gate circuit 31 are used as the signal width varying means.
  • the monostable multivibrator 15 and the AND gate circuit 14 by using the monostable multivibrator 15 and the AND gate circuit 14, an amplification source signal having a signal width shorter than a half cycle of the output frequency is generated, and the amplification source signal power is reduced. Since the signal is amplified by the class amplifier 6, even if the output frequency is high, the signal width of the amplification source signal can be changed according to the control signal with a simple configuration. Adjustment of the output power from the amplified high frequency power supply circuit can be controlled with a simple configuration at a high speed in time, specifically, with an accuracy of about 200 nanoseconds as shown in FIG.
  • the signal width control circuit is connected to the second inverter and the time constant circuit unit 12 by using a DC-AC coupled monostable vibrator as the noise circuit unit. Therefore, it is possible to obtain a vibrator circuit unit having good accuracy with a simple configuration as well as improving the degree of freedom in circuit design.
  • the first inverter 10 is formed by using a NAND gate circuit IC that can operate at a higher speed than a general MSI multivibrator, so that it is shorter.
  • a square wave signal with a signal width can be generated, and the range of output power that can be controlled can be increased.
  • the signal of the amplification source signal It is possible to prevent the width from being reversed, and it is possible to prevent the occurrence of a failure due to the reverse of these signal widths (reverse duty).
  • the signal width of the amplification source signal cut out by the NAND gate circuit 14 serving as the logic gate circuit is equal to the signal propagation delay time. The inconvenience of shortening can be avoided.
  • the time constant is unlikely to fluctuate greatly with time.
  • Stable continuous control can be implemented by the input control signal.
  • the basic drive square wave is generated using the double frequency, and therefore, the basic drive square wave having a duty ratio of about 50% can be generated with high accuracy. it can.
  • a reference operation signal having the same frequency (13.56 MHz) as the high frequency output output from the high frequency power supply circuit is generated, and the double frequency generation circuit 2 uses the double frequency of the reference operation signal. (2nd harmonic; 27.12 MHz) is generated! /,
  • the present invention is not limited to this.
  • the double frequency of the operation signal may be directly generated.
  • a force using a second harmonic as a double frequency is not limited to this.
  • the present invention is not limited to this. It may be used to generate a basic drive square wave or a control square wave that is a square wave with a duty ratio of about 50%.
  • the AND gate circuit 11 is used as the logic gate circuit.
  • the present invention is not limited to this, and a NAND gate circuit is used as these logic gate circuits.
  • the pulse width that is output when either the basic drive square wave or the control square wave exists in the OR gate circuit that is, the basic drive square wave and the control square wave.
  • the square As these logic gate circuits that can be used as amplification source signals by inverting the wave, a multi-input logic gate circuit having an appropriate AND circuit function based on the control method can be used. Logic gate circuits such as NAND gates can also be used.
  • the force using the 3. 39MHz square wave is not limited to this.
  • the 13.56 MHz basic drive square wave and the control square wave itself may be used as the phase comparison square wave.
  • the LPFs 7 and 33 are provided so that both the sine wave output and the pulse output can be implemented.
  • the present invention is not limited to this. Of course, it ’s okay to use only one of them!
  • the fundamental drive square wave is generated using the double frequency.
  • the present invention is not limited to this, and the fundamental drive square wave is used for the double frequency. It can be generated without any problems.
  • the AND gate circuit 14 is used as the logic gate circuit.
  • the logic gate circuit may be an appropriate one based on the control method. It is possible to use a logic gate circuit (NAND gate circuit or OR gate circuit).
  • the force using the delay circuit unit 13 is not limited to this.
  • the output frequency is relatively low.
  • the first counter to the signal width of the output frequency is relatively low.
  • the delay circuit unit 13 may be omitted.
  • the force input to the first inverter 10 using the leading edge differential signal as a trigger signal as the differential signal is not limited to this.
  • FIG. As shown in the figure, the trailing edge differentiation circuit unit 9 ′ is used to input the trailing edge differentiation signal to the first inverter 10, and the delay circuit is a third inverter that is the same inverter as the first inverter 10.
  • the delay circuit By using the inverter 10 ′ as the delay circuit unit 13, it is possible to configure so that it is not necessary to match the delay propagation times of both inputs to the AND gate circuit 14.
  • a field effect transistor (FET) Q is used as a time constant control element.
  • FET field effect transistor
  • the present invention is not limited to this, and as these time constant control elements, CdS photocells or variable capacitance diodes can be used.
  • Cd in the circuit of Fig. 8 is the capacitance of the variable capacitance diode.
  • C1 and C3 are DC blocking, and are generally set to C, C> Cd.
  • the time constant is determined by R and Cd. Also
  • FIG. 8 shows a force that is an example of the use of a general variable capacitance diode.
  • FIG. 9 shows an example of the use of a variable capacitance diode according to the present invention as an application example.
  • the power exemplifying 13.56 MHz in which the signal width cannot be controlled by a thyristor or the like as the output frequency is not limited to this. It goes without saying that the high-frequency power supply device of the present invention can be used at an output frequency of 100 KHz.

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Abstract

[PROBLEMS] To regulate output power at a high speed. [MEANS FOR SOLVING PROBLEMS] A high-frequency power supply device includes: basic drive square wave generation means (5) for generating a basic drive square wave having an output frequency of a high-frequency power to be outputted; signal width varying means (34, 31) for varying a signal width in on cycle of the basic drive square wave generated by the basic drive square wave generation means according to a control signal for controlling the output power; and amplification means (32) for amplifying an amplification source signal having a signal width adjusted by the signal width varying means according to the control signal.

Description

明 細 書  Specification
高周波電源装置  High frequency power supply
技術分野  Technical field
[0001] 本発明は、プラズマ発生装置等に高周波電源を供給するための高周波電源装置 に関する。  The present invention relates to a high frequency power supply device for supplying high frequency power to a plasma generator or the like.
背景技術  Background art
[0002] 従来、プラズマ発生装置等に高周波電源を供給するための高周波電源装置として は、図 7に示すように、（1)の方形波発振部にて所定周波数 (例えば 13.56MHz)の方 形波列を発振させ、（2)の波形整形部にて、（3)の電力増幅部で必要とする所定周 波数と電力の方形波列に生成する。（2)で生成された Duty 1:1の方形波列により、 ( 3)の電力増幅部にて所要の高周波電力を生成する。このとき所要電力に応じた直 流電圧を (4)の直流電源部より供給する。この所要電力に対応した直流電圧を応じ せしめる所定の信号を (6)の電力制御信号として供給する事により (7)に所定の高 周波出力を得るものである。尚、（8)の濾波器は出力に基本波成分以外の不要周波 数成分を取り除く為のものである。  Conventionally, as a high-frequency power supply for supplying a high-frequency power supply to a plasma generator or the like, as shown in FIG. 7, a square wave oscillating unit (1) has a rectangular shape with a predetermined frequency (eg, 13.56 MHz). The wave train is oscillated, and the waveform shaping unit (2) generates a square wave train of the predetermined frequency and power required by the power amplification unit (3). Using the duty 1: 1 square wave train generated in (2), the required high-frequency power is generated in the power amplification unit in (3). At this time, a DC voltage corresponding to the required power is supplied from the DC power supply section (4). By supplying a predetermined signal that makes the DC voltage corresponding to the required power correspond to the power control signal of (6), a predetermined high-frequency output is obtained in (7). The filter in (8) is for removing unnecessary frequency components other than the fundamental wave component in the output.
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0003] これら高周波電源装置を半導体製造装置の例えばプラズマ処理装置等に使用す る場合には、半導体製造装置 (プラズマ処理装置)のチャンバ一内の状態により、負 荷の状態が著しく極端に変化する。高周波電源装置においてはこの変化に追随して 出力電力を制御しなければならない。然るに、（4)の直流電源は大電流であり、仮に 直列制御（シリーズレギュレーション)方式であっても高速で応答させることは難 ヽ 上、低い効率 (50%程度）がさらに悪ィ匕する。  [0003] When these high-frequency power supply devices are used in, for example, a plasma processing apparatus of a semiconductor manufacturing apparatus, the load state changes remarkably extremely depending on the state in the chamber of the semiconductor manufacturing apparatus (plasma processing apparatus). To do. In a high-frequency power supply, the output power must be controlled following this change. However, the DC power source in (4) has a large current, and even if it is a series control system, it is difficult to respond at high speed, and the low efficiency (about 50%) is worse.
[0004] だ力 半導体ウェハーの大型化やトランジスタが組み込まれたディスプレイパネル 等の大型化に伴い、プラズマ処理装置が大型化するのに伴って、高周波電源装置 に要求される出力も大型化するにつれ、従来の低効率増幅器だと装置の容積 ·損失 電力が非常に大きいため、巿場の要求を満たさなくなり、近年では、スイッチングモー ドアンプと呼ばれる、従来よりも効率が高い (80%以上)増幅方式を用いた高周波電 源が実用化されてきている力 このスイッチングモード式であっても、出力制御には最 低電源周期の 1周期を要し、一般的にはこの電源周期は数ミリ秒であるので、結果と して、シリーズレギュレーション方式でもスイッチングモード式であっても、従来の装置 においては、出力制御に数十ミリ秒力も数百ミリ秒を必要としており、最悪の場合には 製品自体を破壊してしまう場合があると 、う問題があった。 [0004] As the size of semiconductor wafers and display panels with built-in transistors increases, the output required for high-frequency power supply devices increases as the plasma processing equipment grows in size. In the case of conventional low-efficiency amplifiers, the volume and loss of the device is so large that it does not meet the requirements of the factory. The power that has been put to practical use of a high-frequency power source that uses an amplification method called a deamplifier, which is more efficient than conventional (80% or more). Since this power supply cycle is generally several milliseconds, as a result, even with the series regulation method or the switching mode method, the output control is several tens of milliseconds for conventional devices. The force required several hundred milliseconds, and in the worst case, the product itself could be destroyed.
[0005] 本発明は、このような問題点に着目してなされたもので、これら高周波電源装置に おける出力電力の調節制御を、高速に実施することのできる高周波電源装置を提供 することを目的とする。 [0005] The present invention has been made paying attention to such problems, and an object of the present invention is to provide a high-frequency power supply device capable of performing high-speed adjustment control of output power in these high-frequency power supply devices. And
課題を解決するための手段  Means for solving the problem
[0006] 上記課題を解決するために、本発明の請求項 1に記載の高周波電源装置は、 出力する高周波電力の出力周波数を有する基本駆動方形波を生成する基本駆動 方形波生成手段と、出力電力を制御するための制御信号に基づいて前記基本駆動 方形波生成手段にて生成された基本駆動方形波の 1周期内における信号幅を可変 させる信号幅可変手段と、該信号幅可変手段にて信号幅が前記制御信号に基づい て調整された増幅源信号を増幅する増幅手段とを有することを特徴としている。 この特徴によれば、信号幅可変手段により制御信号に基づいて基本駆動方形波のIn order to solve the above-described problem, the high frequency power supply device according to claim 1 of the present invention includes a basic drive square wave generating unit that generates a basic drive square wave having an output frequency of high frequency power to be output, and an output A signal width variable means for varying a signal width within one cycle of the basic drive square wave generated by the basic drive square wave generation means based on a control signal for controlling power, and the signal width variable means And amplifying means for amplifying the amplification source signal whose signal width is adjusted based on the control signal. According to this feature, the basic drive square wave is generated based on the control signal by the signal width varying means.
1周期内における信号幅が可変された増幅源信号が増幅されて出力されるので、出 力電力の調節制御を高速に実施することができる。 Since the amplification source signal with a variable signal width within one period is amplified and output, output power adjustment control can be performed at high speed.
[0007] 本発明の請求項 2に記載の高周波電源装置は、請求項 1に記載の高周波電源装 置であって、  [0007] A high frequency power supply device according to claim 2 of the present invention is the high frequency power supply device according to claim 1,
前記信号幅可変手段が、前記基本駆動方形波とほぼ同一な周波数と波形とを有 する制御用方形波を生成する制御用方形波生成回路と、該制御用方形波の前記基 本駆動方形波に対する位相シフトを制御する位相シフト制御回路と、該位相シフト制 御回路にて位相シフト制御された制御用方形波と前記基本駆動方形波とが入力され る論理ゲート回路により形成されて 、ることを特徴として 、る。  The signal width variable means generates a control square wave having a frequency and waveform substantially the same as the basic drive square wave, and the basic drive square wave of the control square wave. A phase shift control circuit for controlling the phase shift with respect to the control signal, and a logic gate circuit to which the control square wave controlled by the phase shift control circuit and the basic driving square wave are input. It is characterized by
この特徴によれば、高周波にて良好に動作可能な信号幅可変手段を、比較的簡 素な構成にて得ることができる。 [0008] 本発明の請求項 3に記載の高周波電源装置は、請求項 2に記載の高周波電源装 置であって、 According to this feature, it is possible to obtain a signal width varying means that can operate satisfactorily at a high frequency with a relatively simple configuration. [0008] A high-frequency power supply device according to claim 3 of the present invention is the high-frequency power supply device according to claim 2,
前記位相シフト制御回路が、前記基本駆動方形波と前記制御用方形波の位相を 同期させるための位相比較器を含む PLL回路と、前記制御用方形波を生成するた めの制御用信号を生成する電圧制御発振器に、前記 PLL回路から印加される制御 電圧にバイアス電圧を印加するノ ィァス電圧印加回路とで構成されていることを特徴 としている。  The phase shift control circuit generates a control signal for generating the control square wave and a PLL circuit including a phase comparator for synchronizing the phases of the basic drive square wave and the control square wave The voltage controlled oscillator includes a noise voltage application circuit that applies a bias voltage to the control voltage applied from the PLL circuit.
この特徴によれば、通常において多くのデバイスが存在する位相比較器を含む PL L回路にバイアス電圧印加回路を加えるのみで位相シフト制御回路を構成できるの で、回路設計の自由度が向上するとともに、簡素な構成にて良好な精度を有する位 相シフト制御回路を得ることができる。  According to this feature, the phase shift control circuit can be configured simply by adding a bias voltage application circuit to a PLL circuit including a phase comparator in which many devices normally exist. Thus, a phase shift control circuit having a simple structure and good accuracy can be obtained.
[0009] 本発明の請求項 4に記載の高周波電源装置は、請求項 1に記載の高周波電源装 置であって、 [0009] A high frequency power supply device according to claim 4 of the present invention is the high frequency power supply device according to claim 1,
前記信号幅可変手段が、  The signal width varying means is
前記基本駆動方形波の前縁または後縁の微分信号を生成する微分信号生成回路 部と、  A differential signal generation circuit section for generating a differential signal of a leading edge or a trailing edge of the basic driving square wave;
前記生成された微分信号の入力を契機として入力信号の反転出力を開始する第 1 の反転器と、前記第 1の反転器からの出力信号を反転して当該第 1の反転器に入力 させる第 2の反転器並びに該第 2の反転器から出力される出力信号の前記第 1の反 転器への入力を、前記制御信号に応じて変化される時定数により決定される時間に お!、て反転を持続する時定数回路部とを有する信号幅制御回路と、を有するパイブ レータ回路部と、  The first inverter that starts the inverted output of the input signal triggered by the input of the generated differential signal, and the first inverter that inverts the output signal from the first inverter and inputs it to the first inverter. 2 and the input of the output signal output from the second inverter to the first inverter at a time determined by a time constant changed according to the control signal !, A signal width control circuit having a time constant circuit part that continues inversion, and a vibrator circuit part having
により形成されて 、ることを特徴として 、る。  It is characterized by being formed by.
この特徴によれば、高周波にて良好に動作可能な信号幅可変手段を、非常に簡素 な構成にて得ることができる。  According to this feature, it is possible to obtain a signal width variable means that can operate satisfactorily at a high frequency with a very simple configuration.
[0010] 本発明の請求項 5に記載の高周波電源装置は、請求項 4に記載の高周波電源装 置であって、 [0010] The high frequency power supply device according to claim 5 of the present invention is the high frequency power supply device according to claim 4,
前記第 1の反転器が、多入力変転論理ゲート回路により形成されていることを特徴 としている。 The first inverter is formed by a multi-input transformation logic gate circuit. It is said.
この特徴によれば、一般的な MSIのマルチノイブレータに比較して高速動作可能 な、例えば NANDゲート等の多入力変転論理ゲート回路を用いて第 1の反転器を形 成することで、より短い信号幅の方形波信号を生成することができ、制御可能な出力 電力の範囲をより大きくすることができる。  According to this feature, the first inverter can be formed by using a multi-input transformation logic gate circuit such as a NAND gate that can operate at a higher speed than a general MSI multi-noiser. A square wave signal with a short signal width can be generated, and the range of controllable output power can be increased.
[0011] 本発明の請求項 6に記載の高周波電源装置は、請求項 4または 5に記載の高周波 電源装置であって、 [0011] A high frequency power supply device according to claim 6 of the present invention is the high frequency power supply device according to claim 4 or 5,
前記信号幅可変手段は、前記バイブレータ回路部からの出力信号と前記基本駆 動方形波とが入力され、該入力されるバイブレータ回路部力 の出力信号により、入 力される基本駆動方形波の切り出しを行う論理ゲート回路を含み、前記増幅手段は 、前記論理ゲート回路からの出力信号を前記増幅源信号として増幅することを特徴と している。  The signal width varying means receives an output signal from the vibrator circuit unit and the basic driving square wave, and cuts out an input basic driving square wave based on the input output signal of the vibrator circuit unit force. The amplification means amplifies an output signal from the logic gate circuit as the amplification source signal.
この特徴によれば、増幅源信号の信号幅が逆転してしまうことを回避でき、これら信 号幅が逆転 (逆転 Duty化）による障害の発生を防止できる。  According to this feature, it is possible to prevent the signal width of the amplification source signal from being reversed, and it is possible to prevent the occurrence of a failure due to the signal width being reversed (reversal duty).
[0012] 本発明の請求項 7に記載の高周波電源装置は、請求項 6に記載の高周波電源装 置であって、 [0012] A high frequency power supply device according to claim 7 of the present invention is the high frequency power supply device according to claim 6,
前記論理ゲート回路に入力される基本駆動方形波を、前記第 1の反転器における 信号伝搬遅延時間にて遅延させる遅延回路を含むことを特徴としている。  It includes a delay circuit for delaying a basic driving square wave input to the logic gate circuit by a signal propagation delay time in the first inverter.
この特徴によれば、論理ゲート回路により切り出された増幅源信号の信号幅が、信 号伝搬遅延時間分だけ短くなつてしまう不都合を回避できる。  According to this feature, it is possible to avoid the disadvantage that the signal width of the amplification source signal cut out by the logic gate circuit is shortened by the signal propagation delay time.
図面の簡単な説明  Brief Description of Drawings
[0013] [図 1]本発明の実施例 1における高周波電源回路の構成を示す回路構成図である。  FIG. 1 is a circuit configuration diagram showing a configuration of a high frequency power supply circuit according to Embodiment 1 of the present invention.
[図 2] (a) , (b)は、本発明の実施例 1の高周波電源回路における増幅源信号の生成 状況を示す説明図である。  [FIG. 2] (a) and (b) are explanatory diagrams showing the state of generation of an amplification source signal in the high frequency power supply circuit according to Embodiment 1 of the present invention.
[図 3]本発明の高周波電源回路の実施例を示す回路構成図である。  FIG. 3 is a circuit configuration diagram showing an embodiment of a high frequency power supply circuit according to the present invention.
[図 4] (a)〜（e)は、図 1の実施例の高周波電源回路における各種信号のタイミングを 示すチャートである。  [FIG. 4] (a) to (e) are charts showing timings of various signals in the high-frequency power circuit of the embodiment of FIG.
[図 5]本発明の実施例における高周波電源回路の構成を示す図である。 圆 6]その他の形態の高周波電源回路を示す回路構成図である。 FIG. 5 is a diagram showing a configuration of a high frequency power supply circuit in an example of the present invention. [6] FIG. 6 is a circuit configuration diagram showing another type of high-frequency power supply circuit.
圆 7]従来における電源回路の構成を示す図である。 [7] FIG. 7 is a diagram showing a configuration of a conventional power supply circuit.
圆 8]その他の形態の高周波電源回路の構成を示す図である。 [8] FIG. 8 is a diagram showing a configuration of a high-frequency power supply circuit in another form.
圆 9]その他の形態の高周波電源回路の構成を示す図である。 [9] FIG. 9 is a diagram showing a configuration of a high-frequency power supply circuit in another form.
圆 10]本発明の実施例における高周波電源回路の制御速度を測定したオシロスコ ープの測定画面を示す図である。 [10] FIG. 10 is a diagram showing an oscilloscope measurement screen for measuring the control speed of the high-frequency power circuit in the embodiment of the present invention.
[図 11]従来の電源回路の制御速度を測定したオシロスコープの測定画面を示す図 である。  FIG. 11 is a diagram showing a measurement screen of an oscilloscope that measures the control speed of a conventional power supply circuit.
符号の説明 Explanation of symbols
1 基本動作信号発生器  1 Basic operation signal generator
2 倍周波生成回路  Double frequency generator
3 波形成形回路  3 Waveform shaping circuit
4 分周波生成回路  4 frequency divider circuit
5 基本駆動方形波生成回路部  5 Basic drive square wave generator
9 (後縁)微分回路部  9 (Rear edge) Differentiating circuit
10 第 1反転器  10 1st inverter
11 反転器  11 Inverter
12 該時定数回路部  12 Time constant circuit
12 E級アンプ  12 Class E amplifier
12 時定数回路部  12 Time constant circuit
13 遅延回路部  13 Delay circuit
14 ANDゲート回路  14 AND gate circuit
15 単安定マルチバイブレータ  15 Monostable multivibrator
26 電圧制御発振器  26 Voltage controlled oscillator
27 波形成形回路  27 Waveform shaping circuit
28 分周波生成回路  28 frequency divider circuit
29 ノ ィァス電圧印加回路  29 Noise voltage application circuit
30 PU^回路 31 ANDゲート回路 30 PU ^ circuit 31 AND gate circuit
32 E級アンプ  32 Class E amplifier
33 ローパスフィルタ（LPF)  33 Low-pass filter (LPF)
34 制御用方形波生成回路部  34 Control square wave generator
14 前記制御用方形波生成回路部  14 Square wave generator for control
35 位相シフト制御回路部  35 Phase shift control circuit
Ql 電界効果型トランジスタ (FET)  Ql Field Effect Transistor (FET)
IC NANDゲート回路  IC NAND gate circuit
2  2
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0015] 本発明の実施例を以下に説明する。  [0015] Examples of the present invention will be described below.
実施例 1  Example 1
[0016] 本発明の実施例を図面に基づいて説明すると、先ず図 1は、本実施例の高周波電 源装置に用いた高周波電源回路の回路構成図である。  An embodiment of the present invention will be described with reference to the drawings. First, FIG. 1 is a circuit configuration diagram of a high frequency power supply circuit used in the high frequency power supply apparatus of the present embodiment.
[0017] この本実施例の高周波電源回路は、図 1に示すように、該高周波電源回路から出 力される出力周波数と同一周波数を有するデューティ比約 50%の方形波である基 本駆動方形波を生成する基本駆動方形波生成回路部 5と、該基本駆動方形波生成 回路部において生成される基本駆動方形波と同一な周波数と波形とを有する制御 用方形波を生成する制御用方形波生成回路部 34と、前記制御用方形波の基本駆 動方形波に対する位相シフトを制御する位相シフト制御回路部 35と、前記基本駆動 方形波生成回路部 5にて生成された基本駆動方形波と制御用方形波生成回路部 3 4にて生成された制御用方形波とが入力される本発明における論理ゲート回路であ る ANDゲート回路 31と、該 ANDゲート回路 31から出力される増幅源信号を増幅す る本発明におけるスイッチングアンプ回路となる E級アンプ 32とから構成される。  As shown in FIG. 1, the high-frequency power supply circuit of this embodiment is a basic drive square which is a square wave having a duty ratio of about 50% and the same frequency as the output frequency output from the high-frequency power supply circuit. Basic drive square wave generating circuit unit 5 for generating a wave, and a control square wave for generating a control square wave having the same frequency and waveform as the basic drive square wave generated in the basic drive square wave generation circuit unit A generation circuit unit 34, a phase shift control circuit unit 35 that controls a phase shift of the control square wave with respect to a basic drive square wave, and a basic drive square wave generated by the basic drive square wave generation circuit unit 5 AND gate circuit 31 which is a logic gate circuit in the present invention to which the control square wave generated by control square wave generation circuit unit 3 4 is input, and an amplification source signal output from AND gate circuit 31 In the present invention for amplifying It is composed of Class E amplifier 32, which is a switching amplifier circuit.
[0018] 本実施例の基本駆動方形波生成回路部 5は、図 1に示すように、基本動作信号発 生器 1と、倍周波生成回路 2と、波形成形回路 3と、分周波生成回路 4とから構成され る。  As shown in FIG. 1, the basic drive square wave generation circuit unit 5 of the present embodiment includes a basic operation signal generator 1, a double frequency generation circuit 2, a waveform shaping circuit 3, and a frequency division generation circuit. It consists of four.
[0019] この基本動作信号発生器 1としては、高周波電源回路から出力される高周波出力、 例えば高周波出力の周波数が 13.56MHzであれば 13.56MHzの高周波信号を出 力する発振器 (オシレータ)を使用すれば良ぐこの基本動作信号発生器 1にて発振 された高周波信号である基本駆動信号は、公知の倍周波回路により 2倍の周波数で ある 27.12MHzとされる。 [0019] The basic operation signal generator 1 outputs a high frequency output from a high frequency power supply circuit, for example, a 13.56MHz high frequency signal if the frequency of the high frequency output is 13.56MHz. The basic drive signal, which is a high-frequency signal oscillated by this basic operation signal generator 1, which is sufficient if a powerful oscillator (oscillator) is used, is set to a double frequency of 27.12 MHz by a known double-frequency circuit. .
[0020] これら 2倍の周波数である 27.12MHzとされた基本駆動信号は、図示しない増幅 用トランジスタにて適宜にその振幅が増幅された後、波形成形回路 3に供給されて、 27.12MHzの方形波に整形される。これら波形成形回路 3としては、通常において デジタル回路等において使用される方形波の生成回路、具体的にはインバータを多 段 (例えば 2段）に用いたもの等を好適に使用することができる。  [0020] The basic drive signal of 27.12 MHz, which is twice the frequency, is amplified by an amplifying transistor (not shown) and then supplied to the waveform shaping circuit 3 to form a 27.12 MHz square. Shaped into waves. As these waveform shaping circuits 3, a square wave generating circuit usually used in a digital circuit or the like, specifically, a circuit using inverters in multiple stages (for example, two stages) can be suitably used.
[0021] そして、これら波形成形回路 3において 2倍の周波数である 27.12MHzの方形波と された基本駆動信号は、例えばパルスカウンタ等力 成る分周波生成回路 4に供給 されて、 2分周である 13.56MHzの方形波と、 8分周である 3. 39MHzの方形波に 変換される。  [0021] Then, the basic drive signal converted into a square wave of 27.12 MHz, which is twice the frequency in the waveform shaping circuit 3, is supplied to, for example, the frequency dividing circuit 4 having a pulse counter equal power and divided by two. It is converted into a certain 13.56MHz square wave and a 3.39MHz square wave that is divided by 8.
[0022] これらの方形波は倍周波の方形波に基づいて生成されることで、図 2に示すように 、そのデューティ比が約 50%の方形波となる基本駆動方形波（13.56MHz)とされて ANDゲート回路 11に供給され、 3. 39MHzの方形波は、位相比較用方形波として 後述する PLL回路 30に入力される。  [0022] These square waves are generated based on the double frequency square wave, and as shown in Fig. 2, the basic drive square wave (13.56MHz) becomes a square wave having a duty ratio of about 50%. Then, it is supplied to the AND gate circuit 11, and the 3.39 MHz square wave is input to the PLL circuit 30 described later as a phase comparison square wave.
[0023] また、本実施例の制御用方形波生成回路部 34は、図 1に示すように、電圧制御発 信器 (VCO) 26と、波形成形回路 27と、分周波生成回路 28とから構成される。この 電圧制御発信器 (VCO) 26は、前述した基本駆動信号の 2倍の周波数である 27.12 MHzの信号を含む所定範囲の周波数の信号を、制御電圧に応じて発振可能なもの であれば良ぐ該電圧制御発信器 (VCO) 26にて発振された 27.12MHzの信号は、 前記した基本駆動方形波生成回路部 5と同様に、図示しない増幅用トランジスタにて 適宜にその振幅が増幅された後、波形成形回路 27に供給されて方形波に整形され る。これら波形成形回路 27としては、前述の波形成形回路 3と同様の回路、具体的 にはインバータを多段 (例えば 2段）に用 、たもの等を好適に使用することができる。  Further, as shown in FIG. 1, the control square wave generation circuit unit 34 of the present embodiment includes a voltage control oscillator (VCO) 26, a waveform shaping circuit 27, and a frequency division generation circuit 28. Composed. This voltage control oscillator (VCO) 26 may be any one that can oscillate a signal in a predetermined range including a 27.12 MHz signal that is twice the frequency of the basic drive signal described above according to the control voltage. The amplitude of the 27.12 MHz signal oscillated by the voltage controlled oscillator (VCO) 26 was appropriately amplified by an amplifying transistor (not shown) in the same manner as the basic drive square wave generation circuit unit 5 described above. After that, it is supplied to the waveform shaping circuit 27 and shaped into a square wave. As these waveform shaping circuits 27, a circuit similar to the waveform shaping circuit 3 described above, specifically, an inverter used in multiple stages (for example, two stages) can be suitably used.
[0024] そして、これら波形成形回路 27において 27.12MHzの方形波とされた制御用信号 は、例えばパルスカウンタ等カゝら成る分周波生成回路 28に供給されて、 2分周である 13.56MHzの方形波と、 8分周である 3. 39MHzの方形波に変換される。 [0025] 尚、これらの方形波も倍周波の方形波に基づいて生成されることで、図 2に示すよう に、そのデューティ比が約 50%の方形波となる制御用方形波（13.56MHz)とされて ANDゲート回路 31に供給され、 3. 39MHzの方形波は、位相比較用方形波として 後述する PLL回路 30に入力される。 [0024] Then, the control signal converted into a 27.12 MHz square wave in these waveform shaping circuits 27 is supplied to a frequency dividing circuit 28 such as a pulse counter, for example. It is converted into a square wave and a 3.39 MHz square wave that is divided by 8. [0025] It should be noted that these square waves are also generated based on the double-frequency square wave, and as shown in Fig. 2, a control square wave (13.56MHz) whose square duty ratio is about 50% is obtained. ) And supplied to the AND gate circuit 31. 3. A 39 MHz square wave is input to the PLL circuit 30 described later as a phase comparison square wave.
[0026] また、本実施例の位相シフト制御回路部 35は、図 1に示すように、前述の基本駆動 方形波生成回路部 5並びに制御用方形波生成回路部 34からの各位相比較用方形 波（3. 39MHz)が入力され、これら入力される位相比較用方形波に基づいて基本 駆動方形波と制御用方形波の位相を比較する位相比較器を含み、これら双方の位 相を同期させるための PLL回路 30と、該 PLL回路 30から前記制御用方形波生成回 路部 34の電圧制御発信器 (VCO) 26に印加される制御電圧信号に、出力制御入力 に応じたバイアス電圧を印加するバイアス電圧印加回路 29とから構成される。  Further, as shown in FIG. 1, the phase shift control circuit unit 35 of the present embodiment includes each of the phase comparison squares from the basic drive square wave generation circuit unit 5 and the control square wave generation circuit unit 34 described above. Including a phase comparator that compares the phase of the basic driving square wave and the control square wave based on the input phase comparison square wave, and synchronizes the phase of both of them. And a bias voltage corresponding to the output control input is applied to the control voltage signal applied from the PLL circuit 30 to the voltage control oscillator (VCO) 26 of the control square wave generating circuit section 34. And a bias voltage applying circuit 29.
[0027] 本実施例の PLL回路 30においては、 PLL回路 30内の位相比較器において前述 の基本駆動方形波生成回路部 5並びに制御用方形波生成回路部 34からの各位相 比較用方形波（3. 39MHz)の位相が比較されて、その位相が同期する、つまりは位 相差がなくなるような位相とするための制御電圧信号が電圧制御発信器 (VCO) 26 に、適宜に増幅されて印加されることで、バイアス電圧印加回路 29によるバイアス電 圧が印加されない場合には、双方の位相比較用方形波が同期するようになり、後述 するように、これら位相が同期された基本駆動方形波と制御用方形波とが、図 1に示 すように ANDゲート回路 31に入力されることで、これら基本駆動方形波と制御用方 形波とほぼ等しいパルス幅であるデューティ比約 50%で 13.56MHzの方形波を有 する増幅源信号が ANDゲート回路 31から E級アンプ 12に出力されて増幅されて、 これら 13.56MHzのパルス出力、或いは該パルス出力をローパスフィルタ 33を通過 させることで正弦波出力として出力される。  In the PLL circuit 30 of the present embodiment, each phase comparison square wave from the basic drive square wave generation circuit unit 5 and the control square wave generation circuit unit 34 described above in the phase comparator in the PLL circuit 30 ( 3.39MHz) phase is compared and the control voltage signal is applied to the voltage controlled oscillator (VCO) 26 after it is amplified appropriately so that the phase is synchronized, that is, the phase is eliminated. As a result, when the bias voltage is not applied by the bias voltage application circuit 29, both phase comparison square waves are synchronized. As will be described later, the basic drive square wave having these phases synchronized is synchronized. 1 and the control square wave are input to the AND gate circuit 31 as shown in FIG. 1, so that the basic drive square wave and the control square wave have a pulse width substantially equal to the duty ratio of about 50%. Amplification source signal with 13.56MHz square wave The signal is output from the AND gate circuit 31 to the class E amplifier 12, amplified, and output as a 13.56 MHz pulse output or a sine wave output by passing the pulse output through the low-pass filter 33.
[0028] これらの出力を絞りたい場合には、前記バイアス電圧印加回路 29において印加さ れるバイアス電圧を増加させれば良ぐこれらバイアス電圧印加回路 29としては、前 記 PLL回路 30から出力される制御電圧信号に印加されるバイアス電圧を、可変抵 抗を用いて増減させる回路を用いることができ、これら可変抵抗による抵抗値を変化 させて制御電圧信号に印加されるバイアス電圧を増加させると、これらバイアス電圧 を相殺する電圧が PLL回路 30から出力される状態、つまり、これらバイアス電圧を相 殺するのに必要な電圧が生じる位相差が基本駆動方形波と制御用方形波との間に 生じるように制御用方形波の位相がシフトされる。 [0028] When it is desired to reduce these outputs, it is sufficient to increase the bias voltage applied in the bias voltage application circuit 29. The bias voltage application circuit 29 is output from the PLL circuit 30. A circuit that increases or decreases the bias voltage applied to the control voltage signal using a variable resistor can be used.When the resistance value by these variable resistors is changed to increase the bias voltage applied to the control voltage signal, These bias voltages Control is performed so that a phase difference is generated between the basic driving square wave and the control square wave, in which the voltage necessary to cancel these bias voltages is generated. The phase of the square wave is shifted.
[0029] そして、これらバイアス電圧印加回路 9において印加されるバイアス電圧によって、 制御用方形波の位相が基本駆動方形波に対して 90度シフトした場合には、図 2 (a) に示すように、制御用方形波と基本駆動方形波の双方のパルスが存在する場合に おいてのみ、つまりは、制御用方形波と基本駆動方形波の双方のパルスが重なる部 分のパルス幅である、制御用方形波のパルス幅の約半分（50%)のパルス幅を有す る増幅源信号が ANDゲート回路 31から E級アンプ 32に出力されて増幅されることで 、出力が絞られるようになる。  [0029] When the phase of the control square wave is shifted by 90 degrees with respect to the basic drive square wave due to the bias voltage applied in these bias voltage application circuits 9, as shown in FIG. Only when both the control square wave and the basic drive square wave are present, that is, the pulse width of the portion where both the control square wave and the basic drive square wave overlap. An amplification source signal having a pulse width that is about half (50%) of the pulse width of the square wave for use is output from the AND gate circuit 31 to the class E amplifier 32 and amplified, thereby reducing the output. .
[0030] そして、更に、ノィァス電圧印加回路 9において印加されるバイアス電圧を増加して 前記制御用方形波の位相が基本駆動方形波に対して 180度シフトした場合には、 図 2 (b)に示すように、制御用方形波と基本駆動方形波の双方のパルスが重なる部 分が無くなるので、 ANDゲート回路 31からはパルスの出力がなくなり、 E級アンプ 32 における増幅源となる信号が無くなるので、出力が殆ど「0」に絞られるようになる。  [0030] Further, when the bias voltage applied in the noise voltage application circuit 9 is increased and the phase of the control square wave is shifted by 180 degrees with respect to the basic drive square wave, FIG. 2 (b) As shown in Fig. 2, there is no overlap between both the control square wave and the basic drive square wave, so there is no pulse output from the AND gate circuit 31, and there is no signal that is the amplification source in the class E amplifier 32. Therefore, the output is almost reduced to “0”.
[0031] 以上、本実施例 1によれば、信号幅可変手段として、制御用方形波生成回路部 34 と位相シフト制御回路部 35と ANDゲート回路 31を用いることで、出力周波数の半周 期よりも短力な信号幅を有する増幅源信号が生成され、該増幅源信号が E級アンプ 32にて増幅されることから、出力周波数が高周波であっても、簡素な構成にて増幅 源信号の信号幅を制御信号に応じて変更することができ、よって、 E級アンプ 32にて 増幅された高周波電源回路からの出力電力の調節を、簡素な構成で時間的に高速 、具体的には図 10に示す、後述する実施例の回路と同様に、数百ナノ秒程度の精 度にて制御することができる。  As described above, according to the first embodiment, by using the control square wave generation circuit unit 34, the phase shift control circuit unit 35, and the AND gate circuit 31 as the signal width variable means, the half cycle of the output frequency can be achieved. Since an amplification source signal having a short signal width is generated and the amplification source signal is amplified by the class E amplifier 32, even if the output frequency is high, the amplification source signal can be generated with a simple configuration. The signal width can be changed according to the control signal, so the output power from the high-frequency power circuit amplified by the class E amplifier 32 can be adjusted quickly with a simple configuration. Similar to the circuit of the embodiment described later shown in FIG. 10, it can be controlled with an accuracy of about several hundred nanoseconds.
[0032] また、本実施例 1によれば、前述のように、位相シフト制御回路を、前記基本駆動方 形波と前記制御用方形波の位相を同期させるための位相比較器を含む PLL回路 1 0と、前記制御用方形波を生成するための制御用信号を生成する電圧制御発振器 6 に、前記 PLL回路 10から印加される制御電圧にバイアス電圧を印加するバイアス電 圧印加回路 9とで構成しており、このようにすることで、通常において多くのデバイス が存在する位相比較器を含む PLL回路にバイアス電圧印加回路を加えるのみで位 相シフト制御回路を構成できるので、回路設計の自由度が向上するとともに、簡素な 構成にて良好な精度を有する位相シフト制御回路を得ることができる。 In addition, according to the first embodiment, as described above, the phase shift control circuit includes a phase comparator for synchronizing the phases of the basic drive square wave and the control square wave. 10 and a bias voltage application circuit 9 that applies a bias voltage to the control voltage applied from the PLL circuit 10 to the voltage controlled oscillator 6 that generates a control signal for generating the control square wave. Many devices that are configured and usually do this Since a phase shift control circuit can be configured simply by adding a bias voltage application circuit to a PLL circuit including a phase comparator with a phase shifter, the degree of freedom in circuit design is improved and a phase with good accuracy with a simple configuration. A shift control circuit can be obtained.
実施例 2  Example 2
[0033] 次に、実施例 2の高周波電源回路について説明する。本実施例 2の高周波電源回 路は、図 3に示すように、該高周波電源回路から出力される出力周波数と同一周波 数を有するデューティ比約 50%の方形波である基本駆動方形波を生成する基本駆 動方形波生成回路部 5と、該基本駆動方形波生成回路部 5にて生成された基本駆 動方形波の前縁微分信号を生成する微分回路部 9と、該微分回路部 9にて生成され た前縁微分信号が入力される第 1反転器 10並びに該第 1反転器 10からの出力信号 を反転出力する第 2反転器 11および第 2反転器 11からの出力信号が第 1反転器 10 に入力される時間を可変制御するための時定数回路部 12とから成る単安定マルチ バイブレータ 15と、前記基本駆動方形波生成回路部 5にて生成された基本駆動方 形波を、第 1反転器 10における信号伝搬遅延時間分だけ遅延させる遅延回路部 13 と、該遅延回路部 13にて遅延された基本駆動方形波と第 1反転器 10からの出力信 号とが入力される本発明における論理ゲート回路である ANDゲート回路 14と、該 A NDゲート回路 14から出力される増幅源信号を増幅する本発明におけるスィッチン グアンプ回路部となる E級アンプ 6とから構成される。  Next, the high frequency power supply circuit of Example 2 will be described. As shown in FIG. 3, the high frequency power supply circuit according to the second embodiment generates a basic drive square wave that is a square wave with a duty ratio of about 50% having the same frequency as the output frequency output from the high frequency power supply circuit. A fundamental driving square wave generating circuit unit 5 for generating a basic driving square wave generated by the basic driving square wave generating circuit unit 5, a differentiating circuit unit 9 for generating a leading edge differential signal, and the differentiating circuit unit 9 The first inverter 10 to which the leading edge differential signal generated in Step 1 is input, and the output signals from the second inverter 11 and the second inverter 11 that invert the output signal from the first inverter 10 are the first output. (1) The basic driving square wave generated by the monostable multivibrator 15 including the time constant circuit unit 12 for variably controlling the time input to the inverter 10 and the basic driving square wave generation circuit unit 5 , Delay time delayed by the signal propagation delay time in the first inverter 10 Unit 13, AND gate circuit 14 which is a logic gate circuit in the present invention to which the basic driving square wave delayed in delay circuit unit 13 and the output signal from first inverter 10 are input, and A It comprises a class E amplifier 6 which is a switching amplifier circuit section in the present invention for amplifying the amplification source signal output from the ND gate circuit 14.
[0034] また、本実施例の基本駆動方形波生成回路部 5は、実施例 1の基本駆動方形波生 成回路部 5と同様であり、基本動作信号発生器 1と、倍周波生成回路 2と、波形成形 回路 3と、分周波生成回路 4とから構成される。  The basic drive square wave generation circuit unit 5 of the present embodiment is the same as the basic drive square wave generation circuit unit 5 of the first embodiment, and includes a basic operation signal generator 1 and a double frequency generation circuit 2. And a waveform shaping circuit 3 and a frequency division generation circuit 4.
[0035] この基本動作信号発生器 1としては、高周波電源回路から出力される高周波出力、 具体的には出力周波数が 13.56MHzであれば 13.56MHzの高周波信号を出力す る発振器 (オシレータ)を使用すれば良ぐこの基本動作信号発生器 1にて発振され た高周波信号である基本駆動信号は、公知の倍周波回路により、一旦 2倍の周波数 である 27.12MHzとされる。  [0035] As the basic operation signal generator 1, a high-frequency output output from a high-frequency power supply circuit, specifically, an oscillator (oscillator) that outputs a 13.56 MHz high-frequency signal if the output frequency is 13.56 MHz is used. The basic drive signal, which is a high-frequency signal oscillated by the basic operation signal generator 1, is once set to a double frequency of 27.12 MHz by a known double-frequency circuit.
[0036] これら 2倍の周波数である 27.12MHzとされた基本駆動信号は、図示しない増幅 用トランジスタにて適宜にその振幅が増幅された後、波形成形回路 3に供給されて、 27.12MHzの方形波に整形される。 [0036] The basic drive signal of 27.12 MHz, which is twice the frequency, is appropriately amplified by an amplifying transistor (not shown) and then supplied to the waveform shaping circuit 3, It is shaped into a 27.12MHz square wave.
[0037] そして、これら波形成形回路 3において 2倍の周波数である 27.12MHzの方形波と された基本駆動信号は、例えばパルスカウンタ等力 成る分周波生成回路 4に供給 されて、出力周波数に応じて、 2分周である 13.56MHzの方形波や、 8分周である 3 . 39MHzの方形波が生成される。尚、本実施例 2でも、出力周波数を 13.56MHzと するために 2分周である 13.56MHzを使用する。  [0037] Then, the basic drive signal converted into a square wave of 27.12 MHz, which is twice the frequency in the waveform shaping circuit 3, is supplied to, for example, a frequency division generation circuit 4 having a pulse counter equal power, and the output frequency depends on the output frequency. As a result, a 13.56 MHz square wave divided by 2 and a 3.39 MHz square wave divided by 8 are generated. In the second embodiment, 13.56 MHz, which is divided by two, is used to set the output frequency to 13.56 MHz.
[0038] このようにして基本駆動方形波生成回路部 5にて生成される方形波は、倍周波の 方形波に基づいて生成されることで、図 4に示すように、そのデューティ比が約 50% の方形波となる基本駆動方形波（13.56MHz)とされ、その一方が遅延回路部 13を 介して ANDゲート回路 14に供給され、他方が微分回路部 9に供給されてその前縁 微分信号とされることで、単安定マルチバイブレータ 15のトリガ信号として使用される  [0038] The square wave generated by the basic drive square wave generation circuit unit 5 in this way is generated based on the double-frequency square wave, so that its duty ratio is approximately as shown in FIG. The basic drive square wave (13.56 MHz) is a 50% square wave, one of which is supplied to the AND gate circuit 14 via the delay circuit section 13, and the other is supplied to the differentiation circuit section 9 and its leading edge derivative Used as a trigger signal for monostable multivibrator 15
[0039] また、本実施例に用いた単安定マルチバイブレータ 15は、その時定数回路部 12 に、出力電力を制御するための制御信号が入力されて、該制御信号に応じて時定数 が変化されることで、出力電力を小さくするための制御信号が入力された場合には、 時定数が小さくなることで短いパルス幅の信号が ANDゲート回路 14へ出力され、出 力電力を大きくするための制御信号が入力された場合には、時定数が大きくなること で長 、パルス幅の信号が ANDゲート回路 14へ出力される。 In the monostable multivibrator 15 used in the present embodiment, a control signal for controlling the output power is input to the time constant circuit unit 12, and the time constant is changed according to the control signal. Therefore, when a control signal for reducing the output power is input, a signal with a short pulse width is output to the AND gate circuit 14 due to the time constant being reduced, and the output power is increased. When a control signal is input, a signal having a long pulse width is output to the AND gate circuit 14 by increasing the time constant.
[0040] また、単安定マルチバイブレータ 15は、図 3に示すように、 2つの反転器が AC— D C結合とされたものである力 ここに用いる第 1反転器 10は、高周波出力周波数の半 周期、具体的に、出力周波数が 13.56MHzであれば、図 4に示すように、 1周期が 7 3.7ナノ秒となるので、その半周期である約 36.8ナノ秒よりも短かなパルス幅 (信号幅 )の方形波を出力可能な高速動作可能なものである必要があり、これら第 1反転器 10 としては、実際の回路として後述する実施例では、図 5に示すように、 NANDゲート 回路 ICを使用した反転器としている。  Further, as shown in FIG. 3, the monostable multivibrator 15 is a force in which two inverters are AC-DC coupled. The first inverter 10 used here is a half of the high frequency output frequency. If the output frequency is 13.56 MHz, as shown in Figure 4, one period is 7 3.7 nanoseconds, so the pulse width (signal) is shorter than the half period, which is about 36.8 nanoseconds. The first inverter 10 is an NAND circuit circuit IC as shown in FIG. 5 in an embodiment to be described later as an actual circuit. Is used as an inverter.
2  2
[0041] このように、 NANDゲート回路 ICを用いることは、これら論理ゲート回路は一般的  [0041] As described above, using the NAND gate circuit IC makes these logic gate circuits common.
2  2
な MSIのマルチバイブレータに比較して高速動作可能であることから、より短く、且つ 精度の高いパルス幅の方形波を出力でき、該 NANDゲート回路 ICにて形成される 第 1反転器 10から出力されるパルス幅 (信号幅）にて、 ANDゲート回路 14 (図 5にお いては IC )において基本駆動方形波が切り出されて増幅源信号とされるので、これ Compared with multi-vibrators of MSI, high-speed operation is possible, so a square wave with a shorter and more accurate pulse width can be output and formed by the NAND gate circuit IC. The basic drive square wave is cut out in the AND gate circuit 14 (IC in FIG. 5) by the pulse width (signal width) output from the first inverter 10 and used as the amplification source signal.
4  Four
らパルス幅を短くできればできる程、増幅源信号の最小のパルス幅、すなわち、当該 パルス幅により制御される出力電力の大きさも小さくでき、よって、制御可能な出力電 力の範囲がより大きくできるとともに、可変範囲内において制御可能な最小単位もより 細力べなるので、より緻密な出力制御を実施することができる。  The shorter the pulse width, the smaller the minimum pulse width of the amplification source signal, that is, the magnitude of the output power controlled by the pulse width, and thus the controllable output power range can be increased. Since the smallest unit that can be controlled within the variable range is more powerful, more precise output control can be performed.
[0042] 尚、後述する図 5の実施例では、第 1反転器 10として NANDゲート回路 ICを使用  In the embodiment of FIG. 5 described later, a NAND gate circuit IC is used as the first inverter 10.
2 しているが、本発明はこれに限定されるものではなぐその他の構成による高速動作 可能な反転器を用いても良い。  However, the present invention is not limited to this, and an inverter capable of high-speed operation with other configurations may be used.
[0043] 尚、第 2反転器 11としては、第 1反転器 10の出力を反転するのみであるので、比較 的伝搬遅延が少なぐ出力周波数レベルにぉ 、て動作が可能なものであれば良 、。  [0043] The second inverter 11 only inverts the output of the first inverter 10, so that the second inverter 11 can operate at an output frequency level with a small relative propagation delay. Good.
[0044] また、単安定マルチバイブレータ 15を構成する時定数回路部 12としては、通常に おいて時定数回路部として使用されるコンデンサ (C)と可変抵抗 (R)とから構成され る時定数回路でも良いが、これらコンデンサ (C)と可変抵抗 (R)を用いた時定数回路 では時定数が経時的に大きく変化し易ぐ安定した連続制御を実施することが難しい ので、図 5に示す実施例においては、時定数が経時的に大きく変化せず、且つ、制 御信号として電圧信号を使用できる電界効果型トランジスタ (FET) Qを時定数制御 素子として用いている。尚、図 3における Rの接地は高周波的接地である。  [0044] Further, the time constant circuit section 12 constituting the monostable multivibrator 15 is a time constant composed of a capacitor (C) and a variable resistor (R) that are normally used as a time constant circuit section. Although a circuit may be used, the time constant circuit using these capacitors (C) and variable resistors (R) is difficult to implement stable continuous control in which the time constant easily changes over time. In the embodiment, a field effect transistor (FET) Q that does not change greatly with time and can use a voltage signal as a control signal is used as a time constant control element. Note that the grounding of R in Fig. 3 is a high-frequency grounding.
[0045] 以下、図 3に示す本実施例の高周波電源回路の動作について、図 4に示す各部の 信号形態 (タイミング)を用いて説明すると、基本駆動方形波生成回路部 5において は、図 4 (a)に示すように、デューティ比が約 50%の基本駆動方形波（13.56MHz) が生成される。  Hereinafter, the operation of the high-frequency power supply circuit of the present embodiment shown in FIG. 3 will be described using the signal forms (timing) of each part shown in FIG. 4. In the basic drive square wave generation circuit unit 5, FIG. As shown in (a), a basic drive square wave (13.56 MHz) with a duty ratio of about 50% is generated.
[0046] そして、該生成された基本駆動方形波は微分回路部 9に入力されることで、図 4 (b) に示すように、その前縁のみが取り出された前縁微分信号に変換され、該前縁微分 信号がトリガー信号として第 1反転器 10に入力される。  Then, the generated basic driving square wave is input to the differentiating circuit unit 9 to be converted into a leading edge differential signal in which only the leading edge is extracted as shown in FIG. 4 (b). The leading edge differential signal is input to the first inverter 10 as a trigger signal.
[0047] 第 1反転器 10は、微分回路部 9からの前縁微分信号の入力を契機として信号出力 を開始し、該信号出力の第 2反転器 11による反転出力が、時定数回路部 12にて設 定されている時定数に基づく期間を過ぎることにより第 1反転器 10に入力された時点 において信号出力を終了する。つまり、第 1反転器 10は、図 4 (c)に示すように、前縁 微分信号の入力時点を契機とし、時定数回路部 12にて設定されている時定数に基 づく期間に応じたパルス幅 (信号幅)の信号を出力する。 [0047] The first inverter 10 starts signal output triggered by the input of the leading edge differential signal from the differentiation circuit unit 9, and the inverted output of the signal output by the second inverter 11 is the time constant circuit unit 12 When the signal is input to the first inverter 10 after the period based on the time constant set in The signal output is terminated at. In other words, as shown in FIG. 4 (c), the first inverter 10 is triggered by the input time of the leading edge differential signal, and according to the period based on the time constant set in the time constant circuit unit 12. Outputs a pulse width (signal width) signal.
[0048] 尚、図 4 (c)に示すように、これら前縁微分信号の入力時点から実際に信号が出力 されるまでには、時間的な遅延、つまり信号伝搬遅延時間が生じることとなるので、こ れら信号伝搬遅延時間分だけ遅延した出力信号を ANDゲート回路 14に入力し、一 方に、直接的に基本駆動方形波を入力してしまうと、 ANDゲート回路 14にて切り出 される基本駆動方形波の信号幅が、該信号伝搬遅延時間分だけ短くなつてしまうの で、これを回避するために、第 1反転器 10における該信号伝搬遅延時間分だけ基本 駆動方形波を遅延させるための遅延回路部 13経由させることで、 ANDゲート回路 1 4に入力される双方の信号の同期がとれ、図 4 (e)に示すように、第 1反転器 10の信 号幅に応じた増幅源信号を得ることができる。  [0048] As shown in FIG. 4 (c), there is a time delay, that is, a signal propagation delay time from when the leading edge differential signal is input until the signal is actually output. Therefore, if the output signal delayed by the signal propagation delay time is input to the AND gate circuit 14, and the basic drive square wave is directly input, the AND gate circuit 14 cuts it out. Therefore, in order to avoid this, the basic drive square wave is reduced by the signal propagation delay time in the first inverter 10 in order to avoid this. By passing through the delay circuit section 13 for delaying, both signals input to the AND gate circuit 14 are synchronized, and as shown in FIG. 4 (e), the signal width of the first inverter 10 is increased. A corresponding amplification source signal can be obtained.
[0049] このように、第 1反転器 10における信号伝搬遅延時間が出力周波数の 1周期時間 に近い長さであったり、 1周期時間よりも長い（大きい)場合や、第 1反転器 10におい て出力可能な最小のパルス幅 (信号幅)の長さ (大きさ）が、出力周波数の 1周期時間 に近 、長さである場合には、基本駆動方形波の同一周期内における信号幅による 出力制御が困難となることから、本発明における方形波信号生成器となるこれら第 1 反転器 10として、出力周波数の 1周期時間の少なくとも 2論理ゲート以下の信号伝搬 遅延時間にて、該 1周期時間の少なくとも 2分の 1以下の信号幅の方形波信号を出 力できるものとすることが好ま 、。  [0049] As described above, when the signal propagation delay time in the first inverter 10 is close to one cycle time of the output frequency or longer (larger) than one cycle time, If the length (size) of the minimum pulse width (signal width) that can be output is close to one cycle time of the output frequency, it depends on the signal width within the same cycle of the basic drive square wave. Since the output control becomes difficult, these first inverters 10 serving as the square wave signal generator in the present invention have the signal propagation delay time of at least two logic gates of one cycle time of the output frequency, and the one cycle. It is preferable to output a square wave signal with a signal width of at least half the time.
[0050] 尚、本実施例では、 ANDゲート回路 14を用いて基本駆動方形波からの切り出しを 実施することで、図 4における波線にて示す如くの過大時定数 (逆転 DUTY比）を防 止できるようにしており、このようにすることは、信号幅が逆転することで、制御力が逆 になることにより機器が損傷する等の不都合が生じることを回避できることから好まし いが、本発明はこれに限定されるものではなぐこれら ANDゲート回路 14を用いるこ となぐ第 1反転器 10からの出力信号を、そのまま増幅源信号として E級アンプ 6に入 力するようにしても良ぐこの場合には、遅延回路部 13を省くことができる。  [0050] In this embodiment, by using the AND gate circuit 14 to cut out from the basic drive square wave, an excessive time constant (reverse duty ratio) as shown by the wavy line in FIG. 4 is prevented. This is preferable because it is possible to avoid the occurrence of inconveniences such as equipment damage due to the reverse of the control force due to the reverse of the signal width. However, the output signal from the first inverter 10 using the AND gate circuit 14 is not limited to this, and the output signal from the first inverter 10 may be directly input to the class E amplifier 6 as an amplification source signal. In this case, the delay circuit unit 13 can be omitted.
[0051] (具体例） [0052] 図 5は、実際に製作した回路を示す回路図であり、前述したように、第 1反転器 10と しては、 NANDゲート回路 ICを使用し、時定数回路部 12としては、コンデンサ C1と [0051] (Specific example) FIG. 5 is a circuit diagram showing a circuit actually manufactured. As described above, the NAND circuit IC is used as the first inverter 10 and the time constant circuit unit 12 is as follows. With capacitor C1
2  2
ともに、電界効果型トランジスタ (FET) Qのドレイン 'ソース間抵抗 (R )とを用いて  Both field effect transistor (FET) Q drain and source resistance (R)
1 DS  1 DS
いる。  Yes.
[0053] 尚、図 5中において、反転回路 ICは、入力される基本駆動方形波を再整形するた めのものであり、入力される基本駆動方形波の伝搬路において基本駆動方形波が 悪影響を受けな 、場合であれば省略しても良 、。  In FIG. 5, the inverting circuit IC is for reshaping the input basic drive square wave, and the basic drive square wave has an adverse effect on the propagation path of the input basic drive square wave. Do not take it if you want.
[0054] また、本実施例では、微分回路部 9を Rと Rおよび Cで構成しており、 R側が Vd  [0054] In the present embodiment, the differentiation circuit unit 9 is composed of R, R, and C, and the R side is Vd.
1 2 2 1 に接続されることで、前縁微分信号の非出力時において NANDゲート回路 ICの入  1 2 2 1 is connected to the NAND gate circuit IC when the leading edge differential signal is not output.
2 力 2には HIGH状態である「 1」が入力され、前縁微分信号の出力時にぉ 、て入力 2 に LOW状態である「0」が入力される。なお、回路素子による動作遅延があるため、 実際には、前縁微分信号は NANDゲート回路 ICの入力 1が LOW状態である「0」に  2 “2” is input to HIGH 2 and “1” is input to input 2 when the leading edge differential signal is output. Since there is an operation delay due to circuit elements, the leading edge differential signal is actually set to `` 0 '' when the input 1 of the NAND gate circuit IC is in the LOW state.
2  2
なるまで LOW状態である「0」を維持するだけの時定数が必要である。  A time constant is needed to keep “0” in the LOW state until it becomes.
[0055] また、図 5中において、 IC〜ICは遅延器であり、該 IC〜ICにより遅延回路部 13 Further, in FIG. 5, IC to IC are delay devices, and the delay circuit section 13 is formed by the IC to IC.
5 7 5 7  5 7 5 7
が形成されているとともに、 ICが第 2反転器 11に該当し、 ICが ANDゲート回路 14  The IC corresponds to the second inverter 11 and the IC is an AND gate circuit 14.
3 4  3 4
に該当する。  It corresponds to.
[0056] この本実施例においては、電界効果型トランジスタ (FET) Qを用いることにより、制 御信号として、電圧信号が FETQのゲートに印加された状態で、前縁微分信号が N ANDゲート回路 ICの入力 1に加わると、該ゲート電圧に対応したドレイン 'ソース間  [0056] In this embodiment, by using a field effect transistor (FET) Q, the leading edge differential signal is NAND gate circuit with the voltage signal applied to the gate of FETQ as the control signal. When applied to input 1 of the IC, drain to source corresponding to the gate voltage
2  2
抵抗 (R )とじにより構成される時定数期間、 NANDゲート回路 ICの入力 1の電位 A time constant period composed of a resistor (R) binding, the potential of input 1 of the NAND gate circuit IC
DS 1 2 力 LOW状態である「0」とされ，時定数期間経過後、 NANDゲート回路 ICの入力 1の DS 1 2 Force It is set to “0” which is LOW state. After the time constant period has elapsed, the input 1 of NAND gate circuit IC
2 電位が HIGH状態である「1」状態となることで、制御信号の電圧信号により NANDゲ ート回路 ICの入力 1の入力状態とその期間を制御できるので、経時的にも安定した  2 Since the potential is set to `` 1 '', which is HIGH, the input state and the period of input 1 of the NAND gate circuit IC can be controlled by the voltage signal of the control signal.
2  2
連続制御を実施できる。  Continuous control can be implemented.
[0057] この本実施例においては、第 1反転器 10としては、 NANDゲート回路 ICを使用す  In this embodiment, a NAND gate circuit IC is used as the first inverter 10.
2 ることで、 13.56MHzにおいても十分に利用可能な短さのパルス幅の得られる反転 器を得ており、この NANDゲート回路 ICの動作について説明すると、前述のように、  Therefore, we have obtained an inverter that can obtain a sufficiently short pulse width even at 13.56 MHz. The operation of this NAND gate circuit IC is explained as follows.
2  2
Rと Rおよび Cで構成された微分回路部 9に接続されている入力 2は、前縁微分信 号の非出力時において HIGH状態である「1」が入力されるとともに、他方の入力 1も 、電界効果型トランジスタ (FET^ i^を介して Vdに接続されることで、 HIGH状態であ る「1」が入力されているので、 NANDゲート回路 ICの出力は LOW状態である「0」 Input 2 connected to the differential circuit section 9 consisting of R, R and C is the leading edge differential signal. When the signal is not output, “1” which is in the HIGH state is input, and the other input 1 is also in the HIGH state by being connected to Vd via the field effect transistor (FET ^ i ^). Since “1” is input, the output of the NAND gate circuit IC is in the LOW state.
2  2
である。なお、 Rと Rの関係は、 ICの入力 2における閾値を Vとしたときに、 Vd'R  It is. The relationship between R and R is as follows: Vd'R when the threshold value at IC input 2 is V
1 2 2 Iし 2 I 1 2 2 I then 2 I
( R +R )> V とする。 Let (R + R)> V.
1 2 Iし  1 2 I
[0058] この状態において、前縁微分信号が出力される、つまり、入力 2に LOW状態である 「0」が入力されると、 NANDゲート回路 ICの出力は HIGH状態である「1」に移行す  In this state, when the leading edge differential signal is output, that is, when “0” that is in the LOW state is input to the input 2, the output of the NAND gate circuit IC shifts to “1” that is in the HIGH state. You
2  2
る。  The
[0059] そして、該 HIGH状態である「1」が出力されることで、第 2反転器 11に該当する IC  [0059] Then, when the HIGH state "1" is output, the IC corresponding to the second inverter 11
3 力 は反転出力である LOW状態である「0」が出力されることで、入力 1にも LOW状 態である「0」が入力されるようになった後 (微分信号入力直後）、前縁微分信号が非 出力状態、つまり LOW状態である「0」となっても、 NANDゲート回路 ICの出力は H  3 Force is output as “0” in the LOW state, which is an inverted output, so that “0” in the LOW state is also input to the input 1 (immediately after the differential signal is input). Even if the edge differential signal is in the non-output state, that is, “0” in the LOW state, the output of the NAND gate circuit IC is H
2  2
IGH状態のまま維持される。  It remains in the IGH state.
[0060] そして、電界効果型トランジスタ (FET) Qのゲート電圧に応じた R · C [秒]時間経 [0060] Then, R · C [second] time depending on the gate voltage of the field effect transistor (FET) Q
1 DS 1 過後 ICの入力 1の電位が再度 HIGH状態である「1」に戻ることで、入力 1と入力 2の 1 DS 1 After the IC's input 1 potential returns to `` 1 '', which is in the HIGH state again, the input 1 and input 2
2 2
双方の電位が HIGH状態である「1」となるので、 NANDゲート回路 ICの出力は LO  Since both potentials are high (1), the output of the NAND gate circuit IC is LO
2  2
W状態である「0」に移行することになるので、 NANDゲート回路 IC力もは、前縁微  Since it will shift to `` 0 '' which is the W state, the NAND gate circuit IC power is also slightly less than the leading edge
2  2
分信号の入力を契機として、時定数回路部 12に設定されている、出力周波数である 13.56MHzの半周期に該当する期間内の信号幅を有する方形波信号が出力される ことになるので、該、 NANDゲート回路 ICにより形成される第 1反転器 10が、本発  As a result of the input of the minute signal, a square wave signal having a signal width within a period corresponding to a half cycle of 13.56 MHz, which is the output frequency, set in the time constant circuit unit 12 is output. The first inverter 10 formed by the NAND gate circuit IC is
2  2
明における方形波信号生成器に該当する。  Corresponds to the square wave signal generator in Ming.
[0061] また、電界効果型トランジスタ (FET) Q等により構成される単安定マルチバイブレ ータ 15の時定数回路部 12は、本発明における方形波信号生成器となる第 1反転器 10を構成する NANDゲート回路 IC力も出力されるパルス幅 (信号幅）を、電力出力 [0061] In addition, the time constant circuit unit 12 of the monostable multivibrator 15 configured by a field effect transistor (FET) Q or the like constitutes the first inverter 10 which is a square wave signal generator in the present invention. NAND gate circuit that outputs the power of the pulse width (signal width) that is also output
2  2
を制御するための制御信号に基づ 、て可変制御するので、該時定数回路部 12が本 発明における信号幅制御回路に該当する。  Therefore, the time constant circuit unit 12 corresponds to the signal width control circuit in the present invention.
[0062] 以上、説明したように、制御信号に応じて可変とされる NANDゲート回路 IC力も出 As described above, the NAND gate circuit IC power that is variable according to the control signal is also output.
2 力されるパルス幅 (信号幅）、例えば、該パルス幅 (信号幅）を基本駆動方形波のパ ルス幅 (信号幅）の半分とした場合には、基本駆動方形波のパルス幅 (信号幅）の約 半分（50%)のパルス幅を有する増幅源信号が ANDゲート回路 14から E級アンプ 6 に出力されて増幅されることで、出力が絞られるようになり、更に、る NANDゲート回 路 IC力も出力されるパルス幅 (信号幅）を基本駆動方形波のパルス幅 (信号幅）の 12 The input pulse width (signal width), for example, the pulse width (signal width) When the pulse width is half the pulse width (signal width), an amplification source signal having a pulse width that is approximately half (50%) the pulse width (signal width) of the basic drive square wave is transferred from the AND gate circuit 14 to the class E amplifier 6 The output is narrowed down and amplified, and the NAND gate circuit IC power is also output. The pulse width (signal width) is also 1% of the pulse width (signal width) of the basic driving square wave.
2 2
Z3とした場合には、基本駆動方形波のパルス幅 (信号幅）の約 1Z3 (33%)のパル ス幅を有する増幅源信号が ANDゲート回路 14力も E級アンプ 6に出力されて増幅さ れることで、出力力 S絞られるよう〖こなる。  In the case of Z3, an amplification source signal having a pulse width of approximately 1Z3 (33%) of the pulse width (signal width) of the basic drive square wave is output to the E-class amplifier 6 and amplified by 14 AND gate circuits. As a result, the output force S is reduced.
[0063] 以上、前記各実施例によれば、信号幅可変手段として、実施例 1に示すように、制 御用方形波生成回路部 34と位相シフト制御回路部 35と ANDゲート回路 31を用い たり、実施例 2に示すように、単安定マルチバイブレータ 15と ANDゲート回路 14を 用いることで、出力周波数の半周期よりも短かな信号幅を有する増幅源信号が生成 され、該増幅源信号力 ¾級アンプ 6にて増幅されることから、出力周波数が高周波で あっても、簡素な構成にて増幅源信号の信号幅を制御信号に応じて変更することが でき、よって、 E級アンプ 6にて増幅された高周波電源回路からの出力電力の調節を 、簡素な構成で時間的に高速、具体的には図 10に示すように、 200ナノ秒程度の精 度にて制御することができる。  As described above, according to each of the above embodiments, as shown in the first embodiment, the control square wave generating circuit unit 34, the phase shift control circuit unit 35, and the AND gate circuit 31 are used as the signal width varying means. As shown in the second embodiment, by using the monostable multivibrator 15 and the AND gate circuit 14, an amplification source signal having a signal width shorter than a half cycle of the output frequency is generated, and the amplification source signal power is reduced. Since the signal is amplified by the class amplifier 6, even if the output frequency is high, the signal width of the amplification source signal can be changed according to the control signal with a simple configuration. Adjustment of the output power from the amplified high frequency power supply circuit can be controlled with a simple configuration at a high speed in time, specifically, with an accuracy of about 200 nanoseconds as shown in FIG.
[0064] また、本実施例 2によれば、ノイブレータ回路部として、 DC— AC結合による単安 定バイブレータを用いることにより、信号幅制御回路を、第 2反転器並びに時定数回 路部 12とにより簡単な構成にて構成できるので、回路設計の自由度が向上するとと もに、簡素な構成にて良好な精度を有するバイブレータ回路部を得ることができる。  [0064] According to the second embodiment, the signal width control circuit is connected to the second inverter and the time constant circuit unit 12 by using a DC-AC coupled monostable vibrator as the noise circuit unit. Therefore, it is possible to obtain a vibrator circuit unit having good accuracy with a simple configuration as well as improving the degree of freedom in circuit design.
[0065] また、本実施例 2によれば、第 1反転器 10を、一般的な MSIのマルチバイブレータ に比較して高速動作可能な NANDゲート回路 ICを用いて形成することで、より短い  In addition, according to the second embodiment, the first inverter 10 is formed by using a NAND gate circuit IC that can operate at a higher speed than a general MSI multivibrator, so that it is shorter.
2  2
信号幅の方形波信号を生成することができ、制御可能な出力電力の範囲をより大き くすることがでさる。  A square wave signal with a signal width can be generated, and the range of output power that can be controlled can be increased.
[0066] また、本実施例 2によれば、出力周波数の一周期毎の信号幅を可変することが可 能となるので、時間的に最も緻密となる同一周期内による出力電力の制御が可能と なる。  [0066] Further, according to the second embodiment, since the signal width of each cycle of the output frequency can be varied, it is possible to control the output power within the same cycle that is the most precise in time. It becomes.
[0067] また、本実施例 2によれば、 ANDゲート回路 14を用いることで、増幅源信号の信号 幅が逆転してしまうことを回避でき、これら信号幅が逆転 (逆転 Duty化）による障害の 発生を防止できる。 Further, according to the second embodiment, by using the AND gate circuit 14, the signal of the amplification source signal It is possible to prevent the width from being reversed, and it is possible to prevent the occurrence of a failure due to the reverse of these signal widths (reverse duty).
[0068] また、本実例 2によれば、遅延回路部 13を有することで、論理ゲート回路となる AN Dゲート回路 14により切り出された増幅源信号の信号幅が、信号伝搬遅延時間分だ け短くなつてしまう不都合を回避できる。  [0068] Also, according to Example 2, by including the delay circuit unit 13, the signal width of the amplification source signal cut out by the NAND gate circuit 14 serving as the logic gate circuit is equal to the signal propagation delay time. The inconvenience of shortening can be avoided.
[0069] また、本実施例 2によれば、時定数制御素子として、電界効果型トランジスタ (FET) を有しているので、時定数が経時的に大きく変動し難いので、時定数回路部に入力 される制御信号により、安定した連続制御を実施することができる。  [0069] Also, according to the second embodiment, since the field effect transistor (FET) is included as the time constant control element, the time constant is unlikely to fluctuate greatly with time. Stable continuous control can be implemented by the input control signal.
[0070] また、本実施例 2によれば、倍周波を用いて基本駆動方形波を生成して 、るので、 デューティ比約 50%の基本駆動方形波を、高精度にて生成することができる。  [0070] Also, according to the second embodiment, the basic drive square wave is generated using the double frequency, and therefore, the basic drive square wave having a duty ratio of about 50% can be generated with high accuracy. it can.
[0071] 以上、本発明の実施例を図面により説明してきたが、具体的な構成はこれら実施例 に限られるものではなぐ本発明の要旨を逸脱しない範囲における変更や追力卩がぁ つても本発明に含まれる。  As described above, the embodiments of the present invention have been described with reference to the drawings. However, the specific configuration is not limited to these embodiments, and there may be changes and additional efforts without departing from the gist of the present invention. It is included in the present invention.
[0072] 例えば、前記各実施例では、高周波電源回路から出力される高周波出力と同一の 周波数（13.56MHz)の基準動作信号を生成して、倍周波生成回路 2により該基準 動作信号の倍周波（2倍波； 27.12MHz)を生成するようにして!/、るが、本発明はこれ に限定されるものではなぐこれら倍周波生成回路 2を用いることなぐ例えば 27.12 MHzのオシレータを用いて基準動作信号の倍周波を直接生成するようにしても良い  For example, in each of the embodiments described above, a reference operation signal having the same frequency (13.56 MHz) as the high frequency output output from the high frequency power supply circuit is generated, and the double frequency generation circuit 2 uses the double frequency of the reference operation signal. (2nd harmonic; 27.12 MHz) is generated! /, However, the present invention is not limited to this. The double frequency of the operation signal may be directly generated.
[0073] また、前記各実施例では、倍周波として 2倍波を用いている力 本発明はこれに限 定されるものではなぐこれら 2倍波より高次の 4倍波や 8倍波を用いてデューティ比 約 50%の方形波である基本駆動方形波や制御用方形波を生成するようにしても良 い。 [0073] Further, in each of the above-described embodiments, a force using a second harmonic as a double frequency is not limited to this. The present invention is not limited to this. It may be used to generate a basic drive square wave or a control square wave that is a square wave with a duty ratio of about 50%.
[0074] また、前記実施例 1では、論理ゲート回路として ANDゲート回路 11を用いているが 、本発明はこれに限定されるものではなぐこれら論理ゲート回路としては、 NANDゲ ート回路を用いても良いし、或いは、 ORゲート回路にて基本駆動方形波と制御用方 形波のいずれか一方のパルス入力が存在する場合に出力されるパルス幅、つまりは 基本駆動方形波と制御用方形波の和のパルス幅を有する方形波を得た後、該方形 波を反転して増幅源信号としても良ぐこれら論理ゲート回路としては制御方式に基 づいた適宜な論理積回路機能を有する多入力論理ゲート回路を用いることができ、 ANDゲート回路 11に代えて NANDゲート等の論理ゲート回路も使用できる。 In the first embodiment, the AND gate circuit 11 is used as the logic gate circuit. However, the present invention is not limited to this, and a NAND gate circuit is used as these logic gate circuits. Alternatively, the pulse width that is output when either the basic drive square wave or the control square wave exists in the OR gate circuit, that is, the basic drive square wave and the control square wave. After obtaining a square wave having a pulse width of the sum of the waves, the square As these logic gate circuits that can be used as amplification source signals by inverting the wave, a multi-input logic gate circuit having an appropriate AND circuit function based on the control method can be used. Logic gate circuits such as NAND gates can also be used.
[0075] また、前記実施例 1では、位相比較用方形波として使用したデバイスの都合等によ り 3. 39MHzの方形波を用いている力 本発明はこれに限定されるものではなぐこ れら位相比較用方形波としては、当選ながら 13.56MHzの基本駆動方形波並びに 制御用方形波自体を用いるようにしても良 、ことは言うまでもな 、。  [0075] Further, in the first embodiment, due to the convenience of the device used as the phase comparison square wave, the force using the 3. 39MHz square wave is not limited to this. As a matter of course, the 13.56 MHz basic drive square wave and the control square wave itself may be used as the phase comparison square wave.
[0076] また、前記各実施例では、 LPF7、 33を設けて正弦波出力とパルス出力の双方の 出力形態を実施できるようにしている力 本発明はこれに限定されるものではなぐこ れらの 、ずれか一方のみとしても良!、。  [0076] Further, in each of the above-described embodiments, the LPFs 7 and 33 are provided so that both the sine wave output and the pulse output can be implemented. The present invention is not limited to this. Of course, it ’s okay to use only one of them!
[0077] また、前記各実施例では、倍周波を用いて基本駆動方形波を生成して 、るが、本 発明はこれに限定されるものではなぐこれら基本駆動方形波を、倍周波を用いるこ となく生成するようにしても良 、。  In each of the above embodiments, the fundamental drive square wave is generated using the double frequency. However, the present invention is not limited to this, and the fundamental drive square wave is used for the double frequency. It can be generated without any problems.
[0078] また、前記実施例 2でも、論理ゲート回路として ANDゲート回路 14を用いているが 、本発明はこれに限定されるものではなぐこれら論理ゲート回路としては、制御方式 に基づいた適宜な論理ゲート回路 (NANDゲート回路や ORゲート回路)を用いるこ とがでさる。  Also in the second embodiment, the AND gate circuit 14 is used as the logic gate circuit. However, the present invention is not limited to this, and the logic gate circuit may be an appropriate one based on the control method. It is possible to use a logic gate circuit (NAND gate circuit or OR gate circuit).
[0079] また、前記実施例 2では、遅延回路部 13を用いている力 本発明はこれに限定され るものではなぐ出力周波数が比較的低ぐ該出力周波数の信号幅に対して第 1反 転器 10における遅延伝搬時間が十分に小さなものである場合には、これら遅延回路 部 13を省略しても良い。  [0079] In the second embodiment, the force using the delay circuit unit 13 is not limited to this. The output frequency is relatively low. The first counter to the signal width of the output frequency is relatively low. When the delay propagation time in the converter 10 is sufficiently small, the delay circuit unit 13 may be omitted.
[0080] また、前記実施例 2では、微分信号として前縁微分信号をトリガー信号として第 1反 転器 10に入力している力 本発明はこれに限定されるものではなぐ例えば、図 6に 示すように、後縁微分回路部 9'を用いて、第 1反転器 10に後縁微分信号を入力す るようにし、遅延回路として、第 1反転器 10と同一の反転器である第 3反転器 10'を 遅延回路部 13として用いることで、 ANDゲート回路 14に入力される双方の遅延伝 搬時間をマッチングさせる必要がな 、ように構成しても良 、。  [0080] In the second embodiment, the force input to the first inverter 10 using the leading edge differential signal as a trigger signal as the differential signal is not limited to this. For example, FIG. As shown in the figure, the trailing edge differentiation circuit unit 9 ′ is used to input the trailing edge differentiation signal to the first inverter 10, and the delay circuit is a third inverter that is the same inverter as the first inverter 10. By using the inverter 10 ′ as the delay circuit unit 13, it is possible to configure so that it is not necessary to match the delay propagation times of both inputs to the AND gate circuit 14.
[0081] また、前記実施例 2では時定数制御素子として、電界効果型トランジスタ (FET) Q を使用した時定数回路部 12を例示しているが、本発明はこれに限定されるものでは なぐこれら時定数制御素子としては、 CdSフォトセルあるいは容量可変ダイオード等 を用いることができる。 In the second embodiment, a field effect transistor (FET) Q is used as a time constant control element. However, the present invention is not limited to this, and as these time constant control elements, CdS photocells or variable capacitance diodes can be used.
[0082] 具体的に容量可変ダイオードを用いる場合には、図 8に示すように、時定数可変を 静電容量で行う事以外、動作自体は図 5の回路と同じである。この図 8の回路におけ る Cdが可変容量ダイオードの静電容量である。周知の如く C1及び C3は直流阻止で あり、一般には C , C > >Cdに設定される。時定数は R及び Cdで決定される。また  [0082] Specifically, when a variable capacitance diode is used, the operation itself is the same as that of the circuit of Fig. 5 except that the time constant is varied by capacitance as shown in Fig. 8. Cd in the circuit of Fig. 8 is the capacitance of the variable capacitance diode. As is well known, C1 and C3 are DC blocking, and are generally set to C, C> Cd. The time constant is determined by R and Cd. Also
1 3  13
、図 8はもつとも一般的な可変容量ダイオードの使用例である力 図 9は応用例として 、本発明に特ィ匕した可変容量ダイオードの使用例を示すものである。  FIG. 8 shows a force that is an example of the use of a general variable capacitance diode. FIG. 9 shows an example of the use of a variable capacitance diode according to the present invention as an application example.
[0083] また、前記実施例では、出力周波数として、サイリスター等にて信号幅の制御不能 な 13.56MHzを例示している力 本発明はこれに限定されるものではなぐこれらサ イリスターが利用できる数百 KHzの出力周波数にて、本発明の高周波電源装置を利 用できることは言うまでもない。 [0083] Further, in the above-described embodiment, the power exemplifying 13.56 MHz in which the signal width cannot be controlled by a thyristor or the like as the output frequency. The present invention is not limited to this. It goes without saying that the high-frequency power supply device of the present invention can be used at an output frequency of 100 KHz.

Claims

請求の範囲 The scope of the claims
[1] 出力する高周波電力の出力周波数を有する基本駆動方形波を生成する基本駆動 方形波生成手段と、出力電力を制御するための制御信号に基づいて前記基本駆動 方形波生成手段にて生成された基本駆動方形波の 1周期内における信号幅を可変 させる信号幅可変手段と、該信号幅可変手段にて信号幅が前記制御信号に基づい て調整された増幅源信号を増幅する増幅手段とを有することを特徴とする高周波電 源装置。  [1] A basic drive square wave generating means for generating a basic drive square wave having an output frequency of high frequency power to be output, and the basic drive square wave generating means based on a control signal for controlling the output power. Signal width varying means for varying the signal width within one cycle of the basic driving square wave, and amplification means for amplifying the amplification source signal whose signal width is adjusted based on the control signal by the signal width varying means. A high frequency power supply device comprising:
[2] 前記信号幅可変手段が、前記基本駆動方形波とほぼ同一な周波数と波形とを有 する制御用方形波を生成する制御用方形波生成回路と、該制御用方形波の前記基 本駆動方形波に対する位相シフトを制御する位相シフト制御回路と、該位相シフト制 御回路にて位相シフト制御された制御用方形波と前記基本駆動方形波とが入力され る論理ゲート回路により形成されていることを特徴とする請求項 1に記載の高周波電 源装置。  [2] The signal width variable means generates a control square wave having a frequency and waveform substantially the same as the basic drive square wave, and the basic square wave for control A phase shift control circuit for controlling a phase shift with respect to the driving square wave, and a logic gate circuit to which the control square wave controlled by the phase shift control circuit and the basic driving square wave are input. 2. The high frequency power supply device according to claim 1, wherein
[3] 前記位相シフト制御回路が、前記基本駆動方形波と前記制御用方形波の位相を 同期させるための位相比較器を含む PLL回路と、前記制御用方形波を生成するた めの制御用信号を生成する電圧制御発振器に、前記 PLL回路から印加される制御 電圧にバイアス電圧を印加するノ ィァス電圧印加回路とで構成されていることを特徴 とする請求項 2に記載の高周波電源装置。  [3] The phase shift control circuit includes a PLL circuit including a phase comparator for synchronizing the phases of the basic driving square wave and the control square wave, and a control circuit for generating the control square wave. 3. The high-frequency power supply device according to claim 2, comprising a voltage-controlled oscillator that generates a signal and a noise voltage application circuit that applies a bias voltage to the control voltage applied from the PLL circuit.
[4] 前記信号幅可変手段が、  [4] The signal width varying means includes
前記基本駆動方形波の前縁または後縁の微分信号を生成する微分信号生成回路 部と、  A differential signal generation circuit section for generating a differential signal of a leading edge or a trailing edge of the basic driving square wave;
前記生成された微分信号の入力を契機として入力信号の反転出力を開始する第 1 の反転器と、前記第 1の反転器からの出力信号を反転して当該第 1の反転器に入力 させる第 2の反転器並びに該第 2の反転器から出力される出力信号の前記第 1の反 転器への入力を、前記制御信号に応じて変化される時定数により決定される時間に お!、て反転を持続する時定数回路部とを有する信号幅制御回路と、を有するパイブ レータ回路部と、  The first inverter that starts the inverted output of the input signal triggered by the input of the generated differential signal, and the first inverter that inverts the output signal from the first inverter and inputs it to the first inverter. 2 and the input of the output signal output from the second inverter to the first inverter at a time determined by a time constant changed according to the control signal !, A signal width control circuit having a time constant circuit part that continues inversion, and a vibrator circuit part having
により形成されて 、ることを特徴とする請求項 1に記載の高周波電源装置。 The high frequency power supply device according to claim 1, wherein the high frequency power supply device is formed by:
[5] 前記第 1の反転器が、多入力変転論理ゲート回路により形成されていることを特徴 とする請求項 4に記載の高周波電源装置。 5. The high-frequency power supply device according to claim 4, wherein the first inverter is formed by a multi-input transformation logic gate circuit.
[6] 前記信号幅可変手段は、前記バイブレータ回路部からの出力信号と前記基本駆 動方形波とが入力され、該入力されるバイブレータ回路部力 の出力信号により、入 力される基本駆動方形波の切り出しを行う論理ゲート回路を含み、前記増幅手段は[6] The signal width variable means receives the output signal from the vibrator circuit section and the basic driving square wave, and is input by the input output signal of the vibrator circuit section force. Including a logic gate circuit for cutting out a wave,
、前記論理ゲート回路からの出力信号を前記増幅源信号として増幅することを特徴と する請求項 4または 5に記載の高周波電源装置。 6. The high frequency power supply device according to claim 4, wherein an output signal from the logic gate circuit is amplified as the amplification source signal.
[7] 前記論理ゲート回路に入力される基本駆動方形波を、前記第 1の反転器における 信号伝搬遅延時間にて遅延させる遅延回路を含むことを特徴とする請求項 6に記載 の高周波電源装置。 7. The high frequency power supply device according to claim 6, further comprising a delay circuit that delays a basic driving square wave input to the logic gate circuit by a signal propagation delay time in the first inverter. .
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