WO2007077739A1 - Transmission device and reception device - Google Patents

Transmission device and reception device Download PDF

Info

Publication number
WO2007077739A1
WO2007077739A1 PCT/JP2006/325383 JP2006325383W WO2007077739A1 WO 2007077739 A1 WO2007077739 A1 WO 2007077739A1 JP 2006325383 W JP2006325383 W JP 2006325383W WO 2007077739 A1 WO2007077739 A1 WO 2007077739A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmission
packet
unit
reception
buffer unit
Prior art date
Application number
PCT/JP2006/325383
Other languages
French (fr)
Japanese (ja)
Inventor
Yasuo Hamamoto
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to CN2006800495883A priority Critical patent/CN101351780B/en
Priority to US12/158,026 priority patent/US8477789B2/en
Priority to JP2007552904A priority patent/JP4970284B2/en
Publication of WO2007077739A1 publication Critical patent/WO2007077739A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Definitions

  • the present invention relates to a technique for performing synchronous transmission between a transmitter and a receiver, such as MPEG2 transport stream (MPEG2 TS) transmission.
  • MPEG2 transport stream MPEG2 TS
  • Synchronous transmission is transmission in which the average bit rate of packets input to the transmitter is equal to the average bit rate of packets output from the receiver, and the time axis jitter of the packets is within a predetermined range. It is
  • the condition is that both the input bit rate of a packet input to the transmitting apparatus and the transmission bit rate on the transmission path are constant bit rates (CBR: Constant Bit Rate), and their values are the same.
  • CBR Constant Bit Rate
  • the fixed bit rate in the present embodiment means that the average bit rate for a given period is a fixed value
  • the variable bit rate means that the average bit rate for a given period is variable. means.
  • FIG. 17 is a block diagram of a receiving apparatus for realizing conventional synchronous transmission.
  • Receiving apparatus 1000 also includes an input terminal 1001 to which a packet is input as transmission path power, an adjustment circuit 1002 including a buffer (not shown) for absorbing transmission fluctuation, a system decoding unit 1003, a time stamp extraction circuit 1004, PLL ( (Phase Looked Loop) circuit 1005, an output terminal 1006 for outputting a packet to the outside, and an output terminal 1007 for outputting a system clock to the outside.
  • an adjustment circuit 1002 including a buffer (not shown) for absorbing transmission fluctuation, a system decoding unit 1003, a time stamp extraction circuit 1004, PLL ( (Phase Looked Loop) circuit 1005, an output terminal 1006 for outputting a packet to the outside, and an output terminal 1007 for outputting a system clock to the outside.
  • PLL Phase Looked Loop
  • BuffR X (t) be an accumulated amount function representing the accumulated amount of packets at time t of the buffer for absorbing transmission fluctuation of the adjustment circuit 1002.
  • Rate function representing the input bit rate of the packet input to the buffer at time t and the bucket output from the buffer
  • G (t) and F (t) be rate functions representing the output bit rate of the
  • the rate function G (t) is 0 until time tO and c (c is a constant value) after time t0, and the rate function F (t) is 0 until time Tl and c (c is a constant value after time T1 ) (Fig. 18 (a)).
  • the accumulated amount function BuffRx (t) at time t after time T1 is represented by the following number (1).
  • the prior art controls the speed at which buffer power packets are output so that the buffer packet accumulation amount becomes constant, and achieves synchronous transmission.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 8-139704
  • the accumulation amount of packets in the buffer provided in the receiving apparatus is not constant, and will be described with reference to FIG.
  • the rate function G (t) is 0 until time TO, and is a fluctuation value after time TO
  • the rate function F (t) is 0 until time T1 and c after time T1 (c is a constant value) ( Figure 19 (a)).
  • the accumulation function BuffRx (t) at time t after time T1 is represented by the following number (2).
  • the above number (2) means that the amount of packet data input to the buffer between time ⁇ and time ⁇ is equal to the amount of packet data output from the buffer during that time. Since it does not exist, it shows that the accumulation function BuffRx (t) does not become constant after time T1 (Fig. 19 (b)). That is, after time T1, the accumulation amount of packets in the router is not constant.
  • the packet of the buffer provided in the transmitting device and the receiving device. It is an object of the present invention to provide a transmitting device and a receiving device, and a transmitting method and a receiving method, which can realize synchronous transmission between the transmitting device and the receiving device by utilizing the storage amount of
  • a transmission device includes a transmission counter unit that counts a clock signal of a fixed cycle, and a first unit that temporarily accumulates input packets and outputs the accumulated packets.
  • a transmission buffer unit, a packet stored in the first transmission buffer unit, and transmission counter information indicating a count value of the transmission counter unit when the packet is input to the own apparatus are transmitted,
  • a transmitter configured to transmit, to the transmission path, first transmission accumulation information for identifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet with respect to the transmission buffer unit; Equipped with
  • the packet stored in the first transmission buffer unit and transmission counter information indicating the count value of the transmission counter unit when the packet is input to the own apparatus The first transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at the first timing related to the first processing of the packet to the first transmission buffer unit to the transmission path Send.
  • a receiver according to the present invention is a transmitter according to the present invention, wherein a packet is transmitted from a transmitter having a transmission counter unit and a first transmission buffer unit that counts clock signals of a fixed cycle, and the transmission counter when the packet is input to the transmitter.
  • Transmission counter information indicating the count value of the unit, and the first transmission for specifying the accumulated amount of packets in the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit
  • a receiving unit that receives accumulated information via a transmission line, and a reception counter that counts clock signals and has a variable counting speed, and a first reception buffer that temporarily accumulates received packets.
  • First reception accumulation information for identifying the first transmission accumulation information, and the first reception accumulation information for identifying the accumulation amount of packets of the first reception buffer section at a second timing related to the second processing of the packet to the first reception buffer section And a correction unit that corrects the count speed of the reception counter unit based on information, the transmission counter information received by the reception unit, and the reception count information indicating the count value of the reception count unit.
  • a first output control unit that controls output of the packet from the first reception buffer unit.
  • the receiving method of the present invention counts a clock signal, and has a reception counter unit that has a variable counting speed, and a first reception buffer unit that temporarily accumulates received packets.
  • a receiving method performed in a receiving apparatus which includes a transmission counter unit that counts a clock signal having a predetermined cycle and a first transmission buffer unit, and the packet when the packet is input to the transmitting apparatus from the transmission apparatus.
  • Transmission counter information indicating the count value of the transmission counter unit; first for identifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit
  • the count speed of the reception counter unit is corrected based on the first reception accumulation information for specifying the accumulation amount of packets of the first reception buffer unit at the second timing related to the second process of the corresponding packet.
  • Control the output packet of the first reception buffer unit based on the correction step, the transmission counter information received by the reception step, and the reception count information indicating the count value of the reception count unit. Has a first output control step.
  • the first transmission accumulation information may be an accumulation amount of packets of the first transmission buffer unit.
  • the first transmission accumulation information may be an accumulation amount of packets of the first transmission buffer unit
  • the first reception accumulation information may be an accumulation amount of packets of the first reception buffer unit. Good.
  • the transmission apparatus further includes a counter information addition unit that adds the transmission counter information to the packet, and the transmission unit transmits the packet and the transmission counter information by the counter information addition unit. It may be performed by transmitting a packet to which transmission counter information is added.
  • the transmission apparatus further includes an accumulation information addition unit that adds the first transmission accumulation information to the packet, and the transmission unit transmits the packet and the first transmission accumulation information by the accumulation information addition unit. It may be performed by transmitting a packet to which the first transmission accumulation information is added.
  • the above transmission apparatus may further include a number adding unit that adds a sequential number to buckets transmitted by the transmission unit in the order in which the packets are input.
  • the receiving unit receives from the transmitting apparatus a sequential number given to the packet in the input order of the packets to the transmitting apparatus in the transmitting apparatus.
  • the receiving apparatus further includes a detecting unit that detects the number of packets that can not be received by the receiving unit based on the sequential number received by the receiving unit, and the correcting unit further includes the first transmission buffer.
  • the count speed of the reception counter unit may be corrected.
  • the first transmission buffer unit outputs a packet accumulated at a fixed bit rate
  • the first transmission buffer unit comprises a second transmission buffer unit for temporarily accumulating the output packet.
  • the first timing relating to the first processing is timing relating to the input processing
  • the transmission unit further relates to a second timing relating to the output processing that is the second processing of the packet to the second transmission buffer unit.
  • Second transmission accumulation information for specifying the accumulation amount of packets in the second transmission buffer unit may be transmitted.
  • the first timing relating to the first processing is timing relating to input processing
  • the first transmission buffer section further has a fixed bit rate.
  • the second transmission buffer unit at a timing related to the output processing of the packet to the second transmission buffer unit from the transmission apparatus having the second transmission buffer unit that temporarily accumulates the packet to be output and outputs the accumulated packet Second transmission accumulation information for specifying the accumulation amount of the data, and the receiving apparatus temporarily accumulates the received packet and outputs the accumulated packet to the first reception buffer unit.
  • the transmitting apparatus and the reception apparatus can be used. Synchronous transmission can be realized with the device.
  • the first transmission buffer unit outputs a packet accumulated at a fixed bit rate
  • the first transmission buffer unit comprises a second transmission buffer unit for temporarily accumulating the output packet.
  • the first timing relating to the first processing may be timing relating to input processing.
  • the first timing according to the first process is a timing according to an input process
  • the transmitting apparatus temporarily outputs a packet output by the first transmission buffer unit at a fixed bit rate.
  • a second transmission buffer unit for outputting the packet accumulated and accumulated, and the receiving apparatus temporarily accumulating the received packet and outputting the accumulated packet to the first reception buffer unit.
  • a buffer unit first transmission accumulation information for specifying an accumulation amount of packets of the first transmission buffer unit at a first timing related to a first process of the packet to the first transmission buffer unit;
  • First reception accumulation information for specifying the accumulation amount of packets of the first reception buffer unit at a second timing related to the second processing of the packet to the first reception buffer unit;
  • a second output control unit for outputting control packet of the second receiving buffer unit force Te may be further provided with a
  • the above transmission apparatus further includes a second transmission buffer unit that temporarily accumulates an input packet and transmits the packet to the first transmission buffer unit at a fixed bit rate, and the first timing according to the first process is It may be timing concerning output processing.
  • the receiving device of the present invention includes a transmission counter unit that counts clock signals of a fixed cycle, a first transmission buffer unit that temporarily accumulates packets, and outputs the accumulated packets at a fixed bit rate, and Indicates the count value of the transmission counter unit when the packet and the packet are input to the transmission device from the transmission device having the second transmission buffer unit that temporarily accumulates the packet output by the first transmission buffer unit.
  • a second output control unit that performs output control of packets of the second reception buffer unit based on reception accumulation information for specifying the accumulation amount of
  • both the input bit rate of the packet input to the transmission apparatus and the transmission bit rate in the transmission path are variable bit rates. Also, synchronous transmission can be realized between the transmitter and the receiver.
  • a receiving method counts a clock signal and has a variable count rate, a reception counter unit, a first reception buffer unit for temporarily accumulating an input packet, and a received packet.
  • a receiving counter having a second receiving buffer unit for temporarily storing the stored packets and outputting the stored packets to the first receiving buffer unit, the transmission counter unit for counting a clock signal of a fixed cycle, the packet Transmission having a first transmission buffer unit that temporarily accumulates the accumulated packets and outputs the accumulated packets at a fixed bit rate, and a second transmission buffer unit that temporarily accumulates the packets output by the first transmission buffer unit.
  • a first output control step for controlling the output of packets from the buffer unit, and for identifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the output processing of the packets to the second transmission buffer unit.
  • the transmission accumulation information, and the reception accumulation information for specifying the accumulation amount of packets of the second reception buffer section at the timing related to the input processing of the packet to the second reception buffer section,
  • the transmission apparatus and the reception apparatus can Synchronous transmission can be realized.
  • FIG. 1 is a block diagram of a synchronous transmission system according to a first embodiment.
  • FIG. 2 A time transition diagram of the bit rate and buffer storage amount of the synchronous transmission system of Fig. 1.
  • FIG. 3 A time transition diagram of packet configuration of the synchronous transmission system of FIG.
  • FIG. 4 The block diagram of the transmission time stamp timer of FIG.
  • FIG. 5 The block diagram of the reception time stamp timer of FIG.
  • FIG. 6 The block diagram of the synchronous transmission system of 2nd Embodiment.
  • FIG. 7 is a block diagram of the packet loss detection unit of FIG. 6;
  • FIG. 8 The block diagram of the synchronous transmission system of 3rd Embodiment.
  • FIG. 9 A time transition diagram of bit rate and buffer accumulation amount of buffer in the synchronous transmission system of Fig. 8.
  • FIG. 10 A time transition diagram of the packet configuration of the synchronous transmission system of FIG.
  • FIG. 11 The block diagram of the synchronous transmission system of 4th Embodiment.
  • FIG. 12 The block diagram of the synchronous transmission system of 5th Embodiment.
  • FIG. 14 is a block diagram of the read rate control unit of FIG. 12;
  • FIG. 15 The block diagram of the synchronous transmission system of 6th Embodiment.
  • FIG. 16 The block diagram of the synchronous transmission system of 7th Embodiment.
  • FIG. 17 The block diagram of the receiver which implement
  • FIG. 18 A time transition diagram of packet input / output bit rate to buffer and buffer accumulation amount of buffer in the prior art.
  • FIG. 19 A time transition diagram of input / output bit rate of packet to buffer and buffer accumulation amount of buffer for explaining problems of the prior art. Explanation of sign
  • the input bit rate of the packet input to the transmitting device is a variable bit rate
  • the transmission bit rate in the transmission path is The case of a fixed bit rate is considered.
  • FIG. 1 is a block diagram of a synchronous transmission system of the present embodiment.
  • the transmitting device 100 and the receiving device 200 transmit and receive packets via the transmission path 300.
  • the transmission path 300 is, for example, a transmission path in an ATM (Asynchronous Transfer Mode) network.
  • FIG. 2 is a time transition diagram of bit rate and packet accumulation amount of the synchronous transmission system of FIG.
  • the input bit rate of the packet input to the first transmission buffer 105 of the transmitting apparatus 100 is a variable bit rate, and its rate function is fl (t). Also, the transmission bit rate in the transmission path is a fixed bit rate, and its rate function is gl (t).
  • control is performed such that the output bit rate of the packet output from the first reception buffer 203 of the receiving device 200 is equal to the input bit rate of the packet input to the first transmission buffer 105. Be done. From this, when the delay time from the input of the packet to the transmitting device 100 to the output of the packet from the receiving device 200 is represented by delay, the first reception buffer 2
  • the output bit rate of the packet output from 03 is the rate function fl (t-delay).
  • (1) start writing a packet to the first transmission buffer 105 at time 0, (2) start reading a packet from the first transmission buffer 105 at time tO, and the first reception buffer 20
  • the rate function fl (t) is a fluctuating value
  • the function gl (t) is 0 until time tO and after time to.
  • C is a constant value
  • the accumulation function representing the accumulation amount of packets in the first transmission buffer 105 at time t is BuffT xl (t)
  • the accumulation function Buff Txl (t) at time t after time t is (3) Is represented by (Fig. 2 (b)).
  • the accumulated amount function representing the accumulated amount of packets in the first reception buffer 203 at time t is BuffRxl (t)
  • the accumulated amount function BuffRxKt) at time t after time tl is represented by the following number (4) ( Figure 2 (b)).
  • the accumulated amount of packets in the first transmission buffer 105 immediately before a certain packet is written to the first transmission buffer 105 and the packet in the first reception buffer 203 just before the certain packet is read out from the first reception buffer 203
  • the sum with the accumulated amount of is constant.
  • the accumulation amount of packets in the first transmission buffer 105 immediately after a certain packet is written to the first transmission buffer 105, and immediately after the certain packet is read out from the first reception buffer 203.
  • the sum with the accumulation amount of packets in the second reception buffer 203 is constant.
  • the present embodiment implements synchronous transmission between transmitting apparatus 100 and receiving apparatus 200 using the above relationship.
  • the accumulated amount of packets in the first transmission buffer 105 immediately before a certain packet is written to the first transmission buffer 105 and the first immediately before the certain packet is read out from the first reception buffer 203 Use the sum with the storage amount of packets in the reception buffer 203
  • the sum with the accumulation amount of packets in the reception buffer 203 may be used.
  • the transmitting apparatus 100 includes an input terminal 101, a transmission time stamp timer 102, a time stamp adding unit 103, a first transmission buffer amount adding unit 104, a first transmission buffer 105, and a first transmission buffer amount reading unit 106. And the transmission processing unit 107.
  • a packet is input to the input terminal 101, and the input packet is output to the time stamp adder 103.
  • the transmission time stamp timer 102 counts clock signals of a fixed frequency and outputs a count value, and an example of its configuration will be described later with reference to FIG.
  • the time stamp adder 103 adds the count value supplied from the transmission time stamp timer 102 as a time stamp to the beginning of the input packet.
  • the count value itself is used as a time stamp, but the count value may be replaced with time, and information indicating the replaced time may be used as a time stamp.
  • the first transmission buffer amount adding unit 104 adds a first transmission buffer amount described later input from the first transmission buffer amount reading unit 106 to the beginning of the packet to which the time stamp is added. Ru.
  • the first transmission buffer 105 is composed of a FIFO (First In First Out) buffer, temporarily accumulates input packets, and outputs the accumulated packets at a fixed bit rate.
  • the first transmission buffer 105 combines a plurality of packets and outputs a combined packet (hereinafter referred to as a combined packet).
  • the first transmission buffer amount reading unit 106 reads the accumulated amount of packets of the first transmission buffer 105 (hereinafter referred to as the first transmission buffer amount), and the first transmission buffer amount read out is referred to as the first transmission buffer. Output to the quantity addition unit 104.
  • the first transmission buffer amount is the packet of the first transmission buffer 105 immediately before the packet to which the first transmission buffer amount is added by the first transmission buffer amount addition unit 104 is written to the first transmission buffer 105. Accumulated amount of
  • the first transmission buffer amount is taken as the data accumulation amount of the first transmission buffer 105 excluding the time stamp and the data amount related to the first transmission buffer amount.
  • the first transmission buffer amount can be calculated, for example, as follows. Each data size of time stamp and first transmission buffer size is fixed. The number of packets stored in the first transmission buffer 105 (the number of input packets minus the number of output packets minus the sum of the data size of the timestamp and the data size of the first transmission buffer amount Multiply). The actual storage capacity of the first transmission buffer 105 also subtracts the multiplication value. This subtraction value becomes the first transmission buffer amount.
  • the transmission processing unit 107 performs modulation processing, protocol processing, destination header processing, and the like suitable for transmission.
  • modulation processing, protocol processing, destination header processing, and the like are not directly related to the present invention, and therefore the description thereof is omitted.
  • the present invention is applicable to any transmission regardless of modulation processing, protocol processing, destination header processing, and the like.
  • the timestamp attachment section 103 appends the count value supplied from the transmission timestamp timer 102 to the beginning of the packet as a timestamp. (N102), and the first transmission buffer amount adding unit 104 adds the first transmission buffer amount read by the first transmission buffer amount reading unit 106 to the beginning of the packet to which the time stamp is added ( N103). Timestamp Packets to which the packet size and the first transmission buffer amount have been added are accumulated in the first transmission buffer 105
  • the first transmission buffer 105 outputs the combined packet (N104).
  • the combined packet is subjected to predetermined processing by the transmission processing unit 107 and sent out to the transmission path 300.
  • FIG. 4 is a block diagram of the transmission time stamp timer 102 of FIG.
  • the transmission time stamp timer 102 includes an oscillator 102 a, a counter 102 b, and an output terminal 102 c.
  • the oscillator 102a is a fixed frequency oscillator, and is configured to oscillate a clock signal of a fixed frequency using a crystal or the like. However, the oscillation frequency is set high enough to keep the remaining time-axis jitter of the bucket after synchronization restoration within a predetermined amount.
  • the counter 102b applies a clock signal of a fixed frequency oscillated by the oscillator 102a, and outputs the count value from the output terminal 102c to the outside.
  • the count value output from the output terminal 102 c is supplied to the time stamp adder 103.
  • the receiving device 200 performs time axis restoration processing, rate control processing, and the like, which are conditions for synchronous transmission.
  • the time axis restoration process is a process for setting the time axis jitter of a packet within a predetermined range.
  • the rate control process is a process for equalizing the average bit rate of packets to be transmitted between the transmitting device and the receiving device.
  • Reception apparatus 200 includes reception processing section 201, separation section 202, first reception buffer 203, time stamp buffer 204, first transmission buffer size buffer 205, and first reception buffer quantity reading section 206.
  • the reception processing unit 201 performs processing reverse to the processing performed by the transmission processing unit 107 on the packet received from the transmission path 300, and restores the combined packet. However, since the processing performed by the reception processing unit 201 is not directly related to the present invention, the description will be omitted.
  • the separation unit 202 is configured to receive the combined packet input from the reception processing unit 201 into a plurality of first transmission Separate buffer size, multiple timestamps, and multiple packets. Then, the separation unit 202 sends the plurality of first transmission buffer amounts, the plurality of time stamps, and the plurality of packets to the first transmission buffer amount buffer 205, the time stamp buffer 204, and the first reception buffer 203, respectively. Output.
  • the first reception buffer 203 is composed of a FIFO buffer, and temporarily accumulates input packets.
  • the packet output from the first reception buffer 203 is output from the output terminal 212 to the outside.
  • the time stamp buffer 204 is composed of a FIFO buffer and temporarily accumulates the inputted time stamp.
  • the first transmission buffer amount buffer 205 is formed of a FIFO buffer, and temporarily accumulates the input first transmission buffer amount.
  • the first reception buffer amount reading unit 206 reads the accumulated amount of packets of the first reception buffer 203 (hereinafter referred to as the first reception buffer amount), and outputs the read first reception buffer amount to the accumulated amount calo calculation unit 207.
  • the first reception buffer amount is the value immediately before the packet to which the first transmission buffer amount output from the first transmission buffer amount buffer 205 is output to the accumulation amount addition unit 207 is read from the first reception buffer 203. It is a direct storage of packets in the first receive buffer 203.
  • the accumulation amount addition unit 207 adds the first transmission buffer amount extracted from the first transmission buffer amount buffer 205 and the first reception buffer amount input from the first reception buffer amount reading unit 206. Since the first reception buffer 203 and the first transmission buffer amount buffer 205 are composed of FIFO buffers, the first transmission buffer amount taken out of the first transmission buffer amount buffer 205 is read from the first reception buffer 203. The first transmission buffer amount that has been added to the
  • the correction unit 208 controls the count speed of the reception time stamp timer 209 so that the added value input from the accumulated amount addition unit 207 becomes constant.
  • correction section 208 outputs a control signal for instructing to increase the count speed to reception time stamp timer 209. Do.
  • the correction unit 208 outputs a control signal for instructing to decrease the momentum speed to the reception time stamp timer 209.
  • the reception time stamp timer 209 instructs to decrease the count speed and the control signal to increase the count speed. If it is, increase the counting speed.
  • the count value of transmission time stamp timer 102 and the count value of reception time stamp timer 209 are viewed at the same time, the count value of reception time stamp timer 209 is fixed delay time from the count value of transmission time stamp timer 102.
  • the reception time stamp timer 209 is preset so as to be smaller by the count value corresponding to. Note that one configuration example of the reception time stamp timer 209 will be described later with reference to FIG.
  • the comparison unit 210 compares the count value indicated by the time stamp to which the time stamp buffer 204 is also input, and the count value input from the reception time stamp timer 209, and when both match, the packet read out unit A packet read signal for instructing the reading of the packet to 211 is output. Since the first reception buffer 203 and the time stamp buffer 204 are composed of F IFO buffers, the time stamp extracted from the time stamp buffer 204 is added to the packet read from the first reception buffer 203. Become a time stamp.
  • the packet read unit 211 receives the packet read signal from the comparison unit 210 and causes the first reception buffer 203 to output one packet.
  • FIG. 5 is a block diagram of the reception time stamp timer 209 of FIG.
  • the reception time stamp timer 209 includes a variable frequency oscillator 209a, a counter 209b, a control terminal 209c, a count value output terminal 209d, an initial value input terminal 209e, and a clock output terminal 209f.
  • the variable frequency oscillator 209a is an oscillator capable of oscillating a frequency within a predetermined range, supplies a clock signal of the oscillated frequency to the counter 209b, and outputs the clock signal to the outside from the clock output terminal 209f.
  • variable frequency oscillator 209 a increases the oscillation frequency and instructs the control signal to lower the count speed. If so, lower the oscillation frequency.
  • the counter 209b takes out the time stamp stored in the time stamp buffer 204 from the time stamp buffer 204 through the input terminal 209e, and is preset based on the count value indicated by the taken time stamp.
  • counter 209b Since the packet input to transmitting apparatus 100 is sent for the fixed transmission delay time and output from receiving apparatus 200, counter 209b sets the offset corresponding to the fixed transmission delay time to counter 102b. It is necessary to keep and output the count value. Therefore, when the count value of force counter 102b and the count value of counter 209b are viewed at the same time, the counter value of counter 209b is smaller than the count value of counter 102b by the count value corresponding to the fixed delay time. Is preset.
  • the counter 209b counts the clock signal oscillated by the variable frequency oscillator 209a, and outputs the count value to the outside from the count value output terminal 209d.
  • the count value output from the count value output terminal 102 c is supplied to the comparison unit 210.
  • the counter 209b preset as described above counts the clock signal oscillated by the variable frequency oscillator 209a, and outputs the count value to the comparison unit 210 from the count value output terminal 209d.
  • Comparing section 210 compares the count value indicated by the time stamp extracted from time stamp buffer 204 with the count value input from reception time stamp timer 209, and if both match, packet reading section 211 is compared. Output a packet read signal.
  • the packet read unit 211 receives the packet read signal from the comparison unit 210 and causes the first reception buffer 203 to output one packet.
  • the packet is recovered on the time axis, and the packet is It can be said that the power is also input to the transmitter 100 and the power is also output from the receiver 200 with a delay of transmission fixed delay time.
  • output control of the buckett from the receiver 200 is performed using a count value obtained by counting a finite frequency. Therefore, when the clock signal used for counting in the transmission time stamp timer 102 and the reception time stamp timer 209 is asynchronous with the processing clock signal, the packet is counted in the transmission time stamp timer 102 and the reception time stamp timer 209.
  • the signal is output from the receiver 200 including residual jitter of 1 to 2 clocks of the clock signal to be used.
  • the first reception buffer amount reading unit 206 reads the first reception buffer amount of the first reception buffer 203, and outputs the read first reception buffer amount to the accumulation amount addition unit 207.
  • the accumulation amount calo calculation unit 207 takes out the first transmission buffer amount from the first transmission buffer amount buffer 205.
  • the accumulation amount addition unit 207 adds the first transmission buffer amount fetched from the first transmission buffer amount buffer 205 and the first reception buffer amount inputted from the first reception buffer amount reading unit 206.
  • correction section 208 outputs a control signal for instructing reception time stamp timer 209 to increase the counting speed, and reception time stamp timer 209 receives this control signal. Receive and increase the counting speed.
  • Correction section 208 outputs a control signal for instructing to decrease the counting speed to reception time stamp timer 209 if the addition result decreases, and reception time stamp timer 209 receives this control signal. Reduce the counting speed.
  • the transmitting device even if the input bit rate of the packet input to the transmitting device is a variable bit rate and the transmission bit rate in the transmission path is a fixed bit rate, the transmitting device It is possible to realize synchronous transmission between a and a receiver.
  • the storage amount of data including at least one of the time stamp and the transmission buffer amount may be used.
  • the oscillation frequency of the variable frequency oscillator 209 a is controlled to make the count speed of the reception time stamp timer 209 variable.
  • the configuration is such that the count speed of the reception time stamp timer 209 can be made variable by changing the direction of counting of the counter 209b while fixing a certain oscillation frequency.
  • a function is added to the first embodiment to realize synchronous transmission between the transmitting device and the receiving device even if there is a missing packet on the transmission path.
  • FIG. 6 is a block diagram of a synchronous transmission system according to this embodiment.
  • the transmitter 100 a and the receiver 200 a transmit and receive packets via the transmission path 300.
  • the packet input to the transmission device 100a is a fixed length packet.
  • the transmitter 1 OOa has a configuration in which a sequence number generator 121 and a sequence number adder 122 are added to the transmitter 100 of the first embodiment.
  • Sequence number generation unit 121 generates a sequential number (hereinafter referred to as a sequence number) from value “1”, and supplies the generated sequence number to sequence number addition unit 122.
  • the sequence number attachment unit 122 attaches the sequence number supplied from the sequence number generation unit 121 to the head of the combined packet output from the first transmission buffer 105.
  • the time stamped character encoding unit 103 adds the count value supplied from the transmission time stamp timer 102 as the time stamp at the beginning of the packet
  • the first transmission buffer amount adding unit 104 adds the first transmission buffer amount read by the first transmission buffer amount reading unit 106 to the head of the packet to which the time stamp is added.
  • the packet to which the time stamp and the first transmission buffer amount are added is accumulated in the first transmission buffer 105.
  • the first transmission buffer 105 outputs a combined packet obtained by combining a fixed number of packets.
  • the sequence number adding unit 122 adds the sequence number supplied from the sequence number generation unit 121 to the beginning of the combined packet output from the first transmission buffer 105.
  • the combined packet to which the sequence number is added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300.
  • the receiving device 200a has a configuration in which a packet loss detecting unit 221 and a buffer amount correcting unit 222 are added to the receiving device 200 of the first embodiment, and a separating unit 202a is provided instead of the separating unit 202. .
  • the separation unit 202a separates the combined packet to which the sequence number input from the reception processing unit 201 is added into a sequence number, a plurality of first transmission buffer amounts, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202a transmits the sequence number, the plurality of first transmission buffer amounts, the plurality of time stamps, and the plurality of packets to the packet loss detection unit 221, the first transmission buffer amount buffer 205, and the time stamp buffer 204, respectively. , And output to the first reception knob 203.
  • the packet loss detection unit 221 based on the sequence number input from the separation unit 202a, is missing on the transmission path between the received combined packet and the combined packet received immediately before that.
  • the number of combined packets is detected, and the number of detected combined packets is output to the buffer amount correction unit 222.
  • a configuration example of the packet loss detection unit 221 will be described later with reference to FIG.
  • the knock out amount correction unit 222 uses the number of missing packets input from the packet missing portion 221 and associates it with the sequence number to “missing” (the combination to which the relevant sequence number is added. Indicates that the packet could not be received. Or “receive” (indicate that the combined packet with the corresponding sequence number has been received).
  • the buffer amount correction unit 222 counts the number of packets output from the first reception buffer 203, and identifies which sequence number the next output packet corresponds to, Among the sequence numbers after the identified sequence number, specify the number of sequence numbers whose associated value is "missing".
  • the knock out amount correction unit 222 multiplies the number of sequence numbers by the number of packets making up the combined packet, and further multiplies the product value by the packet data size. This is the amount of data (hereinafter referred to as a dropout amount) of packets dropped on the transmission path that would otherwise have been accumulated in the first reception buffer 203.
  • the buffer amount correction unit 222 adds the addition value input from the accumulated amount addition unit 207 and the calculated missing amount, and outputs the addition value to the correction unit 208.
  • the correction unit 208 uses the addition value input from the buffer amount correction unit 222 instead of using the addition value of the accumulation amount addition unit 207, and is input from the buffer amount correction unit 222.
  • the count speed of the reception time stamp timer 209 is controlled so that the added value becomes constant.
  • the correction unit 208 outputs a control signal for instructing to increase the count speed to the reception time stamp timer 209.
  • the reception time stamp timer 209 receives this control signal to increase the counting speed.
  • the correction unit 208 sends a control signal to the reception time stamp timer 209 to instruct to decrease the velocity. Output. Receiving time stamp timer 209 receives this control signal to reduce the counting speed.
  • the amount of packets accumulated in the first transmission buffer 105 (the amount of first transmission buffer) and the amount of packets accumulated in the first reception buffer 203 (the first amount of reception buffer)
  • the count speed of the reception time stamp timer 209 is adjusted so that the sum of the amount of dropped packets on the transmission path which should be accumulated in the first reception buffer 203 becomes constant.
  • the time axis restoration process performed by the receiving device 200a is substantially the same as the time axis restoration process of the first embodiment, and thus the description thereof is omitted.
  • FIG. 7 is a block diagram of the packet loss detection unit 221 of FIG.
  • the packet loss detection unit 221 includes a storage unit 221a, an addition unit 221b, a subtraction unit 221c, an input terminal 221d, and an output terminal 221e.
  • the storage unit 221a stores 0 in the initial state.
  • the storage unit 221 a stores the sequence number, and stores the sequence number stored immediately before (the value “0” when the sequence number is first input). It outputs to the addition part 221b.
  • the addition unit 221b adds 1 to the value input from the storage unit 221a, and outputs the addition value to the subtraction unit 221c.
  • the subtraction unit 221c subtracts the addition value input from the addition unit 221b from the sequence number input from the input terminal 221d, and outputs the subtraction value from the output terminal 221e to the buffer amount correction unit 222.
  • the subtraction value obtained by the subtraction unit 221c is the combined packet to which the sequence number currently input to the input terminal 22 Id is added, and the one immediately before the sequence number currently input to the input terminal 22 Id. It shows the number of combined packets lost with the combined packet with the sequence number input to the input terminal 221d.
  • the input bit rate of the packet input to the transmitting device is To realize synchronous transmission between a transmitting device and a receiving device even if packets are dropped on the transmission path when the bit rate is variable and the transmission bit rate in the transmission path is a fixed bit rate. Can.
  • the bit rate of the packet input to the transmitter is a variable bit rate
  • the transmission bit rate in the transmission path is a fixed bit rate.
  • the target is on the other hand, in the present embodiment and the fourth embodiment described later, the input bit rate of the packet input to the transmitter is a variable bit rate, and the transmission bit rate in the transmission path is a fixed bit rate. The case is
  • FIG. 8 is a block diagram of a synchronous transmission system according to the present embodiment.
  • the transmission device 100b and the reception device 200b transmit and receive packets via the transmission path 300b.
  • the transmission line 300 b is, for example, a wireless transmission line.
  • FIG. 9 is a time transition diagram of bit rates and packet storage amounts of the synchronous transmission system of FIG.
  • the input bit rate of the packet input to the second transmission buffer 105 b of the transmitting device 100 b is a fixed bit rate, and its function is f 2 (t). Also, the transmission bit rate in the transmission line is a variable bit rate, and its function is g2 (t).
  • the output bit of the packet output from the second reception buffer 203b The rate is controlled to be equal to the input bit rate of the packet input to the second transmission buffer 105b. From this, if the delay time until the packet is input to the transmitting device 100b and the force is also output from the receiving device 2 OOb is represented by delay, the output bit rate of the packet output from the first receiving buffer 203b is a rate function It becomes f2 (t-delay).
  • (1) start writing of the packet to the second transmission buffer 105b at time 0, (2) start reading of the packet from the second transmission buffer 105b at time tO, and the second reception buffer The writing of the packet to 203b is started, and (2) the second reception buffer 203b starts to read the packet at time tl ( delay).
  • the function f2 (t) is c (c is a constant value), and the function g2 (t) is 0 until time tO and is a fluctuation value after time tO (Fig. 9 (a)).
  • Buf f Tx2 (t)-(t) dt ⁇ ⁇ ⁇ -(6) Assuming that the accumulation function representing the accumulation of packets in the second reception buffer 203b at time t is Buff Rx2 (t), the accumulation function BuffRx2 (t) at time t after time tl is given by the following number (7) It is represented ( Figure 9 (b)).
  • the accumulated amount of packets in the second transmission buffer 105b immediately after a certain packet is read from the second transmission buffer 105b, and the second reception immediately after the certain packet is written to the second reception buffer 203b.
  • the sum of the accumulated amount of packets in the buffer 203b is constant.
  • the amount of stored packets in the second transmission buffer 105b immediately before a certain packet is read out from the second transmission buffer 105b, and the packet in the second reception buffer 203b immediately before the certain packet is written to the second reception buffer 203b.
  • the sum with the accumulated amount of is constant.
  • the present embodiment implements synchronous transmission between transmitting apparatus 100b and receiving apparatus 200b, using the above relationship.
  • the accumulation amount of packets in the second transmission buffer 105b immediately after a certain packet is read out from the second transmission buffer 105b and the second accumulated amount immediately after the certain packet is written to the second reception buffer 203b.
  • the sum of the storage amount of packets in the reception buffer 203b is used.
  • the stored amount of packets in the second transmission buffer 105b immediately before a certain packet is read out to the second transmission buffer 105b, and the second reception buffer 203b just before the certain packet is written to the second reception buffer 203b. You can use the sum of the amount of data stored in.
  • the transmitting apparatus 100b includes an input terminal 101, a transmission time stamp timer 102, a time stamp attaching unit 103, a second transmission buffer 105b, a second transmission buffer amount reading unit 106b, and a second transmission buffer amount attaching unit 104b. And the transmission processing unit 107.
  • the second transmission buffer 105 b is composed of a FIFO buffer, temporarily accumulates input packets, and outputs the accumulated packets at a variable bit rate. In addition, in order to improve transmission efficiency, the second transmission buffer 105 b combines a plurality of packets and combines the combined packets ( Output combined packet).
  • the second transmission buffer amount reading unit 106 b reads the accumulated amount of packets in the second transmission buffer 105 b (hereinafter referred to as the second transmission buffer amount), and the second transmission buffer amount read out is referred to as the second transmission. Output to buffer amount adding section 104 b.
  • the second transmission buffer amount is the second transmission buffer immediately after the target packet to which the second transmission buffer amount is added by the second transmission buffer amount adding unit 104b is read from the second transmission buffer 105b.
  • 105b is the accumulated amount of packets.
  • the second transmission buffer amount is assumed to be the data accumulation amount of the second transmission buffer 105 b excluding the data amount related to the time stamp in order to facilitate the processing in the receiving device 200.
  • the second transmission buffer amount can be calculated, for example, as follows. Fix the timestamp data size. The data size of the time stamp is multiplied by the number of packets stored in the second transmission buffer 105 b (the number of packets input minus the number of packets output). The actual accumulation amount of the second transmission buffer 105b is multiplied by the multiplication value. This subtraction value becomes the second transmission buffer amount.
  • the second transmission buffer amount adding unit 104b adds the second transmission buffer amount input from the second transmission buffer amount reading unit 106b to the head of the combined packet input from the second transmission buffer 105b.
  • the timestamp attachment section 103 appends the count value supplied from the transmission timestamp timer 102 to the beginning of the packet as a timestamp ( N302).
  • the packet to which the time stamp is added is stored in the second buffer 105 b.
  • the second transmission buffer 105 b outputs the combined packet (N 303).
  • the second transmission buffer amount adding unit 104b adds the second transmission buffer amount read by the second transmission buffer amount reading unit 106b to the head of the combined packet (N304).
  • the combined packet to which the second transmission buffer amount has been added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300b.
  • the receiver 200b performs time axis restoration processing and rate control processing which are conditions of synchronous transmission. And the like, the reception processing unit 201, the separation unit 202b, the second reception buffer 203b, the time stamp buffer 204, the second reception buffer amount reading unit 206b, the accumulation amount addition unit 207b, the correction unit 208b, and the like. And a reception time stamp timer 209, a comparison unit 210, a packet reading unit 211, and an output terminal 212.
  • the separation unit 202b separates the combined packet added with the second transmission buffer amount input from the reception processing unit 201 into a second transmission buffer amount, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202b outputs the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the accumulation amount addition unit 207b, the time stamp buffer 204, and the second reception buffer 203b, respectively.
  • the second reception buffer 203 b is formed of a FIFO buffer, and temporarily accumulates an input packet.
  • the packet output from the second receive buffer 203b is also output to the outside through the output terminal 212 (N305 in FIG. 10).
  • the second reception buffer amount reading unit 206b reads the accumulated amount of packets in the second reception buffer 203b (hereinafter referred to as the second reception buffer amount), and outputs the read second reception buffer amount to the accumulated amount addition unit 207b. Do.
  • the second reception buffer amount a plurality of packets constituting the combined packet to which the second transmission buffer amount output from the separation unit 202b to the accumulation amount calo calculation unit 207b has been added is transmitted to the second reception buffer 203b. It is the accumulation amount of the packet of the 2nd reception buffer 203b immediately after being written.
  • the accumulation amount addition unit 207 b adds the second transmission buffer amount input from the separation unit 202 b and the second reception buffer amount input from the second reception buffer amount readout unit 206 b.
  • the second transmission buffer amount added to the combined packet obtained by combining the plurality of written packets is the same. It is input from the separation unit 202b to the accumulated amount addition unit 207b.
  • the correction unit 208 b controls the count speed of the reception time stamp timer 209 so that the addition value of the storage amount addition unit 207 b becomes constant.
  • the correction unit 208b A control signal for instructing to increase the speed is output to reception time stamp timer 209.
  • the correction unit 208b outputs a control signal for instructing to decrease the count speed to the reception time stamp timer 209.
  • the time axis restoration process performed by the receiving device 200b is substantially the same as the time axis restoration process described in the first embodiment, and thus the description thereof is omitted.
  • the second reception buffer amount reading unit 206b reads the second reception buffer amount of the second reception buffer 203b, and outputs the read second reception buffer amount to the accumulation amount addition unit 207b.
  • the second transmission buffer amount is input to the accumulation amount addition unit 207 b from the separation unit 202 b.
  • the accumulation amount addition unit 207 b adds the second transmission buffer amount input from the separation unit 202 b and the second reception buffer amount input from the second reception buffer amount reading unit 206 b.
  • correction section 208 b outputs a control signal for instructing reception time stamp timer 209 to increase the counting speed, and reception time stamp timer 209 receives this control signal. Increase the counting speed.
  • Correction section 208 outputs a control signal for instructing to decrease the counting speed to reception time stamp timer 209 if the addition result decreases, and reception time stamp timer 209 receives this control signal. Reduce the counting speed.
  • the transmitting apparatus even if the input bit rate of the packet input to the transmitting apparatus is a fixed bit rate and the transmission bit rate in the transmission path is a variable bit rate, the transmitting apparatus It is possible to realize synchronous transmission between a and a receiver.
  • the amount of data storage is used.
  • the storage amount of packets including time stamps is not limited to this. May be used.
  • a function is added to the third embodiment for realizing synchronous transmission between the transmitting apparatus and the receiving apparatus even if there is a missing packet on the transmission path.
  • FIG. 11 is a block diagram of a synchronous transmission system according to the present embodiment.
  • the transmitting device 100c and the receiving device 200c transmit and receive packets via the transmission path 300d. It is assumed that the packet input to the transmission device 100b is a fixed-length packet.
  • the transmitting apparatus 100c has a configuration in which a sequence number generating section 121 and a sequence number adding section 122 are added to the transmitting apparatus 100b of the third embodiment.
  • the time stamped carover section 103 adds the count value supplied from the transmission time stamp timer 102 to the beginning of the packet as a time stamp.
  • the packet to which the time stamp is added is accumulated in the second buffer 105 b.
  • the second transmission buffer 105 b outputs a combined packet obtained by combining a certain number of packets.
  • the second transmission buffer amount adder 104b adds the second transmission buffer amount read by the second transmission buffer amount reader 106b to the head of the combined packet, and the sequence number adder 122 adds the second transmission buffer amount.
  • the sequence number supplied from the sequence number generation unit 121 is added to the beginning of the combined packet to which is added.
  • the combined packet to which the sequence number and the second transmission buffer amount have been added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300b.
  • the receiving apparatus 200c has a configuration in which a packet loss detecting unit 221 and a buffer amount correcting unit 222 are added to the receiving apparatus 200 of the third embodiment, and a separating unit 202c is provided instead of the separating unit 202b. .
  • the separation unit 202c separates the combined packet, to which the sequence number and the second transmission buffer amount are input from the reception processing unit 201, into a sequence number, a second transmission buffer amount, a plurality of time stamps, and a plurality of packets. Do. Then, the separation unit 202c transmits the sequence number, the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the packet loss detection unit 221, the storage amount addition unit 207b, the time stamp buffer 204, and the second packet. 2 Output to the receive buffer 203b.
  • the rate control process performed by the receiving device 200c is as follows.
  • the second reception buffer amount reading unit 206b reads the second reception buffer amount of the second reception buffer 203b immediately after the separation unit 202c writes a plurality of packets forming one combined packet in the second reception buffer 203b.
  • the read second reception buffer amount is output to the accumulation amount calo calculating unit 207b.
  • the packet loss detection unit 221 detects the number of coupled packets lost on the transmission path using the sequence number input from the separation unit 202c.
  • the number of combined packets detected is output to the buffer amount correction unit 222.
  • the accumulation amount addition unit 207 b adds the second transmission buffer amount input from the separation unit 202 c and the second reception buffer amount input from the second reception buffer amount reading unit 206 b.
  • the packet amount correction unit 222 is a packet that forms a missing combined packet on the transmission path, which should be originally stored in the second reception buffer 203b. Calculate the amount of data (missing packet amount) of Then, the buffer amount correction unit 222 adds the calculated missing packet amount to the addition value input from the accumulation amount addition unit 207b.
  • the correction unit 208 b controls the count speed of the reception time stamp timer 209 based on the addition value input from the buffer amount correction unit 222 so that the addition value becomes constant.
  • the correction unit 208 b outputs a control signal for instructing to increase the count speed to the reception time stamp timer 209.
  • Reception time stamp timer 209 receives this control signal to increase the counting speed
  • the correction unit 208b outputs a control signal for instructing to decrease the count speed to the reception time stamp timer 209. Receiving time stamp timer 209 receives this control signal to reduce the counting speed.
  • the time axis restoration process performed by the receiving device 200c is substantially the same as the time axis restoration process of the first embodiment, and thus the description thereof is omitted.
  • the packet on the transmission path is Even if L is missing, synchronous transmission can be realized between the transmitting device and the receiving device.
  • the first embodiment and the second embodiment are directed to the case where the bit rate of the packet input to the transmission apparatus is a variable bit rate and the transmission bit rate in the transmission path is a fixed bit rate.
  • the bit rate of the packet input to the transmitter is a fixed bit rate
  • the transmission bit rate in the transmission path is a variable bit rate.
  • the target is on the other hand, in this embodiment and the sixth to seventh embodiments described later, the bit rate of the packet input to the transmitter is a variable bit rate, and the transmission bit rate in the transmission path is variable. The case of bit rate is considered.
  • FIG. 12 is a block diagram of a synchronous transmission system of the present embodiment.
  • the transmitting device lOOod and the receiving device 200d transmit and receive packets via the transmission path 300b.
  • the transmitter lOOd includes an input terminal 101, a first transmitter 150, and a second transmitter 160.
  • the first transmission unit 150 has the same configuration as the block excluding the input terminal 101 of the transmission apparatus 100 according to the first embodiment and the transmission processing unit 107, and receives packets input at a variable bit rate. Output to the second transmission unit 160 at a fixed bit rate.
  • the output control at a fixed bit rate from the first transmission buffer 105 of the packet is, for example, in the case of MPEG2 TS, the stream rate is extracted from the stream header, and the extracted stream rate is added to the input packet. This can be realized by outputting a packet at a rate corresponding to data corresponding to overhead data of the stamp and the first transmission buffer amount.
  • the second transmission unit 160 has the same configuration as the block excluding the input terminal 101 of the transmission device 100b of the third embodiment, the transmission time stamp timer 102, and the time stamp attached portion 103. (1) Transmit a packet input from the transmitting unit 150 at a fixed bit rate to the transmission path 300b at a variable bit rate.
  • the timestamp attachment section 103 appends the count value supplied from the transmission timestamp timer 102 to the beginning of the packet as a timestamp ( N 502) Further, the first transmission buffer amount appending unit 104 adds the first transmission buffer amount read by the first transmission buffer amount reading unit 106 to the beginning of the packet to which the time stamp is added (N 503) .
  • the packet to which the time stamp and the first transmission buffer amount are added is accumulated in the first transmission buffer 105.
  • the packets accumulated in the first transmission buffer 105 are output from the first transmission buffer 105 at a fixed bit rate, and accumulated in the second transmission buffer 105 b.
  • the second transmission buffer 105 b outputs a combined packet obtained by combining a plurality of packets (N 504 ).
  • the second transmission buffer amount adder 104b adds the second transmission buffer amount read by the second transmission buffer amount reader 106b to the head of the combined packet (N505).
  • the combined packet to which the second transmission buffer amount is added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300b.
  • the receiver 200 d includes a second receiver 260, a first receiver 250, and an output terminal 212.
  • the second receiving unit 260 performs substantially the same rate control processing as the rate control processing performed by the receiving device 200b. However, the second receiving unit 260 does not perform the time axis restoration process performed by the receiving device 200b. It is sufficient for the second receiving unit 260 not to perform time-axis restoration processing if it is restored on the time-axis when a packet is output from the receiving device 200 d, and the second receiving unit 260 performs the first transmission unit 150. It is sufficient if the packet can be output to the first receiver 250 at a fixed bit rate equal to the fixed bit rate output to the second transmitter 160.
  • the second reception unit 260 includes a reception processing unit 201, a separation unit 202d, a second reception buffer 203b, a second reception buffer amount reading unit 206b, a storage amount addition unit 207b, a correction unit 208b, and a read rate control unit. And 251.
  • the separation unit 202d is configured to receive the combined packet to which the second transmission buffer amount input from the reception processing unit 201 is added, the plurality of first transmission buffer amounts, the second transmission buffer amount, the plurality of time stamps, and the plurality of packets. To separate. Then, the separation unit 202d is configured to transmit the plurality of first transmission buffer amounts, the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the first transmission buffer amount buffer 205, the accumulation amount addition unit 207b, and the time stamp. Output to the buffer 204 and the second reception buffer 203b.
  • the correction unit 208 b of the present embodiment controls the oscillation frequency of the variable frequency oscillator 209 a of the reception time stamp timer 209 instead of controlling the oscillation frequency of the variable frequency oscillator 25 la described later provided in the read rate control unit 251. Control as described later.
  • the read rate control unit 251 controls the output bit rate of the packet from the second reception buffer 203b.
  • the rate control process performed by the second receiving unit 260 is as follows.
  • the correction unit 208 b is configured to read the second packet immediately after the combined packet is read from the second transmission buffer 105 b.
  • 2 Packet accumulation amount of the transmission buffer 105 b (the second transmission buffer amount input from the separation unit 202 d), and the second of the second reception buffer 203 b immediately after the plurality of packets constituting the combined packet are written.
  • Adds the packet accumulation amount of the reception buffer 203b (the second reception buffer amount read by the second reception buffer amount reading unit 206b and input from the second reception buffer amount reading unit 206b), and the addition value is constant
  • the rate control of the read rate control unit 251 is performed so that
  • the correction unit 208b outputs a control signal for instructing to increase the output bit rate to the read rate control 251.
  • the correction unit 208b outputs a control signal for instructing to reduce the output bit rate to the read rate control 251.
  • the read rate control unit 251 controls the output bit rate of the packet from the second reception buffer 203b based on the control signal from the correction unit 208b.
  • FIG. 14 is a block diagram of the read rate control unit 251 of FIG.
  • the read rate control unit 251 includes a variable frequency oscillator 25 la, a! ⁇ Read unit 2511 ) , a control signal input terminal 251c, a read signal output terminal 251d, and a clock output terminal 251e.
  • the variable frequency oscillator 25 la is an oscillator capable of oscillating a clock signal of a predetermined range of frequency and supplies a clock signal of the oscillated frequency to the counter 209 b and outputs the clock signal to the clock output terminal 251 e. Do.
  • variable frequency oscillator 251a raises the oscillation frequency when the control signal input to the control terminal 209c instructs to increase the read rate at which packets are read from the second receive buffer 203b, and the variable frequency oscillator 251a increases the oscillation frequency.
  • Control signal reads packet from second receive buffer 203b If it is instructed to lower the read rate to be used, the oscillation frequency is lowered.
  • the CBR reading unit 251b is configured by a counter that counts the clock signal input from the variable frequency oscillator 251a, and generates a reading signal by counting a fixed number of clock signals.
  • the CBR read unit 251 outputs the generated read signal from the read signal output terminal 25 Id to the second reception buffer 203b.
  • the second reception buffer 203 b receives the read signal and outputs one stored packet to the first reception buffer 203.
  • the first receiving unit 250 has the same configuration as the block excluding the reception processing unit 201, the separation unit 202, and the output terminal 212 of the receiving device 200 according to the first embodiment. doing.
  • the first reception unit 250 performs time axis restoration processing and rate control processing that are substantially the same as the time axis restoration processing and rate control processing of the reception device 200 according to the first embodiment.
  • the rate control process performed by the first receiver 250 is as follows.
  • the correction unit 208 stores the accumulated amount of packets in the first transmission buffer 105 immediately before the packet is written to the first transmission buffer 105 (the first transmission buffer amount buffer 205 fetches the first (1 transmission buffer amount) and the accumulated amount of packets in the first reception buffer 203 immediately before the packet is read from the first reception buffer (the first reception buffer amount is read by the first reception buffer amount reading unit 206, and the first reception buffer amount
  • the oscillation frequency of the variable oscillation frequency unit 209a of the reception time stamp timer 209 is controlled so as to add the first reception buffer amount) input from the reading unit 206 and make the addition value constant.
  • correction section 208 controls variable frequency oscillator 209a to increase the oscillation frequency of variable frequency oscillator 209a if the added value is increased!], And the added value may be decreased.
  • the variable frequency oscillator 209a is controlled to lower the oscillation frequency of the variable frequency oscillator 209a.
  • the time axis restoration process performed by the first reception unit 250 is as follows.
  • variable frequency oscillator 209a of the reception time stamp timer 209 oscillates at a frequency controlled by the correction unit 208, and the counter 209b counts clock signals of the frequency oscillated by the variable frequency oscillator 209a.
  • Comparison unit 210 compares the count value indicated by the time stamp extracted from time stamp buffer 204 with the count value of counter 209 b, and if both match, the packet read signal Are output to the packet reading unit 211.
  • the packet read unit 211 receives the packet read signal from the comparison unit 210 and outputs one packet from the first reception buffer 203. As a result, one packet is output from the first reception buffer 203, and the packet output from the first output buffer 203 is output from the output terminal 212 to the outside.
  • the transmitting device Even if the input bit rate of the packet input to the transmitting device is a variable bit rate and the transmission bit rate in the transmission path is a variable bit rate, the transmitting device It is possible to realize synchronous transmission between a and a receiver.
  • the sixth embodiment simplifies the configuration of the transmitting apparatus lOOd and the receiving apparatus 200d of the fifth embodiment, and both the input bit rate and the transmission bit rate are variable bit rates. Is also able to realize synchronous transmission.
  • FIG. 15 is a block diagram of a synchronous transmission system according to the present embodiment.
  • the transmitting apparatus 100e and the receiving apparatus 200e transmit and receive packets via the transmission path 300b.
  • the transmitting apparatus 100e includes an input terminal 101, a first transmitting unit 150e, and a second transmitting unit 160e having the same configuration as the second transmitting unit 160 of the fifth embodiment.
  • the first transmission unit 150e temporarily accumulates the packets input at the transmission time stamp timer 102, the time stamp addition unit 103, and the variable bit rate, and outputs the accumulated packets at the fixed bit rate. It has part 105.
  • the output control at a fixed bit rate of the first transmission buffer 105 power of the packet is It is realized by extracting the stream rate from the streamer and outputting the stream at a rate corresponding to the data of the overhead portion of the timestamp added to the input packet to the extracted stream rate. be able to.
  • the time stamped carover unit 103 adds the count value supplied from the transmission time stamp timer 102 to the beginning of the packet as a time stamp.
  • the packet to which the time stamp is added is accumulated in the first transmission buffer 105.
  • the packets accumulated in the first transmission buffer 105 are output from the first transmission buffer 105 at a fixed bit rate, and accumulated in the second transmission buffer 105 b.
  • the second transmission buffer 105 b outputs a combined packet obtained by combining a plurality of packets.
  • the second transmission buffer amount adder 104b adds the second transmission buffer amount read by the second transmission buffer amount reader 106b to the head of the combined packet.
  • the combined packet to which the second transmission buffer amount has been added is subjected to predetermined processing by the transmission processing unit 107, and is sent out to the transmission path 300b.
  • the receiver 200e includes a second receiver 260e, a first receiver 250e, and an input terminal 221. Similar to the second receiver 260, the second receiver 260e performs substantially the same rate control processing as the rate control processing performed by the receiver 200b, but does not perform time-base recovery processing performed by the receiver 200b.
  • the second receiving unit 260 e has a configuration in which the separating unit 202 d is replaced with a separating unit 202 e in the second receiving unit 260 according to the fifth embodiment.
  • the separation unit 202e separates the packet input from the reception processing unit 201 into a second transmission buffer amount, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202d outputs the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the accumulation amount addition unit 207b, the time stamp buffer 204, and the second reception buffer 203b.
  • the rate control process performed by the second receiving unit 260e is substantially the same as the rate control process performed by the second receiving unit 260 according to the fifth embodiment, and thus the description thereof is omitted.
  • the read rate control unit 251 causes the correction unit 208 b to oscillate.
  • the clock signal generated by the variable frequency oscillator 251a whose frequency is controlled is output to the reception time stamp timer 209e via the clock output terminal 25le.
  • the first receiving unit 250e performs a time axis reconstruction process substantially the same as the time axis reconstruction process performed by the receiving device 200. However, the first reception unit 250 e does not perform the rate control process performed by the reception device 200.
  • the reason for not performing the rate control process in the first receiver 250 e is as follows.
  • the second receiver 260 e is performing rate control processing. Therefore, the frequency of the clock signal output from the read rate controller 251 of the second receiver 260 is adjusted to be the frequency of the clock signal oscillated by the oscillator 102a of the transmission time stamp timer 102. Therefore, if the clock signal output from the read rate control unit 251 is used, the clock signal adjusted to have the frequency of the clock signal oscillated by the oscillator 102a of the transmission time stamp timer 102 in the first receiving unit 250e. There is no need to generate.
  • the first reception unit 250 e includes a reception time stamp timer 209 e, a comparison unit 210, a packet read unit 211, and a first reception buffer 203.
  • the reception time stamp timer 209 e has a counter that counts the clock signal input from the read rate control unit 251, and outputs the count value of the counter to the comparison unit 210.
  • the counter possessed by the reception time stamp timer 209e is preset by the same procedure as the counter 209b of the reception time stamp timer 209.
  • the reception time stamp timer 209e has a variable frequency oscillator like the reception time stamp timer 209, and so on.
  • the time axis reconstruction performed by the first reception unit 250e is as follows.
  • the preset reception time stamp timer 209 e counts the clock signal input from the read rate control unit 251, and outputs the count value to the comparison unit 210.
  • the comparison unit 210 compares the counter value indicated by the time stamp extracted from the time stamp buffer 204 with the counter value input from the reception time stamp timer 209e, and if both match, the packet read signal is read out Output to section 211.
  • the packet read unit 211 receives the packet read signal and causes the first reception buffer 203 to output one packet.
  • the transmission bit rate of the packet input to the transmission device can be changed by the transmission device and the reception device with a simple configuration. Even if the transmission bit rate in the transmission path is a variable bit rate, synchronous transmission can be realized between the transmitting device and the receiving device.
  • the oscillation frequency of the oscillator 102a of the transmission time stamp timer 102 and the oscillation frequency of the variable frequency oscillator 251a of the read rate control unit 251 are different, the following is performed. I see.
  • the oscillation frequency of the variable frequency oscillator 25 la is multiplied or divided by using a PLL circuit or the like, and a clock signal of the multiplied or divided frequency is supplied to the reception time stamp timer 209 e.
  • the seventh embodiment simplifies the configuration of the transmitting device lOOd and the receiving device 200d of the fifth embodiment, and synchronous transmission even if both the input bit rate and the transmission bit rate are variable bit rates. To make it possible.
  • FIG. 16 is a block diagram of a synchronous transmission system of the present embodiment.
  • the transmitting device 100f and the receiving device 200f transmit and receive packets via the transmission path 300b.
  • the transmitting apparatus 100 f includes a first transmitting unit 150 f and a second transmitting unit 160 f which have the same configuration as the input terminal 101 and the first transmitting unit 150 e of the fifth embodiment.
  • Second transmission unit 160 f includes second transmission buffer 105 b and transmission processing unit 107.
  • the time stamped carover section 103 adds the count value supplied from the transmission time stamp timer 102 to the beginning of the packet as a time stamp, and performs the first transmission.
  • the buffer amount adding unit 104 adds a time stamp
  • the first transmission buffer amount input from the first transmission buffer amount reading unit 106 is added to the beginning of the received packet.
  • the packet to which the time stamp and the first transmission buffer amount are added is accumulated in the first transmission buffer 105.
  • the packets accumulated in the first transmission buffer 105 are output from the first transmission buffer 105 at a fixed bit rate, and accumulated in the second transmission buffer 105 b.
  • the stream rate is extracted from the stream header, and the extracted stream rate This can be realized by outputting a packet at a rate corresponding to the time stamp added to the packet and data corresponding to overhead of the first transmission buffer amount.
  • the second transmission buffer 105 b outputs a combined packet obtained by combining a plurality of packets, and the combined packet output from the second transmission buffer 105 b is subjected to predetermined processing by the transmission processing unit 107, and the transmission path 300 b is transmitted to the transmission path 300 b. It is sent out.
  • the receiver 200f includes a second receiver 260f, a first receiver 250f, and an input terminal 221.
  • the second reception unit 260f includes a reception processing unit 201, a separation unit 202f, a CBR reading unit 271, and a second reception buffer 203b.
  • the separation unit 202 f separates the combined packet input from the reception processing unit 201 into a plurality of first transmission buffer amounts, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202f outputs the plurality of first transmission buffer amounts, the plurality of time stamps, and the plurality of packets to the first transmission buffer amount buffer 205, the time stamp buffer 204, and the second reception buffer 203b. .
  • the CBR reading unit 271 is configured by a counter that impresses the clock signal supplied from the reception time stamp timer 209, and generates a reading signal by counting a fixed number of clock signals.
  • the second reception buffer 203 b receives this read signal and outputs one packet to the first reception buffer 203.
  • the frequency of the clock signal input from the reception time stamp timer 209 to the CBR reading unit 209 is adjusted to the oscillation frequency of the oscillator 102 a of the transmission time stamp timer 102. Therefore, in the present embodiment, accumulation of packets in the second transmission buffer 105b is performed. There is no need to perform rate control processing using the product amount and the packet accumulation amount of the second reception buffer 203b.
  • the first receiving unit 250f has the same configuration as the first receiving unit 250 of the fifth embodiment, and performs time axis restoration processing and rate control processing.
  • the reception time stamp timer 209 outputs a clock signal oscillated by the variable frequency oscillator 209 included therein to the CBR read unit 271 from the clock output terminal 209 f.
  • the time axis restoration processing and rate control processing performed by the first reception unit 250 f are the same as the time axis restoration processing and rate control processing performed by the first reception unit 250 according to the fifth embodiment, respectively. Omit.
  • the input bit rate of the packet input to the transmitting device is variable bit rate by the transmitting device and the receiving device having a simple configuration, as compared with the fifth embodiment. And, even if the transmission bit rate in the transmission path is a variable bit rate, synchronous transmission can be realized between the transmitting device and the receiving device.
  • the input packet may be a packet related to the MPEG2 TS.
  • the transmitting device transmits the accumulated amount of packets in the transmission buffer (the first transmission buffer 105 or the second transmission buffer) from the transmitting device to the receiving device, and the receiving device utilizes this.
  • the counter speed of each provided counter is adjusted, the present invention is not limited to this, as long as the information transmitted from the transmitting device to the receiving device can be used as long as it can identify the accumulation amount of packets in the transmission buffer. .
  • the accumulation amount of packets in the transmission buffer can be obtained by subtracting the time integral value of the output rate of packets from the transmission buffer from the time integral value of the packet input rate to the transmission buffer. Is equivalent to
  • the accumulation amount of packets in the reception buffer (the first reception buffer 203 or the second reception buffer 203b) is determined by the time integral value of the input rate of the packet to the reception buffer. It is equivalent to the value obtained by subtracting the time integral value of the output rate of the force packet.
  • the input rate and output rate of the transmission buffer are measured, and the input rate and output rate of the transmission buffer are measured.
  • the force may also be sent to the receiver. In this case, the receiver measures the input rate and the output rate of the reception buffer.
  • time integral value of the output rate of the transmission buffer and the time integral value of the input rate of the reception buffer are equal, these time integral values are equal to the storage amount of the packet in the transmission buffer and received. They are mutually canceled when adding a value equivalent to the accumulated amount of packets in the buffer. Therefore, in the case of transmission from the transmitter to the receiver only at the input rate to the transmission buffer, the receiver only needs to measure the output rate of the reception buffer.
  • it may be a reception method that performs processing equivalent to all or part of the components of the transmission apparatus or the reception apparatus.
  • a program in which a processing procedure equivalent to all or a part performed by the transmission device or the reception device described in each of the above embodiments is described is stored in a memory, and processing is performed using a CPU or the like.
  • the present invention can be used for synchronous transmission between a transmitter and a receiver, and is useful, for example, for application to high-quality video transmission using a home network, such as an Internet. It can be used for stream transmission in global networks.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

A transmission device (100) outputs an accumulation amount of packets of a first transmission buffer immediately before a packet is written into the first transmission buffer (105), to a reception device (200). A first reception buffer amount read-out unit (206) of the reception device reads out the amount of the packets accumulated in the first reception buffer immediately before the packet is read out from the first reception buffer. An accumulated amount addition unit (207) adds the amount of packets accumulated in the first transmission buffer and the amount of packets accumulated in the first reception buffer. A correction unit (208) adjusts the oscillation frequency of a variable frequency oscillator of a reception time stamp timer (209) so that the added value is constant.

Description

明 細 書  Specification
送信装置、及び受信装置  Transmitter and receiver
技術分野  Technical field
[0001] 本発明は、 MPEG2トランスポートストリーム（MPEG2 TS)伝送のように、送信装置と 受信装置との間で同期伝送を行うための技術に関する。  The present invention relates to a technique for performing synchronous transmission between a transmitter and a receiver, such as MPEG2 transport stream (MPEG2 TS) transmission.
同期伝送とは、送信装置に入力されるパケットの平均ビットレートと、受信装置から 出力されるパケットの平均ビットレートとが等しぐ且つ、パケットの時間軸ジッタが所 定の範囲内となる伝送のことである。  Synchronous transmission is transmission in which the average bit rate of packets input to the transmitter is equal to the average bit rate of packets output from the receiver, and the time axis jitter of the packets is within a predetermined range. It is
背景技術  Background art
[0002] 従来、送信装置に入力されるパケットの入力ビットレートと、伝送路における伝送ビ ットレートの双方が固定ビットレート（CBR : Constant Bit Rate)であり、それらの値が 同一であることを条件とし、受信装置が備えるバッファによる伝送揺らぎ吸収制御の みで同期伝送を実現する技術がある (例えば、特許文献 1参照。 ) o  Conventionally, the condition is that both the input bit rate of a packet input to the transmitting apparatus and the transmission bit rate on the transmission path are constant bit rates (CBR: Constant Bit Rate), and their values are the same. There is a technique to realize synchronous transmission only by transmission fluctuation absorption control by a buffer provided in the receiving apparatus (see, for example, Patent Document 1) o
なお、本実施の形態の固定ビットレートとは、ある一定期間の平均ビットレートが一 定値であることを意味し、可変ビットレートとは、ある一定期間の平均ビットレートが可 変であることを意味する。  Note that the fixed bit rate in the present embodiment means that the average bit rate for a given period is a fixed value, and the variable bit rate means that the average bit rate for a given period is variable. means.
[0003] ここで、特許文献 1に開示された従来の同期伝送を実現する技術の概要について 図 17を参照しつつ説明する。図 17は従来の同期伝送を実現する受信装置の構成 図である。  Here, an outline of a technique for realizing the conventional synchronous transmission disclosed in Patent Document 1 will be described with reference to FIG. FIG. 17 is a block diagram of a receiving apparatus for realizing conventional synchronous transmission.
受信装置 1000は、伝送路力もパケットが入力される入力端子 1001と、伝送揺らぎ 吸収用のバッファ (不図示）を備える調整回路 1002と、システムデコード部 1003と、 タイムスタンプ取出回路 1004と、 PLL (Phase Looked Loop)回路 1005と、パケットを 外部へ出力するための出力端子 1006と、システムクロックを外部へ出力するための 出力端子 1007と、を備える。  Receiving apparatus 1000 also includes an input terminal 1001 to which a packet is input as transmission path power, an adjustment circuit 1002 including a buffer (not shown) for absorbing transmission fluctuation, a system decoding unit 1003, a time stamp extraction circuit 1004, PLL ( (Phase Looked Loop) circuit 1005, an output terminal 1006 for outputting a packet to the outside, and an output terminal 1007 for outputting a system clock to the outside.
[0004] ここで、調整回路 1002の伝送揺らぎ吸収用のバッファの時刻 tにおけるパケットの 蓄積量を表す蓄積量関数を BuffRX(t)とする。時刻 tにおける当該バッファに入力され るパケットの入力ビットレートを表すレート関数及び当該バッファから出力されるバケツ トの出力ビットレートを表すレート関数を夫々 G(t)、F(t)とする。 Here, let BuffR X (t) be an accumulated amount function representing the accumulated amount of packets at time t of the buffer for absorbing transmission fluctuation of the adjustment circuit 1002. Rate function representing the input bit rate of the packet input to the buffer at time t and the bucket output from the buffer Let G (t) and F (t) be rate functions representing the output bit rate of the
レート関数 G(t)は時刻 tOまでは 0、時刻 t0以降は c (cは一定値)であり、レート関数 F( t)は時刻 Tlまでは 0、時刻 T1以降は c (cは一定値)であるとする（図 18 (a) )。  The rate function G (t) is 0 until time tO and c (c is a constant value) after time t0, and the rate function F (t) is 0 until time Tl and c (c is a constant value after time T1 ) (Fig. 18 (a)).
[0005] このとき、時刻 T1以降の時刻 tにおける蓄積量関数 BuffRx(t)は、下記の数（1)により 表される。 At this time, the accumulated amount function BuffRx (t) at time t after time T1 is represented by the following number (1).
[0006] [数 1] [0006] [Number 1]
BuffRx (  BuffRx (
=「cdt = "Cdt
Figure imgf000004_0001
上記の数（1)は、時刻 Tlから時刻 Tl以降の時刻ほでの間にバッファに入力される パケットのデータ量とその間にバッファから出力されるパケットのデータ量は同じであ るので、時刻 T1以降では蓄積量関数 BuffRx(t)が一定になることを示している（図 18 ( b) )。つまり、時刻 T1以降は、ノ ッファのパケットの蓄積量は一定になる。
Figure imgf000004_0001
In the above number (1), since the data amount of the packet input to the buffer between time Tl and the time after time Tl is the same as the data amount of the packet output from the buffer during that time, It is shown that the accumulation function BuffRx (t) becomes constant after T1 (Fig. 18 (b)). That is, after time T1, the accumulation amount of packets in the router becomes constant.
[0007] これを考慮して、従来技術はバッファのパケットの蓄積量が一定になるようにバッフ ァ力 パケットを出力する速度を制御し、同期伝送を実現して 、る。 Taking this into consideration, the prior art controls the speed at which buffer power packets are output so that the buffer packet accumulation amount becomes constant, and achieves synchronous transmission.
特許文献 1：特開平 8 - 139704号公報  Patent Document 1: Japanese Patent Application Laid-Open No. 8-139704
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problem that invention tries to solve
[0008] ところが、従来技術では、受信装置が備えるバッファのパケットの蓄積量が一定に ならないような通信に対しては送受信装置間の同期伝送を実現することができない。 このような通信として、（1)送信装置に入力されるパケットの入力ビットレートが可変ビ ットレート（VBR: Variable Bit Rate)で、伝送路における伝送ビットレートが固定ビット レートである、（2)送信装置に入力されるパケットの入力ビットレートが固定ビットレー トで、伝送路における伝送ビットレートが可変ビットレートである、（3)送信装置に入力 されるパケットの入力ビットレート及び伝送路における伝送ビットレートの双方が可変 ビットレートである、場合が挙げられる。  However, in the prior art, synchronous transmission between transmitting and receiving devices can not be realized for communication in which the amount of accumulated packets in the buffer provided in the receiving device is not constant. As such communication, (1) the input bit rate of the packet input to the transmitting apparatus is variable bit rate (VBR) and the transmission bit rate in the transmission path is a fixed bit rate (2) transmission The input bit rate of packets input to the device is a fixed bit rate, and the transmission bit rate in the transmission line is a variable bit rate. (3) Input bit rate of packets input to a transmission device and transmission bit rate in a transmission line There are cases where both are variable bit rates.
[0009] ここで、上記（2)の場合にぉ 、て、受信装置が備えるバッファのパケットの蓄積量が 一定にならな 、ことにつ 、て図 19を参照しつつ説明する。 この場合、レート関数 G(t)は時刻 TOまでは 0、時刻 TO以降は変動値であり、レート関 数 F(t)は時刻 T1までは 0、時刻 T1以降は c (cは一定値)であるとする（図 19 (a) )。 このとき、時刻 T1以降の時刻 tにおける蓄積量関数 BuffRx(t)は、下記の数（2)により 表される。 Here, in the case of the above (2), the accumulation amount of packets in the buffer provided in the receiving apparatus is not constant, and will be described with reference to FIG. In this case, the rate function G (t) is 0 until time TO, and is a fluctuation value after time TO, and the rate function F (t) is 0 until time T1 and c after time T1 (c is a constant value) (Figure 19 (a)). At this time, the accumulation function BuffRx (t) at time t after time T1 is represented by the following number (2).
[0010] [数 2] [0010] [Number 2]
Buf fRx (t)  Buf fRx (t)
= fT1 G (t) d= f T1 G (t) d
Figure imgf000005_0001
上記の数（2)は、時刻 τιから時刻 τι以降の時刻ほでの間にバッファに入力される パケットのデータ量とその間にバッファから出力されるパケットのデータ量が同じであ るとは限らないので、時刻 T1以降では蓄積量関数 BuffRx(t)が一定にならないことを 示している（図 19 (b) )。つまり、時刻 T1以降は、ノ ッファのパケットの蓄積量は一定 にならない。
Figure imgf000005_0001
The above number (2) means that the amount of packet data input to the buffer between time τι and time τι is equal to the amount of packet data output from the buffer during that time. Since it does not exist, it shows that the accumulation function BuffRx (t) does not become constant after time T1 (Fig. 19 (b)). That is, after time T1, the accumulation amount of packets in the router is not constant.
[0011] そこで、本発明は、送信装置に入力されるパケットの入力ビットレート及び伝送路に おける伝送ビットレートの少なくとも一方が可変ビットレートであっても、送信装置及び 受信装置が備えるバッファのパケットの蓄積量を利用することにより、送信装置と受信 装置との間で同期伝送を実現できる送信装置及び受信装置並びに送信方法及び受 信方法を提供することを目的とする。  Therefore, according to the present invention, even if at least one of the input bit rate of the packet input to the transmitting device and the transmission bit rate in the transmission path is a variable bit rate, the packet of the buffer provided in the transmitting device and the receiving device It is an object of the present invention to provide a transmitting device and a receiving device, and a transmitting method and a receiving method, which can realize synchronous transmission between the transmitting device and the receiving device by utilizing the storage amount of
課題を解決するための手段  Means to solve the problem
[0012] 上記目的を達成するために本発明の送信装置は、一定周期のクロック信号をカウ ントする送信カウンタ部と、入力されるパケットを一時的に蓄積し、蓄積したパケットを 出力する第 1送信バッファ部と、前記第 1送信バッファ部に蓄積されているパケットと 自装置に当該パケットが入力されるときの前記送信カウンタ部のカウント値を示す送 信カウンタ情報とを送信するとともに、前記第 1送信バッファ部に対する当該パケット の第 1処理に係る第 1タイミングでの当該第 1送信バッファ部のパケットの蓄積量を特 定するための第 1送信蓄積情報を伝送路へ送信する送信部と、を備える。  [0012] In order to achieve the above object, a transmission device according to the present invention includes a transmission counter unit that counts a clock signal of a fixed cycle, and a first unit that temporarily accumulates input packets and outputs the accumulated packets. A transmission buffer unit, a packet stored in the first transmission buffer unit, and transmission counter information indicating a count value of the transmission counter unit when the packet is input to the own apparatus are transmitted, A transmitter configured to transmit, to the transmission path, first transmission accumulation information for identifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet with respect to the transmission buffer unit; Equipped with
[0013] 本発明の送信方法は、第 1送信バッファ部に蓄積されているパケットと自装置に当 該パケットが入力されるときの送信カウンタ部のカウント値を示す送信カウンタ情報と を送信するとともに、前記第 1送信バッファ部に対する当該パケットの第 1処理に係る 第 1タイミングでの当該第 1送信バッファ部のパケットの蓄積量を特定するための第 1 送信蓄積情報を伝送路へ送信する。 According to the transmission method of the present invention, the packet stored in the first transmission buffer unit and transmission counter information indicating the count value of the transmission counter unit when the packet is input to the own apparatus The first transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at the first timing related to the first processing of the packet to the first transmission buffer unit to the transmission path Send.
[0014] 本発明の受信装置は、一定周期のクロック信号をカウントする送信カウンタ部及び 第 1送信バッファ部を有する送信装置から、パケット、当該パケットが当該送信装置に 入力されるときの前記送信カウンタ部のカウント値を示す送信カウンタ情報、前記第 1 送信バッファ部に対する当該パケットの第 1処理に係る第 1タイミングでの当該第 1送 信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情報を伝送路を介し て受信する受信部と、クロック信号をカウントするものであって、カウント速度が可変で ある受信カウンタ部と、受信されるパケットを一時的に蓄積する第 1受信バッファ部と 、前記第 1送信バッファ部に対するパケットの第 1処理に係る第 1タイミングでの当該 第 1送信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情報と、前記 第 1受信バッファ部に対する当該パケットの第 2処理に係る第 2タイミングでの当該第 1受信バッファ部のパケットの蓄積量を特定するための第 1受信蓄積情報と、に基づ いて前記受信カウンタ部のカウント速度を補正する補正部と、前記受信部により受信 される前記送信カウンタ情報と、前記受信カウント部のカウント値を示す受信カウント 情報とに基づいて、前記第 1受信バッファ部からのパケットの出力制御を行う第 1出 力制御部と、を備える。  A receiver according to the present invention is a transmitter according to the present invention, wherein a packet is transmitted from a transmitter having a transmission counter unit and a first transmission buffer unit that counts clock signals of a fixed cycle, and the transmission counter when the packet is input to the transmitter. Transmission counter information indicating the count value of the unit, and the first transmission for specifying the accumulated amount of packets in the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit A receiving unit that receives accumulated information via a transmission line, and a reception counter that counts clock signals and has a variable counting speed, and a first reception buffer that temporarily accumulates received packets. And identifying the accumulated amount of packets in the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit. First reception accumulation information for identifying the first transmission accumulation information, and the first reception accumulation information for identifying the accumulation amount of packets of the first reception buffer section at a second timing related to the second processing of the packet to the first reception buffer section And a correction unit that corrects the count speed of the reception counter unit based on information, the transmission counter information received by the reception unit, and the reception count information indicating the count value of the reception count unit. And a first output control unit that controls output of the packet from the first reception buffer unit.
[0015] 本発明の受信方法は、クロック信号をカウントするものであって、カウント速度が可 変である受信カウンタ部と、受信されるパケットを一時的に蓄積する第 1受信バッファ 部と、有する受信装置において行われる受信方法であって、一定周期のクロック信号 をカウントする送信カウンタ部及び第 1送信バッファ部を有する送信装置から、バケツ ト、当該パケットが当該送信装置に入力されるときの前記送信カウンタ部のカウント値 を示す送信カウンタ情報、前記第 1送信バッファ部に対する当該パケットの第 1処理 に係る第 1タイミングでの当該第 1送信バッファ部のパケットの蓄積量を特定するため の第 1送信蓄積情報を伝送路を介して受信する受信ステップと、前記第 1送信バッフ ァ部に対するパケットの第 1処理に係る第 1タイミングでの当該第 1送信バッファ部の パケットの蓄積量を特定するための第 1送信蓄積情報と、前記第 1受信バッファ部に 対する当該パケットの第 2処理に係る第 2タイミングでの当該第 1受信バッファ部のパ ケットの蓄積量を特定するための第 1受信蓄積情報と、に基づいて前記受信カウンタ 部のカウント速度を補正する補正ステップと、前記受信ステップにより受信される前記 送信カウンタ情報と、前記受信カウント部のカウント値を示す受信カウント情報とに基 づいて、前記第 1受信バッファ部力ものパケットの出力制御を行う第 1出力制御ステツ プと、有する。 [0015] The receiving method of the present invention counts a clock signal, and has a reception counter unit that has a variable counting speed, and a first reception buffer unit that temporarily accumulates received packets. A receiving method performed in a receiving apparatus, which includes a transmission counter unit that counts a clock signal having a predetermined cycle and a first transmission buffer unit, and the packet when the packet is input to the transmitting apparatus from the transmission apparatus. Transmission counter information indicating the count value of the transmission counter unit; first for identifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit A receiving step of receiving transmission accumulation information via a transmission path; and a first timing related to a first processing of a packet for the first transmission buffer unit. A first transmission storage information for specifying the amount of accumulated packets in the first transmission buffer unit in grayed, the first reception buffer unit The count speed of the reception counter unit is corrected based on the first reception accumulation information for specifying the accumulation amount of packets of the first reception buffer unit at the second timing related to the second process of the corresponding packet. Control the output packet of the first reception buffer unit based on the correction step, the transmission counter information received by the reception step, and the reception count information indicating the count value of the reception count unit. Has a first output control step.
発明の効果  Effect of the invention
[0016] 本発明の送信装置と受信装置とを組み合わせることにより、又は送信方法と受信方 法を組み合わせることにより、送信装置と受信装置間のカウンタのカウント速度を合わ せるために、送信装置の第 1送信バッファ部のパケットの蓄積量と受信装置の第 2受 信バッファ部のパケットの蓄積量とを利用することができるようになる。このため、受信 装置が備えるバッファのパケットの蓄積量のみの利用では同期伝送を実現することが できな力つた送信装置と受信装置との間の通信 (送信装置に入力されるパケットの入 力ビットレートが可変ビットレート、又は、伝送路における伝送ビットレートが可変ビット レート)であっても、送信装置と受信装置との間で同期伝送を実現することができる。  In order to match the count speed of the counter between the transmitting device and the receiving device by combining the transmitting device of the present invention and the receiving device, or by combining the transmitting method and the receiving method, (1) It becomes possible to use the accumulation amount of packets in the transmission buffer unit and the accumulation amount of packets in the second reception buffer unit of the receiving apparatus. Therefore, communication between the transmitting device and the receiving device which can not realize synchronous transmission only by using the accumulated amount of packets in the buffer provided in the receiving device (input bit of packet input to transmitting device) Synchronous transmission can be realized between the transmitter and the receiver even if the rate is a variable bit rate or the transmission bit rate in the transmission line is a variable bit rate).
[0017] 上記の送信装置において、前記第 1送信蓄積情報は、前記第 1送信バッファ部の パケットの蓄積量であってもよ ヽ。  In the above transmission apparatus, the first transmission accumulation information may be an accumulation amount of packets of the first transmission buffer unit.
上記の受信装置において、前記第 1送信蓄積情報は前記第 1送信バッファ部のパ ケットの蓄積量であり、前記第 1受信蓄積情報は前記第 1受信バッファ部のパケットの 蓄積量であってもよい。  In the above receiving apparatus, the first transmission accumulation information may be an accumulation amount of packets of the first transmission buffer unit, and the first reception accumulation information may be an accumulation amount of packets of the first reception buffer unit. Good.
[0018] これによれば、受信装置側で、第 1送信バッファ部のパケットの蓄積量の特定を容 易に行うことができる。  According to this, it is possible to easily specify the accumulation amount of packets in the first transmission buffer unit on the receiving device side.
上記の送信装置にぉ 、て、前記パケットに前記送信カウンタ情報を付加するカウン タ情報付加部をさらに備え、前記送信部は、前記パケット及び前記送信カウンタ情報 の送信を、前記カウンタ情報付加部により送信カウンタ情報が付加されたパケットの 送信により行うようにしてもょ 、。  The transmission apparatus further includes a counter information addition unit that adds the transmission counter information to the packet, and the transmission unit transmits the packet and the transmission counter information by the counter information addition unit. It may be performed by transmitting a packet to which transmission counter information is added.
[0019] これによれば、受信装置側で、パケットに対応する当該パケットが送信装置に入力 されたときのカウンタ情報の特定を容易に行うことができるようになる。 上記の送信装置において、前記パケットに前記第 1送信蓄積情報を付加する蓄積 情報付加部をさらに備え、前記送信部は、前記パケット及び前記第 1送信蓄積情報 の送信を、前記蓄積情報付加部により第 1送信蓄積情報が付加されたパケットの送 信により行うようにしてもよい。 According to this, it is possible to easily specify the counter information when the packet corresponding to the packet is input to the transmitting device on the receiving device side. In the above transmission apparatus, the transmission apparatus further includes an accumulation information addition unit that adds the first transmission accumulation information to the packet, and the transmission unit transmits the packet and the first transmission accumulation information by the accumulation information addition unit. It may be performed by transmitting a packet to which the first transmission accumulation information is added.
[0020] これによれば、受信装置側で、パケットに対応する第 1送信蓄積情報の特定を容易 に行うことができるようになる。  [0020] According to this, it is possible to easily identify the first transmission accumulated information corresponding to the packet on the receiving device side.
上記の送信装置において、パケットの入力順に前記送信部により送信されるバケツ トにシーケンシャルな番号を付加する番号付加部をさらに備えるようにしてもょ 、。 上記の受信装置において、前記受信部は、前記送信装置において当該送信装置 へのパケットの入力順にパケットに付与されるシーケンシャルな番号を前記送信装置 から受信し、  The above transmission apparatus may further include a number adding unit that adds a sequential number to buckets transmitted by the transmission unit in the order in which the packets are input. In the above receiving apparatus, the receiving unit receives from the transmitting apparatus a sequential number given to the packet in the input order of the packets to the transmitting apparatus in the transmitting apparatus.
前記受信装置は、前記受信部により受信されるシーケンシャルな番号に基づき、前 記受信部が受信できな力つたパケットの数を検出する検出部をさらに備え、前記補正 部は、前記第 1送信バッファ部のパケットの蓄積量と前記第 1受信バッファ部のバケツ トの蓄積量と前記検出部により検出される受信できな力つたパケットの数に基づくパ ケットの欠損量との和が一定になるように、前記受信カウンタ部のカウント速度の補正 を行うようにしてもよい。  The receiving apparatus further includes a detecting unit that detects the number of packets that can not be received by the receiving unit based on the sequential number received by the receiving unit, and the correcting unit further includes the first transmission buffer. The sum of the accumulated amount of packets in the packet buffer, the accumulated amount of buckets in the first reception buffer unit, and the lost amount of packets based on the number of packets that can not be received detected by the detection unit. In addition, the count speed of the reception counter unit may be corrected.
[0021] 上記の送信装置と受信装置とを組み合わせることにより、伝送路においてパケット が欠落した場合であっても、送信装置と受信装置との間で同期伝送を実現すること ができる。  By combining the above-described transmission device and reception device, synchronous transmission can be realized between the transmission device and the reception device even when a packet is lost in the transmission path.
上記の送信装置において、前記第 1送信バッファ部は固定ビットレートで蓄積した パケットを出力し、前記第 1送信バッファ部力 出力されるパケットを一時的に蓄積す る第 2送信バッファ部を備え、前記第 1処理に係る第 1タイミングは入力処理に係るタ イミングであり、前記送信部は、さらに、前記第 2送信バッファ部に対するパケットの第 2処理である出力処理に係る第 2タイミングでの当該第 2送信バッファ部のパケットの 蓄積量を特定するための第 2送信蓄積情報を送信するようにしてもよい。  In the above transmission apparatus, the first transmission buffer unit outputs a packet accumulated at a fixed bit rate, and the first transmission buffer unit comprises a second transmission buffer unit for temporarily accumulating the output packet. The first timing relating to the first processing is timing relating to the input processing, and the transmission unit further relates to a second timing relating to the output processing that is the second processing of the packet to the second transmission buffer unit. Second transmission accumulation information for specifying the accumulation amount of packets in the second transmission buffer unit may be transmitted.
[0022] 上記の受信装置において、前記第 1処理に係る第 1タイミングは入力処理に係るタ イミングであり、前記受信部は、さらに、前記第 1送信バッファ部が固定ビットレートで 出力するパケットを一時的に蓄積し蓄積したパケットを出力する第 2送信バッファ部を 有する前記送信装置から、前記第 2送信バッファ部に対するパケットの出力処理に係 るタイミングでの当該第 2送信バッファ部の蓄積量を特定するための第 2送信蓄積情 報を受信し、前記受信装置は、受信されるパケットを一時的に蓄積して蓄積したパケ ットを前記第 1受信バッファ部へ出力する第 2受信バッファ部と、前記第 2送信バッフ ァ部に対するパケットの出力処理に係るタイミングでの当該第 2送信バッファ部のパケ ットの蓄積量を特定するための第 2送信蓄積情報と、前記第 2受信バッファ部に対す る当該パケットの入力処理に係るタイミングでの当該第 2受信バッファ部の蓄積量を 特定するための第 2受信蓄積情報と、に基づいて前記第 2受信バッファ部からのパケ ットの出力制御を行なう第 2出力制御部と、をさらに備えるようにしてもよい。 In the above receiving apparatus, the first timing relating to the first processing is timing relating to input processing, and in the receiving section, the first transmission buffer section further has a fixed bit rate. The second transmission buffer unit at a timing related to the output processing of the packet to the second transmission buffer unit from the transmission apparatus having the second transmission buffer unit that temporarily accumulates the packet to be output and outputs the accumulated packet Second transmission accumulation information for specifying the accumulation amount of the data, and the receiving apparatus temporarily accumulates the received packet and outputs the accumulated packet to the first reception buffer unit. (Ii) second transmission accumulation information for specifying an accumulation amount of packets of the second transmission buffer unit at a timing related to output processing of the packet to the second reception buffer unit and the second transmission buffer unit; (2) The second reception based on the second reception accumulation information for specifying the accumulation amount of the second reception buffer unit at the timing related to the input processing of the packet to the reception buffer unit. And a second output control unit that performs output control of a packet from the buffer unit.
[0023] 上記の送信装置と受信装置とを組み合わせることにより、送信装置に入力されるパ ケットの入力ビットレート及び伝送路における伝送ビットレートの双方が可変ビットレー トであっても、送信装置と受信装置との間で同期伝送を実現することができる。  By combining the above transmitting apparatus and receiving apparatus, even if both the input bit rate of the packet input to the transmitting apparatus and the transmission bit rate in the transmission path are variable bit rates, the transmitting apparatus and the reception apparatus can be used. Synchronous transmission can be realized with the device.
上記の送信装置において、前記第 1送信バッファ部は固定ビットレートで蓄積した パケットを出力し、前記第 1送信バッファ部力 出力されるパケットを一時的に蓄積す る第 2送信バッファ部を備え、前記第 1処理に係る第 1タイミングは入力処理に係るタ イミングであってもよい。  In the above transmission apparatus, the first transmission buffer unit outputs a packet accumulated at a fixed bit rate, and the first transmission buffer unit comprises a second transmission buffer unit for temporarily accumulating the output packet. The first timing relating to the first processing may be timing relating to input processing.
[0024] 上記の受信装置において、前記第 1処理に係る第 1タイミングは入力処理に係るタ イミングであり、前記送信装置は、前記第 1送信バッファ部が固定ビットレートで出力 するパケットを一時的に蓄積して蓄積したパケットを出力する第 2送信バッファ部を有 し、前記受信装置は、受信するパケットを一時的に蓄積して蓄積したパケットを前記 第 1受信バッファ部へ出力する第 2受信バッファ部と、前記第 1送信バッファ部に対す る当該パケットの第 1処理に係る第 1タイミングでの当該第 1送信バッファ部のパケット の蓄積量を特定するための第 1送信蓄積情報と、前記第 1受信バッファ部に対する 当該パケットの第 2処理に係る第 2タイミングでの当該第 1受信バッファ部のパケットの 蓄積量を特定するための第 1受信蓄積情報と、に基づいて前記第 2受信バッファ部 力 のパケットの出力制御を行なう第 2出力制御部と、をさらに備えるようにしてもよい [0025] 上記の送信装置と受信装置とを組み合わせることにより、送信装置に入力されるパ ケットの入力ビットレート及び伝送路における伝送ビットレートの双方が可変ビットレー トであっても、送信装置と受信装置との間で同期伝送を実現することができる。 In the above receiving apparatus, the first timing according to the first process is a timing according to an input process, and the transmitting apparatus temporarily outputs a packet output by the first transmission buffer unit at a fixed bit rate. And a second transmission buffer unit for outputting the packet accumulated and accumulated, and the receiving apparatus temporarily accumulating the received packet and outputting the accumulated packet to the first reception buffer unit. A buffer unit, first transmission accumulation information for specifying an accumulation amount of packets of the first transmission buffer unit at a first timing related to a first process of the packet to the first transmission buffer unit; First reception accumulation information for specifying the accumulation amount of packets of the first reception buffer unit at a second timing related to the second processing of the packet to the first reception buffer unit; A second output control unit for outputting control packet of the second receiving buffer unit force Te, may be further provided with a By combining the above transmitting apparatus and receiving apparatus, even if both the input bit rate of the packet input to the transmitting apparatus and the transmission bit rate in the transmission path are variable bit rates, the transmitting apparatus and the reception apparatus can receive Synchronous transmission can be realized with the device.
上記の送信装置において、入力されるパケットを一時的に蓄積し、固定ビットレート で前記第 1送信バッファ部へ送信する第 2送信バッファ部をさらに備え、前記第 1処 理に係る第 1タイミングは出力処理に係るタイミングであってもよい。  The above transmission apparatus further includes a second transmission buffer unit that temporarily accumulates an input packet and transmits the packet to the first transmission buffer unit at a fixed bit rate, and the first timing according to the first process is It may be timing concerning output processing.
[0026] 本発明の受信装置は、一定周期のクロック信号をカウントする送信カウンタ部、パケ ットを一時的に蓄積し、蓄積したパケットを固定ビットレートで出力する第 1送信バッフ ァ部、及び当該第 1送信バッファ部が出力するパケットを一時的に蓄積する第 2送信 バッファ部を有する送信装置から、パケット、当該パケットが当該送信装置に入力さ れるときの前記送信カウンタ部のカウント値を示す送信カウンタ情報、前記第 2送信 バッファ部に対する当該パケットの出力処理に係るタイミングでの当該第 2送信バッフ ァ部のパケットの蓄積量を特定するための送信蓄積情報を伝送路を介して受信する 受信部と、クロック信号をカウントするものであって、カウント速度が可変である受信力 ゥンタ部と、入力されるパケットを一時的に蓄積する第 1受信バッファ部と、受信される パケットを一時的に蓄積して蓄積したパケットを前記第 1受信バッファ部へ出力する 第 2受信バッファ部と、前記第 2送信バッファ部に対するパケットの出力処理に係るタ イミングでの当該第 2送信バッファ部のパケットの蓄積量を特定するための送信蓄積 情報と、前記第 2受信バッファ部に対する当該パケットの入力処理に係るタイミングで の当該第 2受信バッファ部のパケットの蓄積量を特定するための受信蓄積情報と、に 基づいて前記受信カウンタ部のカウント速度を補正する補正部と、前記受信部により 受信される前記送信カウンタ情報と、前記受信カウンタ部のカウント値を示す受信力 ゥンタ情報とに基づいて、前記第 1受信バッファ部力ものパケットの出力制御を行う第 1出力制御部と、前記第 2送信バッファ部に対するパケットの出力処理に係るタイミン グでの当該第 2送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と 、前記第 2受信バッファ部に対する当該パケットの入力処理に係るタイミングでの当 該第 2受信バッファ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ いて前記第 2受信バッファ部力ものパケットの出力制御を行う第 2出力制御部と、を備 える。 The receiving device of the present invention includes a transmission counter unit that counts clock signals of a fixed cycle, a first transmission buffer unit that temporarily accumulates packets, and outputs the accumulated packets at a fixed bit rate, and Indicates the count value of the transmission counter unit when the packet and the packet are input to the transmission device from the transmission device having the second transmission buffer unit that temporarily accumulates the packet output by the first transmission buffer unit. Receiving transmission counter information and transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at the timing related to output processing of the packet to the second transmission buffer unit via the transmission path Unit, and a count unit that counts clock signals and has a variable count speed, and temporarily stores input packets. A first reception buffer unit, and a second reception buffer unit that temporarily accumulates received packets and outputs the accumulated packets to the first reception buffer unit; and output processing of packets to the second transmission buffer unit Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the second reception buffer unit at the timing concerning the input processing of the packet to the second reception buffer unit Reception accumulation information for specifying the accumulation amount of packets, a correction unit that corrects the count speed of the reception counter unit based on the transmission counter information received by the reception unit, and the reception counter unit A first output control unit that performs output control of packets of the first reception buffer unit based on the reception capability information indicating a count value; Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to output processing of the packet to the second transmission buffer unit, and input processing of the packet to the second reception buffer unit A second output control unit that performs output control of packets of the second reception buffer unit based on reception accumulation information for specifying the accumulation amount of packets of the second reception buffer unit at a timing according to And I see.
上記の送信装置と受信装置とを組み合わせることにより、また、上記受信方法によ れば、送信装置に入力されるパケットの入力ビットレート及び伝送路における伝送ビ ットレートの双方が可変ビットレートであっても、送信装置と受信装置との間で同期伝 送を実現することができる。  By combining the above transmission apparatus and reception apparatus, and according to the above reception method, both the input bit rate of the packet input to the transmission apparatus and the transmission bit rate in the transmission path are variable bit rates. Also, synchronous transmission can be realized between the transmitter and the receiver.
本発明の受信方法は、クロック信号をカウントするものであって、カウント速度が可 変である受信カウンタ部と、入力されるパケットを一時的に蓄積する第 1受信バッファ 部と、受信されるパケットを一時的に蓄積し蓄積したパケットを当該第 1受信バッファ 部へ出力する第 2受信バッファ部を有する受信装置において行われる受信方法であ つて、一定周期のクロック信号をカウントする送信カウンタ部、パケットを一時的に蓄 積し、蓄積したパケットを固定ビットレートで出力する第 1送信バッファ部、及び当該 第 1送信バッファ部が出力するパケットを一時的に蓄積する第 2送信バッファ部を有 する送信装置から、パケット、当該パケットが当該送信装置に入力されるときの前記 送信カウンタ部のカウント値を示す送信カウンタ情報、前記第 2送信バッファ部に対 する当該パケットの出力処理に係るタイミングでの当該第 2送信バッファ部のパケット の蓄積量を特定するための送信蓄積情報を伝送路を介して受信する受信ステップと 、前記第 2送信バッファ部に対するパケットの出力処理に係るタイミングでの当該第 2 送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と、前記第 2受信 ノ ッファ部に対する当該パケットの入力処理に係るタイミングでの当該第 2受信バッフ ァ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ 、て前記受信力 ゥンタ部のカウント速度を補正する補正ステップと、前記受信ステップにより受信され る前記送信カウンタ情報と、前記受信カウント部のカウント値を示す受信カウンタ情報 とに基づいて、前記第 1受信バッファ部からのパケットの出力制御を行う第 1出力制 御ステップと、前記第 2送信バッファ部に対するパケットの出力処理に係るタイミング での当該第 2送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と、 前記第 2受信バッファ部に対する当該パケットの入力処理に係るタイミングでの当該 第 2受信バッファ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ 、 て前記第 2受信バッファ部力 のパケットの出力制御を行う第 2出力制御ステップと、 有する。 A receiving method according to the present invention counts a clock signal and has a variable count rate, a reception counter unit, a first reception buffer unit for temporarily accumulating an input packet, and a received packet. A receiving counter having a second receiving buffer unit for temporarily storing the stored packets and outputting the stored packets to the first receiving buffer unit, the transmission counter unit for counting a clock signal of a fixed cycle, the packet Transmission having a first transmission buffer unit that temporarily accumulates the accumulated packets and outputs the accumulated packets at a fixed bit rate, and a second transmission buffer unit that temporarily accumulates the packets output by the first transmission buffer unit. A packet, transmission counter information indicating a count value of the transmission counter unit when the packet is input to the transmission device from the device; A receiving step of receiving transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to output processing of the packet to the second transmission buffer unit via the transmission path; Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at the timing related to the output processing of the packet to the second transmission buffer unit, and input processing of the packet to the second reception buffer unit A correction step of correcting the count speed of the reception power unit based on reception accumulation information for specifying the accumulation amount of packets of the second reception buffer unit at the timing according to The first reception based on the transmission counter information received by the reception counter and the reception counter information indicating the count value of the reception count unit. A first output control step for controlling the output of packets from the buffer unit, and for identifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the output processing of the packets to the second transmission buffer unit. The transmission accumulation information, and the reception accumulation information for specifying the accumulation amount of packets of the second reception buffer section at the timing related to the input processing of the packet to the second reception buffer section, A second output control step of controlling output of a packet of the two reception buffer units; Have.
[0028] 上記の受信方法によれば、送信装置に入力されるパケットの入力ビットレート及び 伝送路における伝送ビットレートの双方が可変ビットレートであっても、送信装置と受 信装置との間で同期伝送を実現することができる。  According to the above reception method, even if both of the input bit rate of the packet input to the transmission apparatus and the transmission bit rate in the transmission path are variable bit rates, the transmission apparatus and the reception apparatus can Synchronous transmission can be realized.
図面の簡単な説明  Brief description of the drawings
[0029] [図 1]第 1の実施の形態の同期伝送システムの構成図。 FIG. 1 is a block diagram of a synchronous transmission system according to a first embodiment.
[図 2]図 1の同期伝送システムのビットレート及びバッファのパケットの蓄積量の時間 遷移図。  [Fig. 2] A time transition diagram of the bit rate and buffer storage amount of the synchronous transmission system of Fig. 1.
[図 3]図 1の同期伝送システムのパケット構成の時間遷移図。  [FIG. 3] A time transition diagram of packet configuration of the synchronous transmission system of FIG.
[図 4]図 1の送信タイムスタンプタイマの構成図。  [FIG. 4] The block diagram of the transmission time stamp timer of FIG.
[図 5]図 1の受信タイムスタンプタイマの構成図。  [FIG. 5] The block diagram of the reception time stamp timer of FIG.
[図 6]第 2の実施の形態の同期伝送システムの構成図。  [FIG. 6] The block diagram of the synchronous transmission system of 2nd Embodiment.
[図 7]図 6のパケット欠落検出部の構成図である。  7 is a block diagram of the packet loss detection unit of FIG. 6;
[図 8]第 3の実施の形態の同期伝送システムの構成図。  [FIG. 8] The block diagram of the synchronous transmission system of 3rd Embodiment.
[図 9]図 8の同期伝送システムのビットレート及びバッファのパケットの蓄積量の時間 遷移図。  [Fig. 9] A time transition diagram of bit rate and buffer accumulation amount of buffer in the synchronous transmission system of Fig. 8.
[図 10]図 8の同期伝送システムのパケット構成の時間遷移図。  [FIG. 10] A time transition diagram of the packet configuration of the synchronous transmission system of FIG.
[図 11]第 4の実施の形態の同期伝送システムの構成図。  [FIG. 11] The block diagram of the synchronous transmission system of 4th Embodiment.
[図 12]第 5の実施の形態の同期伝送システムの構成図。  [FIG. 12] The block diagram of the synchronous transmission system of 5th Embodiment.
[図 13]図 12の同期伝送システムのパケット構成の時間遷移図。  13] A time transition diagram of packet configuration of the synchronous transmission system of FIG.
[図 14]図 12の読出レート制御部の構成図。  14 is a block diagram of the read rate control unit of FIG. 12;
[図 15]第 6の実施の形態の同期伝送システムの構成図。  [FIG. 15] The block diagram of the synchronous transmission system of 6th Embodiment.
[図 16]第 7の実施の形態の同期伝送システムの構成図。  [FIG. 16] The block diagram of the synchronous transmission system of 7th Embodiment.
[図 17]従来の同期伝送を実現する受信装置の構成図。  [FIG. 17] The block diagram of the receiver which implement | achieves the conventional synchronous transmission.
[図 18]従来技術におけるバッファに対するパケットの入出力ビットレート及びバッファ のパケットの蓄積量の時間遷移図。  [FIG. 18] A time transition diagram of packet input / output bit rate to buffer and buffer accumulation amount of buffer in the prior art.
[図 19]従来技術の問題点を説明するためのバッファに対するパケットの入出力ビット レート及びバッファのパケットの蓄積量の時間遷移図。 符号の説明 [FIG. 19] A time transition diagram of input / output bit rate of packet to buffer and buffer accumulation amount of buffer for explaining problems of the prior art. Explanation of sign
[0030] 100  [0030] 100
101 入力端子  101 input terminal
102 送信タイムスタンプタイマ  102 Transmission Time Stamp Timer
103 タイムスタンプ付カロ咅  103 with time stamp
104 第 1送信バッファ量付加部  104 1st transmission buffer amount addition unit
105 第 1送信バッファ  105 1st transmission buffer
106 第 1送信バッファ量バッファ  106 1st send buffer size buffer
107  107
200  200
201  201
202 分離部  202 Separation part
203 第 1受信バッファ  203 First receive buffer
204 タイムスタンプタイマ  204 Time stamp timer
205 第 1送信バッファ量バッファ  205 1st transmission buffer amount buffer
206 第 1受信バッファ量読出部  206 1st reception buffer amount reading unit
207 蓄積量加算部  207 Accumulated amount adder
208 補正部  208 Correction unit
209 受信タイムスタンプタイマ  209 Receive Timestamp Timer
210 比較部  210 Comparison section
211 パケット読出部  211 Packet reader
300 伝送路  300 transmission line
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0031] 《第 1の実施の形態〉〉  First Embodiment
本発明の第 1の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between the transmitting apparatus and the receiving apparatus according to the first embodiment of the present invention will be described with reference to the drawings.
本実施の形態及び後述の第 2の実施の形態は、送信装置に入力されるパケットの 入力ビットレートが可変ビットレートであり、かつ、伝送路における伝送ビットレートが 固定ビットレートである場合を対象とする。 In the present embodiment and the second embodiment described later, the input bit rate of the packet input to the transmitting device is a variable bit rate, and the transmission bit rate in the transmission path is The case of a fixed bit rate is considered.
[0032] <同期伝送システム >  Synchronous Transmission System
本実施の形態の同期伝送システムの構成について図 1を参照しつつ説明する。図 The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. Figure
1は本実施の形態の同期伝送システムの構成図である。 1 is a block diagram of a synchronous transmission system of the present embodiment.
送信装置 100と受信装置 200とは伝送路 300を介してパケットの送受信を行う。伝 送路 300は、例えば ATM (Asynchronous Transfer Mode :非同期転送モード）ネット ワークにおける伝送路である。  The transmitting device 100 and the receiving device 200 transmit and receive packets via the transmission path 300. The transmission path 300 is, for example, a transmission path in an ATM (Asynchronous Transfer Mode) network.
[0033] <パケット蓄積量 > <Packet accumulation amount>
ここで、図 1の各構成要素の説明を行う前に、図 1の第 1送信バッファ 105と第 1受 信バッファ 203のパケットの蓄積量について図 2を参照しつつ説明する。図 2は図 1の 同期伝送システムのビットレート及びパケットの蓄積量の時間遷移図である。  Here, before describing each component of FIG. 1, the packet accumulation amount of the first transmission buffer 105 and the first reception buffer 203 of FIG. 1 will be described with reference to FIG. FIG. 2 is a time transition diagram of bit rate and packet accumulation amount of the synchronous transmission system of FIG.
送信装置 100の第 1送信バッファ 105に入力されるパケットの入力ビットレートは可 変ビットレートであり、そのレート関数を fl(t)とする。また、伝送路における伝送ビットレ ートは固定ビットレートであり、そのレート関数を gl(t)とする。  The input bit rate of the packet input to the first transmission buffer 105 of the transmitting apparatus 100 is a variable bit rate, and its rate function is fl (t). Also, the transmission bit rate in the transmission path is a fixed bit rate, and its rate function is gl (t).
[0034] ただし、同期伝送では、受信装置 200の第 1受信バッファ 203から出力されるパケ ットの出力ビットレートが第 1送信バッファ 105に入力されるパケットの入力ビットレート に等しくなるように制御される。このことから、パケットが送信装置 100に入力されてか ら受信装置 200から出力されるまでの遅延時間を delayで表すと、第 1受信バッファ 2However, in synchronous transmission, control is performed such that the output bit rate of the packet output from the first reception buffer 203 of the receiving device 200 is equal to the input bit rate of the packet input to the first transmission buffer 105. Be done. From this, when the delay time from the input of the packet to the transmitting device 100 to the output of the packet from the receiving device 200 is represented by delay, the first reception buffer 2
03から出力されるパケットの出力ビットレートはレート関数 fl(t- delay)となる。 The output bit rate of the packet output from 03 is the rate function fl (t-delay).
[0035] ここで、 （1)時刻 0で第 1送信バッファ 105へのパケットの書き込みを開始、（2)時刻 tOで第 1送信バッファ 105からパケットの読み出しを開始、且つ、第 1受信バッファ 20Here, (1) start writing a packet to the first transmission buffer 105 at time 0, (2) start reading a packet from the first transmission buffer 105 at time tO, and the first reception buffer 20
3へのパケットの書き込みを開始、（3)時刻 tl (=delay)で第 1受信バッファ 203からパ ケットの読み出しを開始するものとする。 It is assumed that packet writing to 3 is started, and (3) reading of packets from the first reception buffer 203 is started at time tl (= delay).
この場合、レート関数 fl(t)は変動値であり、関数 gl(t)は時刻 tOまでは 0、時刻 to以降 は。（cは一定値）である（図 2 (a) )。なお、関数 fl(t-delay)は時刻 tl(=delay)までは 0、 時刻 tl以降は変動値となる。  In this case, the rate function fl (t) is a fluctuating value, and the function gl (t) is 0 until time tO and after time to. (C is a constant value) (Fig. 2 (a)). The function fl (t-delay) is 0 until time tl (= delay) and becomes a fluctuation value after time tl.
[0036] 時刻 tにおける第 1送信バッファ 105のパケットの蓄積量を表す蓄積量関数を BuffT xl(t)とすると、時刻 tl以降の時刻 tにおける蓄積量関数 Buff Txl(t)は、下記の数（3) により表される（図 2(b))。 Assuming that the accumulation function representing the accumulation amount of packets in the first transmission buffer 105 at time t is BuffT xl (t), the accumulation function Buff Txl (t) at time t after time t is (3) Is represented by (Fig. 2 (b)).
[0037] [数 3] [0037] [Number 3]
Buf f Txl (t) = Γ f 1 (t) dt - I gl (t) dt = I f 1 (t) dt - f cdt ■ · - (3) Buf f Txl (t) = Γ f 1 (t) dt-I gl (t) dt = I f 1 (t) dt-f cdt ■--(3)
Jo Jo Jo Jto  Jo Jo Jo Jto
時刻 tにおける第 1受信バッファ 203のパケットの蓄積量を表す蓄積量関数を BuffRxl (t)とすると、時刻 tl以降の時刻 tにおける蓄積量関数 BuffRxKt)は、下記の数 (4)によ り表される（図 2(b))。 Assuming that the accumulated amount function representing the accumulated amount of packets in the first reception buffer 203 at time t is BuffRxl (t), the accumulated amount function BuffRxKt) at time t after time tl is represented by the following number (4) (Figure 2 (b)).
[0038] [数 4] [0038] [Number 4]
BuffRxl (t) =「 gl (t) dt - ffl (t - delay) dt = fcdt - I f 1 (t - delay) dt · · · ( 4) BuffRxl (t) = "gl (t) dt-ffl (t-delay) dt = fcdt-If 1 (t-delay) dt · · · (4)
上記の数（3)と数 (4)と力 、時刻 tl以降の時刻 tにおける第 1送信バッファ 105のパ ケットの蓄積量と、時刻 t+delayにおける第 1受信バッファ 203のパケットの蓄積量との 和は、下記の数（5)になる。 The above numbers (3) and (4) and the power, the accumulation amount of packets of the first transmission buffer 105 at time t after time t1 and the accumulation amount of packets of the first reception buffer 203 at time t + delay The sum of becomes the following number (5).
[0039] [数 5] [0039] [Number 5]
Buf f Txl (t) + BuffRxl (t + delay) Buf f Txl (t) + BuffRxl (t + delay)
fl(t)dt- f cdt+ f cdt— f fl(t-delay) dt · · · (5)  fl (t) dt-f cdt + f cdt-f fl (t-delay) dt · · · (5)
jfl(t)dt + cdt-|ofl(t)dt = Jt cdt =—定値 このように、時刻 tl以降の時刻 tにおける第 1送信バッファ 105のパケットの蓄積量と、 時刻 t+delayにおける第 1受信バッファ 203のパケットの蓄積量との和は一定になる（ 図 2(b))。 jfl (t) dt + cdt- | o fl (t) dt = J t cdt = - value in this way, the storage amount of packets in the first transmission buffer 105 at time tl after time t, at time t + delay The sum with the accumulated amount of packets in the first reception buffer 203 is constant (FIG. 2 (b)).
言い換えると、あるパケットが第 1送信バッファ 105に書き込まれる直前の第 1送信 ノ ッファ 105のパケットの蓄積量と当該あるパケットが第 1受信バッファ 203から読み 出される直前の第 1受信バッファ 203のパケットの蓄積量との和が一定である。また、 あるパケットが第 1送信バッファ 105に書き込まれた直後の第 1送信バッファ 105のパ ケットの蓄積量と、当該あるパケットが第 1受信バッファ 203から読み出された直後の 第 2受信バッファ 203のパケットの蓄積量との和が一定である。 In other words, the accumulated amount of packets in the first transmission buffer 105 immediately before a certain packet is written to the first transmission buffer 105 and the packet in the first reception buffer 203 just before the certain packet is read out from the first reception buffer 203 The sum with the accumulated amount of is constant. In addition, the accumulation amount of packets in the first transmission buffer 105 immediately after a certain packet is written to the first transmission buffer 105, and immediately after the certain packet is read out from the first reception buffer 203. The sum with the accumulation amount of packets in the second reception buffer 203 is constant.
[0040] 本実施の形態は、上記関係を利用して、送信装置 100と受信装置 200との間の同 期伝送を実現する。 The present embodiment implements synchronous transmission between transmitting apparatus 100 and receiving apparatus 200 using the above relationship.
ただし、本実施の形態では、あるパケットが第 1送信バッファ 105に書き込まれる直 前の第 1送信バッファ 105のパケットの蓄積量と当該あるパケットが第 1受信バッファ 2 03から読み出される直前の第 1受信バッファ 203のパケットの蓄積量との和を用いる  However, in the present embodiment, the accumulated amount of packets in the first transmission buffer 105 immediately before a certain packet is written to the first transmission buffer 105 and the first immediately before the certain packet is read out from the first reception buffer 203 Use the sum with the storage amount of packets in the reception buffer 203
[0041] なお、あるパケットが第 1送信バッファ 105に書き込まれた直後の第 1送信バッファ 1 05のパケットの蓄積量と、当該あるパケットが第 1受信バッファ 203から読み出された 直後の第 1受信バッファ 203のパケットの蓄積量との和を用いてもよい。 The accumulation amount of packets in first transmission buffer 105 immediately after a certain packet is written to first transmission buffer 105, and the first immediately after the certain packet is read from first reception buffer 203. The sum with the accumulation amount of packets in the reception buffer 203 may be used.
なお、同期伝送を実現するために上記の何れかを利用することが望ましいが、パケ ットが第 1送信バッファ 105及び第 1受信バッファ 203に十分蓄積されているとすると 、同期伝送に利用する第 1送信バッファ 105や第 1受信バッファ 203の蓄積量を取得 するタイミングは若干ずれてもょ 、。  Although it is desirable to use any of the above in order to realize synchronous transmission, if packets are sufficiently accumulated in the first transmission buffer 105 and the first reception buffer 203, they are used for synchronous transmission. The timing for acquiring the accumulation amount of the first transmission buffer 105 and the first reception buffer 203 may be slightly shifted.
[0042] <送信装置 > <Transmitting Device>
送信装置 100は、入力端子 101と、送信タイムスタンプタイマ 102と、タイムスタンプ 付加部 103と、第 1送信バッファ量付加部 104と、第 1送信バッファ 105と、第 1送信 ノ ッファ量読出部 106と、送信処理部 107とを備える。  The transmitting apparatus 100 includes an input terminal 101, a transmission time stamp timer 102, a time stamp adding unit 103, a first transmission buffer amount adding unit 104, a first transmission buffer 105, and a first transmission buffer amount reading unit 106. And the transmission processing unit 107.
入力端子 101にパケットが入力され、入力されたパケットがタイムスタンプ付加部 10 3へ出力される。  A packet is input to the input terminal 101, and the input packet is output to the time stamp adder 103.
[0043] 送信タイムスタンプタイマ 102は、一定周波数のクロック信号をカウントし、カウント 値を出力するものであって、その一構成例にっ 、て図 4を用いて後述する。  The transmission time stamp timer 102 counts clock signals of a fixed frequency and outputs a count value, and an example of its configuration will be described later with reference to FIG.
タイムスタンプ付加部 103は、入力されるパケットの先頭に、送信タイムスタンプタイ マ 102から供給されるカウント値をタイムスタンプとして付加する。なお、本実施の形 態では、カウント値そのものをタイムスタンプとして用いるが、カウント値を時刻に置換 して、置換した時刻を示す情報をタイムスタンプとして用いるようにしてもょ 、。  The time stamp adder 103 adds the count value supplied from the transmission time stamp timer 102 as a time stamp to the beginning of the input packet. In the present embodiment, the count value itself is used as a time stamp, but the count value may be replaced with time, and information indicating the replaced time may be used as a time stamp.
[0044] 第 1送信バッファ量付加部 104は、タイムスタンプが付加されたパケットの先頭に、 第 1送信バッファ量読出部 106から入力される後述する第 1送信バッファ量を付加す る。 The first transmission buffer amount adding unit 104 adds a first transmission buffer amount described later input from the first transmission buffer amount reading unit 106 to the beginning of the packet to which the time stamp is added. Ru.
第 1送信バッファ 105は、 FIFO (First In First Out)バッファで構成されており、入 力されるパケットを一時的に蓄積し、蓄積したパケットを固定ビットレートで出力する。 なお、伝送効率を高めるために、第 1送信バッファ 105は複数のパケットを結合し、結 合したパケット（以下、結合パケットという。）を出力する。  The first transmission buffer 105 is composed of a FIFO (First In First Out) buffer, temporarily accumulates input packets, and outputs the accumulated packets at a fixed bit rate. Here, in order to improve transmission efficiency, the first transmission buffer 105 combines a plurality of packets and outputs a combined packet (hereinafter referred to as a combined packet).
[0045] 第 1送信バッファ量読出部 106は、第 1送信バッファ 105のパケットの蓄積量 (以下 、第 1送信バッファ量という。）を読み出し、読み出した第 1送信バッファ量を第 1送信 ノ ッファ量付加部 104へ出力する。ここで、第 1送信バッファ量は、第 1送信バッファ 量付加部 104によって第 1送信バッファ量が付加される対象のパケットが第 1送信バ ッファ 105に書き込まれる直前の第 1送信バッファ 105のパケットの蓄積量である。  The first transmission buffer amount reading unit 106 reads the accumulated amount of packets of the first transmission buffer 105 (hereinafter referred to as the first transmission buffer amount), and the first transmission buffer amount read out is referred to as the first transmission buffer. Output to the quantity addition unit 104. Here, the first transmission buffer amount is the packet of the first transmission buffer 105 immediately before the packet to which the first transmission buffer amount is added by the first transmission buffer amount addition unit 104 is written to the first transmission buffer 105. Accumulated amount of
[0046] ただし、第 1送信バッファ量は、受信装置 200での処理を容易にするために、タイム スタンプや第 1送信バッファ量に関するデータ量を除く第 1送信バッファ 105のデータ 蓄積量とする。  However, in order to facilitate processing in the receiving apparatus 200, the first transmission buffer amount is taken as the data accumulation amount of the first transmission buffer 105 excluding the time stamp and the data amount related to the first transmission buffer amount.
なお、第 1送信バッファ量は、例えば、次のようにして算出することができる。タイムス タンプ及び第 1送信バッファ量の夫々のデータサイズを固定とする。タイムスタンプの データサイズと第 1送信バッファ量のデータサイズとの和に、第 1送信バッファ 105に 蓄積されているパケットの数 (入力されたパケットの数から出力したパケットの数を減 算した値)を乗算する。第 1送信バッファ 105の実際の蓄積量力も乗算値を減算する 。この減算値が第 1送信バッファ量になる。  The first transmission buffer amount can be calculated, for example, as follows. Each data size of time stamp and first transmission buffer size is fixed. The number of packets stored in the first transmission buffer 105 (the number of input packets minus the number of output packets minus the sum of the data size of the timestamp and the data size of the first transmission buffer amount Multiply). The actual storage capacity of the first transmission buffer 105 also subtracts the multiplication value. This subtraction value becomes the first transmission buffer amount.
[0047] 送信処理部 107は、伝送に適した変調処理、プロトコル処理、宛て先ヘッダ処理な どを行う。ただし、変調処理、プロトコル処理、宛て先ヘッダ処理などは本発明に直接 関係しないため説明を省略する。なお、本発明は、変調処理、プロトコル処理、宛て 先ヘッダ処理などに関係なくどのような伝送にも適用できる。 The transmission processing unit 107 performs modulation processing, protocol processing, destination header processing, and the like suitable for transmission. However, modulation processing, protocol processing, destination header processing, and the like are not directly related to the present invention, and therefore the description thereof is omitted. The present invention is applicable to any transmission regardless of modulation processing, protocol processing, destination header processing, and the like.
上述した送信装置 100では、入力端子 101にパケットが入力される（図 3の N101) と、タイプスタンプ付加部 103はパケットの先頭に送信タイムスタンプタイマ 102から 供給されるカウント値をタイムスタンプとして付加し (N102)、さらに、第 1送信バッファ 量付加部 104は、タイムスタンプが付加されたパケットの先頭に第 1送信バッファ量読 出部 106によって読み出された第 1送信バッファ量を付加する (N103)。タイムスタン プ及び第 1送信バッファ量が付加されたパケットが第 1送信バッファ 105に蓄積される In the transmitting apparatus 100 described above, when a packet is input to the input terminal 101 (N101 in FIG. 3), the timestamp attachment section 103 appends the count value supplied from the transmission timestamp timer 102 to the beginning of the packet as a timestamp. (N102), and the first transmission buffer amount adding unit 104 adds the first transmission buffer amount read by the first transmission buffer amount reading unit 106 to the beginning of the packet to which the time stamp is added ( N103). Timestamp Packets to which the packet size and the first transmission buffer amount have been added are accumulated in the first transmission buffer 105
[0048] 第 1送信バッファ 105は結合パケットを出力する（N104)。結合パケットは送信処理 部 107により所定の処理が施され、伝送路 300へ送出される。 The first transmission buffer 105 outputs the combined packet (N104). The combined packet is subjected to predetermined processing by the transmission processing unit 107 and sent out to the transmission path 300.
<送信タイムスタンプタイマ >  <Transmission Time Stamp Timer>
図 1の送信装置 100の送信タイムスタンプタイマ 102の構成について図 4を参照し つつ説明する。図 4は図 1の送信タイムスタンプタイマ 102の構成図である。  The configuration of the transmission time stamp timer 102 of the transmission apparatus 100 of FIG. 1 will be described with reference to FIG. FIG. 4 is a block diagram of the transmission time stamp timer 102 of FIG.
[0049] 送信タイムスタンプタイマ 102は、発振器 102aと、カウンタ 102bと、出力端子 102c とを備える。 The transmission time stamp timer 102 includes an oscillator 102 a, a counter 102 b, and an output terminal 102 c.
発振器 102aは、固定周波数発振器であり、水晶などを用いて一定周波数のクロッ ク信号を発振するように構成されている。但し、発振周波数は、同期復元後のバケツ トの残留時間軸ジッタを所定量以内になるように十分高く設定されている。  The oscillator 102a is a fixed frequency oscillator, and is configured to oscillate a clock signal of a fixed frequency using a crystal or the like. However, the oscillation frequency is set high enough to keep the remaining time-axis jitter of the bucket after synchronization restoration within a predetermined amount.
[0050] カウンタ 102bは、発振器 102aによって発振された一定周波数のクロック信号を力 ゥントし、カウント値を出力端子 102cから外部へ出力する。出力端子 102cから出力 されるカウント値がタイムスタンプ付加部 103に供給される。 The counter 102b applies a clock signal of a fixed frequency oscillated by the oscillator 102a, and outputs the count value from the output terminal 102c to the outside. The count value output from the output terminal 102 c is supplied to the time stamp adder 103.
<受信装置 >  <Receiver>
受信装置 200は、同期伝送の条件である時間軸復元処理、及びレート制御処理な どを行う。なお、時間軸復元処理とは、パケットの時間軸ジッタを所定の範囲内とする ための処理である。また、レート制御処理とは、伝送するパケットの平均ビットレートを 送信装置と受信装置との間で等しくするための処理である。  The receiving device 200 performs time axis restoration processing, rate control processing, and the like, which are conditions for synchronous transmission. The time axis restoration process is a process for setting the time axis jitter of a packet within a predetermined range. The rate control process is a process for equalizing the average bit rate of packets to be transmitted between the transmitting device and the receiving device.
[0051] 受信装置 200は、受信処理部 201と、分離部 202と、第 1受信バッファ 203と、タイ ムスタンプバッファ 204と、第 1送信バッファ量バッファ 205と、第 1受信バッファ量読 出部 206と、蓄積量加算部 207と、補正部 208と、受信タイムスタンプタイマ 209と、 比較部 210と、パケット読出部 211と、出力端子 212とを備える。  Reception apparatus 200 includes reception processing section 201, separation section 202, first reception buffer 203, time stamp buffer 204, first transmission buffer size buffer 205, and first reception buffer quantity reading section 206. A storage amount addition unit 207, a correction unit 208, a reception time stamp timer 209, a comparison unit 210, a packet reading unit 211, and an output terminal 212.
[0052] 受信処理部 201は、伝送路 300から受信したパケットに対して、送信処理部 107が 行う処理と逆の処理を行い、結合パケットの復元を行う。ただし、受信処理部 201が 行う処理は本発明に直接関係しないため説明を省略する。  The reception processing unit 201 performs processing reverse to the processing performed by the transmission processing unit 107 on the packet received from the transmission path 300, and restores the combined packet. However, since the processing performed by the reception processing unit 201 is not directly related to the present invention, the description will be omitted.
分離部 202は、受信処理部 201から入力される結合パケットを、複数の第 1送信バ ッファ量、複数のタイムスタンプ、及び複数のパケットに分離する。そして、分離部 20 2は、複数の第 1送信バッファ量、複数のタイムスタンプ、及び複数のパケットを、夫々 、第 1送信バッファ量バッファ 205、タイムスタンプバッファ 204、及び第 1受信バッフ ァ 203へ出力する。 The separation unit 202 is configured to receive the combined packet input from the reception processing unit 201 into a plurality of first transmission Separate buffer size, multiple timestamps, and multiple packets. Then, the separation unit 202 sends the plurality of first transmission buffer amounts, the plurality of time stamps, and the plurality of packets to the first transmission buffer amount buffer 205, the time stamp buffer 204, and the first reception buffer 203, respectively. Output.
[0053] 第 1受信バッファ 203は、 FIFOバッファで構成されており、入力されるパケットを一 時的に蓄積する。第 1受信バッファ 203から出力されるパケットは、出力端子 212から 外部へ送出される。  The first reception buffer 203 is composed of a FIFO buffer, and temporarily accumulates input packets. The packet output from the first reception buffer 203 is output from the output terminal 212 to the outside.
タイムスタンプバッファ 204は、 FIFOバッファで構成されており、入力されるタイムス タンプを一時的に蓄積する。  The time stamp buffer 204 is composed of a FIFO buffer and temporarily accumulates the inputted time stamp.
[0054] 第 1送信バッファ量バッファ 205は、 FIFOバッファで構成されており、入力される第 1送信バッファ量を一時的に蓄積する。 The first transmission buffer amount buffer 205 is formed of a FIFO buffer, and temporarily accumulates the input first transmission buffer amount.
第 1受信バッファ量読出部 206は、第 1受信バッファ 203のパケットの蓄積量 (以下 、第 1受信バッファ量という。）を読み出し、読み出した第 1受信バッファ量を蓄積量カロ 算部 207へ出力する。ここで、第 1受信バッファ量は、第 1送信バッファ量バッファ 20 5から蓄積量加算部 207へ出力される第 1送信バッファ量が付加されていたパケット が第 1受信バッファ 203から読み出される直前の第 1受信バッファ 203のパケットの蓄 禾貝直である。  The first reception buffer amount reading unit 206 reads the accumulated amount of packets of the first reception buffer 203 (hereinafter referred to as the first reception buffer amount), and outputs the read first reception buffer amount to the accumulated amount calo calculation unit 207. Do. Here, the first reception buffer amount is the value immediately before the packet to which the first transmission buffer amount output from the first transmission buffer amount buffer 205 is output to the accumulation amount addition unit 207 is read from the first reception buffer 203. It is a direct storage of packets in the first receive buffer 203.
[0055] 蓄積量加算部 207は、第 1送信バッファ量バッファ 205から取り出す第 1送信バッフ ァ量と、第 1受信バッファ量読出部 206から入力される第 1受信バッファ量とを加算す る。なお、第 1受信バッファ 203と第 1送信バッファ量バッファ 205とが FIFOバッファ で構成されているので、第 1送信バッファ量バッファ 205から取り出す第 1送信バッフ ァ量は、第 1受信バッファ 203から読み出されるパケットに付加されていた第 1送信バ ッファ量になる。  The accumulation amount addition unit 207 adds the first transmission buffer amount extracted from the first transmission buffer amount buffer 205 and the first reception buffer amount input from the first reception buffer amount reading unit 206. Since the first reception buffer 203 and the first transmission buffer amount buffer 205 are composed of FIFO buffers, the first transmission buffer amount taken out of the first transmission buffer amount buffer 205 is read from the first reception buffer 203. The first transmission buffer amount that has been added to the
[0056] 補正部 208は、蓄積量加算部 207から入力される加算値が一定になるように、受信 タイムスタンプタイマ 209のカウント速度の制御を行う。  The correction unit 208 controls the count speed of the reception time stamp timer 209 so that the added value input from the accumulated amount addition unit 207 becomes constant.
加算値が増加すれば送信タイムスタンプタイマ 102のカウント速度より受信タイムス タンプタイマ 209のカウント速度が遅くなつている。このため、補正部 208は、カウント 速度を上げることを指示するための制御信号を受信タイムスタンプタイマ 209へ出力 する。 If the addition value increases, the count speed of the reception time stamp timer 209 is slower than the count speed of the transmission time stamp timer 102. Therefore, correction section 208 outputs a control signal for instructing to increase the count speed to reception time stamp timer 209. Do.
[0057] また、加算値が減少すれば送信タイムスタンプタイマ 102のカウント速度より受信タ ィムスタンプタイマ 209のカウント速度が速くなつている。このため、補正部 208は、力 ゥント速度を下げることを指示するための制御信号を受信タイムスタンプタイマ 209へ 出力する。  Also, if the addition value decreases, the count speed of the reception time stamp timer 209 is faster than the count speed of the transmission time stamp timer 102. For this reason, the correction unit 208 outputs a control signal for instructing to decrease the momentum speed to the reception time stamp timer 209.
受信タイムスタンプタイマ 209は、補正部 208から入力される制御信号がカウント速 度を下げることを指示している場合にはカウント速度を下げ、当該制御信号がカウン ト速度を上げることを指示している場合にはカウント速度を上げる。ただし、送信タイ ムスタンプタイマ 102のカウント値と受信タイムスタンプタイマ 209のカウント値とを同 時刻で見た場合、受信タイムスタンプタイマ 209のカウント値が、送信タイムスタンプ タイマ 102のカウント値より固定遅延時間に相当するカウント値分小さくなるように、受 信タイムスタンプタイマ 209はプリセットされている。なお、受信タイムスタンプタイマ 2 09の一構成例にっ 、ては図 5を用いて後述する。  When the control signal input from the correction unit 208 instructs to decrease the count speed, the reception time stamp timer 209 instructs to decrease the count speed and the control signal to increase the count speed. If it is, increase the counting speed. However, when the count value of transmission time stamp timer 102 and the count value of reception time stamp timer 209 are viewed at the same time, the count value of reception time stamp timer 209 is fixed delay time from the count value of transmission time stamp timer 102. The reception time stamp timer 209 is preset so as to be smaller by the count value corresponding to. Note that one configuration example of the reception time stamp timer 209 will be described later with reference to FIG.
[0058] 比較部 210は、タイムスタンプバッファ 204力も入力されるタイムスタンプが示すカウ ント値と、受信タイムスタンプタイマ 209から入力されるカウント値とを比較し、両者が 一致した場合にパケット読出部 211へパケットの読み出しを指示するためのパケット 読出信号を出力する。なお、第 1受信バッファ 203とタイムスタンプバッファ 204とが F IFOバッファで構成されて!、るので、タイムスタンプバッファ 204から取り出されるタイ ムスタンプは第 1受信バッファ 203から読み出されるパケットに付加されていたタイム スタンプになる。 The comparison unit 210 compares the count value indicated by the time stamp to which the time stamp buffer 204 is also input, and the count value input from the reception time stamp timer 209, and when both match, the packet read out unit A packet read signal for instructing the reading of the packet to 211 is output. Since the first reception buffer 203 and the time stamp buffer 204 are composed of F IFO buffers, the time stamp extracted from the time stamp buffer 204 is added to the packet read from the first reception buffer 203. Become a time stamp.
[0059] パケット読出部 211は、比較部 210からのパケット読出信号を受けて、第 1受信バッ ファ 203から 1つのパケットを出力させる。  The packet read unit 211 receives the packet read signal from the comparison unit 210 and causes the first reception buffer 203 to output one packet.
<受信タイムスタンプタイマ >  <Receive Time Stamp Timer>
図 1の受信装置 200の受信タイムスタンプタイマ 209の構成について図 5を参照し つつ説明する。図 5は図 1の受信タイムスタンプタイマ 209の構成図である。  The configuration of reception time stamp timer 209 of reception apparatus 200 in FIG. 1 will be described with reference to FIG. FIG. 5 is a block diagram of the reception time stamp timer 209 of FIG.
[0060] 受信タイムスタンプタイマ 209は、可変周波数発振器 209aと、カウンタ 209bと、制 御端子 209cと、カウント値出力端子 209dと、初期値入力端子 209eと、クロック出力 端子 209fとを備える。 可変周波数発振器 209aは、所定範囲の周波数を発振することが可能な発振器で あり、発振した周波数のクロック信号をカウンタ 209bへ供給するとともに、クロック信 号をクロック出力端子 209fから外部へ出力する。 The reception time stamp timer 209 includes a variable frequency oscillator 209a, a counter 209b, a control terminal 209c, a count value output terminal 209d, an initial value input terminal 209e, and a clock output terminal 209f. The variable frequency oscillator 209a is an oscillator capable of oscillating a frequency within a predetermined range, supplies a clock signal of the oscillated frequency to the counter 209b, and outputs the clock signal to the outside from the clock output terminal 209f.
[0061] 可変周波数発振器 209aは、制御端子 209cに入力される制御信号がカウント速度 を上げることを指示している場合には発振周波数を上げ、当該制御信号がカウント速 度を下げることを指示している場合には発振周波数を下げる。  When the control signal input to the control terminal 209 c instructs to increase the count speed, the variable frequency oscillator 209 a increases the oscillation frequency and instructs the control signal to lower the count speed. If so, lower the oscillation frequency.
カウンタ 209bは、入力端子 209eを介して、タイムスタンプバッファ 204に最初に蓄 積されたタイムスタンプをタイムスタンプバッファ 204から取り出し、取り出したタイムス タンプが示すカウント値を基にプリセットされる。  The counter 209b takes out the time stamp stored in the time stamp buffer 204 from the time stamp buffer 204 through the input terminal 209e, and is preset based on the count value indicated by the taken time stamp.
[0062] なお、送信装置 100に入力されるパケットは伝送固定遅延時間分送れて受信装置 200から出力されるため、カウンタ 209bは、カウンタ 102bに対して、伝送固定遅延 時間分に相当するオフセットを保ってカウント値を出力する必要がある。このため、力 ゥンタ 102bのカウント値とカウンタ 209bのカウント値を同時刻で見た場合に、カウン タ 209bのカウンタ値力 カウンタ 102bのカウント値より固定遅延時間に相当するカウ ント値分小さくなるように、プリセットされる。  Since the packet input to transmitting apparatus 100 is sent for the fixed transmission delay time and output from receiving apparatus 200, counter 209b sets the offset corresponding to the fixed transmission delay time to counter 102b. It is necessary to keep and output the count value. Therefore, when the count value of force counter 102b and the count value of counter 209b are viewed at the same time, the counter value of counter 209b is smaller than the count value of counter 102b by the count value corresponding to the fixed delay time. Is preset.
[0063] カウンタ 209bは、可変周波数発振器 209aによって発振されたクロック信号をカウ ントし、カウント値をカウント値出力端子 209dから外部へ出力する。カウント値出力端 子 102cから出力されるカウント値は比較部 210へ供給される。  The counter 209b counts the clock signal oscillated by the variable frequency oscillator 209a, and outputs the count value to the outside from the count value output terminal 209d. The count value output from the count value output terminal 102 c is supplied to the comparison unit 210.
<時間軸復元処理 >  <Time axis restoration process>
上述したようにプリセットされたカウンタ 209bは可変周波数発振器 209aが発振す るクロック信号をカウントし、カウント値をカウント値出力端子 209dから比較部 210へ 出力する。  The counter 209b preset as described above counts the clock signal oscillated by the variable frequency oscillator 209a, and outputs the count value to the comparison unit 210 from the count value output terminal 209d.
[0064] 比較部 210は、タイムスタンプバッファ 204から取り出したタイムスタンプが示すカウ ント値と、受信タイムスタンプタイマ 209から入力されるカウント値とを比較し、両者が 一致するとパケット読出部 211に対してパケット読出信号を出力する。パケット読出部 211は、比較部 210からのパケット読出信号を受けて、第 1受信バッファ 203から 1つ のパケットを出力させる。  Comparing section 210 compares the count value indicated by the time stamp extracted from time stamp buffer 204 with the count value input from reception time stamp timer 209, and if both match, packet reading section 211 is compared. Output a packet read signal. The packet read unit 211 receives the packet read signal from the comparison unit 210 and causes the first reception buffer 203 to output one packet.
[0065] この処理により、図 3の N105に示すように、パケットは時間軸で復元され、パケット は送信装置 100に入力されて力も伝送固定遅延時間遅れて受信装置 200から出力 されること〖こなる。 By this processing, as shown at N 105 in FIG. 3, the packet is recovered on the time axis, and the packet is It can be said that the power is also input to the transmitter 100 and the power is also output from the receiver 200 with a delay of transmission fixed delay time.
ただし、有限の周波数をカウントしたカウント値を用いて受信装置 200からのバケツ トの出力制御が行われている。このため、送信タイムスタンプタイマ 102や受信タイム スタンプタイマ 209においてカウントに用いるクロック信号が処理系のクロック信号と 非同期の場合には、パケットは、送信タイムスタンプタイマ 102や受信タイムスタンプ タイマ 209においてカウントに用いるクロック信号の 1から 2クロック分の残留ジッタを 含んで、受信装置 200から出力される。  However, output control of the buckett from the receiver 200 is performed using a count value obtained by counting a finite frequency. Therefore, when the clock signal used for counting in the transmission time stamp timer 102 and the reception time stamp timer 209 is asynchronous with the processing clock signal, the packet is counted in the transmission time stamp timer 102 and the reception time stamp timer 209. The signal is output from the receiver 200 including residual jitter of 1 to 2 clocks of the clock signal to be used.
[0066] <レート制御処理 > <Rate Control Processing>
第 1受信バッファ量読出部 206は、第 1受信バッファ 203の第 1受信バッファ量を読 み出し、読み出した第 1受信バッファ量を蓄積量加算部 207へ出力する。蓄積量カロ 算部 207は第 1送信バッファ量バッファ 205から第 1送信バッファ量を取り出す。 蓄積量加算部 207は、第 1送信バッファ量バッファ 205から取り出した第 1送信バッ ファ量と、第 1受信バッファ量読出部 206から入力された第 1受信バッファ量とを加算 する。  The first reception buffer amount reading unit 206 reads the first reception buffer amount of the first reception buffer 203, and outputs the read first reception buffer amount to the accumulation amount addition unit 207. The accumulation amount calo calculation unit 207 takes out the first transmission buffer amount from the first transmission buffer amount buffer 205. The accumulation amount addition unit 207 adds the first transmission buffer amount fetched from the first transmission buffer amount buffer 205 and the first reception buffer amount inputted from the first reception buffer amount reading unit 206.
[0067] 補正部 208は、加算結果が増加していれば受信タイムスタンプタイマ 209へカウン ト速度を上げることを指示するための制御信号を出力し、受信タイムスタンプタイマ 2 09はこの制御信号を受けてカウント速度を上げる。  If the addition result is increasing, correction section 208 outputs a control signal for instructing reception time stamp timer 209 to increase the counting speed, and reception time stamp timer 209 receives this control signal. Receive and increase the counting speed.
補正部 208は、加算結果が減少して ヽれば受信タイムスタンプタイマ 209へカウン ト速度を下げることを指示するための制御信号を出力し、受信タイムスタンプタイマ 2 09はこの制御信号を受けてカウント速度を下げる。  Correction section 208 outputs a control signal for instructing to decrease the counting speed to reception time stamp timer 209 if the addition result decreases, and reception time stamp timer 209 receives this control signal. Reduce the counting speed.
[0068] 上述し本実施の形態によれば、送信装置に入力されるパケットの入力ビットレートが 可変ビットレートであり、かつ、伝送路における伝送ビットレートが固定ビットレートであ つても、送信装置と受信装置との間での同期伝送を実現することができる。  According to the embodiment described above, according to the present embodiment, even if the input bit rate of the packet input to the transmitting device is a variable bit rate and the transmission bit rate in the transmission path is a fixed bit rate, the transmitting device It is possible to realize synchronous transmission between a and a receiver.
<補足 >  <Supplement>
(1)第 1の実施の形態及び後述する実施の形態では、受信タイムスタンプタイマ 20 9のカウント速度の補正に用いる第 1送信バッファ 105の蓄積量及び第 1受信バッフ ァ 203のパケットの蓄積量として、タイムスタンプ及び送信バッファ量が付加されて！ヽ ないパケットの蓄積量を用いている。しかしながら、これに限らず、タイムスタンプ及び 送信バッファ量の少なくとも一方を含むデータの蓄積量を用いるようにしてもょ 、。 (1) In the first embodiment and the embodiments to be described later, the accumulation amount of the first transmission buffer 105 and the accumulation amount of the packets of the first reception buffer 203 used to correct the count speed of the reception time stamp timer 209 As time stamp and send buffer amount are added! Moth There is no accumulation of packets. However, the storage amount of data including at least one of the time stamp and the transmission buffer amount may be used.
[0069] (2)第 1の実施の形態及び後述する実施の形態では、受信タイムスタンプタイマ 20 9のカウント速度を可変にするために可変周波数発振器 209aの発振周波数を制御 して 、る場合である力 発振周波数を固定にしたままカウンタ 209bのカウントの行 ヽ 方を変化させることによって受信タイムスタンプタイマ 209のカウント速度を可変にす るように構成してちょい。  (2) In the first embodiment and embodiments to be described later, the oscillation frequency of the variable frequency oscillator 209 a is controlled to make the count speed of the reception time stamp timer 209 variable. The configuration is such that the count speed of the reception time stamp timer 209 can be made variable by changing the direction of counting of the counter 209b while fixing a certain oscillation frequency.
[0070] 《第 2の実施の形態》 Second Embodiment
本発明の第 2の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between a transmitting apparatus and a receiving apparatus according to the second embodiment of the present invention will be described with reference to the drawings.
本実施の形態は、第 1の実施の形態に、伝送路上で欠落したパケットがあっても送 信装置と受信装置との間で同期伝送を実現するための機能を付加したものである。  In this embodiment, a function is added to the first embodiment to realize synchronous transmission between the transmitting device and the receiving device even if there is a missing packet on the transmission path.
[0071] なお、第 1の実施の形態と実質的に同じ機能を有する構成要素には同じ符号を付 し、その構成要素については第 1の実施の形態における説明が適用できるため説明 を省略する。 Components having substantially the same functions as those of the first embodiment are denoted by the same reference numerals, and the description of the first embodiment can be applied to the components, and the description thereof is omitted. .
<同期伝送システム >  <Synchronous transmission system>
本実施の形態の同期伝送システムの構成について図 6を参照しつつ説明する。図 6は本実施の形態の同期伝送システムの構成図である。  The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. FIG. 6 is a block diagram of a synchronous transmission system according to this embodiment.
[0072] 送信装置 100aと受信装置 200aとは伝送路 300を介してパケットの送受信を行う。 The transmitter 100 a and the receiver 200 a transmit and receive packets via the transmission path 300.
なお、送信装置 100aに入力されるパケットは固定長パケットであるとする。  It is assumed that the packet input to the transmission device 100a is a fixed length packet.
<送信装置 >  <Transmitter>
送信装置 1 OOaは、第 1の実施の形態の送信装置 100にシーケンス番号発生部 12 1とシーケンス番号付加部 122とを付加した構成になって 、る。  The transmitter 1 OOa has a configuration in which a sequence number generator 121 and a sequence number adder 122 are added to the transmitter 100 of the first embodiment.
[0073] シーケンス番号発生部 121は、値" 1"からシーケンシャルな番号（以下、シーケンス 番号という。）を発生し、発生したシーケンス番号をシーケンス番号付加部 122へ供 給する。 Sequence number generation unit 121 generates a sequential number (hereinafter referred to as a sequence number) from value “1”, and supplies the generated sequence number to sequence number addition unit 122.
シーケンス番号付加部 122は、第 1送信バッファ 105から出力される結合パケットの 先頭にシーケンス番号発生部 121から供給されるシーケンス番号を付加する。 [0074] 送信装置 100aでは、入力端子 101にパケットが入力されると、タイプスタンプ付カロ 部 103はパケットの先頭に送信タイムスタンプタイマ 102から供給されるカウント値を タイムスタンプとして付カ卩し、さらに、第 1送信バッファ量付加部 104は、タイムスタン プが付加されたパケットの先頭に第 1送信バッファ量読出部 106によって読み出され た第 1送信バッファ量を付加する。タイムスタンプ及び第 1送信バッファ量が付加され たパケットが第 1送信バッファ 105に蓄積される。 The sequence number attachment unit 122 attaches the sequence number supplied from the sequence number generation unit 121 to the head of the combined packet output from the first transmission buffer 105. In the transmitting device 100 a, when a packet is input to the input terminal 101, the time stamped character encoding unit 103 adds the count value supplied from the transmission time stamp timer 102 as the time stamp at the beginning of the packet, Furthermore, the first transmission buffer amount adding unit 104 adds the first transmission buffer amount read by the first transmission buffer amount reading unit 106 to the head of the packet to which the time stamp is added. The packet to which the time stamp and the first transmission buffer amount are added is accumulated in the first transmission buffer 105.
[0075] 第 1送信バッファ 105は一定数のパケットを結合した結合パケットを出力する。シー ケンス番号付加部 122は、第 1送信バッファ 105から出力された結合パケットの先頭 に、シーケンス番号発生部 121から供給されたシーケンス番号を付加する。シーケン ス番号が付加された結合パケットは、送信処理部 107により所定の処理が施され、伝 送路 300へ送出される。  The first transmission buffer 105 outputs a combined packet obtained by combining a fixed number of packets. The sequence number adding unit 122 adds the sequence number supplied from the sequence number generation unit 121 to the beginning of the combined packet output from the first transmission buffer 105. The combined packet to which the sequence number is added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300.
[0076] <受信装置 >  <Receiver>
受信装置 200aは、第 1の実施の形態の受信装置 200に、パケット欠落検出部 221 とバッファ量補正部 222とを付加し、分離部 202の代わりに分離部 202aを有する構 成になっている。  The receiving device 200a has a configuration in which a packet loss detecting unit 221 and a buffer amount correcting unit 222 are added to the receiving device 200 of the first embodiment, and a separating unit 202a is provided instead of the separating unit 202. .
分離部 202aは、受信処理部 201から入力されるシーケンス番号が付加された結合 パケットを、シーケンス番号、複数の第 1送信バッファ量、複数のタイムスタンプ、及び 複数のパケットに分離する。そして、分離部 202aは、シーケンス番号、複数の第 1送 信バッファ量、複数のタイムスタンプ、及び複数のパケットを、夫々、パケット欠落検出 部 221、第 1送信バッファ量バッファ 205、タイムスタンプバッファ 204、及び第 1受信 ノッファ 203へ出力する。  The separation unit 202a separates the combined packet to which the sequence number input from the reception processing unit 201 is added into a sequence number, a plurality of first transmission buffer amounts, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202a transmits the sequence number, the plurality of first transmission buffer amounts, the plurality of time stamps, and the plurality of packets to the packet loss detection unit 221, the first transmission buffer amount buffer 205, and the time stamp buffer 204, respectively. , And output to the first reception knob 203.
[0077] パケット欠落検出部 221は、分離部 202aから入力されるシーケンス番号を基に、受 信された結合パケットとその一つ前に受信された結合パケットとの間で、伝送路上で 欠落した結合パケットの数を検出し、検出した結合パケットの数をバッファ量補正部 2 22へ出力する。なお、パケット欠落検出部 221の一構成例について図 7を用いて後 述する。 The packet loss detection unit 221, based on the sequence number input from the separation unit 202a, is missing on the transmission path between the received combined packet and the combined packet received immediately before that. The number of combined packets is detected, and the number of detected combined packets is output to the buffer amount correction unit 222. A configuration example of the packet loss detection unit 221 will be described later with reference to FIG.
[0078] ノ ッファ量補正部 222は、パケット欠落部 221から入力される欠落パケットの数を利 用し、シーケンス番号に対応付けて"欠落"（当該シーケンス番号が付加された結合 パケットを受信できな力つたことを示す。）、または、 "受信"（当該シーケンス番号が付 加された結合パケットを受信できたことを示す。 )を記憶する。 The knock out amount correction unit 222 uses the number of missing packets input from the packet missing portion 221 and associates it with the sequence number to “missing” (the combination to which the relevant sequence number is added. Indicates that the packet could not be received. Or “receive” (indicate that the combined packet with the corresponding sequence number has been received).
例えば、パケット欠落検出部 221から入力される欠落した結合パケットの数が 1、 0、 2、 0の場合には、シーケンス番号" 1"に"欠落"、シーケンス番号" 2"に"受信"、シー ケンス番号" 3"に"受信"、シーケンス番号" 4"に"欠落"、シーケンス番号" 5"に"欠 落"、シーケンス番号" 6"に"受信"、シーケンス番号" 7"に"受信"が対応付けられる  For example, if the number of missing combined packets input from the packet loss detection unit 221 is 1, 0, 2, 0, the sequence number "1" is "missing", the sequence number "2" is "receiving", Sequence number "3" to "receive", sequence number "4" to "missing", sequence number "5" to "missing", sequence number "6" to "receive", sequence number "7" to "receive "Is associated
[0079] ノ ッファ量補正部 222は、第 1受信バッファ 203から出力されるパケットの数をカウ ントし、次に出力されるパケットがいずれのシーケンス番号に対応するものであるかを 特定し、特定したシーケンス番号以降のシーケンス番号のうち対応付けられた値が" 欠落"であるシーケンス番号の数を特定する。 The buffer amount correction unit 222 counts the number of packets output from the first reception buffer 203, and identifies which sequence number the next output packet corresponds to, Among the sequence numbers after the identified sequence number, specify the number of sequence numbers whose associated value is "missing".
そして、ノ ッファ量補正部 222は、シーケンス番号の数に結合パケットを構成するパ ケットの数を乗算し、さらに乗算値にパケットのデータサイズを乗算する。この結果得 られる乗算値が本来なら第 1受信バッファ 203に蓄積されているはずの伝送路上で 欠落したパケットのデータ量 (以下、欠落量という。）である。  Then, the knock out amount correction unit 222 multiplies the number of sequence numbers by the number of packets making up the combined packet, and further multiplies the product value by the packet data size. This is the amount of data (hereinafter referred to as a dropout amount) of packets dropped on the transmission path that would otherwise have been accumulated in the first reception buffer 203.
[0080] バッファ量補正部 222は、蓄積量加算部 207から入力される加算値と求めた欠落 量を加算し、加算値を補正部 208へ出力する。  The buffer amount correction unit 222 adds the addition value input from the accumulated amount addition unit 207 and the calculated missing amount, and outputs the addition value to the correction unit 208.
第 2の実施の形態の補正部 208は、蓄積量加算部 207の加算値を用いる代わりに 、ノ ッファ量補正部 222から入力される加算値を利用し、バッファ量補正部 222から 入力される加算値が一定になるように、受信タイムスタンプタイマ 209のカウント速度 の制御を行う。  The correction unit 208 according to the second embodiment uses the addition value input from the buffer amount correction unit 222 instead of using the addition value of the accumulation amount addition unit 207, and is input from the buffer amount correction unit 222. The count speed of the reception time stamp timer 209 is controlled so that the added value becomes constant.
[0081] 加算値が増加すれば送信タイムスタンプタイマ 102のカウント速度より受信タイムス タンプタイマ 209のカウント速度が遅くなつている。このため、補正部 208は、カウント 速度を上げることを指示するための制御信号を受信タイムスタンプタイマ 209へ出力 する。受信タイムスタンプタイマ 209はこの制御信号を受けてカウント速度を上げる。  If the addition value increases, the count speed of the reception time stamp timer 209 is slower than the count speed of the transmission time stamp timer 102. Therefore, the correction unit 208 outputs a control signal for instructing to increase the count speed to the reception time stamp timer 209. The reception time stamp timer 209 receives this control signal to increase the counting speed.
[0082] また、加算値が減少すれば送信タイムスタンプタイマ 102のカウント速度より受信タ ィムスタンプタイマ 209のカウント速度が速くなつている。このため、補正部 208は、力 ゥント速度を下げることを指示するための制御信号を受信タイムスタンプタイマ 209へ 出力する。受信タイムスタンプタイマ 209はこの制御信号を受けてカウント速度を下げ る。 Also, if the added value decreases, the count speed of the reception time stamp timer 209 is faster than the count speed of the transmission time stamp timer 102. Therefore, the correction unit 208 sends a control signal to the reception time stamp timer 209 to instruct to decrease the velocity. Output. Receiving time stamp timer 209 receives this control signal to reduce the counting speed.
[0083] 本実施の形態のレート制御処理では、第 1送信バッファ 105のパケットの蓄積量 (第 1送信バッファ量)と第 1受信バッファ 203のパケットの蓄積量 (第 1受信バッファ量)と 本来なら第 1受信バッファ 203に蓄積されているはずの伝送路上で欠落したパケット の欠落量との和が一定になるように受信タイムスタンプタイマ 209のカウント速度の調 整が行われる。  In the rate control process of the present embodiment, the amount of packets accumulated in the first transmission buffer 105 (the amount of first transmission buffer) and the amount of packets accumulated in the first reception buffer 203 (the first amount of reception buffer) In this case, the count speed of the reception time stamp timer 209 is adjusted so that the sum of the amount of dropped packets on the transmission path which should be accumulated in the first reception buffer 203 becomes constant.
[0084] なお、受信装置 200aが行う時間軸復元処理は第 1の実施の形態の時間軸復元処 理と実質的に同じであるため、説明を省略する。  The time axis restoration process performed by the receiving device 200a is substantially the same as the time axis restoration process of the first embodiment, and thus the description thereof is omitted.
く欠落パケット検出部〉  Missing Packet Detection Unit>
図 6の受信装置 200のパケット欠落検出部 221の構成について図 7を参照しつつ 説明する。図 7は図 6のパケット欠落検出部 221の構成図である。  The configuration of the packet loss detection unit 221 of the receiving apparatus 200 of FIG. 6 will be described with reference to FIG. FIG. 7 is a block diagram of the packet loss detection unit 221 of FIG.
[0085] パケット欠落検出部 221は、記憶部 221aと、加算部 221bと、減算部 221cと、入力 端子 221dと、出力端子 221eとを有している。 The packet loss detection unit 221 includes a storage unit 221a, an addition unit 221b, a subtraction unit 221c, an input terminal 221d, and an output terminal 221e.
記憶部 221aは初期状態では 0を記憶している。  The storage unit 221a stores 0 in the initial state.
記憶部 221aは、入力端子 221dからシーケンス番号が入力されると、シーケンス番 号を記憶し、一つ前に記憶したシーケンス番号 (最初にシーケンス番号が入力された 場合には値" 0")を加算部 221bへ出力する。  When the sequence number is input from the input terminal 221 d, the storage unit 221 a stores the sequence number, and stores the sequence number stored immediately before (the value “0” when the sequence number is first input). It outputs to the addition part 221b.
[0086] 加算部 221bは、記憶部 221aから入力される値に 1を加算し、加算値を減算部 221 cへ出力する。 The addition unit 221b adds 1 to the value input from the storage unit 221a, and outputs the addition value to the subtraction unit 221c.
減算部 221cは、入力端子 221dから入力されているシーケンス番号から、加算部 2 21bから入力されている加算値を減算し、減算値を出力端子 221eからバッファ量補 正部 222へ出力する。ただし、減算部 221cにより求められた減算値は、入力端子 22 Idに現在入力されているシーケンス番号が付加された結合パケットと、入力端子 22 Idに現在入力されているシーケンス番号の一つ前に入力端子 221dに入力されたシ 一ケンス番号が付加された結合パケットとの間で失われた結合パケットの数を示して いる。  The subtraction unit 221c subtracts the addition value input from the addition unit 221b from the sequence number input from the input terminal 221d, and outputs the subtraction value from the output terminal 221e to the buffer amount correction unit 222. However, the subtraction value obtained by the subtraction unit 221c is the combined packet to which the sequence number currently input to the input terminal 22 Id is added, and the one immediately before the sequence number currently input to the input terminal 22 Id. It shows the number of combined packets lost with the combined packet with the sequence number input to the input terminal 221d.
[0087] 上述し本実施の形態によれば、送信装置に入力されるパケットの入力ビットレートが 可変ビットレートであり、かつ、伝送路における伝送ビットレートが固定ビットレートであ る場合において、伝送路上でパケットが欠落しても、送信装置と受信装置との間での 同期伝送を実現することができる。 As described above, according to the present embodiment, the input bit rate of the packet input to the transmitting device is To realize synchronous transmission between a transmitting device and a receiving device even if packets are dropped on the transmission path when the bit rate is variable and the transmission bit rate in the transmission path is a fixed bit rate. Can.
《第 3の実施の形態〉〉  Third Embodiment
本発明の第 3の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between a transmitting apparatus and a receiving apparatus according to the third embodiment of the present invention will be described with reference to the drawings.
[0088] 第 1の実施の形態及び第 2の実施の形態は、送信装置に入力されるパケットのビッ トレートが可変ビットレートであり、かつ、伝送路における伝送ビットレートが固定ビット レートである場合を対象としている。これに対して、本実施の形態及び後述の第 4の 実施の形態は、送信装置に入力されるパケットの入力ビットレートが可変ビットレート であり、かつ、伝送路における伝送ビットレートが固定ビットレートである場合を対象と する。 In the first embodiment and the second embodiment, the bit rate of the packet input to the transmitter is a variable bit rate, and the transmission bit rate in the transmission path is a fixed bit rate. The target is On the other hand, in the present embodiment and the fourth embodiment described later, the input bit rate of the packet input to the transmitter is a variable bit rate, and the transmission bit rate in the transmission path is a fixed bit rate. The case is
[0089] なお、第 1の実施の形態と実質的に同じ機能を有する構成要素には同じ符号を付 し、その構成要素については第 1の実施の形態における説明が適用できるため説明 を省略する。  Components having substantially the same functions as those of the first embodiment are denoted by the same reference numerals, and the description of the first embodiment can be applied to the components, and the description thereof is omitted. .
<同期伝送システム >  <Synchronous transmission system>
本実施の形態の同期伝送システムの構成について図 8を参照しつつ説明する。図 8は本実施の形態の同期伝送システムの構成図である。  The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. FIG. 8 is a block diagram of a synchronous transmission system according to the present embodiment.
[0090] 送信装置 100bと受信装置 200bとは伝送路 300bを介してパケットの送受信を行う 。伝送路 300bは、例えば無線伝送路である。 The transmission device 100b and the reception device 200b transmit and receive packets via the transmission path 300b. The transmission line 300 b is, for example, a wireless transmission line.
くパケット蓄積量〉  Packet storage capacity>
ここで、図 9の各構成要素の説明を行う前に、図 8の第 2送信バッファ 105bと第 2受 信バッファ 203bのパケットの蓄積量について図 9を参照しつつ説明する。図 9は図 8 の同期伝送システムのビットレート及びパケットの蓄積量の時間遷移図である。  Here, before describing each component of FIG. 9, the packet accumulation amount of the second transmission buffer 105b and the second reception buffer 203b of FIG. 8 will be described with reference to FIG. FIG. 9 is a time transition diagram of bit rates and packet storage amounts of the synchronous transmission system of FIG.
[0091] 送信装置 100bの第 2送信バッファ 105bに入力されるパケットの入力ビットレートは 固定ビットレートであり、その関数を f2(t)とする。また、伝送路における伝送ビットレー トは可変ビットレートであり、その関数を g2(t)とする。 The input bit rate of the packet input to the second transmission buffer 105 b of the transmitting device 100 b is a fixed bit rate, and its function is f 2 (t). Also, the transmission bit rate in the transmission line is a variable bit rate, and its function is g2 (t).
ただし、同期伝送では、第 2受信バッファ 203bから出力されるパケットの出力ビット レートは第 2送信バッファ 105bに入力されるパケットの入力ビットレートに等しくなるよ うに制御される。このことから、パケットが送信装置 100bに入力されて力も受信装置 2 OObから出力されるまでの遅延時間を delayで表すと、第 1受信バッファ 203bから出 力されるパケットの出力ビットレートはレート関数 f2(t- delay)となる。 However, in synchronous transmission, the output bit of the packet output from the second reception buffer 203b The rate is controlled to be equal to the input bit rate of the packet input to the second transmission buffer 105b. From this, if the delay time until the packet is input to the transmitting device 100b and the force is also output from the receiving device 2 OOb is represented by delay, the output bit rate of the packet output from the first receiving buffer 203b is a rate function It becomes f2 (t-delay).
[0092] ここで、（1)時刻 0で第 2送信バッファ 105bへのパケットの書き込みを開始、（2)時 刻 tOで第 2送信バッファ 105bからパケットの読み出しを開始、且つ、第 2受信バッファ 203bへのパケットの書き込みを開始、（3)時刻 tl (=delay)で第 2受信バッファ 203b 力 パケットの読み出しを開始するものとする。 Here, (1) start writing of the packet to the second transmission buffer 105b at time 0, (2) start reading of the packet from the second transmission buffer 105b at time tO, and the second reception buffer The writing of the packet to 203b is started, and (2) the second reception buffer 203b starts to read the packet at time tl (= delay).
この場合、関数 f2(t)は c(cは一定値)であり、関数 g2(t)は時刻 tOまでは 0、時刻 tO以 降は変動値である（図 9(a))。なお、関数 f2(t- delay)は時刻 tl(=delay)までは 0、時刻 t 1以降は cとなる。  In this case, the function f2 (t) is c (c is a constant value), and the function g2 (t) is 0 until time tO and is a fluctuation value after time tO (Fig. 9 (a)). The function f2 (t-delay) is 0 until time tl (= delay) and c after time t1.
[0093] 時刻 tにおける第 2送信バッファ 105bのパケットの蓄積量を表す蓄積量関数を Buff Tx2(t)とすると、時刻 tl以降の時刻 tにおける蓄積量関数 BuffTx2(t)は、下記の数 (6) により表される（図 9(b))。  Assuming that the accumulation function representing the accumulation amount of packets in the second transmission buffer 105b at time t is Buff Tx2 (t), the accumulation function BuffTx2 (t) at time t after time tl is 6) (Figure 9 (b)).
[0094] [数 6]  [0094] [Number 6]
Buf f Tx2 (t) - (t) dt · .· - (6)
Figure imgf000028_0001
時刻 tにおける第 2受信バッファ 203bのパケットの蓄積量を表す蓄積量関数を Buff Rx2(t)とすると、時刻 tl以降の時刻 tにおける蓄積量関数 BuffRx2(t)は、下記の数（7) により表される（図 9(b))。 Buf f Tx2 (t)-(t) dt · · ·-(6)
Figure imgf000028_0001
Assuming that the accumulation function representing the accumulation of packets in the second reception buffer 203b at time t is Buff Rx2 (t), the accumulation function BuffRx2 (t) at time t after time tl is given by the following number (7) It is represented (Figure 9 (b)).
[0095] [数 7] [0095] [Number 7]
BuffRx2(t)= rg2(t)dt-f f2 (t- delay) dt= I g2(t)dt—「cdt ' · - (7) BuffRx 2 (t) = r g 2 (t) dt-f f 2 (t-delay) dt = I g 2 (t) dt-"cdt '·-(7)
Jo Jo Jto JtO 上記の数 (6)と数（7)と力 、時刻 tl以降の時刻 tにおける第 2送信バッファ 105bの パケットの蓄積量と、時刻 tにおける第 2受信バッファ 203bのパケットの蓄積量との和 は、下記の数 (8)になる。  Jo Jo Jto JtO The above number (6) and number (7) and the power, the amount of accumulated packets of the second transmission buffer 105b at time t after time t1 and the amount of accumulation of packets at the second receive buffer 203b at time t The sum with is the following number (8).
[0096] [数 8] [Number 8]
BuffTx2(t) + BuffRx2(t) BuffTx2 (t) + BuffRx2 (t)
. . . ヽ  ....
=一定値 = Fixed value
Figure imgf000028_0002
このように、時刻 tl以降における時刻 tにおける第 2送信バッファ 105bのパケットの 蓄積量と、時刻 tにおける第 2受信バッファ 203bのパケットの蓄積量との和は一定に なる（図 9 (b) )。
Figure imgf000028_0002
Thus, the sum of the accumulated amount of packets in the second transmission buffer 105b at time t after time tl and the accumulated amount of packets in the second receive buffer 203b at time t becomes constant (FIG. 9 (b)). .
言い換えると、あるパケットが第 2送信バッファ 105bから読み出された直後の第 2送 信バッファ 105bのパケットの蓄積量と当該あるパケットが第 2受信バッファ 203bに書 き込まれた直後の第 2受信バッファ 203bのパケットの蓄積量との和が一定である。ま た、あるパケットが第 2送信バッファ 105bから読み出される直前の第 2送信バッファ 1 05bのパケットの蓄積量と、当該あるパケットが第 2受信バッファ 203bに書き込まれる 直前の第 2受信バッファ 203bのパケットの蓄積量との和が一定である。  In other words, the accumulated amount of packets in the second transmission buffer 105b immediately after a certain packet is read from the second transmission buffer 105b, and the second reception immediately after the certain packet is written to the second reception buffer 203b. The sum of the accumulated amount of packets in the buffer 203b is constant. Also, the amount of stored packets in the second transmission buffer 105b immediately before a certain packet is read out from the second transmission buffer 105b, and the packet in the second reception buffer 203b immediately before the certain packet is written to the second reception buffer 203b. The sum with the accumulated amount of is constant.
[0097] 本実施の形態は、上記関係を利用して、送信装置 100bと受信装置 200bとの間の 同期伝送を実現する。 The present embodiment implements synchronous transmission between transmitting apparatus 100b and receiving apparatus 200b, using the above relationship.
本実施の形態では、あるパケットが第 2送信バッファ 105bから読み出された直後の 第 2送信バッファ 105bのパケットの蓄積量と当該あるパケットが第 2受信バッファ 203 bに書き込まれた直後の第 2受信バッファ 203bのパケットの蓄積量との和を用いる。  In the present embodiment, the accumulation amount of packets in the second transmission buffer 105b immediately after a certain packet is read out from the second transmission buffer 105b and the second accumulated amount immediately after the certain packet is written to the second reception buffer 203b. The sum of the storage amount of packets in the reception buffer 203b is used.
[0098] なお、あるパケットが第 2送信バッファ 105bに読み出される直前の第 2送信バッファ 105bのパケットの蓄積量と、当該あるパケットが第 2受信バッファ 203bに書き込まれ る直前の第 2受信バッファ 203bのパケットの蓄積量との和を用いてもょ 、。 The stored amount of packets in the second transmission buffer 105b immediately before a certain packet is read out to the second transmission buffer 105b, and the second reception buffer 203b just before the certain packet is written to the second reception buffer 203b. You can use the sum of the amount of data stored in.
なお、同期伝送を実現するために上記の何れかを利用することが望ましいが、パケ ットが第 2送信バッファ 105b及び第 2受信バッファ 203bに十分蓄積されているとする と、同期伝送に利用する第 2送信バッファ 105bや第 2受信バッファ 203bの蓄積量を 取得するタイミングは若干ずれてもょ 、。  Although it is desirable to use any of the above to realize synchronous transmission, if packets are sufficiently accumulated in the second transmission buffer 105b and the second reception buffer 203b, it is used for synchronous transmission. The timing to acquire the accumulation amount of the second transmission buffer 105b and the second reception buffer 203b may be slightly shifted.
[0099] <送信装置 > <Sender Device>
送信装置 100bは、入力端子 101と、送信タイムスタンプタイマ 102と、タイムスタン プ付加部 103と、第 2送信バッファ 105bと、第 2送信バッファ量読出部 106bと、第 2 送信バッファ量付加部 104bと、送信処理部 107とを備える。  The transmitting apparatus 100b includes an input terminal 101, a transmission time stamp timer 102, a time stamp attaching unit 103, a second transmission buffer 105b, a second transmission buffer amount reading unit 106b, and a second transmission buffer amount attaching unit 104b. And the transmission processing unit 107.
第 2送信バッファ 105bは、 FIFOバッファで構成されており、入力されるパケットを 一時的に蓄積し、蓄積したパケットを可変ビットレートで出力する。なお、伝送効率を 高めるために、第 2送信バッファ 105bは複数のパケットを結合し、結合したパケット（ 結合パケット）を出力する。 The second transmission buffer 105 b is composed of a FIFO buffer, temporarily accumulates input packets, and outputs the accumulated packets at a variable bit rate. In addition, in order to improve transmission efficiency, the second transmission buffer 105 b combines a plurality of packets and combines the combined packets ( Output combined packet).
[0100] 第 2送信バッファ量読出部 106bは、第 2送信バッファ 105bのパケットの蓄積量 (以 下、第 2送信バッファ量という。）を読み出し、読み出した第 2送信バッファ量を第 2送 信バッファ量付加部 104bへ出力する。ここで、第 2送信バッファ量は、第 2送信バッ ファ量付加部 104bによって第 2送信バッファ量が付加される対象のパケットが第 2送 信バッファ 105bから読み出された直後の第 2送信バッファ 105bのパケットの蓄積量 である。  The second transmission buffer amount reading unit 106 b reads the accumulated amount of packets in the second transmission buffer 105 b (hereinafter referred to as the second transmission buffer amount), and the second transmission buffer amount read out is referred to as the second transmission. Output to buffer amount adding section 104 b. Here, the second transmission buffer amount is the second transmission buffer immediately after the target packet to which the second transmission buffer amount is added by the second transmission buffer amount adding unit 104b is read from the second transmission buffer 105b. 105b is the accumulated amount of packets.
[0101] ただし、第 2送信バッファ量は、受信装置 200での処理を容易にするために、タイム スタンプに関するデータ量を除く第 2送信バッファ 105bのデータ蓄積量とする。 なお、第 2送信バッファ量は、例えば、次のようにして算出することができる。タイムス タンプのデータサイズを固定とする。タイムスタンプのデータサイズに、第 2送信バッ ファ 105bに蓄積されているパケットの数 (入力されたパケットの数から出力したバケツ トの数を減算した値)を乗算する。第 2送信バッファ 105bの実際の蓄積量カゝら乗算値 を減算する。この減算値が第 2送信バッファ量になる。  However, the second transmission buffer amount is assumed to be the data accumulation amount of the second transmission buffer 105 b excluding the data amount related to the time stamp in order to facilitate the processing in the receiving device 200. The second transmission buffer amount can be calculated, for example, as follows. Fix the timestamp data size. The data size of the time stamp is multiplied by the number of packets stored in the second transmission buffer 105 b (the number of packets input minus the number of packets output). The actual accumulation amount of the second transmission buffer 105b is multiplied by the multiplication value. This subtraction value becomes the second transmission buffer amount.
[0102] 第 2送信バッファ量付加部 104bは、第 2送信バッファ 105bから入力される結合パ ケットの先頭に、第 2送信バッファ量読出部 106bから入力される第 2送信バッファ量 を付加する。  The second transmission buffer amount adding unit 104b adds the second transmission buffer amount input from the second transmission buffer amount reading unit 106b to the head of the combined packet input from the second transmission buffer 105b.
送信装置 100bでは、入力端子 101にパケットが入力される（図 10の N301)と、タ ィプスタンプ付加部 103はパケットの先頭に送信タイムスタンプタイマ 102から供給さ れるカウント値をタイムスタンプとして付加する（N302)。タイムスタンプが付加された パケットが第 2バッファ 105bに蓄積される。  In the transmitting apparatus 100b, when a packet is input to the input terminal 101 (N301 in FIG. 10), the timestamp attachment section 103 appends the count value supplied from the transmission timestamp timer 102 to the beginning of the packet as a timestamp ( N302). The packet to which the time stamp is added is stored in the second buffer 105 b.
[0103] 第 2送信バッファ 105bは結合パケットを出力する（N303)。第 2送信バッファ量付 加部 104bは、結合パケットの先頭に第 2送信バッファ量読出部 106bによって読み 出された第 2送信バッファ量を付加する (N304)。第 2送信バッファ量が付加された 結合パケットは送信処理部 107により所定の処理が施され、伝送路 300bへ送出され る。 The second transmission buffer 105 b outputs the combined packet (N 303). The second transmission buffer amount adding unit 104b adds the second transmission buffer amount read by the second transmission buffer amount reading unit 106b to the head of the combined packet (N304). The combined packet to which the second transmission buffer amount has been added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300b.
[0104] <受信装置 >  <Receiving Device>
受信装置 200bは、同期伝送の条件である時間軸復元処理、及びレート制御処理 などを行い、受信処理部 201と、分離部 202bと、第 2受信バッファ 203bと、タイムス タンプバッファ 204と、第 2受信バッファ量読出部 206bと、蓄積量加算部 207bと、補 正部 208bと、受信タイムスタンプタイマ 209と、比較部 210と、パケット読出部 211と 、出力端子 212とを備える。 The receiver 200b performs time axis restoration processing and rate control processing which are conditions of synchronous transmission. And the like, the reception processing unit 201, the separation unit 202b, the second reception buffer 203b, the time stamp buffer 204, the second reception buffer amount reading unit 206b, the accumulation amount addition unit 207b, the correction unit 208b, and the like. And a reception time stamp timer 209, a comparison unit 210, a packet reading unit 211, and an output terminal 212.
[0105] 分離部 202bは、受信処理部 201から入力される第 2送信バッファ量が付加された 結合パケットを、第 2送信バッファ量、複数のタイムスタンプ、及び複数のパケットに分 離する。そして、分離部 202bは、第 2送信バッファ量、複数のタイムスタンプ、及び複 数のパケットを、夫々、蓄積量加算部 207b、タイムスタンプバッファ 204、及び第 2受 信バッファ 203bへ出力する。  [0105] The separation unit 202b separates the combined packet added with the second transmission buffer amount input from the reception processing unit 201 into a second transmission buffer amount, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202b outputs the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the accumulation amount addition unit 207b, the time stamp buffer 204, and the second reception buffer 203b, respectively.
[0106] 第 2受信バッファ 203bは、 FIFOバッファで構成されており、入力されるパケットを 一時的に蓄積する。第 2受信バッファ 203bから出力されるパケットは出力端子 212 力も外部へ出力される（図 10の N305)。  The second reception buffer 203 b is formed of a FIFO buffer, and temporarily accumulates an input packet. The packet output from the second receive buffer 203b is also output to the outside through the output terminal 212 (N305 in FIG. 10).
第 2受信バッファ量読出部 206bは、第 2受信バッファ 203bのパケットの蓄積量 (以 下、第 2受信バッファ量という。）を読み出し、読み出した第 2受信バッファ量を蓄積量 加算部 207bへ出力する。ここで、第 2受信バッファ量は、分離部 202bから蓄積量カロ 算部 207bへ出力される第 2送信バッファ量が付加されていた結合パケットを構成す る複数のパケットが第 2受信バッファ 203bに書き込まれた直後の第 2受信バッファ 20 3bのパケットの蓄積量である。  The second reception buffer amount reading unit 206b reads the accumulated amount of packets in the second reception buffer 203b (hereinafter referred to as the second reception buffer amount), and outputs the read second reception buffer amount to the accumulated amount addition unit 207b. Do. Here, for the second reception buffer amount, a plurality of packets constituting the combined packet to which the second transmission buffer amount output from the separation unit 202b to the accumulation amount calo calculation unit 207b has been added is transmitted to the second reception buffer 203b. It is the accumulation amount of the packet of the 2nd reception buffer 203b immediately after being written.
[0107] 蓄積量加算部 207bは、分離部 202bから入力される第 2送信バッファ量と、第 2受 信バッファ量読出部 206bから入力される第 2受信バッファ量とを加算する。  The accumulation amount addition unit 207 b adds the second transmission buffer amount input from the separation unit 202 b and the second reception buffer amount input from the second reception buffer amount readout unit 206 b.
なお、分離部 202bから第 2受信バッファ 203bへ結合パケットを構成する複数のパ ケットが書き込まれた直後は、書き込まれた複数のパケットを結合した結合パケットに 付加されていた第 2送信バッファ量が分離部 202bから蓄積量加算部 207bに入力さ れている。  Immediately after the plurality of packets making up the combined packet are written from the separation unit 202b to the second reception buffer 203b, the second transmission buffer amount added to the combined packet obtained by combining the plurality of written packets is the same. It is input from the separation unit 202b to the accumulated amount addition unit 207b.
[0108] 補正部 208bは、蓄積量加算部 207bの加算値が一定になるように、受信タイムスタ ンプタイマ 209のカウント速度の制御を行う。  The correction unit 208 b controls the count speed of the reception time stamp timer 209 so that the addition value of the storage amount addition unit 207 b becomes constant.
加算値が増加すれば送信タイムスタンプタイマ 102のカウント速度より受信タイムス タンプタイマ 209のカウント速度が遅くなつている。このため、補正部 208bは、カウン ト速度を上げることを指示するための制御信号を受信タイムスタンプタイマ 209へ出 力する。 If the addition value increases, the count speed of the reception time stamp timer 209 is slower than the count speed of the transmission time stamp timer 102. Therefore, the correction unit 208b A control signal for instructing to increase the speed is output to reception time stamp timer 209.
[0109] また、加算値が減少すれば送信タイムスタンプタイマ 102のカウント速度より受信タ ィムスタンプタイマ 209のカウント速度が速くなつている。このため、補正部 208bは、 カウント速度を下げることを指示するための制御信号を受信タイムスタンプタイマ 209 へ出力する。  Also, if the addition value decreases, the count speed of the reception time stamp timer 209 is faster than the count speed of the transmission time stamp timer 102. Therefore, the correction unit 208b outputs a control signal for instructing to decrease the count speed to the reception time stamp timer 209.
なお、受信装置 200bが行う時間軸復元処理は、第 1の実施の形態で説明した時 間軸復元処理と実質的に同じであるため、説明を省略する。  The time axis restoration process performed by the receiving device 200b is substantially the same as the time axis restoration process described in the first embodiment, and thus the description thereof is omitted.
[0110] <レート制御処理 > <Rate Control Processing>
第 2受信バッファ量読出部 206bは、第 2受信バッファ 203bの第 2受信バッファ量を 読み出し、読み出した第 2受信バッファ量を蓄積量加算部 207bへ出力する。蓄積量 加算部 207bには分離部 202bから第 2送信バッファ量が入力されている。  The second reception buffer amount reading unit 206b reads the second reception buffer amount of the second reception buffer 203b, and outputs the read second reception buffer amount to the accumulation amount addition unit 207b. The second transmission buffer amount is input to the accumulation amount addition unit 207 b from the separation unit 202 b.
蓄積量加算部 207bは、分離部 202bから入力されている第 2送信バッファ量と、第 2受信バッファ量読出部 206bから入力された第 2受信バッファ量とを加算する。  The accumulation amount addition unit 207 b adds the second transmission buffer amount input from the separation unit 202 b and the second reception buffer amount input from the second reception buffer amount reading unit 206 b.
[0111] 補正部 208bは、加算結果が増加していれば受信タイムスタンプタイマ 209へカウ ント速度を上げることを指示するための制御信号を出力し、受信タイムスタンプタイマ 209はこの制御信号を受けてカウント速度を上げる。 If the addition result is increasing, correction section 208 b outputs a control signal for instructing reception time stamp timer 209 to increase the counting speed, and reception time stamp timer 209 receives this control signal. Increase the counting speed.
補正部 208は、加算結果が減少して ヽれば受信タイムスタンプタイマ 209へカウン ト速度を下げることを指示するための制御信号を出力し、受信タイムスタンプタイマ 2 09はこの制御信号を受けてカウント速度を下げる。  Correction section 208 outputs a control signal for instructing to decrease the counting speed to reception time stamp timer 209 if the addition result decreases, and reception time stamp timer 209 receives this control signal. Reduce the counting speed.
[0112] 上述し本実施の形態によれば、送信装置に入力されるパケットの入力ビットレートが 固定ビットレートであり、かつ、伝送路における伝送ビットレートが可変ビットレートであ つても、送信装置と受信装置との間での同期伝送を実現することができる。 According to the present embodiment described above, even if the input bit rate of the packet input to the transmitting apparatus is a fixed bit rate and the transmission bit rate in the transmission path is a variable bit rate, the transmitting apparatus It is possible to realize synchronous transmission between a and a receiver.
<補足 >  <Supplement>
(1)第 3の実施の形態及び後述する実施の形態では、受信タイムスタンプタイマ 20 9のカウント速度の補正に用いる第 2送信バッファ 105aの蓄積量及び第 2受信バッフ ァ 203aのパケットの蓄積量として、タイムスタンプが付加されて!ヽな 、データの蓄積 量を用いている。しかしながら、これに限らず、タイムスタンプを含むパケットの蓄積量 を用いるようにしてもよい。 (1) In the third embodiment and the embodiments to be described later, the accumulation amount of the second transmission buffer 105a and the accumulation amount of the packets of the second reception buffer 203a used to correct the count speed of the reception time stamp timer 209 As the time stamp is added! The amount of data storage is used. However, the storage amount of packets including time stamps is not limited to this. May be used.
[0113] 《第 4の実施の形態〉〉  Fourth Embodiment
本発明の第 4の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between a transmitting apparatus and a receiving apparatus according to the fourth embodiment of the present invention will be described with reference to the drawings.
本実施の形態は、第 3の実施の形態に、伝送路上で欠落したパケットがあっても送 信装置と受信装置との間で同期伝送を実現するための機能を付加したものである。  In this embodiment, a function is added to the third embodiment for realizing synchronous transmission between the transmitting apparatus and the receiving apparatus even if there is a missing packet on the transmission path.
[0114] なお、第 1から第 3の実施の形態と実質的に同じ機能を有する構成要素には同じ符 号を付し、その構成要素については第 1から第 3の実施の形態における説明が適用 できるため説明を省略する。 The components having substantially the same functions as those in the first to third embodiments are given the same reference numerals, and the description of the components in the first to third embodiments is omitted. Description is omitted as it is applicable.
<同期伝送システム >  <Synchronous transmission system>
本実施の形態の同期伝送システムの構成について図 11を参照しつつ説明する。 図 11は本実施の形態の同期伝送システムの構成図である。  The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. FIG. 11 is a block diagram of a synchronous transmission system according to the present embodiment.
[0115] 送信装置 100cと受信装置 200cとは伝送路 300dを介してパケットの送受信を行う 。なお、送信装置 100bに入力されるパケットは固定長パケットであるとする。 The transmitting device 100c and the receiving device 200c transmit and receive packets via the transmission path 300d. It is assumed that the packet input to the transmission device 100b is a fixed-length packet.
<送信装置 >  <Transmitter>
送信装置 100cは、第 3の実施の形態の送信装置 100bにシーケンス番号発生部 1 21とシーケンス番号付加部 122とを付加した構成になっている。  The transmitting apparatus 100c has a configuration in which a sequence number generating section 121 and a sequence number adding section 122 are added to the transmitting apparatus 100b of the third embodiment.
[0116] 送信装置 100cでは、入力端子 101にパケットが入力されると、タイプスタンプ付カロ 部 103はパケットの先頭に送信タイムスタンプタイマ 102から供給されるカウント値を タイムスタンプとして付加する。タイムスタンプが付加されたパケットが第 2バッファ 10 5bに蓄積される。 In the transmitting apparatus 100c, when a packet is input to the input terminal 101, the time stamped carover section 103 adds the count value supplied from the transmission time stamp timer 102 to the beginning of the packet as a time stamp. The packet to which the time stamp is added is accumulated in the second buffer 105 b.
第 2送信バッファ 105bは一定数のパケットを結合した結合パケットを出力する。第 2 送信バッファ量付加部 104bは、結合パケットの先頭に第 2送信バッファ量読出部 10 6bによって読み出された第 2送信バッファ量を付加し、シーケンス番号付加部 122は 、第 2送信バッファ量が付加された結合パケットの先頭に、シーケンス番号発生部 12 1から供給されたシーケンス番号を付加する。シーケンス番号と第 2送信バッファ量と が付加された結合パケットは、送信処理部 107により所定の処理が施され、伝送路 3 00bへ送出される。 [0117] <受信装置 > The second transmission buffer 105 b outputs a combined packet obtained by combining a certain number of packets. The second transmission buffer amount adder 104b adds the second transmission buffer amount read by the second transmission buffer amount reader 106b to the head of the combined packet, and the sequence number adder 122 adds the second transmission buffer amount. The sequence number supplied from the sequence number generation unit 121 is added to the beginning of the combined packet to which is added. The combined packet to which the sequence number and the second transmission buffer amount have been added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300b. <Receiver>
受信装置 200cは、第 3の実施の形態の受信装置 200に、パケット欠落検出部 221 とバッファ量補正部 222とを付加し、分離部 202bの代わりに分離部 202cを有する構 成になっている。  The receiving apparatus 200c has a configuration in which a packet loss detecting unit 221 and a buffer amount correcting unit 222 are added to the receiving apparatus 200 of the third embodiment, and a separating unit 202c is provided instead of the separating unit 202b. .
分離部 202cは、受信処理部 201から入力されるシーケンス番号及び第 2送信バッ ファ量が付加された結合パケットを、シーケンス番号、第 2送信バッファ量、複数のタ ィムスタンプ、及び複数のパケットに分離する。そして、分離部 202cは、シーケンス 番号、第 2送信バッファ量、複数のタイムスタンプ、及び複数のパケットを、夫々、パケ ット欠落検出部 221、蓄積量加算部 207b、タイムスタンプバッファ 204、及び第 2受 信バッファ 203bへ出力する。  The separation unit 202c separates the combined packet, to which the sequence number and the second transmission buffer amount are input from the reception processing unit 201, into a sequence number, a second transmission buffer amount, a plurality of time stamps, and a plurality of packets. Do. Then, the separation unit 202c transmits the sequence number, the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the packet loss detection unit 221, the storage amount addition unit 207b, the time stamp buffer 204, and the second packet. 2 Output to the receive buffer 203b.
[0118] 受信装置 200cにより行われるレート制御処理は以下の通りである。  The rate control process performed by the receiving device 200c is as follows.
分離部 202cによって第 2受信バッファ 203bに 1つの結合パケットを構成する複数 のパケットが書き込まれた直後、第 2受信バッファ量読出部 206bは、第 2受信バッフ ァ 203bの第 2受信バッファ量を読み出し、読み出した第 2受信バッファ量を蓄積量カロ 算部 207bへ出力する。  The second reception buffer amount reading unit 206b reads the second reception buffer amount of the second reception buffer 203b immediately after the separation unit 202c writes a plurality of packets forming one combined packet in the second reception buffer 203b. The read second reception buffer amount is output to the accumulation amount calo calculating unit 207b.
[0119] また、パケット欠落検出部 221は、第 2の実施の形態において説明した手順により、 分離部 202cから入力されるシーケンス番号を利用して伝送路上で欠落した結合パ ケットの数を検出し、検出した結合パケットの数をバッファ量補正部 222へ出力する。 蓄積量加算部 207bは、分離部 202cから入力される第 2送信バッファ量と、第 2受 信バッファ量読出部 206bから入力される第 2受信バッファ量とを加算する。  Also, according to the procedure described in the second embodiment, the packet loss detection unit 221 detects the number of coupled packets lost on the transmission path using the sequence number input from the separation unit 202c. The number of combined packets detected is output to the buffer amount correction unit 222. The accumulation amount addition unit 207 b adds the second transmission buffer amount input from the separation unit 202 c and the second reception buffer amount input from the second reception buffer amount reading unit 206 b.
[0120] ノ ッファ量補正部 222は、第 2の実施の形態において説明した手順により、本来な ら第 2受信バッファ 203bに蓄積されているはずの、伝送路上で欠落した結合パケット を構成するパケットのデータ量 (欠落パケット量)を算出する。そして、バッファ量補正 部 222は、蓄積量加算部 207bから入力される加算値に、算出した欠落パケット量を 加算する。  According to the procedure described in the second embodiment, the packet amount correction unit 222 is a packet that forms a missing combined packet on the transmission path, which should be originally stored in the second reception buffer 203b. Calculate the amount of data (missing packet amount) of Then, the buffer amount correction unit 222 adds the calculated missing packet amount to the addition value input from the accumulation amount addition unit 207b.
[0121] 補正部 208bは、バッファ量補正部 222から入力される加算値を基に当該加算値が 一定になるように受信タイムスタンプタイマ 209のカウント速度を制御する。  The correction unit 208 b controls the count speed of the reception time stamp timer 209 based on the addition value input from the buffer amount correction unit 222 so that the addition value becomes constant.
加算値が増加すれば送信タイムスタンプタイマ 102のカウント速度より受信タイムス タンプタイマ 209のカウント速度が遅くなつている。このため、補正部 208bは、カウン ト速度を上げることを指示するための制御信号を受信タイムスタンプタイマ 209へ出 力する。受信タイムスタンプタイマ 209はこの制御信号を受けてカウント速度を上げる If the added value increases, the reception timestamp is greater than the count speed of the transmission timestamp timer 102. The counting speed of the tamp timer 209 is slow. Therefore, the correction unit 208 b outputs a control signal for instructing to increase the count speed to the reception time stamp timer 209. Reception time stamp timer 209 receives this control signal to increase the counting speed
[0122] また、加算値が減少すれば送信タイムスタンプタイマ 102のカウント速度より受信タ ィムスタンプタイマ 209のカウント速度が速くなつている。このため、補正部 208bは、 カウント速度を下げることを指示するための制御信号を受信タイムスタンプタイマ 209 へ出力する。受信タイムスタンプタイマ 209はこの制御信号を受けてカウント速度を 下げる。 Also, if the addition value decreases, the count speed of the reception time stamp timer 209 is faster than the count speed of the transmission time stamp timer 102. Therefore, the correction unit 208b outputs a control signal for instructing to decrease the count speed to the reception time stamp timer 209. Receiving time stamp timer 209 receives this control signal to reduce the counting speed.
[0123] なお、受信装置 200cが行う時間軸復元処理は第 1の実施の形態の時間軸復元処 理と実質的に同じであるため、説明を省略する。  The time axis restoration process performed by the receiving device 200c is substantially the same as the time axis restoration process of the first embodiment, and thus the description thereof is omitted.
上述し本実施の形態によれば、送信装置に入力されるパケットの入力ビットレートが 固定ビットレートであり、かつ、伝送路における伝送ビットレートが可変ビットレートであ る場合において、伝送路上でパケットが欠落しても、送信装置と受信装置との間での 同期伝送を実現することができる。  According to the embodiment described above, when the input bit rate of the packet input to the transmission apparatus is a fixed bit rate and the transmission bit rate in the transmission path is a variable bit rate, the packet on the transmission path is Even if L is missing, synchronous transmission can be realized between the transmitting device and the receiving device.
[0124] 《第 5の実施の形態〉〉  Fifth Embodiment
本発明の第 5の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between a transmitting apparatus and a receiving apparatus according to the fifth embodiment of the present invention will be described with reference to the drawings.
第 1の実施の形態及び第 2の実施の形態は、送信装置に入力されるパケットのビッ トレートが可変ビットレートであり、かつ、伝送路における伝送ビットレートが固定ビット レートである場合を対象としている。また、第 3の実施の形態及び第 4の実施の形態 は、送信装置に入力されるパケットのビットレートが固定ビットレートであり、かつ、伝 送路における伝送ビットレートが可変ビットレートである場合を対象としている。これに 対して、本実施の形態及び後述する第 6〜第 7の実施の形態は、送信装置に入力さ れるパケットのビットレートが可変ビットレートであり、かつ、伝送路における伝送ビット レートが可変ビットレートである場合を対象とする。  The first embodiment and the second embodiment are directed to the case where the bit rate of the packet input to the transmission apparatus is a variable bit rate and the transmission bit rate in the transmission path is a fixed bit rate. There is. In the third and fourth embodiments, the bit rate of the packet input to the transmitter is a fixed bit rate, and the transmission bit rate in the transmission path is a variable bit rate. The target is On the other hand, in this embodiment and the sixth to seventh embodiments described later, the bit rate of the packet input to the transmitter is a variable bit rate, and the transmission bit rate in the transmission path is variable. The case of bit rate is considered.
[0125] なお、第 1〜第 4の実施の形態と実質的に同じ機能を有する構成要素には同じ符 号を付し、その構成要素については第 1〜第 4の実施の形態における説明が適用で きるため説明を省略する。 The components having substantially the same functions as those in the first to fourth embodiments are given the same reference numerals, and the description of the components in the first to fourth embodiments is omitted. Apply Description is omitted because it is possible.
<同期伝送システム >  <Synchronous transmission system>
本実施の形態の同期伝送システムの構成について図 12を参照しつつ説明する。 図 12は本実施の形態の同期伝送システムの構成図である。  The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. FIG. 12 is a block diagram of a synchronous transmission system of the present embodiment.
[0126] 送信装置 lOOdと受信装置 200dとは伝送路 300bを介してパケットの送受信を行う The transmitting device lOOod and the receiving device 200d transmit and receive packets via the transmission path 300b.
<送信装置 > <Transmitter>
送信装置 lOOdは、入力端子 101と第 1送信部 150と第 2送信部 160とを備える。  The transmitter lOOd includes an input terminal 101, a first transmitter 150, and a second transmitter 160.
[0127] 第 1送信部 150は、第 1の実施の形態の送信装置 100の入力端子 101と送信処理 部 107とを除くブロックと同じ構成をしており、可変ビットレートで入力されるパケットを 固定ビットレートで第 2送信部 160へ出力する。パケットの第 1送信バッファ 105から の固定ビットレートでの出力制御は、例えば、 MPEG2 TSの場合、ストリームのヘッダ からストリームレートを抽出し、抽出したストリームレートに、入力されるパケットに付カロ したタイムスタンプや第 1送信バッファ量のオーバヘッド分のデータに相当するレート をカロえたレートでパケットの出力を行うことにより実現することができる。 The first transmission unit 150 has the same configuration as the block excluding the input terminal 101 of the transmission apparatus 100 according to the first embodiment and the transmission processing unit 107, and receives packets input at a variable bit rate. Output to the second transmission unit 160 at a fixed bit rate. The output control at a fixed bit rate from the first transmission buffer 105 of the packet is, for example, in the case of MPEG2 TS, the stream rate is extracted from the stream header, and the extracted stream rate is added to the input packet. This can be realized by outputting a packet at a rate corresponding to data corresponding to overhead data of the stamp and the first transmission buffer amount.
[0128] 第 2送信部 160は、第 3の実施の形態の送信装置 100bの入力端子 101、送信タイ ムスタンプタイマ 102及びタイムスタンプ付カ卩部 103を除くブロックと同じ構成をして おり、第 1送信部 150から固定ビットレートで入力されるパケットを可変ビットレートで 伝送路 300bへ送出する。 The second transmission unit 160 has the same configuration as the block excluding the input terminal 101 of the transmission device 100b of the third embodiment, the transmission time stamp timer 102, and the time stamp attached portion 103. (1) Transmit a packet input from the transmitting unit 150 at a fixed bit rate to the transmission path 300b at a variable bit rate.
送信装置 100dでは、入力端子 101にパケットが入力される（図 13の N501)と、タ ィプスタンプ付加部 103はパケットの先頭に送信タイムスタンプタイマ 102から供給さ れるカウント値をタイムスタンプとして付加し (N502)、さらに、第 1送信バッファ量付 加部 104は、タイムスタンプが付加されたパケットの先頭に第 1送信バッファ量読出部 106によって読み出された第 1送信バッファ量を付加する (N503)。タイムスタンプ及 び第 1送信バッファ量が付加されたパケットが第 1送信バッファ 105に蓄積される。  In the transmitting apparatus 100d, when a packet is input to the input terminal 101 (N501 in FIG. 13), the timestamp attachment section 103 appends the count value supplied from the transmission timestamp timer 102 to the beginning of the packet as a timestamp ( N 502) Further, the first transmission buffer amount appending unit 104 adds the first transmission buffer amount read by the first transmission buffer amount reading unit 106 to the beginning of the packet to which the time stamp is added (N 503) . The packet to which the time stamp and the first transmission buffer amount are added is accumulated in the first transmission buffer 105.
[0129] 第 1送信バッファ 105に蓄積されたパケットは、第 1送信バッファ 105から固定ビット レートで出力され、第 2送信バッファ 105bに蓄積される。 The packets accumulated in the first transmission buffer 105 are output from the first transmission buffer 105 at a fixed bit rate, and accumulated in the second transmission buffer 105 b.
第 2送信バッファ 105bは複数のパケットを結合した結合パケットを出力する (N504 ) o第 2送信バッファ量付加部 104bは、結合パケットの先頭に第 2送信バッファ量読 出部 106bによって読み出された第 2送信バッファ量を付加する（N505)。第 2送信 バッファ量が付加された結合パケットは送信処理部 107により所定の処理が施され、 伝送路 300bへ送出される。 The second transmission buffer 105 b outputs a combined packet obtained by combining a plurality of packets (N 504 The second transmission buffer amount adder 104b adds the second transmission buffer amount read by the second transmission buffer amount reader 106b to the head of the combined packet (N505). The combined packet to which the second transmission buffer amount is added is subjected to predetermined processing by the transmission processing unit 107, and is sent to the transmission path 300b.
[0130] <受信装置 >  <Receiver>
受信装置 200dは、第 2受信部 260と第 1受信部 250と出力端子 212とを備える。 第 2受信部 260は、受信装置 200bが行うレート制御処理と実質的に同じレート制 御処理を行う。ただし、第 2受信部 260は、受信装置 200bが行う時間軸復元処理を 行わない。第 2受信部 260で時間軸復元処理を行わないのは、受信装置 200dから パケットが出力されるときに時間軸で復元されれば十分であり、第 2受信部 260は、 第 1送信部 150から第 2送信部 160へ出力される固定ビットレートに等しい固定ビット レートで第 1受信部 250へパケットを出力することができれば十分だ力もである。  The receiver 200 d includes a second receiver 260, a first receiver 250, and an output terminal 212. The second receiving unit 260 performs substantially the same rate control processing as the rate control processing performed by the receiving device 200b. However, the second receiving unit 260 does not perform the time axis restoration process performed by the receiving device 200b. It is sufficient for the second receiving unit 260 not to perform time-axis restoration processing if it is restored on the time-axis when a packet is output from the receiving device 200 d, and the second receiving unit 260 performs the first transmission unit 150. It is sufficient if the packet can be output to the first receiver 250 at a fixed bit rate equal to the fixed bit rate output to the second transmitter 160.
[0131] 第 2受信部 260は、受信処理部 201と、分離部 202dと、第 2受信バッファ 203bと第 2受信バッファ量読出部 206bと蓄積量加算部 207bと補正部 208bと読出レート制御 部 251とを備える。  The second reception unit 260 includes a reception processing unit 201, a separation unit 202d, a second reception buffer 203b, a second reception buffer amount reading unit 206b, a storage amount addition unit 207b, a correction unit 208b, and a read rate control unit. And 251.
分離部 202dは、受信処理部 201から入力される第 2送信バッファ量が付加された 結合パケットを、複数の第 1送信バッファ量、第 2送信バッファ量、複数のタイムスタン プ、及び複数のパケットに分離する。そして、分離部 202dは、複数の第 1送信バッフ ァ量、第 2送信バッファ量、複数のタイムスタンプ、及び複数のパケットを、第 1送信バ ッファ量バッファ 205、蓄積量加算部 207b、タイムスタンプバッファ 204、及び第 2受 信バッファ 203bへ出力する。  The separation unit 202d is configured to receive the combined packet to which the second transmission buffer amount input from the reception processing unit 201 is added, the plurality of first transmission buffer amounts, the second transmission buffer amount, the plurality of time stamps, and the plurality of packets. To separate. Then, the separation unit 202d is configured to transmit the plurality of first transmission buffer amounts, the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the first transmission buffer amount buffer 205, the accumulation amount addition unit 207b, and the time stamp. Output to the buffer 204 and the second reception buffer 203b.
[0132] 本実施の形態の補正部 208bは、受信タイムスタンプタイマ 209の可変周波数発振 器 209aの発振周波数を制御する代わりに、読出レート制御部 251の備える後述する 可変周波数発振器 25 laの発振周波数を後述するように制御する。 The correction unit 208 b of the present embodiment controls the oscillation frequency of the variable frequency oscillator 209 a of the reception time stamp timer 209 instead of controlling the oscillation frequency of the variable frequency oscillator 25 la described later provided in the read rate control unit 251. Control as described later.
読出レート制御部 251は、第 2受信バッファ 203bからのパケットの出力ビットレート を制御する。  The read rate control unit 251 controls the output bit rate of the packet from the second reception buffer 203b.
[0133] 第 2受信部 260により行われるレート制御処理は以下の通りである。  The rate control process performed by the second receiving unit 260 is as follows.
補正部 208bは、第 2送信バッファ 105bから結合パケットが読み出された直後の第 2送信バッファ 105bのパケットの蓄積量 (分離部 202dから入力される第 2送信バッフ ァ量)と、第 2受信バッファ 203bに当該結合パケットを構成する複数のパケットが書き 込まれた直後の第 2受信バッファ 203bのパケットの蓄積量 (第 2受信バッファ量読出 部 206bにより読み出され、第 2受信バッファ量読出部 206bから入力された第 2受信 ノ ッファ量）とを加算し、加算値が一定になるように読出レート制御部 251のレート制 御を行う。 The correction unit 208 b is configured to read the second packet immediately after the combined packet is read from the second transmission buffer 105 b. 2 Packet accumulation amount of the transmission buffer 105 b (the second transmission buffer amount input from the separation unit 202 d), and the second of the second reception buffer 203 b immediately after the plurality of packets constituting the combined packet are written. Adds the packet accumulation amount of the reception buffer 203b (the second reception buffer amount read by the second reception buffer amount reading unit 206b and input from the second reception buffer amount reading unit 206b), and the addition value is constant The rate control of the read rate control unit 251 is performed so that
[0134] 加算値が増加すれば第 2送信バッファ 105bからのパケットの出力ビットレートより第 2受信バッファ 203bからのパケットの出力ビットレートが低くなつている。このため、補 正部 208bは、出力ビットレートを上げることを指示するための制御信号を読出レート 制御 251へ出力する。  If the addition value increases, the output bit rate of the packet from the second reception buffer 203b becomes lower than the output bit rate of the packet from the second transmission buffer 105b. Therefore, the correction unit 208b outputs a control signal for instructing to increase the output bit rate to the read rate control 251.
また、加算値が減少すれば第 2送信バッファ 105bからのパケットの出力ビットレート より第 2受信バッファ 203bからのパケットの出力ビットレートが高くなつている。このた め、補正部 208bは、出力ビットレートを下げることを指示するための制御信号を読出 レート制御 251へ出力する。  Also, if the added value decreases, the output bit rate of the packet from the second reception buffer 203b becomes higher than the output bit rate of the packet from the second transmission buffer 105b. Therefore, the correction unit 208b outputs a control signal for instructing to reduce the output bit rate to the read rate control 251.
[0135] 読出レート制御部 251は、補正部 208bからの制御信号に基づき第 2受信バッファ 203bからのパケットの出力ビットレートを制御する。  The read rate control unit 251 controls the output bit rate of the packet from the second reception buffer 203b based on the control signal from the correction unit 208b.
<読出レート制御部 >  <Read rate control unit>
図 12の受信装置 200dの読出レート制御部 251の構成について図 14を参照しつ つ説明する。図 14は図 12の読出レート制御部 251の構成図である。  The configuration of the read rate control unit 251 of the receiver 200d of FIG. 12 will be described with reference to FIG. FIG. 14 is a block diagram of the read rate control unit 251 of FIG.
[0136] 読出レート制御部 251は、可変周波数発振器 25 laと、じ !^読出部2511)と、制御 信号入力端子 251cと、読出信号出力端子 251dと、クロック出力端子 251eとを備え る。 The read rate control unit 251 includes a variable frequency oscillator 25 la, a! ^ Read unit 2511 ) , a control signal input terminal 251c, a read signal output terminal 251d, and a clock output terminal 251e.
可変周波数発振器 25 laは、所定範囲の周波数のクロック信号を発振することが可 能な発振器であり、発振した周波数のクロック信号をカウンタ 209bへ供給するととも に、クロック信号をクロック出力端子 251eへ出力する。  The variable frequency oscillator 25 la is an oscillator capable of oscillating a clock signal of a predetermined range of frequency and supplies a clock signal of the oscillated frequency to the counter 209 b and outputs the clock signal to the clock output terminal 251 e. Do.
[0137] 可変周波数発振器 251aは、制御端子 209cに入力される制御信号が第 2受信バッ ファ 203bからパケットの読み出しを行う読出レートを上げることを指示している場合に は発振周波数を上げ、当該制御信号が第 2受信バッファ 203bからパケットの読み出 しを行う読出レートを下げることを指示している場合には発振周波数を下げる。 The variable frequency oscillator 251a raises the oscillation frequency when the control signal input to the control terminal 209c instructs to increase the read rate at which packets are read from the second receive buffer 203b, and the variable frequency oscillator 251a increases the oscillation frequency. Control signal reads packet from second receive buffer 203b If it is instructed to lower the read rate to be used, the oscillation frequency is lowered.
CBR読出部 251bは、可変周波数発振器 251aから入力されるクロック信号をカウ ントするカウンタで構成されており、一定数のクロック信号をカウントすることにより読 出信号を生成する。 CBR読出部 251は、生成した読出信号を読出信号出力端子 25 Idから第 2受信バッファ 203bへ出力する。第 2受信バッファ 203bは読出信号を受け て、蓄積していた 1つのパケットを第 1受信バッファ 203へ出力する。  The CBR reading unit 251b is configured by a counter that counts the clock signal input from the variable frequency oscillator 251a, and generates a reading signal by counting a fixed number of clock signals. The CBR read unit 251 outputs the generated read signal from the read signal output terminal 25 Id to the second reception buffer 203b. The second reception buffer 203 b receives the read signal and outputs one stored packet to the first reception buffer 203.
[0138] 図 12の説明に戻って、第 1受信部 250は、第 1の実施の形態の受信装置 200の受 信処理部 201と分離部 202と出力端子 212とを除くブロックと同じ構成をしている。第 1受信部 250は、第 1の実施の形態の受信装置 200の時間軸復元処理とレート制御 処理と実質的に同じ時間軸復元処理とレート制御処理を行う。  Returning to the description of FIG. 12, the first receiving unit 250 has the same configuration as the block excluding the reception processing unit 201, the separation unit 202, and the output terminal 212 of the receiving device 200 according to the first embodiment. doing. The first reception unit 250 performs time axis restoration processing and rate control processing that are substantially the same as the time axis restoration processing and rate control processing of the reception device 200 according to the first embodiment.
第 1受信部 250により行われるレート制御処理は以下の通りである。  The rate control process performed by the first receiver 250 is as follows.
[0139] 第 1受信部 250において、補正部 208は第 1送信バッファ 105にパケットが書き込ま れる直前の第 1送信バッファ 105のパケットの蓄積量（第 1送信バッファ量バッファ 20 5から取り出された第 1送信バッファ量)と当該パケットが第 1受信バッファから読み出 される直前の第 1受信バッファ 203のパケットの蓄積量 (第 1受信バッファ量読出部 2 06により読み出され、第 1受信バッファ量読出部 206から入力された第 1受信バッフ ァ量）とを加算し、加算値が一定になるように、受信タイムスタンプタイマ 209の可変 発振周波数器 209aの発振周波数の制御を行う。  In the first reception unit 250, the correction unit 208 stores the accumulated amount of packets in the first transmission buffer 105 immediately before the packet is written to the first transmission buffer 105 (the first transmission buffer amount buffer 205 fetches the first (1 transmission buffer amount) and the accumulated amount of packets in the first reception buffer 203 immediately before the packet is read from the first reception buffer (the first reception buffer amount is read by the first reception buffer amount reading unit 206, and the first reception buffer amount The oscillation frequency of the variable oscillation frequency unit 209a of the reception time stamp timer 209 is controlled so as to add the first reception buffer amount) input from the reading unit 206 and make the addition value constant.
[0140] なお、補正部 208は加算値が増力!]していれば可変周波数発振器 209aの発振周 波数が高くなるように可変周波数発振器 209aを制御し、加算値が減少して 、れば可 変周波数発振器 209aの発振周波数が低くなるように可変周波数発振器 209aを制 御する。  It should be noted that correction section 208 controls variable frequency oscillator 209a to increase the oscillation frequency of variable frequency oscillator 209a if the added value is increased!], And the added value may be decreased. The variable frequency oscillator 209a is controlled to lower the oscillation frequency of the variable frequency oscillator 209a.
第 1受信部 250により行われる時間軸復元処理は以下の通りである。  The time axis restoration process performed by the first reception unit 250 is as follows.
受信タイムスタンプタイマ 209の可変周波数発振器 209aは補正部 208により制御 された周波数で発振し、カウンタ 209bは可変周波数発振器 209aにより発振された 周波数のクロック信号をカウントする。  The variable frequency oscillator 209a of the reception time stamp timer 209 oscillates at a frequency controlled by the correction unit 208, and the counter 209b counts clock signals of the frequency oscillated by the variable frequency oscillator 209a.
[0141] 比較部 210は、タイムスタンプバッファ 204から取り出したタイムスタンプが示すカウ ント値とカウンタ 209bのカウント値とを比較し、両者が一致すればパケット読出信号 をパケット読出部 211へ出力する。パケット読出部 211は比較部 210からのパケット 読出信号を受けて、第 1受信バッファ 203から 1つのパケットを出力される。これにより 、第 1受信バッファ 203から 1つのパケットが出力され、第 1出力バッファ 203から出力 されたパケットは出力端子 212から外部へ出力される。 Comparison unit 210 compares the count value indicated by the time stamp extracted from time stamp buffer 204 with the count value of counter 209 b, and if both match, the packet read signal Are output to the packet reading unit 211. The packet read unit 211 receives the packet read signal from the comparison unit 210 and outputs one packet from the first reception buffer 203. As a result, one packet is output from the first reception buffer 203, and the packet output from the first output buffer 203 is output from the output terminal 212 to the outside.
[0142] 上述し本実施の形態によれば、送信装置に入力されるパケットの入力ビットレートが 可変ビットレートであり、かつ、伝送路における伝送ビットレートが可変ビットレートであ つても、送信装置と受信装置との間での同期伝送を実現することができる。 According to the present embodiment described above, even if the input bit rate of the packet input to the transmitting device is a variable bit rate and the transmission bit rate in the transmission path is a variable bit rate, the transmitting device It is possible to realize synchronous transmission between a and a receiver.
《第 6の実施の形態〉〉  Sixth Embodiment
本発明の第 6の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between a transmitting apparatus and a receiving apparatus according to the sixth embodiment of the present invention will be described with reference to the drawings.
[0143] 第 6の実施の形態は、第 5の実施の形態の送信装置 lOOd及び受信装置 200dの 構成を簡単にし、入力ビットレート及び伝送ビットレートの双方が可変ビットレートの場 合であっても同期伝送を実現することができるようにしたものである。 The sixth embodiment simplifies the configuration of the transmitting apparatus lOOd and the receiving apparatus 200d of the fifth embodiment, and both the input bit rate and the transmission bit rate are variable bit rates. Is also able to realize synchronous transmission.
なお、第 1〜第 5の実施の形態と実質的に同じ機能を有する構成要素には同じ符 号を付し、その構成要素については第 1〜第 5の実施の形態における説明が適用で きるため説明を省略する。  The components having substantially the same functions as those in the first to fifth embodiments are given the same reference numerals, and the description in the first to fifth embodiments can be applied to the components. Therefore, the explanation is omitted.
[0144] <同期伝送システム > <Synchronous Transmission System>
本実施の形態の同期伝送システムの構成について図 15を参照しつつ説明する。 図 15は本実施の形態の同期伝送システムの構成図である。  The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. FIG. 15 is a block diagram of a synchronous transmission system according to the present embodiment.
送信装置 100eと受信装置 200eとは伝送路 300bを介してパケットの送受信を行う  The transmitting apparatus 100e and the receiving apparatus 200e transmit and receive packets via the transmission path 300b.
[0145] <送信装置 > <Transmitter>
送信装置 100eは、入力端子 101と第 1送信部 150eと第 5の実施の形態の第 2送 信部 160と同じ構成をした第 2送信部 160eと備える。  The transmitting apparatus 100e includes an input terminal 101, a first transmitting unit 150e, and a second transmitting unit 160e having the same configuration as the second transmitting unit 160 of the fifth embodiment.
第 1送信部 150eは、送信タイムスタンプタイマ 102と、タイムスタンプ付加部 103と、 可変ビットレートで入力されるパケットを一時的に蓄積し、蓄積したパケットを固定ビッ トレートで出力する第 1送信バッファ部 105を有する。パケットの第 1送信バッファ 105 力もの固定ビットレートでの出力制御は、例えば、 MPEG2 TSの場合、ストリームのへ ッダからストリームレートを抽出し、抽出したストリームレートに、入力されるパケットに 付カ卩したタイムスタンプのオーバヘッド分のデータに相当するレートをカ卩えたレートで パケットの出力を行うことにより実現することができる。 The first transmission unit 150e temporarily accumulates the packets input at the transmission time stamp timer 102, the time stamp addition unit 103, and the variable bit rate, and outputs the accumulated packets at the fixed bit rate. It has part 105. For example, in the case of MPEG2 TS, the output control at a fixed bit rate of the first transmission buffer 105 power of the packet is It is realized by extracting the stream rate from the streamer and outputting the stream at a rate corresponding to the data of the overhead portion of the timestamp added to the input packet to the extracted stream rate. be able to.
[0146] 送信装置 lOOeでは、入力端子 101にパケットが入力されると、タイプスタンプ付カロ 部 103はパケットの先頭に送信タイムスタンプタイマ 102から供給されるカウント値を タイムスタンプとして付加する。タイムスタンプが付加されたパケットが第 1送信バッフ ァ 105に蓄積される。  In the transmitting apparatus lOOe, when a packet is input to the input terminal 101, the time stamped carover unit 103 adds the count value supplied from the transmission time stamp timer 102 to the beginning of the packet as a time stamp. The packet to which the time stamp is added is accumulated in the first transmission buffer 105.
第 1送信バッファ 105に蓄積されたパケットは、第 1送信バッファ 105から固定ビット レートで出力され、第 2送信バッファ 105bに蓄積される。  The packets accumulated in the first transmission buffer 105 are output from the first transmission buffer 105 at a fixed bit rate, and accumulated in the second transmission buffer 105 b.
[0147] 第 2送信バッファ 105bは複数のパケットを結合した結合パケットを出力する。第 2送 信バッファ量付加部 104bは、結合パケットの先頭に第 2送信バッファ量読出部 106b によって読み出された第 2送信バッファ量を付加する。第 2送信バッファ量が付加さ れた結合パケットは送信処理部 107により所定の処理が施され、伝送路 300bへ送 出される。 The second transmission buffer 105 b outputs a combined packet obtained by combining a plurality of packets. The second transmission buffer amount adder 104b adds the second transmission buffer amount read by the second transmission buffer amount reader 106b to the head of the combined packet. The combined packet to which the second transmission buffer amount has been added is subjected to predetermined processing by the transmission processing unit 107, and is sent out to the transmission path 300b.
[0148] <受信装置 > <Receiver>
受信装置 200eは、第 2受信部 260eと第 1受信部 250eと入力端子 221とを備える。 第 2受信部 260eは、第 2受信部 260と同様に、受信装置 200bが行うレート制御処 理と実質的に同じレート制御処理を行うが、受信装置 200bが行う時間軸復元処理を 行わない。  The receiver 200e includes a second receiver 260e, a first receiver 250e, and an input terminal 221. Similar to the second receiver 260, the second receiver 260e performs substantially the same rate control processing as the rate control processing performed by the receiver 200b, but does not perform time-base recovery processing performed by the receiver 200b.
[0149] 第 2受信部 260eは、第 5の実施の形態の第 2受信部 260において、その分離部 20 2dを分離部 202eに置き換えた構成になって 、る。  The second receiving unit 260 e has a configuration in which the separating unit 202 d is replaced with a separating unit 202 e in the second receiving unit 260 according to the fifth embodiment.
分離部 202eは、受信処理部 201から入力されるパケットを、第 2送信バッファ量、 複数のタイムスタンプ、及び複数のパケットに分離する。そして、分離部 202dは、第 2 送信バッファ量、複数のタイムスタンプ、及び複数のパケットを、蓄積量加算部 207b 、タイムスタンプバッファ 204、及び第 2受信バッファ 203bへ出力する。  The separation unit 202e separates the packet input from the reception processing unit 201 into a second transmission buffer amount, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202d outputs the second transmission buffer amount, the plurality of time stamps, and the plurality of packets to the accumulation amount addition unit 207b, the time stamp buffer 204, and the second reception buffer 203b.
[0150] 第 2受信部 260eが行うレート制御処理は、第 5の実施の形態の第 2受信部 260が 行うレート制御処理と実質的に同じであるため、説明を省略する。 The rate control process performed by the second receiving unit 260e is substantially the same as the rate control process performed by the second receiving unit 260 according to the fifth embodiment, and thus the description thereof is omitted.
ただし、第 6の実施の形態では、読出レート制御部 251は、補正部 208bにより発振 周波数が制御された可変周波数発振器 251aが発振するクロック信号を、クロック出 力端子 25 leを介して、受信タイムスタンプタイマ 209eへ出力する。 However, in the sixth embodiment, the read rate control unit 251 causes the correction unit 208 b to oscillate. The clock signal generated by the variable frequency oscillator 251a whose frequency is controlled is output to the reception time stamp timer 209e via the clock output terminal 25le.
[0151] 第 1受信部 250eは、受信装置 200が行う時間軸復元処理と実質的に同じ時間軸 復元処理を行う。ただし、第 1受信部 250eは、受信装置 200が行うレート制御処理を 行わない。 The first receiving unit 250e performs a time axis reconstruction process substantially the same as the time axis reconstruction process performed by the receiving device 200. However, the first reception unit 250 e does not perform the rate control process performed by the reception device 200.
第 1受信部 250eでレート制御処理を行わないのは、以下の理由による。 第 2受信部 260eはレート制御処理を行っている。このため、第 2受信部 260の読出 レート制御部 251が出力するクロック信号の周波数は送信タイムスタンプタイマ 102 の発振器 102aが発振するクロック信号の周波数になるように調整されて 、る。このた め、読出レート制御部 251が出力するクロック信号を利用すれば、第 1受信部 250e で、送信タイムスタンプタイマ 102の発振器 102aが発振するクロック信号の周波数に なるように調整されたクロック信号を生成する必要がなくなるからである。  The reason for not performing the rate control process in the first receiver 250 e is as follows. The second receiver 260 e is performing rate control processing. Therefore, the frequency of the clock signal output from the read rate controller 251 of the second receiver 260 is adjusted to be the frequency of the clock signal oscillated by the oscillator 102a of the transmission time stamp timer 102. Therefore, if the clock signal output from the read rate control unit 251 is used, the clock signal adjusted to have the frequency of the clock signal oscillated by the oscillator 102a of the transmission time stamp timer 102 in the first receiving unit 250e. There is no need to generate.
[0152] 第 1受信部 250eは、受信タイムスタンプタイマ 209eと比較部 210とパケット読出部 211と第 1受信バッファ 203とを備える。 The first reception unit 250 e includes a reception time stamp timer 209 e, a comparison unit 210, a packet read unit 211, and a first reception buffer 203.
受信タイムスタンプタイマ 209eは、読出レート制御部 251から入力されるクロック信 号をカウントするカウンタを有し、カウンタによるカウント値を比較部 210へ出力する。 ただし、受信タイムスタンプタイマ 209eが有するカウンタは受信タイムスタンプタイマ 209のカウンタ 209bと同じ手順によりプリセットされる。なお、受信タイムスタンプタイ マ 209eは受信タイムスタンプタイマ 209のように可変周波数発振器を有して 、な 、。  The reception time stamp timer 209 e has a counter that counts the clock signal input from the read rate control unit 251, and outputs the count value of the counter to the comparison unit 210. However, the counter possessed by the reception time stamp timer 209e is preset by the same procedure as the counter 209b of the reception time stamp timer 209. The reception time stamp timer 209e has a variable frequency oscillator like the reception time stamp timer 209, and so on.
[0153] 第 1受信部 250eにより行われる時間軸復元は以下の通りである。 The time axis reconstruction performed by the first reception unit 250e is as follows.
プリセットされた受信タイムスタンプタイマ 209eは、読出レート制御部 251から入力 されるクロック信号をカウントし、カウント値を比較部 210へ出力する。比較部 210はタ ィムスタンプバッファ 204から取り出したタイムスタンプが示すカウンタ値と受信タイム スタンプタイマ 209eから入力されるカウンタ値とを比較し、両者が一致して 、ればパ ケット読出信号をパケット読出部 211へ出力する。パケット読出部 211はパケット読出 信号を受けて、第 1受信バッファ 203から 1つのパケットを出力させる。  The preset reception time stamp timer 209 e counts the clock signal input from the read rate control unit 251, and outputs the count value to the comparison unit 210. The comparison unit 210 compares the counter value indicated by the time stamp extracted from the time stamp buffer 204 with the counter value input from the reception time stamp timer 209e, and if both match, the packet read signal is read out Output to section 211. The packet read unit 211 receives the packet read signal and causes the first reception buffer 203 to output one packet.
[0154] 上述し本実施の形態によれば、第 5の実施の形態に比べ、簡易な構成の送信装置 と受信装置とにより、送信装置に入力されるパケットの入力ビットレートが可変ビットレ ートであり、かつ、伝送路における伝送ビットレートが可変ビットレートであっても、送 信装置と受信装置との間での同期伝送を実現することができる。 As described above, according to the present embodiment, compared with the fifth embodiment, the transmission bit rate of the packet input to the transmission device can be changed by the transmission device and the reception device with a simple configuration. Even if the transmission bit rate in the transmission path is a variable bit rate, synchronous transmission can be realized between the transmitting device and the receiving device.
<補足 >  <Supplement>
(1)第 6の実施の形態において、送信タイムスタンプタイマ 102の発振器 102aの発 振周波数と、読出レート制御部 251の可変周波数発振器 251aの発振周波数が異な るような場合には次のようにしてもょ 、。 PLL回路などを用いて可変周波数発振器 25 laの発振周波数を遁倍又は分周し、遁倍又は分周した周波数のクロック信号を受信 タイムスタンプタイマ 209eへ供給する。  (1) In the sixth embodiment, when the oscillation frequency of the oscillator 102a of the transmission time stamp timer 102 and the oscillation frequency of the variable frequency oscillator 251a of the read rate control unit 251 are different, the following is performed. I see. The oscillation frequency of the variable frequency oscillator 25 la is multiplied or divided by using a PLL circuit or the like, and a clock signal of the multiplied or divided frequency is supplied to the reception time stamp timer 209 e.
[0155] 《第 7の実施の形態〉〉 Seventh Embodiment
本発明の第 7の実施の形態の送信装置と受信装置との間で同期伝送を実現する 同期伝送システムについて図面を参照しつつ説明する。  A synchronous transmission system for realizing synchronous transmission between the transmitting apparatus and the receiving apparatus according to the seventh embodiment of the present invention will be described with reference to the drawings.
第 7の実施の形態は、第 5の実施の形態の送信装置 lOOd及び受信装置 200dの 構成を簡単にし、入力ビットレート及び伝送ビットレートの双方が可変ビットレートの場 合であっても同期伝送を実現することができるようにしたものである。  The seventh embodiment simplifies the configuration of the transmitting device lOOd and the receiving device 200d of the fifth embodiment, and synchronous transmission even if both the input bit rate and the transmission bit rate are variable bit rates. To make it possible.
[0156] なお、第 1〜第 6の実施の形態と実質的に同じ機能を有する構成要素には同じ符 号を付し、その構成要素については第 1〜第 6の実施の形態における説明が適用で きるため説明を省略する。 The components having substantially the same functions as those in the first to sixth embodiments are given the same reference numerals, and the description of the components in the first to sixth embodiments is omitted. Description is omitted as it is applicable.
<同期伝送システム >  <Synchronous transmission system>
本実施の形態の同期伝送システムの構成について図 16を参照しつつ説明する。 図 16は本実施の形態の同期伝送システムの構成図である。  The configuration of the synchronous transmission system of the present embodiment will be described with reference to FIG. FIG. 16 is a block diagram of a synchronous transmission system of the present embodiment.
[0157] 送信装置 100fと受信装置 200fとは伝送路 300bを介してパケットの送受信を行う。 The transmitting device 100f and the receiving device 200f transmit and receive packets via the transmission path 300b.
<送信装置 >  <Transmitter>
送信装置 100fは、入力端子 101と第 5の実施の形態の第 1送信部 150eと同じ構 成をした第 1送信部 150fと第 2送信部 160fと備える。  The transmitting apparatus 100 f includes a first transmitting unit 150 f and a second transmitting unit 160 f which have the same configuration as the input terminal 101 and the first transmitting unit 150 e of the fifth embodiment.
[0158] 第 2送信部 160fは、第 2送信バッファ 105bと送信処理部 107とを備える。 Second transmission unit 160 f includes second transmission buffer 105 b and transmission processing unit 107.
送信装置 100fでは、入力端子 101にパケットが入力されると、タイプスタンプ付カロ 部 103はパケットの先頭に送信タイムスタンプタイマ 102から供給されるカウント値を タイムスタンプとして付カ卩し、第 1送信バッファ量付加部 104はタイムスタンプが付加さ れたパケットの先頭に第 1送信バッファ量読出部 106から入力される第 1送信バッファ 量を付加する。タイムスタンプ及び第 1送信バッファ量が付加されたパケットが第 1送 信バッファ 105に蓄積される。 In the transmitting apparatus 100f, when a packet is input to the input terminal 101, the time stamped carover section 103 adds the count value supplied from the transmission time stamp timer 102 to the beginning of the packet as a time stamp, and performs the first transmission. The buffer amount adding unit 104 adds a time stamp The first transmission buffer amount input from the first transmission buffer amount reading unit 106 is added to the beginning of the received packet. The packet to which the time stamp and the first transmission buffer amount are added is accumulated in the first transmission buffer 105.
[0159] 第 1送信バッファ 105に蓄積されたパケットは、第 1送信バッファ 105から固定ビット レートで出力され、第 2送信バッファ 105bに蓄積される。なお、パケットの第 1送信バ ッファ 105からの固定ビットレートでの出力制御は、例えば、 MPEG2 TSの場合、ストリ ームのヘッダからストリームレートを抽出し、抽出したストリームレートに、入力されるパ ケットに付加したタイムスタンプや第 1送信バッファ量のオーバヘッド分のデータに相 当するレートをカ卩えたレートでパケットの出力を行うことにより実現することができる。  The packets accumulated in the first transmission buffer 105 are output from the first transmission buffer 105 at a fixed bit rate, and accumulated in the second transmission buffer 105 b. Note that, for output control at a fixed bit rate from the first transmission buffer 105 of the packet, for example, in the case of MPEG2 TS, the stream rate is extracted from the stream header, and the extracted stream rate This can be realized by outputting a packet at a rate corresponding to the time stamp added to the packet and data corresponding to overhead of the first transmission buffer amount.
[0160] 第 2送信バッファ 105bは複数のパケットを結合した結合パケットを出力し、第 2送信 ノ ッファ 105bから出力された結合パケットは送信処理部 107により所定の処理が施 され、伝送路 300bへ送出される。  The second transmission buffer 105 b outputs a combined packet obtained by combining a plurality of packets, and the combined packet output from the second transmission buffer 105 b is subjected to predetermined processing by the transmission processing unit 107, and the transmission path 300 b is transmitted to the transmission path 300 b. It is sent out.
<受信装置 >  <Receiver>
受信装置 200fは、第 2受信部 260fと第 1受信部 250fと入力端子 221とを備える。  The receiver 200f includes a second receiver 260f, a first receiver 250f, and an input terminal 221.
[0161] 第 2受信部 260fは、受信処理部 201と分離部 202fと CBR読出部 271と第 2受信 バッファ 203bとを備える。 The second reception unit 260f includes a reception processing unit 201, a separation unit 202f, a CBR reading unit 271, and a second reception buffer 203b.
分離部 202fは、受信処理部 201から入力される結合パケットを、複数の第 1送信バ ッファ量、複数のタイムスタンプ、及び複数のパケットに分離する。そして、分離部 20 2fは、複数の第 1送信バッファ量、複数のタイムスタンプ、及び複数のパケットを、第 1 送信バッファ量バッファ 205、タイムスタンプバッファ 204、及び第 2受信バッファ 203 bへ出力する。  The separation unit 202 f separates the combined packet input from the reception processing unit 201 into a plurality of first transmission buffer amounts, a plurality of time stamps, and a plurality of packets. Then, the separation unit 202f outputs the plurality of first transmission buffer amounts, the plurality of time stamps, and the plurality of packets to the first transmission buffer amount buffer 205, the time stamp buffer 204, and the second reception buffer 203b. .
[0162] CBR読出部 271は、受信タイムスタンプタイマ 209から供給されるクロック信号を力 ゥントするカウンタで構成されており、一定数のクロック信号をカウントすることにより読 出信号を生成する。第 2受信バッファ 203bはこの読出信号を受けて 1つのパケットを 第 1受信バッファ 203へ出力する。  The CBR reading unit 271 is configured by a counter that impresses the clock signal supplied from the reception time stamp timer 209, and generates a reading signal by counting a fixed number of clock signals. The second reception buffer 203 b receives this read signal and outputs one packet to the first reception buffer 203.
ただし、受信タイムスタンプタイマ 209から CBR読出部 209に入力されるクロック信 号の周波数は送信タイムスタンプタイマ 102の発振器 102aの発振周波数に調整さ れたものである。このため、本実施の形態では第 2送信バッファ 105bのパケットの蓄 積量と第 2受信バッファ 203bのパケットの蓄積量とを利用したレート制御処理を行う 必要がない。 However, the frequency of the clock signal input from the reception time stamp timer 209 to the CBR reading unit 209 is adjusted to the oscillation frequency of the oscillator 102 a of the transmission time stamp timer 102. Therefore, in the present embodiment, accumulation of packets in the second transmission buffer 105b is performed. There is no need to perform rate control processing using the product amount and the packet accumulation amount of the second reception buffer 203b.
[0163] なお、第 2受信部 260fは、第 1受信バッファ 203から出力されるパケットが時間軸で 復元されて ヽれば十分であるので、時間軸復元処理を行って ヽな 、。  [0163] Note that it is sufficient for the second receiving unit 260f to restore the packet output from the first reception buffer 203 on the time axis, and therefore, performs time axis restoration processing.
第 1受信部 250fは、第 5の実施の形態の第 1受信部 250と同じ構成をしており、時 間軸復元処理及びレート制御処理を行う。受信タイムスタンプタイマ 209は、それが 備える可変周波数発振器 209が発振するクロック信号をクロック出力端子 209fから C BR読出部 271へ出力する。  The first receiving unit 250f has the same configuration as the first receiving unit 250 of the fifth embodiment, and performs time axis restoration processing and rate control processing. The reception time stamp timer 209 outputs a clock signal oscillated by the variable frequency oscillator 209 included therein to the CBR read unit 271 from the clock output terminal 209 f.
[0164] 第 1受信部 250fが行う時間軸復元処理及びレート制御処理は、夫々、第 5の実施 の形態の第 1受信部 250が行う時間軸復元処理及びレート制御処理と同じであり、 説明を省略する。  The time axis restoration processing and rate control processing performed by the first reception unit 250 f are the same as the time axis restoration processing and rate control processing performed by the first reception unit 250 according to the fifth embodiment, respectively. Omit.
上述し本実施の形態によれば、第 5の実施の形態に比べ、簡易な構成の送信装置 と受信装置とにより、送信装置に入力されるパケットの入力ビットレートが可変ビットレ ートであり、かつ、伝送路における伝送ビットレートが可変ビットレートであっても、送 信装置と受信装置との間での同期伝送を実現することができる。  According to the present embodiment as described above, the input bit rate of the packet input to the transmitting device is variable bit rate by the transmitting device and the receiving device having a simple configuration, as compared with the fifth embodiment. And, even if the transmission bit rate in the transmission path is a variable bit rate, synchronous transmission can be realized between the transmitting device and the receiving device.
《補足〉〉  Supplement
(1)上記の各実施の形態において、入力されるパケットが、 MPEG2 TSに関するパケ ットであってもよい。  (1) In each of the above embodiments, the input packet may be a packet related to the MPEG2 TS.
(2)上記の各実施の形態において、送信バッファ (第 1送信バッファ 105又は第 2送 信バッファ)のパケットの蓄積量を、送信装置から受信装置へ送信し、これを利用して 受信装置が備える各カウンタのカウンタ速度を調整しているが、これに限らず、送信 装置から受信装置へ送信する情報として、送信バッファのパケットの蓄積量を特定す ることができる情報であればよ!、。  (2) In each of the above embodiments, the transmitting device transmits the accumulated amount of packets in the transmission buffer (the first transmission buffer 105 or the second transmission buffer) from the transmitting device to the receiving device, and the receiving device utilizes this. Although the counter speed of each provided counter is adjusted, the present invention is not limited to this, as long as the information transmitted from the transmitting device to the receiving device can be used as long as it can identify the accumulation amount of packets in the transmission buffer. .
[0165] 例えば、送信バッファのパケットの蓄積量は、送信バッファへのパケットの入力レー トの時間積分値力も送信バッファからのパケットの出力レートの時間積分値を減算す ること〖こより得られる値と等価である。  For example, the accumulation amount of packets in the transmission buffer can be obtained by subtracting the time integral value of the output rate of packets from the transmission buffer from the time integral value of the packet input rate to the transmission buffer. Is equivalent to
同様に、受信バッファ（第 1受信バッファ 203又は第 2受信バッファ 203b)のパケット の蓄積量は、受信バッファへのパケットの入力レートの時間積分値力 受信バッファ 力 のパケットの出力レートの時間積分値を減算することにより得られる値と等価であ る。 Similarly, the accumulation amount of packets in the reception buffer (the first reception buffer 203 or the second reception buffer 203b) is determined by the time integral value of the input rate of the packet to the reception buffer. It is equivalent to the value obtained by subtracting the time integral value of the output rate of the force packet.
[0166] このため、入出力レートを用いて送信バッファのパケットの蓄積量に等価な値と受信 ノ ッファのパケットの蓄積量と等価の値を算出し、それらの等価な値の和が一定にな るようにカウンタのカウント速度を調整する。  Therefore, using the input / output rate, a value equivalent to the amount of packet accumulation in the transmission buffer and a value equivalent to the amount of packet accumulation in the reception buffer are calculated, and the sum of these equivalent values is made constant. Adjust the counter's counting speed as you like.
そこで、送信バッファのパケットの蓄積量を送信装置から受信装置へ送信する代わ りに、送信バッファの入力レートと出力レートとを測定し、測定した送信バッファの入 力レートと出力レートとを送信装置力も受信装置へ送信するようにしてもよい。この場 合、受信装置では、受信バッファの入力レートと出力レートとを測定する。  Therefore, instead of transmitting the accumulated amount of packets in the transmission buffer from the transmission device to the reception device, the input rate and output rate of the transmission buffer are measured, and the input rate and output rate of the transmission buffer are measured. The force may also be sent to the receiver. In this case, the receiver measures the input rate and the output rate of the reception buffer.
[0167] なお、送信バッファの出力レートの時間積分値と受信バッファの入力レートとの時間 積分値とは等しいので、これらの時間積分値は送信バッファのパケットの蓄積量と等 価な値と受信バッファのパケットの蓄積量と等価な値とを加算する際に互いに打ち消 される。このため、送信装置から受信装置への送信は送信バッファへの入力レートの みでよぐ受信装置では受信バッファの出力レートのみを測定すればよい。  Since the time integral value of the output rate of the transmission buffer and the time integral value of the input rate of the reception buffer are equal, these time integral values are equal to the storage amount of the packet in the transmission buffer and received. They are mutually canceled when adding a value equivalent to the accumulated amount of packets in the buffer. Therefore, in the case of transmission from the transmitter to the receiver only at the input rate to the transmission buffer, the receiver only needs to measure the output rate of the reception buffer.
(3)上記の各実施の形態において、送信装置又は受信装置の構成要素の全て又は 一部と等価な処理を行う受信方法であってもよ 、。  (3) In each of the above embodiments, it may be a reception method that performs processing equivalent to all or part of the components of the transmission apparatus or the reception apparatus.
[0168] また、上記の各実施の形態において説明した送信装置又は受信装置が行う全部 又は一部と等価な処理手順を記述したプログラムをメモリに格納し、 CPU等を用いて 処理を行わせるようにしてもょ ヽ。  In addition, a program in which a processing procedure equivalent to all or a part performed by the transmission device or the reception device described in each of the above embodiments is described is stored in a memory, and processing is performed using a CPU or the like. Anyway.
産業上の利用可能性  Industrial applicability
[0169] 本発明は、送信装置と受信装置との間の同期伝送に利用することができ、例えば、 ホームネットワークを用いた高品質映像伝送などへの応用に有用であり、インターネ ットなどのグローバルなネットワークでのストリーム伝送に利用できる。 The present invention can be used for synchronous transmission between a transmitter and a receiver, and is useful, for example, for application to high-quality video transmission using a home network, such as an Internet. It can be used for stream transmission in global networks.

Claims

請求の範囲  The scope of the claims
[1] 一定周期のクロック信号をカウントする送信カウンタ部と、  [1] A transmission counter unit that counts clock signals of a fixed cycle,
入力されるパケットを一時的に蓄積し、蓄積したパケットを出力する第 1送信バッフ ァ部と、  A first transmission buffer unit that temporarily accumulates input packets and outputs the accumulated packets;
前記第 1送信バッファ部に蓄積されているパケットと自装置に当該パケットが入力さ れるときの前記送信カウンタ部のカウント値を示す送信カウンタ情報とを送信するとと もに、前記第 1送信バッファ部に対する当該パケットの第 1処理に係る第 1タイミング での当該第 1送信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情 報を伝送路へ送信する送信部と、  The packet stored in the first transmission buffer unit and transmission counter information indicating the count value of the transmission counter unit when the packet is input to the own device are transmitted, and the first transmission buffer unit A transmitter for transmitting, to the transmission path, first transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet for
を備える送信装置。  A transmitter comprising:
[2] 前記第 1送信蓄積情報は、前記第 1送信バッファ部のパケットの蓄積量である 請求項 1記載の送信装置。  [2] The transmission device according to claim 1, wherein the first transmission accumulation information is an accumulation amount of packets of the first transmission buffer unit.
[3] 前記パケットに前記送信カウンタ情報を付加するカウンタ情報付加部をさらに備え 前記送信部は、前記パケット及び前記送信カウンタ情報の送信を、前記カウンタ情 報付加部により送信カウンタ情報が付加されたパケットの送信により行う [3] The information processing apparatus further includes a counter information addition unit that adds the transmission counter information to the packet. The transmission unit transmits the packet and the transmission counter information by adding the transmission counter information by the counter information addition unit. Done by sending a packet
請求項 1記載の送信装置。  The transmitter according to claim 1.
[4] 前記パケットに前記第 1送信蓄積情報を付加する蓄積情報付加部をさらに備え、 前記送信部は、前記パケット及び前記第 1送信蓄積情報の送信を、前記蓄積情報 付加部により第 1送信蓄積情報が付加されたパケットの送信により行う [4] The storage information addition unit for adding the first transmission storage information to the packet is further provided, and the transmission unit performs first transmission of the packet and the first transmission storage information by the storage information addition unit. Send by sending packet with stored information added
請求項 1記載の送信装置。  The transmitter according to claim 1.
[5] パケットの入力順に前記送信部により送信されるパケットにシーケンシャルな番号を 付加する番号付加部 [5] A number adding unit for adding sequential numbers to packets transmitted by the transmitting unit in the order of packet input
をさらに備える請求項 1記載の送信装置。  The transmitter according to claim 1, further comprising:
[6] 前記第 1送信バッファ部は固定ビットレートで蓄積したパケットを出力し、 [6] The first transmission buffer unit outputs the accumulated packet at a fixed bit rate,
前記第 1送信バッファ部力 出力されるパケットを一時的に蓄積する第 2送信バッフ ァ部を備え、  The first transmission buffer unit comprises a second transmission buffer unit for temporarily storing output packets,
前記第 1処理に係る第 1タイミングは入力処理に係るタイミングであり、 前記送信部は、さらに、前記第 2送信バッファ部に対するパケットの第 2処理である 出力処理に係る第 2タイミングでの当該第 2送信バッファ部のパケットの蓄積量を特 定するための第 2送信蓄積情報を送信する The first timing related to the first processing is the timing related to input processing, The transmission unit is further configured to perform second transmission for identifying the accumulated amount of packets in the second transmission buffer unit at a second timing related to output processing, which is second processing of packets to the second transmission buffer unit. Send stored information
請求項 1記載の送信装置。  The transmitter according to claim 1.
[7] 前記第 1送信バッファ部は固定ビットレートで蓄積したパケットを出力し、 [7] The first transmission buffer unit outputs the accumulated packet at a fixed bit rate,
前記第 1送信バッファ部力 出力されるパケットを一時的に蓄積する第 2送信バッフ ァ部を備え、  The first transmission buffer unit comprises a second transmission buffer unit for temporarily storing output packets,
前記第 1処理に係る第 1タイミングは入力処理に係るタイミングである  The first timing related to the first processing is the timing related to the input processing
請求項 1記載の送信装置。  The transmitter according to claim 1.
[8] 入力されるパケットを一時的に蓄積し、固定ビットレートで前記第 1送信バッファ部 へ送信する第 2送信バッファ部をさらに備え、 [8] A second transmission buffer unit is further provided which temporarily accumulates the input packet and transmits the packet to the first transmission buffer unit at a fixed bit rate,
前記第 1処理に係る第 1タイミングは出力処理に係るタイミングである  The first timing related to the first processing is the timing related to the output processing
請求項 1記載の送信装置。  The transmitter according to claim 1.
[9] 一定周期のクロック信号をカウントする送信カウンタ部及び第 1送信バッファ部を有 する送信装置から、パケット、当該パケットが当該送信装置に入力されるときの前記 送信カウンタ部のカウント値を示す送信カウンタ情報、前記第 1送信バッファ部に対 する当該パケットの第 1処理に係る第 1タイミングでの当該第 1送信バッファ部のパケ ットの蓄積量を特定するための第 1送信蓄積情報を伝送路を介して受信する受信部 と、 [9] Indicates a count value of the transmission counter unit when the packet and the packet are input to the transmission device from the transmission device having the transmission counter unit and the first transmission buffer unit that count clock signals of a fixed cycle and the first transmission buffer unit. Transmission counter information, first transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at the first timing related to the first processing of the packet to the first transmission buffer unit A receiving unit that receives via a transmission line;
クロック信号をカウントするものであって、カウント速度が可変である受信カウンタ部 と、  A reception counter unit that counts clock signals and has a variable count speed;
受信されるパケットを一時的に蓄積する第 1受信バッファ部と、  A first reception buffer unit that temporarily accumulates received packets;
前記第 1送信バッファ部に対するパケットの第 1処理に係る第 1タイミングでの当該 第 1送信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情報と、前記 第 1受信バッファ部に対する当該パケットの第 2処理に係る第 2タイミングでの当該第 1受信バッファ部のパケットの蓄積量を特定するための第 1受信蓄積情報と、に基づ いて前記受信カウンタ部のカウント速度を補正する補正部と、  First transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit; Correction for correcting the count speed of the reception counter based on the first reception accumulation information for specifying the accumulation amount of packets of the first reception buffer at the second timing related to the second processing of the packet Department,
前記受信部により受信される前記送信カウンタ情報と、前記受信カウント部のカウン ト値を示す受信カウント情報とに基づいて、前記第 1受信バッファ部力 のパケットの 出力制御を行う第 1出力制御部と、 The transmission counter information received by the reception unit, and the count of the reception count unit A first output control unit that performs output control of the packet of the first reception buffer unit based on reception count information indicating the transmission value;
を備える受信装置。  Receiver comprising:
[10] 前記第 1送信蓄積情報は前記第 1送信バッファ部のパケットの蓄積量であり、  [10] The first transmission accumulation information is the accumulation amount of packets of the first transmission buffer unit,
前記第 1受信蓄積情報は前記第 1受信バッファ部のパケットの蓄積量である 請求項 9記載の受信装置。  The receiving apparatus according to claim 9, wherein the first reception accumulation information is an accumulation amount of packets of the first reception buffer unit.
[11] 前記補正部は、前記第 1送信バッファ部のパケットの蓄積量と前記第 1受信バッファ 部のパケットの蓄積量とが一定になるように、前記受信カウンタ部のカウント速度の補 正を行う  [11] The correction unit corrects the count speed of the reception counter unit so that the packet accumulation amount of the first transmission buffer unit and the packet accumulation amount of the first reception buffer unit become constant. Do
請求項 9記載の受信装置。  The receiver according to claim 9.
[12] 前記第 1処理に係る第 1タイミングが入力処理に係るタイミングである場合、前記第 2処理に係る第 2タイミングは出力処理に係るタイミングである [12] If the first timing related to the first processing is the timing related to the input processing, the second timing related to the second processing is the timing related to the output processing
請求項 9記載の受信装置。  The receiver according to claim 9.
[13] 前記送信装置に入力されるパケットの入力ビットレートは可変ビットレートであり、前 記伝送路の伝送ビットレートは固定ビットレートである [13] The input bit rate of the packet input to the transmitter is a variable bit rate, and the transmission bit rate of the transmission path is a fixed bit rate
請求項 12記載の受信装置。  A receiver according to claim 12.
[14] 前記第 1処理に係る第 1タイミングが出力処理に係るタイミングである場合、前記第 2処理に係る第 2タイミングは入力処理に係るタイミングである [14] If the first timing related to the first processing is the timing related to the output processing, the second timing related to the second processing is the timing related to the input processing
請求項 9記載の受信装置。  The receiver according to claim 9.
[15] 前記送信装置に入力されるパケットの入力ビットレートは固定ビットレートであり、前 記伝送路の伝送ビットレートは可変ビットレートである [15] The input bit rate of the packet input to the transmitter is a fixed bit rate, and the transmission bit rate of the transmission path is a variable bit rate
請求項 14記載の受信装置。  The receiver according to claim 14.
[16] 前記受信部は、前記送信装置において当該送信装置へのパケットの入力順にパ ケットに付与されるシーケンシャルな番号を前記送信装置力 受信し、 [16] The receiving unit receives, in the transmitting device, the sequential number given to the packet in the input order of packets to the transmitting device in the transmitting device;
前記受信装置は、  The receiving device is
前記受信部により受信されるシーケンシャルな番号に基づき、前記受信部が受信 できな力つたパケットの数を検出する検出部  A detection unit that detects the number of packets that the reception unit can not receive based on the sequential number received by the reception unit
をさらに備え、 前記補正部は、前記第 1送信バッファ部のパケットの蓄積量と前記第 1受信バッファ 部のパケットの蓄積量と前記検出部により検出される受信できな力つたパケットの数 に基づくパケットの欠損量との和が一定になるように、前記受信カウンタ部のカウント 速度の補正を行う And further The correction unit is a packet loss amount based on the packet accumulation amount of the first transmission buffer unit, the packet accumulation amount of the first reception buffer unit, and the number of unacceptable packets detected by the detection unit. Correction of the count speed of the reception counter unit so that the sum of
請求項 9記載の受信装置。  The receiver according to claim 9.
[17] 前記第 1処理に係る第 1タイミングは入力処理に係るタイミングであり、 [17] The first timing related to the first processing is the timing related to input processing,
前記受信部は、さらに、前記第 1送信バッファ部が固定ビットレートで出力するパケ ットを一時的に蓄積し蓄積したパケットを出力する第 2送信バッファ部を有する前記 送信装置から、前記第 2送信バッファ部に対するパケットの出力処理に係るタイミング での当該第 2送信バッファ部の蓄積量を特定するための第 2送信蓄積情報を受信し 前記受信装置は、  The receiving unit further includes a second transmitting buffer unit for temporarily storing a packet output by the first transmitting buffer unit at a fixed bit rate and outputting the accumulated packet, from the transmitting device including the second transmitting buffer unit. Receiving the second transmission accumulation information for specifying the accumulation amount of the second transmission buffer unit at a timing related to the output processing of the packet to the transmission buffer unit;
受信されるパケットを一時的に蓄積して蓄積したパケットを前記第 1受信バッファ部 へ出力する第 2受信バッファ部と、  A second reception buffer unit that temporarily accumulates received packets and outputs the accumulated packets to the first reception buffer unit;
前記第 2送信バッファ部に対するパケットの出力処理に係るタイミングでの当該第 2 送信バッファ部のパケットの蓄積量を特定するための第 2送信蓄積情報と、前記第 2 受信バッファ部に対する当該パケットの入力処理に係るタイミングでの当該第 2受信 バッファ部の蓄積量を特定するための第 2受信蓄積情報と、に基づいて前記第 2受 信バッファ部力ものパケットの出力制御を行なう第 2出力制御部と、  Second transmission accumulation information for specifying the accumulated amount of packets of the second transmission buffer unit at the timing related to the output processing of the packet to the second transmission buffer unit, and input of the packet to the second reception buffer unit A second output control unit that performs output control of packets of the second reception buffer unit based on second reception accumulation information for specifying an accumulation amount of the second reception buffer unit at a timing related to processing; When,
をさらに備える請求項 9記載の受信装置。  The receiver according to claim 9, further comprising:
[18] 前記第 1処理に係る第 1タイミングは入力処理に係るタイミングであり、 [18] The first timing related to the first processing is the timing related to input processing,
前記送信装置は、前記第 1送信バッファ部が固定ビットレートで出力するパケットを 一時的に蓄積して蓄積したパケットを出力する第 2送信バッファ部を有し、  The transmitting apparatus further includes a second transmission buffer unit that temporarily accumulates and outputs a packet output from the first transmission buffer unit at a fixed bit rate.
前記受信装置は、  The receiving device is
受信するパケットを一時的に蓄積して蓄積したパケットを前記第 1受信バッファ部へ 出力する第 2受信バッファ部と、  A second reception buffer unit for temporarily accumulating received packets and outputting the accumulated packets to the first reception buffer unit;
前記第 1送信バッファ部に対する当該パケットの第 1処理に係る第 1タイミングでの 当該第 1送信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情報と、 前記第 1受信バッファ部に対する当該パケットの第 2処理に係る第 2タイミングでの当 該第 1受信バッファ部のパケットの蓄積量を特定するための第 1受信蓄積情報と、に 基づいて前記第 2受信バッファ部力ものパケットの出力制御を行なう第 2出力制御部 と、 First transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit; First reception accumulation information for specifying the accumulation amount of packets of the first reception buffer unit at a second timing related to the second processing of the packet to the first reception buffer unit; A second output control unit for controlling output of packets in the reception buffer unit;
をさらに備える請求項 9記載の受信装置。  The receiver according to claim 9, further comprising:
一定周期のクロック信号をカウントする送信カウンタ部、パケットを一時的に蓄積し、 蓄積したパケットを固定ビットレートで出力する第 1送信バッファ部、及び当該第 1送 信バッファ部が出力するパケットを一時的に蓄積する第 2送信バッファ部を有する送 信装置から、パケット、当該パケットが当該送信装置に入力されるときの前記送信カウ ンタ部のカウント値を示す送信カウンタ情報、前記第 2送信バッファ部に対する当該 パケットの出力処理に係るタイミングでの当該第 2送信バッファ部のパケットの蓄積量 を特定するための送信蓄積情報を伝送路を介して受信する受信部と、  A transmission counter unit that counts clock signals of a fixed cycle, a first transmission buffer unit that temporarily accumulates packets, and outputs the accumulated packets at a fixed bit rate, and a packet that the first transmission buffer unit outputs temporarily Packet, transmission counter information indicating the count value of the transmission counter unit when the packet is input to the transmission device from the transmission device having the second transmission buffer unit that accumulates A reception unit that receives transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to output processing of the packet with respect to the reception unit via the transmission path;
クロック信号をカウントするものであって、カウント速度が可変である受信カウンタ部 と、  A reception counter unit that counts clock signals and has a variable count speed;
入力されるパケットを一時的に蓄積する第 1受信バッファ部と、  A first reception buffer unit that temporarily accumulates input packets;
受信されるパケットを一時的に蓄積して蓄積したパケットを前記第 1受信バッファ部 へ出力する第 2受信バッファ部と、  A second reception buffer unit that temporarily accumulates received packets and outputs the accumulated packets to the first reception buffer unit;
前記第 2送信バッファ部に対するパケットの出力処理に係るタイミングでの当該第 2 送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と、前記第 2受信 バッファ部に対する当該パケットの入力処理に係るタイミングでの当該第 2受信バッフ ァ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ 、て前記受信力 ゥンタ部のカウント速度を補正する補正部と、  Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the output process of the packet to the second transmission buffer unit, and input processing of the packet to the second reception buffer unit A correction unit that corrects the count speed of the reception power unit based on reception accumulation information for specifying the accumulation amount of packets of the second reception buffer unit at such timing;
前記受信部により受信される前記送信カウンタ情報と、前記受信カウンタ部のカウ ント値を示す受信カウンタ情報とに基づいて、前記第 1受信バッファ部力 のパケット の出力制御を行う第 1出力制御部と、  A first output control unit that performs output control of the packet of the first reception buffer unit based on the transmission counter information received by the reception unit and the reception counter information indicating the count value of the reception counter unit; When,
前記第 2送信バッファ部に対するパケットの出力処理に係るタイミングでの当該第 2 送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と、前記第 2受信 バッファ部に対する当該パケットの入力処理に係るタイミングでの当該第 2受信バッフ ァ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ 、て前記第 2受 信バッファ部力 のパケットの出力制御を行う第 2出力制御部と、 Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the output process of the packet to the second transmission buffer unit, and input processing of the packet to the second reception buffer unit The second reception buffer at the relevant timing A second output control unit that performs output control of the packet of the second reception buffer unit based on reception accumulation information for specifying the accumulation amount of packets of the second unit;
を備える受信装置。  Receiver comprising:
[20] 第 1送信バッファ部に蓄積されているパケットと自装置に当該パケットが入力される ときの送信カウンタ部のカウント値を示す送信カウンタ情報とを送信するとともに、前 記第 1送信バッファ部に対する当該パケットの第 1処理に係る第 1タイミングでの当該 第 1送信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情報を伝送路 へ送信する送信方法。  [20] A packet stored in the first transmission buffer unit and transmission counter information indicating the count value of the transmission counter unit when the packet is input to the own device are transmitted, and the first transmission buffer unit described above A transmission method for transmitting, to a transmission line, first transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet for the first.
[21] クロック信号をカウントするものであって、カウント速度が可変である受信カウンタ部 と、受信されるパケットを一時的に蓄積する第 1受信バッファ部と、有する受信装置に お!、て行われる受信方法であって、  [21] A receiving apparatus having a receiving counter section that counts clock signals and has a variable counting speed, a first receiving buffer section that temporarily accumulates received packets, and a receiving apparatus. The receiving method to be
一定周期のクロック信号をカウントする送信カウンタ部及び第 1送信バッファ部を有 する送信装置から、パケット、当該パケットが当該送信装置に入力されるときの前記 送信カウンタ部のカウント値を示す送信カウンタ情報、前記第 1送信バッファ部に対 する当該パケットの第 1処理に係る第 1タイミングでの当該第 1送信バッファ部のパケ ットの蓄積量を特定するための第 1送信蓄積情報を伝送路を介して受信する受信ス テツプと、  Transmission counter information indicating a count value of the transmission counter unit when the packet and the packet are input to the transmission device from the transmission device having the transmission counter unit and the first transmission buffer unit that counts clock signals of a fixed cycle The first transmission accumulation information for specifying the accumulation amount of packets in the first transmission buffer unit at a first timing related to the first processing of the packet with respect to the first transmission buffer unit is used as a transmission path. Receive step through and
前記第 1送信バッファ部に対するパケットの第 1処理に係る第 1タイミングでの当該 第 1送信バッファ部のパケットの蓄積量を特定するための第 1送信蓄積情報と、前記 第 1受信バッファ部に対する当該パケットの第 2処理に係る第 2タイミングでの当該第 1受信バッファ部のパケットの蓄積量を特定するための第 1受信蓄積情報と、に基づ いて前記受信カウンタ部のカウント速度を補正する補正ステップと、  First transmission accumulation information for specifying the accumulation amount of packets of the first transmission buffer unit at a first timing related to the first processing of the packet to the first transmission buffer unit; Correction for correcting the count speed of the reception counter based on the first reception accumulation information for specifying the accumulation amount of packets of the first reception buffer at the second timing related to the second processing of the packet Step and
前記受信ステップにより受信される前記送信カウンタ情報と、前記受信カウント部の カウント値を示す受信カウント情報とに基づいて、前記第 1受信バッファ部からのパケ ットの出力制御を行う第 1出力制御ステップと、  First output control for controlling output of a packet from the first reception buffer unit based on the transmission counter information received by the reception step and reception count information indicating the count value of the reception count unit. Step and
有する受信方法。  Have a receiving method.
[22] クロック信号をカウントするものであって、カウント速度が可変である受信カウンタ部 と、入力されるパケットを一時的に蓄積する第 1受信バッファ部と、受信されるパケット を一時的に蓄積し蓄積したパケットを当該第 1受信バッファ部へ出力する第 2受信バ ッファ部を有する受信装置において行われる受信方法であって、 [22] A reception counter unit that counts clock signals and has a variable count speed, a first reception buffer unit that temporarily accumulates an input packet, and a received packet A receiving method having a second receiving buffer unit that temporarily stores the stored data and outputs the stored packet to the first receiving buffer unit,
一定周期のクロック信号をカウントする送信カウンタ部、パケットを一時的に蓄積し、 蓄積したパケットを固定ビットレートで出力する第 1送信バッファ部、及び当該第 1送 信バッファ部が出力するパケットを一時的に蓄積する第 2送信バッファ部を有する送 信装置から、パケット、当該パケットが当該送信装置に入力されるときの前記送信カウ ンタ部のカウント値を示す送信カウンタ情報、前記第 2送信バッファ部に対する当該 パケットの出力処理に係るタイミングでの当該第 2送信バッファ部のパケットの蓄積量 を特定するための送信蓄積情報を伝送路を介して受信する受信ステップと、 前記第 2送信バッファ部に対するパケットの出力処理に係るタイミングでの当該第 2 送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と、前記第 2受信 バッファ部に対する当該パケットの入力処理に係るタイミングでの当該第 2受信バッフ ァ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ 、て前記受信力 ゥンタ部のカウント速度を補正する補正ステップと、  A transmission counter unit that counts clock signals of a fixed cycle, a first transmission buffer unit that temporarily accumulates packets, and outputs the accumulated packets at a fixed bit rate, and a packet that the first transmission buffer unit outputs temporarily Packet, transmission counter information indicating the count value of the transmission counter unit when the packet is input to the transmission device from the transmission device having the second transmission buffer unit that accumulates Receiving the transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the output processing of the packet with respect to the packet via the transmission path, the packet for the second transmission buffer unit Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at the timing related to the output processing of And the reception accumulation information for specifying the accumulation amount of packets of the second reception buffer unit at the timing related to the input processing of the packet to the second reception buffer unit. A correction step of correcting the count speed of the
前記受信ステップにより受信される前記送信カウンタ情報と、前記受信カウント部の カウント値を示す受信カウンタ情報とに基づいて、前記第 1受信バッファ部力 のパケ ットの出力制御を行う第 1出力制御ステップと、  A first output control for controlling the output of the first reception buffer section packet based on the transmission counter information received by the reception step and the reception counter information indicating the count value of the reception count unit Step and
前記第 2送信バッファ部に対するパケットの出力処理に係るタイミングでの当該第 2 送信バッファ部のパケットの蓄積量を特定するための送信蓄積情報と、前記第 2受信 バッファ部に対する当該パケットの入力処理に係るタイミングでの当該第 2受信バッフ ァ部のパケットの蓄積量を特定するための受信蓄積情報と、に基づ 、て前記第 2受 信バッファ部力 のパケットの出力制御を行う第 2出力制御ステップと、  Transmission accumulation information for specifying the accumulation amount of packets of the second transmission buffer unit at a timing related to the output process of the packet to the second transmission buffer unit, and input processing of the packet to the second reception buffer unit A second output control that performs output control of a packet of the second reception buffer unit based on reception accumulation information for specifying the accumulation amount of packets of the second reception buffer unit at the timing Step and
有する受信方法。  Have a receiving method.
PCT/JP2006/325383 2005-12-28 2006-12-20 Transmission device and reception device WO2007077739A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2006800495883A CN101351780B (en) 2005-12-28 2006-12-20 Transmission device and reception device
US12/158,026 US8477789B2 (en) 2005-12-28 2006-12-20 Transmission device and reception device
JP2007552904A JP4970284B2 (en) 2005-12-28 2006-12-20 Transmitting apparatus and receiving apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005377927 2005-12-28
JP2005-377927 2005-12-28

Publications (1)

Publication Number Publication Date
WO2007077739A1 true WO2007077739A1 (en) 2007-07-12

Family

ID=38228095

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/325383 WO2007077739A1 (en) 2005-12-28 2006-12-20 Transmission device and reception device

Country Status (4)

Country Link
US (1) US8477789B2 (en)
JP (1) JP4970284B2 (en)
CN (1) CN101351780B (en)
WO (1) WO2007077739A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100040065A1 (en) * 2008-08-15 2010-02-18 Xuejun Lu Two Division Method for Quality of Service (QoS)
JP5419493B2 (en) * 2009-03-03 2014-02-19 キヤノン株式会社 Data processing apparatus, data processing apparatus control method, and program
US8379659B2 (en) * 2010-03-29 2013-02-19 Intel Corporation Performance and traffic aware heterogeneous interconnection network
US10356143B2 (en) * 2012-10-10 2019-07-16 Samsung Electronics Co., Ltd. Method and apparatus for media data delivery control
JP5948361B2 (en) * 2014-03-28 2016-07-06 株式会社Pfu Information processing apparatus and output adjustment method
CN107562397B (en) * 2017-09-04 2020-11-10 歌尔科技有限公司 Dynamic frequency modulation method and device
KR102479513B1 (en) * 2018-02-26 2022-12-21 삼성전자주식회사 Display apparatus and the control method thereof
CN111327386B (en) * 2018-12-14 2023-08-08 深圳市中兴微电子技术有限公司 Delay jitter compensation method and device and computer storage medium
CN112188257A (en) * 2020-08-26 2021-01-05 深圳市拔超科技有限公司 Clock control method and system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03117219A (en) * 1989-09-29 1991-05-20 Toshiba Corp Variable length coding transmission system and transmitter and receiver for variable length coding transmission
JP2004180127A (en) * 2002-11-28 2004-06-24 Sony Corp Communication equipment, and transmitter and receiver

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05183579A (en) 1991-11-08 1993-07-23 Mitsubishi Electric Corp Communication path selection device, communication path selection method and data exchange
US5541852A (en) * 1994-04-14 1996-07-30 Motorola, Inc. Device, method and system for variable bit-rate packet video communications
US5901149A (en) * 1994-11-09 1999-05-04 Sony Corporation Decode and encode system
JPH08139704A (en) 1994-11-09 1996-05-31 Sony Corp Data processing device and method
US5543853A (en) * 1995-01-19 1996-08-06 At&T Corp. Encoder/decoder buffer control for variable bit-rate channel
US6188700B1 (en) * 1996-11-07 2001-02-13 Sony Corporation Method and apparatus for encoding MPEG signals using variable rate encoding and dynamically varying transmission buffers
EP0905935A1 (en) * 1997-01-21 1999-03-31 Sony Corporation Coded signal transmission method and device
JPH11328065A (en) * 1998-05-20 1999-11-30 Nippon Hoso Kyokai <Nhk> Method and device for data input and output
DE19914838A1 (en) * 1999-04-01 2000-10-05 Thomson Brandt Gmbh Isochronous transmission method for MPEG2 coded video or audio data by dividing data into source packets of defined value/size
JP4193297B2 (en) * 1999-08-04 2008-12-10 ソニー株式会社 COMMUNICATION DEVICE AND METHOD, COMMUNICATION SYSTEM, AND RECORDING MEDIUM
US7047308B2 (en) * 2001-08-31 2006-05-16 Sharp Laboratories Of America, Inc. System and method for simultaneous media playout
TWI334289B (en) * 2003-05-20 2010-12-01 Panasonic Corp Access control method and system
US7391769B2 (en) * 2003-06-27 2008-06-24 Lucent Technologies Inc. Packet aggregation for real time services on packet data networks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03117219A (en) * 1989-09-29 1991-05-20 Toshiba Corp Variable length coding transmission system and transmitter and receiver for variable length coding transmission
JP2004180127A (en) * 2002-11-28 2004-06-24 Sony Corp Communication equipment, and transmitter and receiver

Also Published As

Publication number Publication date
JPWO2007077739A1 (en) 2009-06-11
US20090168791A1 (en) 2009-07-02
US8477789B2 (en) 2013-07-02
CN101351780B (en) 2012-04-11
JP4970284B2 (en) 2012-07-04
CN101351780A (en) 2009-01-21

Similar Documents

Publication Publication Date Title
WO2007077739A1 (en) Transmission device and reception device
JP3687188B2 (en) Packet transmission method
CN1669290B (en) Jitter compensation method for systems having wall clocks
JP4905060B2 (en) Reception device and data reproduction method
JP4193297B2 (en) COMMUNICATION DEVICE AND METHOD, COMMUNICATION SYSTEM, AND RECORDING MEDIUM
US7729391B2 (en) Transmitting device with discard control of specific media data
JPH0697927A (en) Apparatus for recovery of timing in receiver
EP1089482A1 (en) Communication device, communication method, and recorded medium
US7466967B2 (en) Communication system
AU740271B2 (en) AAL5 jitter reduction method and apparatus
JP3857533B2 (en) Signal receiving apparatus and signal receiving method
JP4612688B2 (en) Receiver
US20020075404A1 (en) Method and apparatus for receiving and playing back data
JP4923701B2 (en) Streaming data receiving apparatus and jitter removal circuit
US7567814B2 (en) Time synchronized radio transmission system
KR101196823B1 (en) Method and apparatus for constant-bit-rate traffic clock recovery
JP4274477B2 (en) Packet transmission control device, method and program thereof
US20130142192A1 (en) Voice communication apparatus for intermittently discarding packets
US9438379B2 (en) Communication device, communication program, communication method, and information processing device
JP2017028385A (en) Receiving device and system
JP2001292448A (en) Video encoder, video converter, and video data conversion system
KR20150145661A (en) A method and apparatus for controlling reception of a broadcast service provided using application layer forward error correction scheme
JP4671915B2 (en) Adaptive clock recovery apparatus and method
JP2005323029A (en) Gateway device for asynchronous voice communication
WO2014059846A1 (en) Method and device for fixing time delay

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680049588.3

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007552904

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 12158026

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06842937

Country of ref document: EP

Kind code of ref document: A1