WO2007060970A1 - Schottky barrier diode and method for using the same - Google Patents

Schottky barrier diode and method for using the same Download PDF

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Publication number
WO2007060970A1
WO2007060970A1 PCT/JP2006/323272 JP2006323272W WO2007060970A1 WO 2007060970 A1 WO2007060970 A1 WO 2007060970A1 JP 2006323272 W JP2006323272 W JP 2006323272W WO 2007060970 A1 WO2007060970 A1 WO 2007060970A1
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Prior art keywords
schottky
electrode
diode
silicon carbide
film
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PCT/JP2006/323272
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French (fr)
Japanese (ja)
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Tomonori Nakamura
Hidekazu Tsuchida
Toshiyuki Miyanagi
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Central Research Institute Of Electric Power Industry
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Application filed by Central Research Institute Of Electric Power Industry filed Critical Central Research Institute Of Electric Power Industry
Priority to US12/094,922 priority Critical patent/US8178940B2/en
Priority to EP06823499A priority patent/EP1962347A4/en
Priority to CN2006800438626A priority patent/CN101313407B/en
Publication of WO2007060970A1 publication Critical patent/WO2007060970A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a Schottky noria diode and a method of using the same. More specifically, in the present invention, a Schottky electrode is provided on the surface of a silicon carbide epitaxial film grown by surface force of a silicon carbide single crystal substrate, and is electrically connected to the outside on the Schottky electrode. The present invention relates to a Schottky Noria diode provided with a nod electrode.
  • SiC Silicon carbide
  • SiC is a wide-gap semiconductor with excellent physical properties such as a band gap of about 3 times, a saturation drift velocity of about 2 times, and a breakdown electric field strength of about 10 times that of Si.
  • FIG. 3 is a cross-sectional view of a conventional SiC Schottky barrier diode.
  • chemical vapor deposition CVD: Chemical Vapor
  • CVD Chemical Vapor
  • SiC single crystal substrate 2 obtained by slicing a SiC Balta single crystal grown by sublimation or the like into a wafer.
  • the substrate on which the SiC epitaxial film 3 is grown by Deposition is used, and the Schottky electrode 4 is formed on the surface of the SiC epitaxial film 3 by sputtering, vacuum deposition, etc.
  • An ohmic electrode 7 is formed on the surface (Patent Document 1 and Patent Document 2).
  • a pad electrode 6 is provided on the Schottky electrode 4, and is electrically connected to an external circuit such as a circuit board through the pad electrode 6 by, for example, wire bonding, solder connection, terminal connection, or the like. Connected to.
  • Patent Document 1 JP 2000-299479 A
  • Patent Document 2 Japanese Patent Laid-Open No. 2003-243323
  • a small hole may be formed in the Schottky electrode 4.
  • the pinhole 9 is formed in this way, a portion where the pad electrode 6 and the SiC epitaxial film 3 are directly joined locally is formed.
  • the pad electrode 6 gold or the like may be used as in Patent Document 2 A metal material having a small work function such as aluminum is often used, and this locally formed pad electrode is used.
  • the Schottky Barrier Height (SBH) at the junction between 6 and the n-type SiC epitaxial film 3 is smaller than the SBH at the junction between the Schottky electrode 4 and the SiC epitaxial film 3 .
  • the present invention provides a Schottky barrier diode that can reliably prevent an increase in excess current and reverse leakage current during forward energization due to pinholes formed in a Schottky electrode.
  • the present invention provides a method for using a Schottky diode capable of reliably preventing an increase in excess current and reverse leakage current during forward energization due to pinholes formed in a Schottky electrode. It is intended to provide.
  • a Schottky electrode is provided on the surface of a silicon carbide epitaxial film in which the surface force of a silicon carbide single crystal substrate is also grown.
  • an Schottky barrier height force between the silicon carbide epitaxial film and an intermediate metal film that is higher than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film is provided. , Characterized by that! /
  • the Schottky diode of the present invention includes a Schottky barrier height force between the pad electrode and the silicon carbide epitaxial film, and the Schottky electrode and the silicon carbide epitaxial film. It is characterized by being smaller than the Schottky barrier height.
  • the method of using the Schottky barrier diode of the present invention performs the forward and reverse switching operations using the Schottky barrier diode, and uses the Schottky electrode by the intermediate metal film. It is characterized by preventing excessive current during forward energization through the pinhole.
  • a method of using the Schottky barrier diode of the present invention performs the forward and reverse switching operations using the Schottky barrier diode, and uses the Schottky electrode by the intermediate metal film. It is characterized by suppressing reverse leakage current through the pinhole.
  • the Schottky diode of the present invention can reliably prevent an increase in excess current and reverse leakage current during forward energization due to pinholes formed in the Schottky electrode. Therefore, the yield in mass production can be improved.
  • FIG. 1 is a cross-sectional view showing an example of a Schottky diode according to the present invention.
  • FIG. 2 is a partially enlarged cross-sectional view showing a case where a pinhole is formed in a Schottky electrode in the Schottky barrier diode of the present invention.
  • FIG. 3 is a cross-sectional view showing a conventional Schottky diode.
  • FIG. 4 is a partial enlarged cross-sectional view showing a case where a pinhole is formed on a Schottky electrode in a conventional Schottky barrier diode.
  • FIG. 1 is a cross-sectional view showing an embodiment of a Schottky diode of the present invention.
  • an n-type SiC epitaxial film 3 is provided on the surface of an n-type SiC single crystal substrate 2.
  • a Schottky electrode 4 made of molybdenum is provided on the surface of the SiC epitaxial film 3.
  • an ohmic electrode 7 made of nickel is provided on the surface of the SiC single crystal substrate 2 on the opposite side.
  • a pad electrode 6 made of aluminum is provided on the upper surface side of the Schottky electrode 4.
  • an intermediate metal film 5 made of nickel is provided between the Schottky electrode 4 and the pad electrode 6.
  • a pinhole 9 may be formed in the Schottky electrode 4 in the process of manufacturing the SiC Schottky diode. In such a case, the pinhole 9 A local Schottky junction is formed between the intermediate metal film 5 and the SiC epitaxial film 3.
  • Nickel which is the material of the intermediate metal film 5 has SBH at the junction between the SiC epitaxial film 3 and SBH at the junction between the Schottky electrode 4 made of molybdenum and the SiC epitaxial film 3. Larger than
  • the SiC single crystal substrate 2 is a 4H—SiC single crystal substrate doped with 5 ⁇ 10 18 cm 3 nitrogen as an impurity.
  • the SiC epitaxial film 3 is a 4% -SiC single crystal having a film thickness of 30 ⁇ m grown from the surface of the SiC single crystal substrate 2 by CVD.
  • Reference numeral 8 denotes an ion implantation layer (JTE Junction Termination Extension) formed in the peripheral portion of the Schottky electrode 4 and is formed by heat treatment after implanting aluminum ions.
  • This ion implantation layer 8 is for relaxing the electric field concentration at the peripheral edge of the Schottky electrode 4 and improving the voltage resistance.
  • the Schottky electrode 4 has a film thickness of lOOnm, and is formed by depositing molybdenum by a sputtering method and then heat-treating it.
  • the intermediate metal film 5 has a film thickness of 50 nm, and is formed by depositing molybdenum, performing heat treatment, and then depositing nickel by a sputtering method.
  • the nod electrode 6 has a film thickness of 2 m and is formed by electron beam evaporation.
  • the ohmic electrode 7 has a thickness of 350 nm, and is formed by depositing nickel by electron beam evaporation and then heat-treating.
  • an SBH force with the SiC epitaxial film is provided, and an intermediate metal film that becomes SBH or more with the Schottky electrode and the silicon carbide epitaxial film is provided.
  • q n q (m-%).
  • q n SBH when a metal is brought into contact with an n-type semiconductor
  • ⁇ is a work function of the metal
  • X is an electron affinity of the ⁇ -type semiconductor.
  • the metal material of the intermediate metal film is close to the work function of the metal material of the Schottky electrode, or has a work function larger than that, I prefer to use something.
  • ⁇ is the work function of the metal
  • X is the electron affinity of the ⁇ -type semiconductor
  • Eg is the band gap of the ⁇ -type semiconductor.
  • the metal material of the intermediate metal film is close to the work function of the metal material of the Schottky electrode or has a work function smaller than that! /, Prefer to use things.
  • the magnitude of the work function in the metal material of the intermediate metal film and the Schottky electrode is It is not necessarily limited to the above.
  • Pad electrode Mo (work function 4.6 eV)
  • Pad electrode Mo (work function 4.6 eV)
  • Nod electrode Ti (work function 4. 33eV)
  • Examples of methods for depositing the Schottky electrode and the intermediate metal film include sputtering, vacuum deposition, and electron beam deposition.
  • Examples of the method for depositing the nod electrode include a plating method, a sputtering method, a vacuum evaporation method, and an electron beam evaporation method.
  • the SiC single crystal substrate for example, a substrate grown by a butterfly by an improved Rayleigh method, a substrate grown by a CVD method, or the like can be used.
  • SiC single crystal substrates of various crystal types can be used, and specific examples include 4H—
  • Examples include SiC (hexagonal four-period type), 6H—SiC (hexagonal six-period type), and 3C (cubic three-period type).
  • the crystal plane and crystal orientation for epitaxial growth of the SiC single crystal substrate are not particularly limited, Examples of crystal planes for epitaxial growth of SiC single crystal substrates include (OOOl) Si plane, (000-1) C plane, (11 20) plane, (01-10) plane, (03-38) plane, etc. Is mentioned.
  • SiC is epitaxially grown from this crystal plane by the step flow growth technique.
  • the surface of the SiC single crystal substrate on which epitaxial growth is performed is smoothed by polishing, etc., and if necessary, it is smoothed to a mirror surface by hydrogen etching, chemical mechanical polishing (CMP), etc. To do.
  • the SiC single crystal film is epitaxially grown by the smooth surface force CVD of the SiC single crystal substrate.
  • Propane or the like is used as the C source gas, and silane or the like is used as the Si source gas.
  • a mixed gas of these source gas, a carrier gas such as hydrogen, and a dopant gas is supplied to the surface of the SiC single crystal substrate, and SiC is epitaxially grown.
  • a SiC single crystal having the same crystal type as that of the SiC single crystal substrate is step-flow grown to form a SiC epitaxial film.
  • various conventionally known means and structures such as an ion implantation layer as in the above-described embodiment can be applied in order to alleviate electric field concentration at the periphery of the Schottky electrode.
  • the aluminum ion concentration in the ion implantation layer 8 is controlled so that the concentration decreases toward the outside of the central force, and the aluminum ion concentration is 2.2 ⁇ 10 18 cm 3 at the center, 3 X 10 17 cm— 3 .
  • heat treatment is performed at 1700 ° C, for example, to electrically activate aluminum.
  • An oxide film such as SiO is formed on a necessary portion such as the surface of the SiC epitaxial film of the Schottky diode for the purpose of protecting the element.
  • the ohmic electrode, the Schottky electrode, the intermediate metal film, and the pad electrode can be formed by applying photolithography using a resist.
  • a SiC single crystal substrate or a SiC epitaxial film can be used as a method for forming an electrode or the like using such photolithography.
  • a protective oxide film is formed on the surface of the film by heating, and then a resist film having an opening formed at a predetermined position is formed on the protective oxide film, and then the above-mentioned film is formed with noferred hydrofluoric acid or the like.
  • a method of removing the protective oxide film in the opening is mentioned.
  • a method can be used in which a predetermined metal film is deposited, a resist film is then formed on a portion where an electrode or the like is to be formed, and then a portion of the metal film not covered with the resist film is removed by etching. .
  • a metal film serving as an ohmic electrode is formed on the back surface of the SiC single crystal substrate, and then heat treatment (sinter treatment) in an atmosphere of an inert gas such as argon or nitrogen Then, an alloy with SiC is formed to form an ohmic electrode.
  • a metal film to be a Schottky electrode is formed on the surface of the SiC epitaxial film using the same photolithography technique. Subsequently, for example, after forming a metal film serving as an intermediate metal film thereon, heat treatment (sinter treatment) is performed in an atmosphere of an inert gas such as argon or nitrogen to form a Schottky electrode. Thereafter, a metal film to be a pad electrode is formed on the intermediate metal film by using the photolithography technique described above.
  • the Schottky diode of the present invention is electrically connected to an external circuit such as a circuit board through pad bonding, for example, via bonding such as aluminum, connection by solder, connection by terminal, and the like.
  • a wire electrode is wire-bonded on a terminal, and then sealed in a general-purpose sealing resin with each end of the terminal exposed, thereby forming a resin-sealed package.
  • the semiconductor device is obtained.
  • Such a semiconductor device may be a semiconductor module in which an element structure other than a plurality of Schottky diodes or Schottky diodes is formed on the same SiC single crystal substrate.
  • the Schottky diode of the present invention can be preferably applied to, for example, a Schottky diode having a reverse withstand voltage of about 0.6 to 5. OkV.
  • the yield of the Schottky diode of the present invention is improved by mass-producing a Schottky diode provided with an intermediate metal film, which is not limited to the one having a pinhole formed in the Schottky electrode. To do.

Abstract

An intermediate metal film is provided between a Schottky electrode and a pad electrode. The Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is higher than or equal to the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. The current conducted through a pinhole is thereby suppressed even when the Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is lower than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.

Description

明 細 書  Specification
ショットキーバリアダイオードおよびその使用方法  Schottky barrier diode and method of using the same
技術分野  Technical field
[0001] 本発明は、ショットキーノリアダイオードおよびその使用方法に関する。さらに詳しく は、本発明は、炭化珪素単結晶基板の表面力 成長させた炭化珪素ェピタキシャル 膜の表面にショットキー電極が設けられ、ショットキー電極の上に、外部と電気的に接 続するためのノッド電極が設けられたショットキーノリアダイオードに関する。  [0001] The present invention relates to a Schottky noria diode and a method of using the same. More specifically, in the present invention, a Schottky electrode is provided on the surface of a silicon carbide epitaxial film grown by surface force of a silicon carbide single crystal substrate, and is electrically connected to the outside on the Schottky electrode. The present invention relates to a Schottky Noria diode provided with a nod electrode.
背景技術  Background art
[0002] 炭化珪素（SiC)は、 Siと比べてバンドギャップが約 3倍、飽和ドリフト速度が約 2倍、 絶縁破壊電界強度が約 10倍と優れた物性値を有するワイドギャップ半導体であるこ とから、電力用半導体装置の材料として開発が進み、現在では SiCを用いたショット キーノリアダイオードが巿販されるに至っている。  [0002] Silicon carbide (SiC) is a wide-gap semiconductor with excellent physical properties such as a band gap of about 3 times, a saturation drift velocity of about 2 times, and a breakdown electric field strength of about 10 times that of Si. As a result, development has progressed as a material for power semiconductor devices, and Schottky noria diodes using SiC are now on the market.
[0003] 図 3は、従来の SiCショットキーバリアダイオードの断面図である。この SiCショットキ ーノリアダイオード 11では、昇華法などにより結晶成長させた SiCのバルタ単結晶を ウェハ状にスライスして得られた SiC単結晶基板 2の表面から、化学気相蒸着 (CVD ： Chemical Vapor Deposition)によって SiCェピタキシャル膜 3を成長させた基板が用 いられ、 SiCェピタキシャル膜 3の表面にはスパッタ法、真空蒸着法などによりショット キー電極 4が形成され、 SiC単結晶基板 2の他方の表面にはォーミック電極 7が形成 される（特許文献 1および特許文献 2)。  FIG. 3 is a cross-sectional view of a conventional SiC Schottky barrier diode. In this SiC Schottky diode 11, chemical vapor deposition (CVD: Chemical Vapor) is performed from the surface of a SiC single crystal substrate 2 obtained by slicing a SiC Balta single crystal grown by sublimation or the like into a wafer. The substrate on which the SiC epitaxial film 3 is grown by Deposition is used, and the Schottky electrode 4 is formed on the surface of the SiC epitaxial film 3 by sputtering, vacuum deposition, etc. An ohmic electrode 7 is formed on the surface (Patent Document 1 and Patent Document 2).
[0004] ショットキー電極 4の上には、パッド電極 6が設けられ、パッド電極 6を介して、例え ばワイヤボンディング、半田による接続、端子による接続などにより回路基板などの外 部回路へ電気的に接続される。  [0004] A pad electrode 6 is provided on the Schottky electrode 4, and is electrically connected to an external circuit such as a circuit board through the pad electrode 6 by, for example, wire bonding, solder connection, terminal connection, or the like. Connected to.
特許文献 1：特開 2000 - 299479号公報  Patent Document 1: JP 2000-299479 A
特許文献 2：特開 2003 - 243323号公報  Patent Document 2: Japanese Patent Laid-Open No. 2003-243323
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] しかし、上記の SiCショットキーダイオードを製造する過程において、図 4に拡大して 示したように、ショットキー電極 4に微小な穴 (ピンホール 9)が形成されることがある。こ のようにピンホール 9が形成されると、局所的にパッド電極 6と SiCェピタキシャル膜 3 とが直接に接合する部分が形成される。 [0005] However, in the process of manufacturing the above SiC Schottky diode, As shown, a small hole (pinhole 9) may be formed in the Schottky electrode 4. When the pinhole 9 is formed in this way, a portion where the pad electrode 6 and the SiC epitaxial film 3 are directly joined locally is formed.
[0006] パッド電極 6には、特許文献 2のように金などが用いられることもある力 アルミニウム のように仕事関数の小さな金属材料が用いられることが多ぐこの局所的に形成され たパッド電極 6と n型の SiCェピタキシャル膜 3との接合部分におけるショットキー障壁 高さ（SBH : Schottky Barrier Height)は、ショットキー電極 4と SiCェピタキシャル膜 3 との接合部分における SBHに比べて小さくなる。  As the pad electrode 6, gold or the like may be used as in Patent Document 2 A metal material having a small work function such as aluminum is often used, and this locally formed pad electrode is used. The Schottky Barrier Height (SBH) at the junction between 6 and the n-type SiC epitaxial film 3 is smaller than the SBH at the junction between the Schottky electrode 4 and the SiC epitaxial film 3 .
[0007] このように局所的に SBHが小さくなると、ピンホール 9を通じて電流が流れ易くなり、 順方向動作時において過剰電流が生じ、逆方向動作時において逆方向リーク電流 が増大する。このように性能が低下したものは製品として出荷できず、歩留まりが低下 してしまう。  [0007] When SBH is locally reduced in this way, current easily flows through pinhole 9, an excess current is generated during forward operation, and a reverse leakage current is increased during reverse operation. Products with such reduced performance cannot be shipped as products, resulting in reduced yield.
[0008] 本発明は、ショットキー電極に形成されたピンホールを起因とする順方向通電時に おける過剰電流および逆方向リーク電流の増加を確実に防止可能なショットキーバリ ァダイオードを提供することを目的として!/、る。  [0008] The present invention provides a Schottky barrier diode that can reliably prevent an increase in excess current and reverse leakage current during forward energization due to pinholes formed in a Schottky electrode. As a goal!
[0009] また本発明は、ショットキー電極に形成されたピンホールを起因とする順方向通電 時における過剰電流および逆方向リーク電流の増加を確実に防止可能なショットキ ーノ リアダイオードの使用方法を提供することを目的としている。  [0009] Further, the present invention provides a method for using a Schottky diode capable of reliably preventing an increase in excess current and reverse leakage current during forward energization due to pinholes formed in a Schottky electrode. It is intended to provide.
課題を解決するための手段  Means for solving the problem
[0010] 本発明のショットキーノ リアダイオードは、炭化珪素単結晶基板の表面力も成長さ せた炭化珪素ェピタキシャル膜の表面にショットキー電極が設けられ、ショットキー電 極の上に、外部と電気的に接続するためのパッド電極が設けられたショットキーノ リア ダイオードであって、 In the Schottky diode of the present invention, a Schottky electrode is provided on the surface of a silicon carbide epitaxial film in which the surface force of a silicon carbide single crystal substrate is also grown. A Schottky diode with a pad electrode for electrical connection,
ショットキー電極とパッド電極との間に、炭化珪素ェピタキシャル膜とのショットキー 障壁高さ力 ショットキー電極と炭化珪素ェピタキシャル膜とのショットキー障壁高さ 以上である中間金属膜が設けられて 、ることを特徴として！/、る。  Between the Schottky electrode and the pad electrode, an Schottky barrier height force between the silicon carbide epitaxial film and an intermediate metal film that is higher than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film is provided. , Characterized by that! /
[0011] 本発明のショットキーノ リアダイオードは、前記パッド電極と炭化珪素ェピタキシャ ル膜とのショットキー障壁高さ力 前記ショットキー電極と炭化珪素ェピタキシャル膜と のショットキー障壁高さよりも小さ 、ことを特徴として 、る。 [0011] The Schottky diode of the present invention includes a Schottky barrier height force between the pad electrode and the silicon carbide epitaxial film, and the Schottky electrode and the silicon carbide epitaxial film. It is characterized by being smaller than the Schottky barrier height.
[0012] 本発明のショットキーバリアダイオードの使用方法は、上記のショットキーバリアダイ オードを用 、て順方向および逆方向へのスィッチ動作を行 、、前記中間金属膜によ つて、ショットキー電極のピンホールを通じた順方向通電時における過剰電流を防止 することを特徴としている。  [0012] The method of using the Schottky barrier diode of the present invention performs the forward and reverse switching operations using the Schottky barrier diode, and uses the Schottky electrode by the intermediate metal film. It is characterized by preventing excessive current during forward energization through the pinhole.
[0013] 本発明のショットキーバリアダイオードの使用方法は、上記のショットキーバリアダイ オードを用 、て順方向および逆方向へのスィッチ動作を行 、、前記中間金属膜によ つて、ショットキー電極のピンホールを通じた逆方向リーク電流を抑制することを特徴 としている。  [0013] A method of using the Schottky barrier diode of the present invention performs the forward and reverse switching operations using the Schottky barrier diode, and uses the Schottky electrode by the intermediate metal film. It is characterized by suppressing reverse leakage current through the pinhole.
発明の効果  The invention's effect
[0014] 本発明のショットキーダイオードは、ショットキー電極に形成されたピンホールを起 因とする順方向通電時における過剰電流および逆方向リーク電流の増加を確実に 防止できる。そのため、量産する際における歩留まりを向上させることができる。  [0014] The Schottky diode of the present invention can reliably prevent an increase in excess current and reverse leakage current during forward energization due to pinholes formed in the Schottky electrode. Therefore, the yield in mass production can be improved.
[0015] 本発明のショットキーダイオードの使用方法によれば、ショットキー電極に形成され たピンホールを起因とする順方向通電時における過剰電流および逆方向リーク電流 の増加を確実に防止できる。  According to the method of using the Schottky diode of the present invention, it is possible to reliably prevent an increase in excess current and reverse leakage current during forward energization due to pinholes formed in the Schottky electrode.
図面の簡単な説明  Brief Description of Drawings
[0016] [図 1]図 1は、本発明のショットキーノ リアダイオードの実施例を示した断面図である。  FIG. 1 is a cross-sectional view showing an example of a Schottky diode according to the present invention.
[図 2]図 2は、本発明のショットキーバリアダイオードにおいて、ショットキー電極にピン ホールが形成された場合を示した部分拡大断面図である。  FIG. 2 is a partially enlarged cross-sectional view showing a case where a pinhole is formed in a Schottky electrode in the Schottky barrier diode of the present invention.
[図 3]図 3は、従来のショットキーノ リアダイオードを示した断面図である。  FIG. 3 is a cross-sectional view showing a conventional Schottky diode.
[図 4]図 4は、従来のショットキーバリアダイオードにおいて、ショットキー電極にピンホ ールが形成された場合を示した部分拡大断面図である。  FIG. 4 is a partial enlarged cross-sectional view showing a case where a pinhole is formed on a Schottky electrode in a conventional Schottky barrier diode.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0017] 以下、図面を参照しながら本発明について説明する。図 1は、本発明のショットキー ノ リアダイオードにおける実施例を示した断面図である。このショットキーノ リアダイォ ード 1は、 n型の SiC単結晶基板 2の表面に、 n型の SiCェピタキシャル膜 3が設けら れている。 [0018] SiCェピタキシャル膜 3の表面には、モリブデンを材料としたショットキー電極 4が設 けられている。一方、その反対側における SiC単結晶基板 2の表面には、ニッケルを 材料としたォーミック電極 7が設けられている。ショットキー電極 4の上面側には、アル ミニゥムを材料としたパッド電極 6が設けられている。 Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing an embodiment of a Schottky diode of the present invention. In this Schottky diode 1, an n-type SiC epitaxial film 3 is provided on the surface of an n-type SiC single crystal substrate 2. [0018] On the surface of the SiC epitaxial film 3, a Schottky electrode 4 made of molybdenum is provided. On the other hand, an ohmic electrode 7 made of nickel is provided on the surface of the SiC single crystal substrate 2 on the opposite side. On the upper surface side of the Schottky electrode 4, a pad electrode 6 made of aluminum is provided.
[0019] 本実施例では、ショットキー電極 4とパッド電極 6との間に、ニッケルを材料とした中 間金属膜 5が設けられている。図 2に拡大して示したように、 SiCショットキーノ リアダ ィオードを製造する過程において、ショットキー電極 4にピンホール 9が形成されること があるが、このような場合には、ピンホール 9において、中間金属膜 5と SiCェピタキシ ャル膜 3との間で局所的なショットキー接合が形成される。 In this embodiment, an intermediate metal film 5 made of nickel is provided between the Schottky electrode 4 and the pad electrode 6. As shown in an enlarged view in FIG. 2, a pinhole 9 may be formed in the Schottky electrode 4 in the process of manufacturing the SiC Schottky diode. In such a case, the pinhole 9 A local Schottky junction is formed between the intermediate metal film 5 and the SiC epitaxial film 3.
[0020] 中間金属膜 5の材料であるニッケルは、 SiCェピタキシャル膜 3との接合部分にお ける SBHが、モリブデンを材料としたショットキー電極 4と SiCェピタキシャル膜 3との 接合部分における SBHに比べて大きくなる。 [0020] Nickel, which is the material of the intermediate metal film 5, has SBH at the junction between the SiC epitaxial film 3 and SBH at the junction between the Schottky electrode 4 made of molybdenum and the SiC epitaxial film 3. Larger than
[0021] したがって、ピンホール 9を通じた電流が充分に抑制され、順方向動作時にはピン ホール 9を通じた過剰電流が防止されると共に、逆方向動作時にはピンホール 9を通 じた逆方向リーク電流が充分に抑制される。 [0021] Therefore, the current through the pinhole 9 is sufficiently suppressed, excessive current through the pinhole 9 is prevented during forward operation, and reverse leakage current through the pinhole 9 is prevented during reverse operation. Sufficiently suppressed.
[0022] 本実施例において、 SiC単結晶基板 2は、不純物として 5 X 1018cm 3の窒素がドー プされた 4H— SiC単結晶の基板である。 In the present example, the SiC single crystal substrate 2 is a 4H—SiC single crystal substrate doped with 5 × 10 18 cm 3 nitrogen as an impurity.
[0023] SiCェピタキシャル膜 3は、 CVDにより SiC単結晶基板 2の表面から成長させた膜 厚 30 μ mの 4Η— SiC単結晶である。 The SiC epitaxial film 3 is a 4% -SiC single crystal having a film thickness of 30 μm grown from the surface of the SiC single crystal substrate 2 by CVD.
[0024] 符号 8は、ショットキー電極 4の周縁部に形成されたイオン注入層（JTE Junction T ermination Extension)であり、アルミイオンを注入した後に熱処理して形成される。こ のイオン注入層 8は、ショットキー電極 4の周縁部における電界集中を緩和して耐電 圧性を向上するためのものである。 Reference numeral 8 denotes an ion implantation layer (JTE Junction Termination Extension) formed in the peripheral portion of the Schottky electrode 4 and is formed by heat treatment after implanting aluminum ions. This ion implantation layer 8 is for relaxing the electric field concentration at the peripheral edge of the Schottky electrode 4 and improving the voltage resistance.
[0025] ショットキー電極 4は、膜厚が lOOnmであり、スパッタ法によりモリブデンを堆積した 後、熱処理して形成したものである。 [0025] The Schottky electrode 4 has a film thickness of lOOnm, and is formed by depositing molybdenum by a sputtering method and then heat-treating it.
[0026] 中間金属膜 5は、膜厚が 50nmであり、モリブデンを堆積した後熱処理を施し、その 後スパッタ法によりニッケルを堆積して形成したものである。 The intermediate metal film 5 has a film thickness of 50 nm, and is formed by depositing molybdenum, performing heat treatment, and then depositing nickel by a sputtering method.
[0027] ノッド電極 6は、膜厚が 2 mであり、電子ビーム蒸着により形成したものである。 [0028] ォーミック電極 7は、膜厚が 350nmであり、電子ビーム蒸着によりニッケルを堆積し た後、熱処理して形成したものである。 The nod electrode 6 has a film thickness of 2 m and is formed by electron beam evaporation. The ohmic electrode 7 has a thickness of 350 nm, and is formed by depositing nickel by electron beam evaporation and then heat-treating.
[0029] 以上に本発明の実施例を示したが、本発明はこの実施例に限定されるものではな ぐその要旨を逸脱しない範囲内において各種の変形、変更が可能である。その一 例を以下に説明する。 The embodiment of the present invention has been described above, but the present invention is not limited to this embodiment, and various modifications and changes can be made without departing from the scope of the present invention. An example is described below.
[0030] 本発明では、ショットキー電極とパッド電極との間に、 SiCェピタキシャル膜との SB H力 ショットキー電極と炭化珪素ェピタキシャル膜との SBH以上となる中間金属膜 が設けられる。  In the present invention, between the Schottky electrode and the pad electrode, an SBH force with the SiC epitaxial film is provided, and an intermediate metal film that becomes SBH or more with the Schottky electrode and the silicon carbide epitaxial film is provided.
[0031] 一般的に、金属と n型半導体との接触により生じる SBHは、 q n=q ( m— % )の 式で与えられる。ここで、 q nは、 n型半導体に金属を接触させたときの SBHであり、 Φπιは金属の仕事関数、 Xは η型半導体の電子親和力である。  [0031] Generally, SBH generated by contact between a metal and an n-type semiconductor is given by the following equation: q n = q (m-%). Here, q n is SBH when a metal is brought into contact with an n-type semiconductor, Φπι is a work function of the metal, and X is an electron affinity of the η-type semiconductor.
[0032] したがって、 SiCェピタキシャル膜が η型である場合には、中間金属膜の金属材料 には、ショットキー電極の金属材料の仕事関数に近いもの、またはそれよりも仕事関 数が大き 、ものを用いることが好まし 、。  [0032] Therefore, when the SiC epitaxial film is η-type, the metal material of the intermediate metal film is close to the work function of the metal material of the Schottky electrode, or has a work function larger than that, I prefer to use something.
[0033] 一方、金属と ρ型半導体との接触により生じる SBHは、 q p = Eg— q ( m— % )の 式で与えられる。ここで、 p型半導体に金属を接触させたときの SBHであり、 Φπιは金 属の仕事関数、 Xは ρ型半導体の電子親和力、 Egは ρ型半導体のバンドギャップで ある。  On the other hand, SBH generated by contact between a metal and a ρ-type semiconductor is given by the equation q p = Eg−q (m−%). Here, SBH when a metal is brought into contact with a p-type semiconductor, Φπι is the work function of the metal, X is the electron affinity of the ρ-type semiconductor, and Eg is the band gap of the ρ-type semiconductor.
[0034] したがって、 SiCェピタキシャル膜が p型である場合には、中間金属膜の金属材料 には、ショットキー電極の金属材料の仕事関数に近いもの、またはそれよりも仕事関 数が小さ!/、ものを用いることが好ま 、。  [0034] Therefore, when the SiC epitaxial film is p-type, the metal material of the intermediate metal film is close to the work function of the metal material of the Schottky electrode or has a work function smaller than that! /, Prefer to use things.
[0035] しかし、金属膜を堆積した後の熱処理によって SiCとの合金が形成されることにより SBHの大きさは変化するので、中間金属膜とショットキー電極の金属材料における 仕事関数の大小は、必ずしも上記に限定されるものではない。  However, since the size of SBH changes due to the formation of an alloy with SiC by heat treatment after depositing the metal film, the magnitude of the work function in the metal material of the intermediate metal film and the Schottky electrode is It is not necessarily limited to the above.
[0036] SiCェピタキシャル膜が n型である場合のショットキー電極、中間金属膜、およびパ ッド電極に用いられる金属材料の好ま 、組み合わせを以下に例示する。  [0036] Preferable combinations of metal materials used for the Schottky electrode, the intermediate metal film, and the pad electrode when the SiC epitaxial film is n-type are exemplified below.
<具体例 1 >  <Specific example 1>
ショットキー電極: Ti (仕事関数 4. 33eV) 中間金属膜: Ni (仕事関数 5. 15eV) Schottky electrode: Ti (work function 4. 33eV) Intermediate metal film: Ni (work function 5. 15eV)
ノ ッド電極: A1 (仕事関数 4. 28eV)  Node electrode: A1 (work function 4.28eV)
<具体例 2>  <Specific example 2>
ショットキー電極: W (仕事関数 4. 55eV)  Schottky electrode: W (work function 4. 55eV)
中間金属膜: Ni (仕事関数 5. 15eV)  Intermediate metal film: Ni (work function 5. 15eV)
ノッド電極: A1 (仕事関数 4. 28eV)  Nod electrode: A1 (work function 4. 28eV)
<具体例 3 >  <Specific example 3>
ショットキー電極: Ti (仕事関数 4. 33eV)  Schottky electrode: Ti (work function 4. 33eV)
中間金属膜: Ni (仕事関数 5. 15eV)  Intermediate metal film: Ni (work function 5. 15eV)
パッド電極： Mo (仕事関数 4. 6eV)  Pad electrode: Mo (work function 4.6 eV)
<具体例 4>  <Specific example 4>
ショットキー電極: W (仕事関数 4. 55eV)  Schottky electrode: W (work function 4. 55eV)
中間金属膜: Ni (仕事関数 5. 15eV)  Intermediate metal film: Ni (work function 5. 15eV)
パッド電極： Mo (仕事関数 4. 6eV)  Pad electrode: Mo (work function 4.6 eV)
<具体例 5 >  <Specific example 5>
ショットキー電極: W (仕事関数 4. 55eV)  Schottky electrode: W (work function 4. 55eV)
中間金属膜: Ni (仕事関数 5. 15eV)  Intermediate metal film: Ni (work function 5. 15eV)
ノッド電極: Ti (仕事関数 4. 33eV)  Nod electrode: Ti (work function 4. 33eV)
ショットキー電極および中間金属膜を堆積する方法としては、スパッタ法、真空蒸着 法、電子ビーム蒸着法などが挙げられる。  Examples of methods for depositing the Schottky electrode and the intermediate metal film include sputtering, vacuum deposition, and electron beam deposition.
[0037] ノッド電極を堆積する方法としては、メツキ法、スパッタ法、真空蒸着法、電子ビー ム蒸着法などが挙げられる。 [0037] Examples of the method for depositing the nod electrode include a plating method, a sputtering method, a vacuum evaporation method, and an electron beam evaporation method.
[0038] 本発明において、 SiC単結晶基板としては、例えば、改良レーリー法によりバルタ 成長させたもの、 CVD法によってバルタ成長させたものなどを用いることができる。 [0038] In the present invention, as the SiC single crystal substrate, for example, a substrate grown by a butterfly by an improved Rayleigh method, a substrate grown by a CVD method, or the like can be used.
[0039] SiC単結晶基板には各種の結晶型のものを使用でき、その具体例としては、 4H—[0039] SiC single crystal substrates of various crystal types can be used, and specific examples include 4H—
SiC (六方晶四回周期型）、 6H— SiC (六方晶六回周期型）、 3C (立方晶三回周期 型)などが挙げられる。 Examples include SiC (hexagonal four-period type), 6H—SiC (hexagonal six-period type), and 3C (cubic three-period type).
[0040] SiC単結晶基板のェピタキシャル成長を行う結晶面、結晶方位は特に限定されず、 SiC単結晶基板のェピタキシャル成長を行う結晶面としては、例えば (OOOl) Si面、（ 000— 1) C面、（11 20)面、（01— 10)面、（03— 38)面などが挙げられる。 [0040] The crystal plane and crystal orientation for epitaxial growth of the SiC single crystal substrate are not particularly limited, Examples of crystal planes for epitaxial growth of SiC single crystal substrates include (OOOl) Si plane, (000-1) C plane, (11 20) plane, (01-10) plane, (03-38) plane, etc. Is mentioned.
[0041] (OOOl) Si面、（000— 1) C面でェピタキシャル成長させる場合、例えば、 [01— 10 ]方向、 [11 20]方向、あるいは [01— 10]方向と [11 20]方向との中間方向のオフ 方位に、好ましくは 1〜12° のオフ角で傾斜させて切り出した基板を使用し、この結 晶面からステップフロー成長技術により SiCをェピタキシャル成長させる。 SiC単結晶 基板のェピタキシャル成長させる側の表面は、研磨処理などで平滑化し、必要に応 じて水素エッチング、化学機械研磨（CMP : Chemical Mechanical Polishing)な どにより処理して鏡面状に平滑化する。  [0041] In the case of epitaxial growth on the (OOOl) Si face and the (000-1) C face, for example, [01-10] direction, [11 20] direction, or [01-10] direction and [11 20] Using a substrate cut off at an off-direction of 1 to 12 ° in the off-direction in the middle direction with respect to the direction, SiC is epitaxially grown from this crystal plane by the step flow growth technique. The surface of the SiC single crystal substrate on which epitaxial growth is performed is smoothed by polishing, etc., and if necessary, it is smoothed to a mirror surface by hydrogen etching, chemical mechanical polishing (CMP), etc. To do.
[0042] この SiC単結晶基板の平滑ィ匕した表面力 CVDによって SiC単結晶膜をェピタキ シャル成長させる。 Cの原料ガスとしはプロパン等が用いられ、 Siの原料ガスとしては シラン等が用いられる。これらの原料ガスと、水素等のキャリアガスと、ドーパントガス との混合ガスを SiC単結晶基板の表面に供給し、 SiCをェピタキシャル成長させる。 これにより、 SiC単結晶基板と同一の結晶型である SiC単結晶がステップフロー成長 し、 SiCェピタキシャル膜が形成される。  [0042] The SiC single crystal film is epitaxially grown by the smooth surface force CVD of the SiC single crystal substrate. Propane or the like is used as the C source gas, and silane or the like is used as the Si source gas. A mixed gas of these source gas, a carrier gas such as hydrogen, and a dopant gas is supplied to the surface of the SiC single crystal substrate, and SiC is epitaxially grown. As a result, a SiC single crystal having the same crystal type as that of the SiC single crystal substrate is step-flow grown to form a SiC epitaxial film.
[0043] 本発明では、ショットキー電極の周縁部における電界集中を緩和するために、上記 の実施例のようなイオン注入層など、従来公知である各種の手段および構造を適用 することができる。上記の実施例では、イオン注入層 8中のアルミイオン濃度は、中心 力 外部に向かって濃度が低くなるように制御され、アルミイオン濃度は中心におい て 2. 2 X 1018cm 3、外部において 3 X 1017cm— 3となっている。アルミイオンを注入した 後、アルミニウムを電気的に活性化するために、例えば 1700°Cで熱処理が施される In the present invention, various conventionally known means and structures such as an ion implantation layer as in the above-described embodiment can be applied in order to alleviate electric field concentration at the periphery of the Schottky electrode. In the above embodiment, the aluminum ion concentration in the ion implantation layer 8 is controlled so that the concentration decreases toward the outside of the central force, and the aluminum ion concentration is 2.2 × 10 18 cm 3 at the center, 3 X 10 17 cm— 3 . After implanting aluminum ions, heat treatment is performed at 1700 ° C, for example, to electrically activate aluminum.
[0044] 上記の実施例では図示省略している力 ショットキーダイオードの SiCェピタキシャ ル膜表面などの必要な部位には、素子の保護等を目的として SiOなどの酸ィ匕膜が [0044] Force not shown in the above-mentioned embodiments An oxide film such as SiO is formed on a necessary portion such as the surface of the SiC epitaxial film of the Schottky diode for the purpose of protecting the element.
2  2
形成される。  It is formed.
[0045] ォーミック電極、ショットキー電極、中間金属膜、およびパッド電極は、レジストを用 いたフォトリソグラフィーを適用して形成することができる。このようなフォトリソグラフィ 一を用いた電極等の形成方法としては、 SiC単結晶基板または SiCェピタキシャル 膜の表面に加熱によって保護酸ィ匕膜を形成し、次いで、所定の位置に開口部が形 成されたレジスト膜を保護酸ィ匕膜の上に形成し、その後、ノ ッファードフッ酸等により 上記開口部の保護酸ィ匕膜を除去する方法が挙げられる。あるいは、所定の金属膜を 堆積し、次いで、電極等を形成する部分にレジスト膜を形成し、その後、エッチングに よりレジスト膜で覆われていない部分の金属膜を除去する方法を用いることができる。 [0045] The ohmic electrode, the Schottky electrode, the intermediate metal film, and the pad electrode can be formed by applying photolithography using a resist. As a method for forming an electrode or the like using such photolithography, a SiC single crystal substrate or a SiC epitaxial film can be used. A protective oxide film is formed on the surface of the film by heating, and then a resist film having an opening formed at a predetermined position is formed on the protective oxide film, and then the above-mentioned film is formed with noferred hydrofluoric acid or the like. A method of removing the protective oxide film in the opening is mentioned. Alternatively, a method can be used in which a predetermined metal film is deposited, a resist film is then formed on a portion where an electrode or the like is to be formed, and then a portion of the metal film not covered with the resist film is removed by etching. .
[0046] 上記のフォトリソグラフィー技術を用いて、 SiC単結晶基板の裏面にォーミック電極 となる金属膜を形成し、次いで、アルゴン、窒素などの不活性ガスの雰囲気下で熱処 理 (シンター処理)して SiCとの合金を形成し、ォーミック電極とする。  [0046] Using the photolithography technique described above, a metal film serving as an ohmic electrode is formed on the back surface of the SiC single crystal substrate, and then heat treatment (sinter treatment) in an atmosphere of an inert gas such as argon or nitrogen Then, an alloy with SiC is formed to form an ohmic electrode.
[0047] ォーミック電極を形成した後、同様にフォトリソグラフィー技術を用いて、 SiCェピタ キシャル膜の表面にショットキー電極となる金属膜を形成する。続いて、例えば中間 金属膜となる金属膜をその上に形成した後、アルゴン、窒素などの不活性ガスの雰 囲気下で熱処理 (シンター処理）してショットキー電極とする。その後、上記のフォトリ ソグラフィー技術を用いて、中間金属膜の上にパッド電極となる金属膜を形成する。  [0047] After the ohmic electrode is formed, a metal film to be a Schottky electrode is formed on the surface of the SiC epitaxial film using the same photolithography technique. Subsequently, for example, after forming a metal film serving as an intermediate metal film thereon, heat treatment (sinter treatment) is performed in an atmosphere of an inert gas such as argon or nitrogen to form a Schottky electrode. Thereafter, a metal film to be a pad electrode is formed on the intermediate metal film by using the photolithography technique described above.
[0048] 本発明のショットキーダイオードは、パッド電極を介して、例えばアルミニウム等のヮ ィャボンディング、半田による接続、端子による接続などにより回路基板などの外部 回路へ電気的に接続される。例えば、ノ ッド電極を端子上にワイヤボンディングし、 その後、端子の各端部を露出させた状態で、汎用の封止榭脂内に封止することによ り、榭脂封止パッケージとしての半導体デバイスが得られる。このような半導体デバイ スは、同一の SiC単結晶基板に複数のショットキーダイオードまたはショットキーダイ オード以外の素子構造が形成された半導体モジュールであってもよい。  [0048] The Schottky diode of the present invention is electrically connected to an external circuit such as a circuit board through pad bonding, for example, via bonding such as aluminum, connection by solder, connection by terminal, and the like. For example, a wire electrode is wire-bonded on a terminal, and then sealed in a general-purpose sealing resin with each end of the terminal exposed, thereby forming a resin-sealed package. The semiconductor device is obtained. Such a semiconductor device may be a semiconductor module in which an element structure other than a plurality of Schottky diodes or Schottky diodes is formed on the same SiC single crystal substrate.
[0049] 本発明のショットキーダイオードは、例えば、逆方向耐電圧が 0. 6〜5. OkV程度で あるショットキーダイオードに好ましく適用できる。  [0049] The Schottky diode of the present invention can be preferably applied to, for example, a Schottky diode having a reverse withstand voltage of about 0.6 to 5. OkV.
[0050] なお、本発明のショットキーダイオードは、ショットキー電極にピンホールが形成され ているものに限定されるものではなぐ中間金属膜を設けたものを量産することによつ て歩留まりが向上する。  [0050] The yield of the Schottky diode of the present invention is improved by mass-producing a Schottky diode provided with an intermediate metal film, which is not limited to the one having a pinhole formed in the Schottky electrode. To do.

Claims

請求の範囲 The scope of the claims
[1] 炭化珪素単結晶基板の表面から成長させた炭化珪素ェピタキシャル膜の表面にシ ヨットキー電極が設けられ、ショットキー電極の上に、外部と電気的に接続するための パッド電極が設けられたショットキーバリアダイオードであって、  [1] A silicon key electrode is provided on the surface of the silicon carbide epitaxial film grown from the surface of the silicon carbide single crystal substrate, and a pad electrode for electrical connection to the outside is provided on the Schottky electrode. A Schottky barrier diode,
ショットキー電極とパッド電極との間に、炭化珪素ェピタキシャル膜とのショットキー 障壁高さ力 ショットキー電極と炭化珪素ェピタキシャル膜とのショットキー障壁高さ 以上である中間金属膜が設けられて 、ることを特徴とするショットキーノ リアダイォー ド、。  Between the Schottky electrode and the pad electrode, an Schottky barrier height force between the silicon carbide epitaxial film and an intermediate metal film that is higher than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film is provided. A Schottky rear diode, characterized by
[2] 前記パッド電極と炭化珪素ェピタキシャル膜とのショットキー障壁高さが、前記ショッ トキ一電極と炭化珪素ェピタキシャル膜とのショットキー障壁高さよりも小さいことを特 徴とする請求項 1に記載のショットキーバリアダイオード。  [2] The Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is smaller than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. The Schottky barrier diode described in 1.
[3] 請求項 1または 2に記載のショットキーノ リアダイオードを用いて順方向および逆方 向へのスィッチ動作を行い、前記中間金属膜によって、ショットキー電極のピンホー ルを通じた順方向通電時における過剰電流を防止することを特徴とするショットキー ノ リアダイオードの使用方法。  [3] A forward and reverse switching operation is performed using the Schottky diode according to claim 1 or 2, and the intermediate metal film is used during forward energization through a pinhole of a Schottky electrode. A method of using a Schottky NORIO diode characterized by preventing excessive current.
[4] 請求項 1または 2に記載のショットキーノ リアダイオードを用いて順方向および逆方 向へのスィッチ動作を行い、前記中間金属膜によって、ショットキー電極のピンホー ルを通じた逆方向リーク電流を抑制することを特徴とするショットキーノ リアダイオード の使用方法。  [4] A forward and reverse switching operation is performed using the Schottky NOR diode according to claim 1 or 2, and a reverse leakage current through the pinhole of the Schottky electrode is reduced by the intermediate metal film. A method of using a Schottky diode, which is characterized by suppression.
PCT/JP2006/323272 2005-11-25 2006-11-22 Schottky barrier diode and method for using the same WO2007060970A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320601B (en) * 2008-06-18 2011-08-17 西北工业大学 Silicon carbide Schottky junction type nuclear cell and preparation thereof

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4800239B2 (en) * 2007-02-26 2011-10-26 三菱電機株式会社 Manufacturing method of semiconductor device
JP5307381B2 (en) * 2007-11-12 2013-10-02 Ｈｏｙａ株式会社 Semiconductor device and semiconductor device manufacturing method
US8866342B2 (en) * 2008-03-19 2014-10-21 Mitsubishi Electric Corporation Power converting apparatus
JP2010157547A (en) 2008-12-26 2010-07-15 Showa Denko Kk Method of manufacturing silicon carbide semiconductor device
JP5453867B2 (en) * 2009-03-24 2014-03-26 株式会社デンソー Silicon carbide semiconductor device having Schottky barrier diode and method for manufacturing the same
JPWO2010110252A1 (en) * 2009-03-27 2012-09-27 住友電気工業株式会社 MOSFET and MOSFET manufacturing method
WO2010119491A1 (en) * 2009-04-16 2010-10-21 三菱電機株式会社 Method for manufacturing silicon carbide semiconductor device
JP5598015B2 (en) * 2010-02-23 2014-10-01 株式会社デンソー Silicon carbide semiconductor device having Schottky barrier diode and method for manufacturing the same
JP5790214B2 (en) * 2010-09-09 2015-10-07 株式会社デンソー Horizontal insulated gate bipolar transistor
CN102569421B (en) * 2010-12-17 2015-06-17 浙江大学 Novel silicon carbide Schottky diode
JP6042658B2 (en) * 2011-09-07 2016-12-14 トヨタ自動車株式会社 Method for manufacturing SiC semiconductor device
KR20130049919A (en) * 2011-11-07 2013-05-15 현대자동차주식회사 Silicon carbide schottky-barrier diode and method for manufacturing thr same
JP5656889B2 (en) * 2012-01-24 2015-01-21 三菱電機株式会社 Semiconductor device and semiconductor module including the same
JP5811930B2 (en) * 2012-04-03 2015-11-11 株式会社デンソー Method for manufacturing silicon carbide semiconductor device
EP2860760A4 (en) * 2012-06-06 2016-06-15 Rohm Co Ltd Semiconductor device and method for manufacturing same
JP5678341B2 (en) * 2013-08-23 2015-03-04 株式会社レーザーシステム Schottky barrier diode, method for manufacturing Schottky barrier diode, power transmission system, and wireless connector for power line
EP2905806B1 (en) * 2013-10-08 2016-08-24 Shindengen Electric Manufacturing Co., Ltd. Method for manufacturing a silicon carbide semiconductor device.
US10204778B2 (en) * 2016-12-28 2019-02-12 QROMIS, Inc. Method and system for vertical power devices
US10411108B2 (en) * 2017-03-29 2019-09-10 QROMIS, Inc. Vertical gallium nitride Schottky diode
CN108321212A (en) * 2017-12-21 2018-07-24 秦皇岛京河科学技术研究院有限公司 The preparation method and its structure of SiC Schottky diode

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11233796A (en) * 1998-02-17 1999-08-27 Matsushita Electron Corp Manufacture of schottky diode
JP2000299479A (en) 1999-04-13 2000-10-24 New Japan Radio Co Ltd Schottky diode and manufacture thereof
JP2001015771A (en) 1999-07-01 2001-01-19 Shindengen Electric Mfg Co Ltd Semiconductor rectifying element
JP2001053293A (en) 1999-08-10 2001-02-23 Fuji Electric Co Ltd SiC SCHOTTKY DIODE AND MANUFACTURE THEREOF
US20020121641A1 (en) 1999-12-07 2002-09-05 Philips Electronics North America Corporation Passivated silicon carbide devices with low leakage current and method of fabricating
JP2003243323A (en) 2001-12-14 2003-08-29 Matsushita Electric Ind Co Ltd Semiconductor element and its manufacturing method
EP1349202A2 (en) 2002-03-28 2003-10-01 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4782238A (en) 1987-10-20 1988-11-01 Eastman Kodak Company Apparatus for generating edge position signals for use in locating an address element on a mailpiece
JP2005310844A (en) * 2004-04-16 2005-11-04 Toshiba Corp Power semiconductor module

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11233796A (en) * 1998-02-17 1999-08-27 Matsushita Electron Corp Manufacture of schottky diode
JP2000299479A (en) 1999-04-13 2000-10-24 New Japan Radio Co Ltd Schottky diode and manufacture thereof
JP2001015771A (en) 1999-07-01 2001-01-19 Shindengen Electric Mfg Co Ltd Semiconductor rectifying element
JP2001053293A (en) 1999-08-10 2001-02-23 Fuji Electric Co Ltd SiC SCHOTTKY DIODE AND MANUFACTURE THEREOF
US20020121641A1 (en) 1999-12-07 2002-09-05 Philips Electronics North America Corporation Passivated silicon carbide devices with low leakage current and method of fabricating
JP2003243323A (en) 2001-12-14 2003-08-29 Matsushita Electric Ind Co Ltd Semiconductor element and its manufacturing method
EP1349202A2 (en) 2002-03-28 2003-10-01 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1962347A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320601B (en) * 2008-06-18 2011-08-17 西北工业大学 Silicon carbide Schottky junction type nuclear cell and preparation thereof

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