WO2007054611A1 - A method of manufacturing a 3d semiconductor that minimize stress and void formation - Google Patents

A method of manufacturing a 3d semiconductor that minimize stress and void formation Download PDF

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Publication number
WO2007054611A1
WO2007054611A1 PCT/FI2006/000364 FI2006000364W WO2007054611A1 WO 2007054611 A1 WO2007054611 A1 WO 2007054611A1 FI 2006000364 W FI2006000364 W FI 2006000364W WO 2007054611 A1 WO2007054611 A1 WO 2007054611A1
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semiconductor material
region
semiconductor
semiconductor device
observed
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PCT/FI2006/000364
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French (fr)
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Artto Mikael Aurola
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Artto Mikael Aurola
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Publication of WO2007054611A1 publication Critical patent/WO2007054611A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02625—Liquid deposition using melted materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that includes three dimensional (3D) structures.
  • the semiconductor device manufactured with the aforesaid method can be used for instance in radiation detection devices, solar cells and in electronics including radio frequency (RF) and power electronics.
  • RF radio frequency
  • a semiconductor device comprising a 3D structure is hereinafter referred to as a semiconductor device including a first region 100 of semiconductor material having a first surface 101 , and at a defined first distance D1 from the first surface, a second surface 102, characterized by the semiconductor device including a second region 111 , 112 of semiconductor material protruding from the first surface to a second distance D2 (D2 ⁇ D1) into the first region 100 of semiconductor material, the second distance D2 being longer than the smallest distance D3 of the second region 111 , 112 of semiconductor material at the first surface.
  • D2 is considerably bigger than D3, so advantageously inequalities can be listed in order of preference: D2 > 20*D3, D2 > 10xD3, D2 > 5 ⁇ D3, D2 > 4*D3, D2 > 3> ⁇ D3, D2 > 2 ⁇ D3, D2 > D3, where the first one is the most beneficial inequality.
  • the second region 111 , 112 of semiconductor material is hereinafter referred to as the 3D structure
  • the first surface 101 is hereinafter referred to as the front surface
  • the second surface 102 is hereinafter referred to as the back surface
  • the distances D1 and D2 are hereinafter referred to extend into a vertical dimension
  • the distance D3 is hereinafter referred to be on a horizontal plane
  • the horizontal plane is hereinafter referred to extend to two horizontal dimensions.
  • the first and second region semiconductor materials are different semiconductor materials or they have a different doping concentration.
  • the first and second region semiconductor materials are lattice matched.
  • the first and second region semiconductor materials can exhibit the same type of conductivity or they can be of opposite conductivity.
  • the semiconductor device may also have 3D structures 111 , 132 of opposite conductivity types, a situation which is depicted in Figure 3.
  • the 3D structures 111 , 132 can be formed of same or of different semiconductor materials.
  • the 3D structure 132 is protruding to a distance D2' from the front surface and has a smallest distance D3' on the front surface.
  • the 3D structure 132 could equally well protrude from the back surface into the first region semiconductor material.
  • Examples of semiconductor devices corresponding to Figures 1 , 2 and 3 are presented in the United States (US) patents US 5,889,313 and US 6,204,087 and in the patent application PCT/FI2005/050148, which are all included here as references.
  • the 3D structures are 3D electrodes, i.e. they are always neutral inside.
  • Another example is presented in the patent application PCT/FI2005/050148 wherein the 3D structures are within tolerance fully depleted. The full depletion of a 3D structure can be achieved by connecting a suitable reverse bias between the first region semiconductor material and the second region semiconductor material through the voltage source 140 presented in Figure 1.
  • 3D semiconductor devices presented in Figures 1 , 2 and 3 are not limited to afore described examples, i.e. they can be used for instance in various different devices like in radiation detection devices, solar cells and in electronics including radio frequency (RF) and power electronics.
  • RF radio frequency
  • the manufacturing process of the 3D semiconductor device presented in Figures 1 , 2 and 3 involves at least one process step where semiconductor material is removed for instance by etching and at least one process step where the removed volume is filled with semiconductor material.
  • the latter process step is usually more critical since voids may be generated inside the semiconductor device, which act as dark current sources and as traps.
  • An appealing approach to avoid the void formation is to use liquid phase epitaxy (LPE) for the manufacturing of the 3D semiconductor device (presented in PCT/FI2005/050148).
  • LPE liquid phase epitaxy
  • the problem of LPE process for the manufacturing of the 3D semiconductor device is, however, that the liquid semiconductor material solidifies first at the front and back surfaces when ambient temperature is decreased. Thus a volume of liquid semiconductor material is formed inside solid semiconductor material.
  • the density of solid and liquid semiconductor material is different and thus when the liquid semiconductor material surrounded by the solid semiconductor transforms to solid semiconductor material the semiconductor device is prone to high stress.
  • the stress is typically relaxed by the formation of dislocations.
  • the dislocations act as dark current sources and as traps and are thus highly unwanted.
  • the stress is relaxed by device break up, i.e. the semiconductor device breaks into pieces.
  • planar devices such stress induced device brake up is not likely since stress is located only near the surface of the semiconductor substrate.
  • the 3D devices are, however, prone to device brake up since the magnitude of stress is much higher and it affects the whole semiconductor body.
  • the object of this invention is to provide a manufacturing method for the 3D semiconductor device that minimizes stress and void formation in the semiconductor device.
  • the object of the invention is achieved by manufacturing the semiconductor device according to the method of claim 1 , the method including a process step where at least one volume of material is removed from a semiconductor substrate that is formed of the first region semiconductor material or of the second region semiconductor material, a process step where the at least one volume of material that is removed from the substrate is filled with liquid semiconductor material that belongs to a group formed of the first and the second region semiconductor materials and that is not substrate semiconductor material, the liquid semiconductor material being referred to as the observed semiconductor material and having a lower melting temperature or the same melting temperature than the substrate semiconductor material; and a process step where the observed semiconductor material is solidified, the method further including observed semiconductor material having a temperature lower than its melting temperature on a former surface and observed semiconductor material having a temperature higher than its melting temperature on a latter surface during the solidification of the liquid observed semiconductor material that is situated in between the former surface and the latter surface, the former surface and the latter surface defined as being parallel to the first surface and to the second surface, and the locations of the former surface and the latter surface defined as to divide the local space into
  • the invention is based on the idea of having a first temperature on the former surface and a second temperature on the latter surface and of decreasing the second temperature or both the first and second temperature during the solidification process of the observed semiconductor material. Accordingly an essentially vertical temperature gradient exists between the former and the latter surfaces during the solidification of the observed semiconductor material. In this manner the solidification of the observed semiconductor material starts from the former surface and continues from the former surface towards the latter surface. If such an essentially vertical temperature gradient is not used during the solidification process liquid volumes of the observed semiconductor material surrounded by solid semiconductor material are left in between the former surface and the latter surface. The liquid semiconductor material has a different density than the solid semiconductor material and thus when the liquid observed semiconductor material volumes solidify the density of such volumes is changed creating stress in the semiconductor device.
  • liquid observed semiconductor material may flow through the latter surface to the volume in between the former surface and the latter surface if the density of the solid observed semiconductor material is higher than the density of the liquid observed semiconductor material.
  • liquid observed semiconductor material may flow from the volume in between the former surface and the latter surface through the latter surface if the density of the solid observed semiconductor material is lower than the density of the liquid observed semiconductor material.
  • Figure 1 illustrates an embodiment of the semiconductor device
  • Figure 2 illustrates a top view of the first surface 101 of the semiconductor device presented in Figure 1 ;
  • Figure 3 illustrates an alternative configuration of the semiconductor device
  • Figure 4 illustrates a semiconductor substrate
  • FIG. 5 illustrates an optional process step
  • Figure 6 illustrates a process step where holes are etched through the substrate
  • FIG. 7 illustrates an optional process step
  • FIG. 8 illustrates an optional process step
  • Figure 9 illustrates a process step where the holes are filled using liquid phase epitaxy
  • Figure 10 illustrates the semiconductor device during the solidification process
  • Figure 11 illustrates the semiconductor device after the both front and back surfaces have been polished
  • Figure 12 illustrates an optional process step
  • Figure 13 illustrates another process step where holes are etched to a semiconductor substrate
  • Figure 14 illustrates a process step where the holes are filled with liquid semiconductor material and where a vertical temperature gradient is applied to the structure;
  • Figure 15 illustrates a process step where the front surface of the semiconductor device is polished;
  • Figure 16 illustrates a semiconductor substrate
  • Figure 17 illustrates yet another process step where holes are etched to the semiconductor substrate
  • Figure 18 illustrates a process step where the holes are filled with liquid semiconductor material and where a temperature gradient is applied to the structure
  • Figure 19 illustrates a process step where the front surface of the semiconductor device is polished
  • Figure 20 illustrates a third alternative configuration of the semiconductor device.
  • the LPE manufacturing process of the semiconductor device presented in Figures 1 - 3 includes a process step where at least one volume of semiconductor material is removed from a semiconductor substrate using for instance a patterned etch and another process step where the removed volume of semiconductor material is at least partially filled with liquid semiconductor material.
  • the LPE process further includes an invented process step where an essentially vertical temperature gradient is used during the solidification process of the liquid semiconductor material.
  • the substrate corresponds either to the first region semiconductor material and the liquid semiconductor material to the second region semiconductor material or the substrate corresponds to the second region semiconductor material and the liquid semiconductor material to the first region semiconductor material.
  • the two different cases correspond to different embodiments of the invention.
  • the above described solidification process is explained more precisely in the next chapter where the semiconductor material experiencing the solidification process is referred to as the observed semiconductor material.
  • Figure 10 illustrates former surface 470 and latter surface 480 that are parallel to the front and back surfaces of the semiconductor device.
  • the locations of the former surface 470 and the latter surface 480 divide the local space into three different parts, where the part in between the former surface 470 and the latter surface 480 contains both first and second region semiconductor material and where the two other parts contain only either first or second region semiconductor material or neither first nor second region semiconductor material.
  • the invention is based on the idea of observed semiconductor material having a first temperature on the former surface 470 the first temperature being lower than the melting temperature of observed semiconductor material and observed semiconductor material having a second temperature on the latter surface 480 the second temperature being higher than the melting temperature of observed semiconductor material and of decreasing the second temperature or both the first and second temperature during the solidification process of the observed semiconductor material.
  • the temperature is decreased steadily. Accordingly an essentially vertical temperature gradient is applied to the volume situated in between the two surfaces 470 and 480 during the solidification process of the observed semiconductor material.
  • the essentially vertical temperature gradient applied during the solidification process can be defined with the help of the former surface 470 and the latter surface 480, i.e. the first temperature of the observed semiconductor material at the former surface 470 has to be below and the second temperature of the observed semiconductor material on the latter surface 480 has to be above the solidification temperature of the observed semiconductor material between the start and the end point of the solidification process of the liquid observed semiconductor material that exists in between the former surface 470 and the latter surface 480.
  • liquid observed semiconductor material inside the volume in between the former surface 470 and the latter surface 480 solidifies first at the former surface 470 and last at the latter surface 480.
  • liquid observed semiconductor material can flow through the latter surface 480 from outside to inside of the volume in between the former surface 470 and the latter surface 480, if the density of the liquid observed semiconductor material is less than the density of the solid observed semiconductor material.
  • liquid observed semiconductor material may flow through the latter surface 480 from inside to outside of the volume in between the former surface 470 and the latter surface 480, if the density of the liquid observed semiconductor material is higher than the density of the solid observed semiconductor material.
  • liquid volumes of the observed semiconductor material surrounded by solid semiconductor material are created inside the volume in between the former surface 470 and the latter surface 480. Since the density of the liquid semiconductor material is different than the solid semiconductor material and since no material can flow into or out of afore described liquid volumes, stress is created inside the semiconductor device after the solidification of these liquid volumes. The stress is relaxed by the formation of dislocations which act as dark current sources and as traps. In the worst case the stress relaxation breaks the semiconductor device to pieces.
  • Figure 4 illustrates a semiconductor substrate 400 formed of first region semiconductor material, having a front surface 401' and a back surface 402'.
  • Figure 5 is presented an optional process step where preferably epitaxial layers 403 and 404 of the second region semiconductor material having a doping concentration C are deposited on both surfaces of the substrate.
  • the new front surface 401" and back surface 402" of the semiconductor device are depicted in Figure 5.
  • Figure 6 at least one volume of material is removed from the semiconductor substrate. More precisely said holes 405 and 406 are made through the semiconductor substrate for instance by etching.
  • the holes 405 and 406 are manufactured for instance using a photo resist layer (not shown in the figure) which is exposed to ultraviolet/extreme ultraviolet light through a patterned mask. The non-exposed or the exposed area of the photo resist layer is next removed after which the holes are etched.
  • the applied etching process can be selected from a large variety of different etching processes.
  • Figure 7 illustrates an optional process step where preferably epitaxial layers 407 and 408 of the second region semiconductor material having a doping concentration C are deposited on the walls of the holes 405 and 406 using for instance atomic layer deposition (ALD). Before this optional process step the walls of the holes 405 and 406 may be wet etched.
  • ALD atomic layer deposition
  • Figure 8 illustrates an optional process step where the surfaces of the layers 407 and 408 are melted using e.g. hot inert gas 450 before the LPE process step. If the optional process steps depicted in Figures 5, 7 and 8 are used, the temperature of the first region semiconductor material should be slightly less than the melting point of the second region semiconductor material before the LPE process step takes place. If the afore said optional process steps are not used and if the first region semiconductor material is different and has a higher melting point than the second region semiconductor material, the temperature of the first region semiconductor material can be higher than the melting temperature of the second region semiconductor material.
  • Figure 9 illustrates the LPE process, where one surface of the first region semiconductor material is attached to a layer 409 of liquid second region semiconductor material having a doping concentration C.
  • the semiconductor substrate may be pressed against the liquid layer 409 in order to assist the filling of the holes 405 and 406.
  • the liquid second region semiconductor material may also be poured on top of the first region semiconductor material.
  • Figure 10 illustrates the solidification process of the volume in between the former surface 470 and the latter surface 480.
  • the solidification i.e. the cooling process can be actively controlled for instance by blowing inert gas 460 on the front side of the semiconductor device and/or by radiating the front side of the semiconductor device by an infrared radiator.
  • the former surface 470 is held at a temperature that is lower than the melting point of the second region semiconductor material and the temperature at the latter surface 480 is held at a temperature that is higher than the melting point of the second region semiconductor material during the solidification process of the second region semiconductor material (which is in this case observed semiconductor material) that is situated between the two surfaces 470 and 480.
  • the temperature at the former surface 470 and/or at the latter surface 480 can be reduced during the solidification process of the observed semiconductor material (which is in this case second region semiconductor material) that is situated between the two surfaces 470 and 480 in such a manner that in the end of the solidification process the temperature at the latter surface 480 reaches the solidification temperature of the observed semiconductor material.
  • the solidification of the observed semiconductor material which is in this case the second region semiconductor material starts at the former surface 470 and proceeds towards the latter 480 surface.
  • the temperature at the front surface 401"' and/or at back surface 402'" of the device can be actively controlled during the solidification process for instance by infrared radiators and/or by a flow of gas which is beneficially inert.
  • the new front surface 401' does not necessarily have to be continuous like in Figure 10 but it can be discontinuous like is the case in Figure 9.
  • the new back surface 402'" is also depicted in Figure 10.
  • Figure 11 presents the semiconductor device after the front and back surfaces 401'", 402'" have been polished so that only the regions 413 and 414 are left from the solid region 410.
  • Figure 12 illustrates an optional process step where a layer 415 of the first region semiconductor material is deposited on the polished back surface 402"". This completes the manufacturing process of the semiconductor device presented in Figures 1 and 2.
  • the oppositely doped 3D structure 312 presented in Figure 3 can be manufactured with a similar process than the 3D structure 111.
  • Figures 13 - 15 correspond to another embodiment of the invented manufacturing process.
  • at least one volume of material is removed from the semiconductor substrate 500. More precisely said: in Figure 13 holes 525, 526 are processed for instance by etching to a substrate 500 of first region semiconductor material having a front surface 521 and a back surface 502.
  • a layer 520 of liquid second region semiconductor material is deposited on the front side of the device forming a new front surface 521 ' of the device.
  • the temperature at the front surface 521' and/or at back surface 502 of the device can be actively controlled during the solidification process for instance by infrared radiators or by a flow of beneficially inert gas.
  • the temperatures on the front and possibly on the back surface can be constantly reduced in such a manner that the solidification of the second semiconductor material existing between the former surface 470 and the latter surface 480 starts at the former surface 470 and ends at the latter surface 480.
  • An essentially vertical temperature gradient is thus applied inside the volume in between the former surface 470 and the latter surface 480 during the solidification process of the liquid second region semiconductor material.
  • the front side 521' of the device is polished. The result is shown in Figure 15.
  • Figures 16 - 19 correspond to yet another embodiment of the invented manufacturing method of the 3D semiconductor device.
  • the starting point of the process is a substrate 600 of second region semiconductor material having a front surface 601 and a back surface 602.
  • Figure 17 at least one volume of material is removed from the back surface 602 of the device for instance by etching resulting in the areas 606, 607 and 608 depicted in Figure 17.
  • the remaining second region semiconductor material 611 , 612 on the back surface 602 form later on the 3D semiconductor structures.
  • liquid first region semiconductor material 610 is deposited on the back surface 602 of the device resulting in a new back surface 102 of the device.
  • the temperature at the front surface 601 and/or at the new back surface 102 of the device can be actively controlled during the solidification process for instance by infrared radiators or by a flow of inert gas.
  • the temperatures on the front and possibly on the back surface can be reduced in such a manner that the solidification of the first semiconductor material existing between the surfaces 470 and 480 starts at the surface 470 and ends at the surface 480.
  • an essentially vertical temperature gradient is applied inside the volume defined by the former surface 470 and the latter surface 480 during the solidification process of the liquid first region semiconductor material.
  • the front surface 601 of the device is polished resulting in a new front surface 101. The result is shown in Figure 19.
  • Figure 20 is shown a situation where a source of radiation 790 is relatively close to the semiconductor device which has 3D structures 711 , 712, 713 that protrude in different angles into the first region semiconductor material.
  • the holes corresponding to the 3D structures 711 , 712, 713 are manufactured in different directions in order to sharpen the image at the borders of the semiconductor device, i.e. the angles of the holes are defined by the location of the radiation source 790. Holes pointing in different directions can be manufactured for instance by laser drilling.
  • the presented manufacturing method of the 3D semiconductor devices according to the invention can be used for the manufacturing of for example of radiation detection devices, solar cells and electronics including radio frequency (RF) and power electronics.
  • RF radio frequency

Abstract

A method of manufacturing a 3D semiconductor that minimize stress and void formation. The process is characterized by the process step of : 1. remove a deep recess in a semiconductor substrate; 2. fill the recess with a liquid semiconductor material that has lower or the same melting temperature as the substrate material; 3. create a temperature gradient in the recess to control the solidification process; 4. decreasing the temperature and enabling a flow of the liquid semiconductor material.

Description

A method of manufacturing a 3D semiconductor that minimize stress and void formation
FIELD OFTHE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that includes three dimensional (3D) structures. The semiconductor device manufactured with the aforesaid method can be used for instance in radiation detection devices, solar cells and in electronics including radio frequency (RF) and power electronics.
BACKGROUND OF THE INVENTION
An embodiment of a semiconductor device comprising 3D structures is presented in Figures 1 and 2. The line 130 in Figure 2 presents the image plane of Figure 1. A semiconductor device comprising a 3D structure is hereinafter referred to as a semiconductor device including a first region 100 of semiconductor material having a first surface 101 , and at a defined first distance D1 from the first surface, a second surface 102, characterized by the semiconductor device including a second region 111 , 112 of semiconductor material protruding from the first surface to a second distance D2 (D2 < D1) into the first region 100 of semiconductor material, the second distance D2 being longer than the smallest distance D3 of the second region 111 , 112 of semiconductor material at the first surface. Typically the distance D2 is considerably bigger than D3, so advantageously inequalities can be listed in order of preference: D2 > 20*D3, D2 > 10xD3, D2 > 5χD3, D2 > 4*D3, D2 > 3><D3, D2 > 2χD3, D2 > D3, where the first one is the most beneficial inequality.
The second region 111 , 112 of semiconductor material is hereinafter referred to as the 3D structure, the first surface 101 is hereinafter referred to as the front surface, the second surface 102 is hereinafter referred to as the back surface, the distances D1 and D2 are hereinafter referred to extend into a vertical dimension, the distance D3 is hereinafter referred to be on a horizontal plane, and the horizontal plane is hereinafter referred to extend to two horizontal dimensions. The first and second region semiconductor materials are different semiconductor materials or they have a different doping concentration. Beneficially the first and second region semiconductor materials are lattice matched. The first and second region semiconductor materials can exhibit the same type of conductivity or they can be of opposite conductivity. The semiconductor device may also have 3D structures 111 , 132 of opposite conductivity types, a situation which is depicted in Figure 3. The 3D structures 111 , 132 can be formed of same or of different semiconductor materials. The 3D structure 132 is protruding to a distance D2' from the front surface and has a smallest distance D3' on the front surface. However, the 3D structure 132 could equally well protrude from the back surface into the first region semiconductor material. The 3D structure 132 in Figure 3 corresponds to a special case where D1 = D2'.
Examples of semiconductor devices corresponding to Figures 1 , 2 and 3 are presented in the United States (US) patents US 5,889,313 and US 6,204,087 and in the patent application PCT/FI2005/050148, which are all included here as references. In the patents US 5,889,313 and US 6,204,087 the 3D structures are 3D electrodes, i.e. they are always neutral inside. Another example is presented in the patent application PCT/FI2005/050148 wherein the 3D structures are within tolerance fully depleted. The full depletion of a 3D structure can be achieved by connecting a suitable reverse bias between the first region semiconductor material and the second region semiconductor material through the voltage source 140 presented in Figure 1. One can also incorporate both 3D structures presented in US 5,889,313 and US 6,204,087 and PCT/FI2005/050148 in the same device. The 3D semiconductor devices presented in Figures 1 , 2 and 3 are not limited to afore described examples, i.e. they can be used for instance in various different devices like in radiation detection devices, solar cells and in electronics including radio frequency (RF) and power electronics.
The manufacturing process of the 3D semiconductor device presented in Figures 1 , 2 and 3 involves at least one process step where semiconductor material is removed for instance by etching and at least one process step where the removed volume is filled with semiconductor material. The latter process step is usually more critical since voids may be generated inside the semiconductor device, which act as dark current sources and as traps. An appealing approach to avoid the void formation is to use liquid phase epitaxy (LPE) for the manufacturing of the 3D semiconductor device (presented in PCT/FI2005/050148). The problem of LPE process for the manufacturing of the 3D semiconductor device is, however, that the liquid semiconductor material solidifies first at the front and back surfaces when ambient temperature is decreased. Thus a volume of liquid semiconductor material is formed inside solid semiconductor material. The density of solid and liquid semiconductor material is different and thus when the liquid semiconductor material surrounded by the solid semiconductor transforms to solid semiconductor material the semiconductor device is prone to high stress. The stress is typically relaxed by the formation of dislocations. The dislocations act as dark current sources and as traps and are thus highly unwanted. In the worst case the stress is relaxed by device break up, i.e. the semiconductor device breaks into pieces. In planar devices such stress induced device brake up is not likely since stress is located only near the surface of the semiconductor substrate. The 3D devices are, however, prone to device brake up since the magnitude of stress is much higher and it affects the whole semiconductor body.
BRIEF DESCRIPTION OF THE INVENTION
The object of this invention is to provide a manufacturing method for the 3D semiconductor device that minimizes stress and void formation in the semiconductor device.
The object of the invention is achieved by manufacturing the semiconductor device according to the method of claim 1 , the method including a process step where at least one volume of material is removed from a semiconductor substrate that is formed of the first region semiconductor material or of the second region semiconductor material, a process step where the at least one volume of material that is removed from the substrate is filled with liquid semiconductor material that belongs to a group formed of the first and the second region semiconductor materials and that is not substrate semiconductor material, the liquid semiconductor material being referred to as the observed semiconductor material and having a lower melting temperature or the same melting temperature than the substrate semiconductor material; and a process step where the observed semiconductor material is solidified, the method further including observed semiconductor material having a temperature lower than its melting temperature on a former surface and observed semiconductor material having a temperature higher than its melting temperature on a latter surface during the solidification of the liquid observed semiconductor material that is situated in between the former surface and the latter surface, the former surface and the latter surface defined as being parallel to the first surface and to the second surface, and the locations of the former surface and the latter surface defined as to divide the local space into three different parts, where the part in between the former surface and the latter surface contains both first and second region semiconductor material and where the two other parts contain only either first or second region semiconductor material or neither first nor second region semiconductor material, decreasing the temperature on the latter surface or on both the latter surface and the former surface during the solidification of the liquid observed semiconductor material that is situated in between the former surface and the latter surface enabling the flow of liquid observed semiconductor material through the latter surface during the solidification of the liquid observed semiconductor material that is situated in between the former surface and the latter surface and resulting in reduced amount of stress in the semiconductor device.
The invention is based on the idea of having a first temperature on the former surface and a second temperature on the latter surface and of decreasing the second temperature or both the first and second temperature during the solidification process of the observed semiconductor material. Accordingly an essentially vertical temperature gradient exists between the former and the latter surfaces during the solidification of the observed semiconductor material. In this manner the solidification of the observed semiconductor material starts from the former surface and continues from the former surface towards the latter surface. If such an essentially vertical temperature gradient is not used during the solidification process liquid volumes of the observed semiconductor material surrounded by solid semiconductor material are left in between the former surface and the latter surface. The liquid semiconductor material has a different density than the solid semiconductor material and thus when the liquid observed semiconductor material volumes solidify the density of such volumes is changed creating stress in the semiconductor device. The stress relaxation creates dislocations which act as dark current sources and as traps. In the worst case the stress relaxation may break the semiconductor device into peaces. In the present invention liquid observed semiconductor material may flow through the latter surface to the volume in between the former surface and the latter surface if the density of the solid observed semiconductor material is higher than the density of the liquid observed semiconductor material. On the other hand, in the present invention liquid observed semiconductor material may flow from the volume in between the former surface and the latter surface through the latter surface if the density of the solid observed semiconductor material is lower than the density of the liquid observed semiconductor material.
BRIEF DESCRIPTION OF THE DRAVINGS
In the following the invention will be described in greater detail by means of some embodiments with reference to the attached drawings, in which
Figure 1 illustrates an embodiment of the semiconductor device;
Figure 2 illustrates a top view of the first surface 101 of the semiconductor device presented in Figure 1 ;
Figure 3 illustrates an alternative configuration of the semiconductor device;
Figure 4 illustrates a semiconductor substrate;
Figure 5 illustrates an optional process step;
Figure 6 illustrates a process step where holes are etched through the substrate;
Figure 7 illustrates an optional process step;
Figure 8 illustrates an optional process step;
Figure 9 illustrates a process step where the holes are filled using liquid phase epitaxy;
Figure 10 illustrates the semiconductor device during the solidification process;
Figure 11 illustrates the semiconductor device after the both front and back surfaces have been polished;
Figure 12 illustrates an optional process step;
Figure 13 illustrates another process step where holes are etched to a semiconductor substrate;
Figure 14 illustrates a process step where the holes are filled with liquid semiconductor material and where a vertical temperature gradient is applied to the structure; Figure 15 illustrates a process step where the front surface of the semiconductor device is polished;
Figure 16 illustrates a semiconductor substrate;
Figure 17 illustrates yet another process step where holes are etched to the semiconductor substrate;
Figure 18 illustrates a process step where the holes are filled with liquid semiconductor material and where a temperature gradient is applied to the structure;
Figure 19 illustrates a process step where the front surface of the semiconductor device is polished; and
Figure 20 illustrates a third alternative configuration of the semiconductor device.
DETAILED DESCRIPTION OF THE INVENTION
The LPE manufacturing process of the semiconductor device presented in Figures 1 - 3 includes a process step where at least one volume of semiconductor material is removed from a semiconductor substrate using for instance a patterned etch and another process step where the removed volume of semiconductor material is at least partially filled with liquid semiconductor material. The LPE process further includes an invented process step where an essentially vertical temperature gradient is used during the solidification process of the liquid semiconductor material. The substrate corresponds either to the first region semiconductor material and the liquid semiconductor material to the second region semiconductor material or the substrate corresponds to the second region semiconductor material and the liquid semiconductor material to the first region semiconductor material. The two different cases correspond to different embodiments of the invention. The above described solidification process is explained more precisely in the next chapter where the semiconductor material experiencing the solidification process is referred to as the observed semiconductor material.
Figure 10 illustrates former surface 470 and latter surface 480 that are parallel to the front and back surfaces of the semiconductor device. The locations of the former surface 470 and the latter surface 480 divide the local space into three different parts, where the part in between the former surface 470 and the latter surface 480 contains both first and second region semiconductor material and where the two other parts contain only either first or second region semiconductor material or neither first nor second region semiconductor material. The invention is based on the idea of observed semiconductor material having a first temperature on the former surface 470 the first temperature being lower than the melting temperature of observed semiconductor material and observed semiconductor material having a second temperature on the latter surface 480 the second temperature being higher than the melting temperature of observed semiconductor material and of decreasing the second temperature or both the first and second temperature during the solidification process of the observed semiconductor material. Advantageously the temperature is decreased steadily. Accordingly an essentially vertical temperature gradient is applied to the volume situated in between the two surfaces 470 and 480 during the solidification process of the observed semiconductor material. The essentially vertical temperature gradient applied during the solidification process can be defined with the help of the former surface 470 and the latter surface 480, i.e. the first temperature of the observed semiconductor material at the former surface 470 has to be below and the second temperature of the observed semiconductor material on the latter surface 480 has to be above the solidification temperature of the observed semiconductor material between the start and the end point of the solidification process of the liquid observed semiconductor material that exists in between the former surface 470 and the latter surface 480.
Due to the introduction of the essentially vertical temperature gradient into the LPE process the liquid observed semiconductor material inside the volume in between the former surface 470 and the latter surface 480 solidifies first at the former surface 470 and last at the latter surface 480. Thus liquid observed semiconductor material can flow through the latter surface 480 from outside to inside of the volume in between the former surface 470 and the latter surface 480, if the density of the liquid observed semiconductor material is less than the density of the solid observed semiconductor material. On the other hand, liquid observed semiconductor material may flow through the latter surface 480 from inside to outside of the volume in between the former surface 470 and the latter surface 480, if the density of the liquid observed semiconductor material is higher than the density of the solid observed semiconductor material. If the essentially vertical temperature gradient is not introduced during the solidification process of the liquid observed semiconductor material that exists inside the volume in between the former surface 470 and the latter surface 480, liquid volumes of the observed semiconductor material surrounded by solid semiconductor material are created inside the volume in between the former surface 470 and the latter surface 480. Since the density of the liquid semiconductor material is different than the solid semiconductor material and since no material can flow into or out of afore described liquid volumes, stress is created inside the semiconductor device after the solidification of these liquid volumes. The stress is relaxed by the formation of dislocations which act as dark current sources and as traps. In the worst case the stress relaxation breaks the semiconductor device to pieces.
The essentially vertical thermal gradient can be introduced in many different ways to a variety of different manufacturing processes of the 3D semiconductor device. One embodiment according to the invention is described in Figures 4 - 12. Figure 4 illustrates a semiconductor substrate 400 formed of first region semiconductor material, having a front surface 401' and a back surface 402'. In Figure 5 is presented an optional process step where preferably epitaxial layers 403 and 404 of the second region semiconductor material having a doping concentration C are deposited on both surfaces of the substrate. The new front surface 401" and back surface 402" of the semiconductor device are depicted in Figure 5. In Figure 6 at least one volume of material is removed from the semiconductor substrate. More precisely said holes 405 and 406 are made through the semiconductor substrate for instance by etching. The holes 405 and 406 are manufactured for instance using a photo resist layer (not shown in the figure) which is exposed to ultraviolet/extreme ultraviolet light through a patterned mask. The non-exposed or the exposed area of the photo resist layer is next removed after which the holes are etched. The applied etching process can be selected from a large variety of different etching processes. Figure 7 illustrates an optional process step where preferably epitaxial layers 407 and 408 of the second region semiconductor material having a doping concentration C are deposited on the walls of the holes 405 and 406 using for instance atomic layer deposition (ALD). Before this optional process step the walls of the holes 405 and 406 may be wet etched. Figure 8 illustrates an optional process step where the surfaces of the layers 407 and 408 are melted using e.g. hot inert gas 450 before the LPE process step. If the optional process steps depicted in Figures 5, 7 and 8 are used, the temperature of the first region semiconductor material should be slightly less than the melting point of the second region semiconductor material before the LPE process step takes place. If the afore said optional process steps are not used and if the first region semiconductor material is different and has a higher melting point than the second region semiconductor material, the temperature of the first region semiconductor material can be higher than the melting temperature of the second region semiconductor material.
Figure 9 illustrates the LPE process, where one surface of the first region semiconductor material is attached to a layer 409 of liquid second region semiconductor material having a doping concentration C. The semiconductor substrate may be pressed against the liquid layer 409 in order to assist the filling of the holes 405 and 406. The liquid second region semiconductor material may also be poured on top of the first region semiconductor material.
Figure 10 illustrates the solidification process of the volume in between the former surface 470 and the latter surface 480. The solidification, i.e. the cooling process can be actively controlled for instance by blowing inert gas 460 on the front side of the semiconductor device and/or by radiating the front side of the semiconductor device by an infrared radiator. The former surface 470 is held at a temperature that is lower than the melting point of the second region semiconductor material and the temperature at the latter surface 480 is held at a temperature that is higher than the melting point of the second region semiconductor material during the solidification process of the second region semiconductor material (which is in this case observed semiconductor material) that is situated between the two surfaces 470 and 480. The temperature at the former surface 470 and/or at the latter surface 480 can be reduced during the solidification process of the observed semiconductor material (which is in this case second region semiconductor material) that is situated between the two surfaces 470 and 480 in such a manner that in the end of the solidification process the temperature at the latter surface 480 reaches the solidification temperature of the observed semiconductor material. Thus the solidification of the observed semiconductor material which is in this case the second region semiconductor material starts at the former surface 470 and proceeds towards the latter 480 surface. The temperature at the front surface 401"' and/or at back surface 402'" of the device can be actively controlled during the solidification process for instance by infrared radiators and/or by a flow of gas which is beneficially inert.
When the solidification of the second region semiconductor material reaches the latter surface 480 the semiconductor device is pulled off from the liquid layer 409. As a result a solid region 410 of the second region semiconductor material is formed on the backside of the semiconductor device. One should note that the new front surface 401'" does not necessarily have to be continuous like in Figure 10 but it can be discontinuous like is the case in Figure 9. The new back surface 402'" is also depicted in Figure 10.
In another embodiment the places of the two surfaces 470, 480 presented in Figure 10 are interchanged. This corresponds to a situation where the second region semiconductor material solidifies first at the backside of the device and last at the front side of the device.
Figure 11 presents the semiconductor device after the front and back surfaces 401'", 402'" have been polished so that only the regions 413 and 414 are left from the solid region 410. Figure 12 illustrates an optional process step where a layer 415 of the first region semiconductor material is deposited on the polished back surface 402"". This completes the manufacturing process of the semiconductor device presented in Figures 1 and 2. The oppositely doped 3D structure 312 presented in Figure 3 can be manufactured with a similar process than the 3D structure 111.
Figures 13 - 15 correspond to another embodiment of the invented manufacturing process. In Figure 13 at least one volume of material is removed from the semiconductor substrate 500. More precisely said: in Figure 13 holes 525, 526 are processed for instance by etching to a substrate 500 of first region semiconductor material having a front surface 521 and a back surface 502. In Figure 14 a layer 520 of liquid second region semiconductor material is deposited on the front side of the device forming a new front surface 521 ' of the device. The temperature at the front surface 521' and/or at back surface 502 of the device can be actively controlled during the solidification process for instance by infrared radiators or by a flow of beneficially inert gas. The temperatures on the front and possibly on the back surface can be constantly reduced in such a manner that the solidification of the second semiconductor material existing between the former surface 470 and the latter surface 480 starts at the former surface 470 and ends at the latter surface 480. An essentially vertical temperature gradient is thus applied inside the volume in between the former surface 470 and the latter surface 480 during the solidification process of the liquid second region semiconductor material. After the solidification process is completed the front side 521' of the device is polished. The result is shown in Figure 15.
Figures 16 - 19 correspond to yet another embodiment of the invented manufacturing method of the 3D semiconductor device. The starting point of the process is a substrate 600 of second region semiconductor material having a front surface 601 and a back surface 602. In Figure 17 at least one volume of material is removed from the back surface 602 of the device for instance by etching resulting in the areas 606, 607 and 608 depicted in Figure 17. The remaining second region semiconductor material 611 , 612 on the back surface 602 form later on the 3D semiconductor structures. In Figure 18 liquid first region semiconductor material 610 is deposited on the back surface 602 of the device resulting in a new back surface 102 of the device. The temperature at the front surface 601 and/or at the new back surface 102 of the device can be actively controlled during the solidification process for instance by infrared radiators or by a flow of inert gas. The temperatures on the front and possibly on the back surface can be reduced in such a manner that the solidification of the first semiconductor material existing between the surfaces 470 and 480 starts at the surface 470 and ends at the surface 480. Thus an essentially vertical temperature gradient is applied inside the volume defined by the former surface 470 and the latter surface 480 during the solidification process of the liquid first region semiconductor material. After the solidification process is completed the front surface 601 of the device is polished resulting in a new front surface 101. The result is shown in Figure 19.
One should note that optional manufacturing steps presented in Figures 5, 7 and 8 may also be applied to the manufacturing process presented in Figures 13 - 15 and to the manufacturing process presented in Figures 16 - 19. The back surfaces 102 of the devices in Figures 19 and 15 can also be polished in order to reach the special case where D1 = D2. It is also important to note that in the embodiments corresponding to Figures 4 - 12 and to Figures 13 - 15 the melting temperature of the second region semiconductor material has to be lower than or equal to the melting temperature of the first region semiconductor material and that in the embodiment corresponding to Figures 15 - 19 the melting temperature of the first region semiconductor material has to be lower than or equal to the melting temperature of the second region semiconductor material.
In Figure 20 is shown a situation where a source of radiation 790 is relatively close to the semiconductor device which has 3D structures 711 , 712, 713 that protrude in different angles into the first region semiconductor material. The holes corresponding to the 3D structures 711 , 712, 713 are manufactured in different directions in order to sharpen the image at the borders of the semiconductor device, i.e. the angles of the holes are defined by the location of the radiation source 790. Holes pointing in different directions can be manufactured for instance by laser drilling.
It is important to note that the presented manufacturing method of the 3D semiconductor devices according to the invention can be used for the manufacturing of for example of radiation detection devices, solar cells and electronics including radio frequency (RF) and power electronics.

Claims

1. A method of manufacturing a semiconductor device, the semiconductor device including a first region (100) of semiconductor material having a first surface (101), and at a defined first distance D1 from the first surface, a second surface (102); and a second region (111 , 112) of semiconductor material protruding from the first surface (101) to a second distance D2 into the first region (100) of semiconductor material, the second distance D2 being longer than the smallest distance D3 of the second region of semiconductor material at the first surface (101) of the first region of semiconductor material, the method of manufacturing the semiconductor device including a process step where at least one volume of material is removed (405, 406,
525, 526, 605, 606, 607) from a semiconductor substrate (400, 500, 600) that is formed of the first region semiconductor material or of the second region semiconductor material, a process step where the at least one volume of material (405, 406, 525,
526, 605, 606, 607) that is removed from the substrate is filled with liquid semiconductor material that belongs to a group formed of the first and the second region semiconductor materials and that is not substrate semiconductor material, the liquid semiconductor material being referred to as the observed semiconductor material and having a lower melting temperature or the same melting temperature than the substrate semiconductor material; and a process step where the observed semiconductor material is solidified, c h a r a c t e r i z e d by the method including observed semiconductor material having a temperature lower than its melting temperature on a former surface (470) and observed semiconductor material having a temperature higher than its melting temperature on a latter surface (480) during the solidification of the liquid observed semiconductor material that is situated in between the former surface (470) and the latter surface (480), the former surface (470) and the latter surface (480) defined as being parallel to the first surface (101) and to the second surface (102), and the locations of the former surface (470) and the latter surface (480) defined as to divide the local space into three different parts, where the part in between the former surface (470) and the latter surface (480) contains both first and second region semiconductor material and where the two other parts contain only either first or second region semiconductor material or neither first nor second region semiconductor material decreasing the temperature on the latter surface (480) or on both the latter surface (480) and the former surface (470) during the solidification of the liquid observed semiconductor material that is situated in between the former surface (470) and the latter surface (480) enabling the flow of liquid observed semiconductor material through the latter surface (480) during the solidification of the liquid observed semiconductor material that is situated in between the former surface (470) and the latter surface (480) and resulting in reduced amount of stress in the semiconductor device.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor device fulfills the inequality D2 > 2*D3.
3. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device fulfills the inequality D2 > 5χD3.
4. A method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor device fulfills the inequality D2 > 10χD3.
5. A method of manufacturing a semiconductor device according to claim 1 , wherein the temperature on the latter surface (480) or both at the latter surface (480) and at the former surface (470) is decreased steadily during the solidification of the observed semiconductor material situated in between the former surface (470) and the latter surface (480).
6. A method of manufacturing a semiconductor device according to claim 1 and/or 5, wherein the temperature decrease on the latter surface (480) or both at the latter surface (480) and at the former surface (470) is resulted in by infrared radiators and/or by a flow of gas.
7. A method of manufacturing a semiconductor device according to any of claims 1 - 6, wherein the first and second region semiconductor materials of the semiconductor device are connected to a voltage source (140) and a suitable reverse bias is applied between the first and second region semiconductor materials in order within tolerance to fully deplete the second region.
8. A method of manufacturing a semiconductor device according to any of claims 1 - 6, wherein the second region of semiconductor material of the semiconductor device forms an electrode.
PCT/FI2006/000364 2005-11-10 2006-11-10 A method of manufacturing a 3d semiconductor that minimize stress and void formation WO2007054611A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981988A (en) * 1996-04-26 1999-11-09 The Regents Of The University Of California Three-dimensional charge coupled device
US6204087B1 (en) * 1997-02-07 2001-03-20 University Of Hawai'i Fabrication of three-dimensional architecture for solid state radiation detectors
US6231667B1 (en) * 1997-11-28 2001-05-15 Canon Kabushiki Kaisha Liquid phase growth method and liquid phase growth apparatus
US20040038527A1 (en) * 2002-04-09 2004-02-26 Geusic Joseph E. Method of forming spatial regions of a second material in a first material

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981988A (en) * 1996-04-26 1999-11-09 The Regents Of The University Of California Three-dimensional charge coupled device
US6204087B1 (en) * 1997-02-07 2001-03-20 University Of Hawai'i Fabrication of three-dimensional architecture for solid state radiation detectors
US6231667B1 (en) * 1997-11-28 2001-05-15 Canon Kabushiki Kaisha Liquid phase growth method and liquid phase growth apparatus
US20040038527A1 (en) * 2002-04-09 2004-02-26 Geusic Joseph E. Method of forming spatial regions of a second material in a first material

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