WO2007052873A1

WO2007052873A1 - Image sensor with high frame

Info

Publication number: WO2007052873A1
Application number: PCT/KR2006/001332
Authority: WO
Inventors: Hoon Kim; Kwang Sue Park
Original assignee: Planet82 Inc.
Priority date: 2005-11-07
Filing date: 2006-04-12
Publication date: 2007-05-10
Also published as: KR20070049016A; KR100748426B1

Abstract

Disclosed is an image sensor with high speed frame, more specifically which can carry out an imaging process at high speed even in low illumination conditions, by conducting a sampling process of data signals outputted from a unit pixel, i.e. the picture element part, only once. According to the present invention, an image sensor comprised of a sample and hold amplifier (SHA), PGA and ADC, is characterized by comprising: a picture element part; a switch which is operated by a data sampling signal for sampling data voltage after completion of a voltage drop of image data signals applied from the picture element part; a capacitor for storing the data voltage applied from the switch; and a comparator for comparing the data voltage stored in said capacitor with a reference voltage of a lamp voltage applied from outside.

Description

Description IMAGE SENSOR WITH HIGH FRAME

Technical Field

[1] The present invention relates to an image sensor with high speed frame, more specifically to an image sensor which can carry out an imaging process at high speed even in low illumination conditions, by conducting a sampling process of data signals outputted from a unit pixel, i.e. the picture element part, only once. Background Art

[2] An image sensor is a device which captures images by utilizing the characteristics of a semiconductor, which reacts on external energy such as light energy. Light being generated from an object present in the nature has a characteristic inherent value in properties such as wavelength. A pixel of an image sensor detects the light generated from each object and converts it into a certain electric value.

[3] That means, the pixel of an image sensor responds to the light energy generated from an object, and then generates an electric value corresponding to the wavelength of the light received. Among those, CCD (Charge Coupled Device) is a device in which MOS capacitors are disposed very near to each other, and an electric charge carrier is stored in the capacitor and transferred. While CMOS (Complementary Metal Oxide Semiconductor) image sensor is a device which has a pixel array formed by utilizing CMOS integrated circuit fabrication technique and employs a switching mode for detecting output of the pixel array one after another. CMOS image sensors have an important advantage of lower power consumption, thereby being very usefully applied to a personal mobile system such as a mobile phone.

[4] Fig.l represents a conventional 3-transistor CMOS active pixel, which illustrates the cross-section of a photodiode comprising circuits for peripheral components. Fig. 2 is an equivalent circuit diagram of the conventional 3-transistor CMOS active pixel represented in Fig. 1.

[5] Referring to Figs. 1 and 2, in conventional 3-transistor CMOS active pixels, an N+ type impurity region (11) and an N+ type floating diffusion region (13) which constitute a junction of a photodiode at one side, contact to each other. Thus, the capacitance component of a photodiode is substantially the sum of the capacitor components formed by the N+ type impurity region (11) and the N+ type floating diffusion region (13).

[6] Accordingly, an image sensor where a conventional 3-transistor CMOS active pixel is applied has a problem of low sensitivity. For making up such problem of a 3-transistor CMOS active pixel, 4-transistor CMOS active pixel has been suggested. [7] Fig. 3 represents a conventional 4-transistor CMOS active pixel, which illustrates the cross-section of a photodiode comprising circuits for peripheral components. Fig. 4 is an equivalent circuit diagram of the conventional 4-transistor CMOS active pixel represented in Fig. 3.

[8] Referring to Figs. 3 and 4, in conventional 4-transistor CMOS active pixels, a transfer transistor (25) which is controlled by a transfer control signal (Tx) is used for removing noises generated from a 3-transistor CMOS active pixel. The N+ type impurity region (21) and the N+ type floating diffusion region (23) which constitute a junction of a photodiode on one side are separated from each other.

[9] By doing so, the sensitivity of an image sensor and the quality of the image can be improved in conventional 4-transistor CMOS active pixels. However, the 4-transistor CMOS active pixel also has a problem of having a reduced light receiving area, owing to the addition of a transfer transistor (25).

[10] In summary, a conventional 3-transistor CMOS active pixel has a problem of low sensitivity, and a conventional 4-transistor CMOS active pixel also has a problem of a reduced light receiving area.

[11] Fig. 5 represents a circuit diagram connected with unit pixels represented in Figs. 1 and 3. The picture element part (30) used herein refers to one column comprised of unit pixels. The picture element part (30) is provided as many as the number of the columns, and the number of the unit pixels in the picture element is provided as many as the number of the rows.

[12] Those generally used expressions '640x480 VGA', '1024x768 XGA' and

'1280x1024 SXGA', respectively, refer to the image resolution of '640 columns x 480 rows' '1024 columns x 768 rows' and '1280 columns x 1024 rows'. Meanwhile, each number of columns and rows practically used in the processes is more than the numbers above represented. Fig. 6 represents the signals applied to the unit pixels of Figs. 1 and 3.

[13] The circuit and the signal processing illustrated in Figs. 5 and 6 are as follows.

When a select signal is applied to a row consisting of pluralities of unit pixels, a captured image data signal during the row enable section (R_en) in the pluralities of unit pixels is applied from the common junctional) of a column to CDS (correlated double sampling) (36). Image data signals include data signals corresponding to various levels of illumination depending on the surrounding environment, from a high illumination signal which is the data signal of bright light to a low illumination signal which is the data signal of dimmed light.

[14] These data signals having various levels of illumination drop the reference voltage applied to a circuit comprising CDS (36) according to each level. It means that the low illumination data signal drops the reference voltage relatively little, but the high il- lumination data signal drops the reference voltage relatively large.

[15] Fig. 7 represents the voltage drop of a data signal according to each illumination level. Three levels are disclosed in Fig. 7, for the sake of convenience; however data signals at more various levels may be present in practical.

[16] In Fig. 7, the 'A' and 'C sections are the stable sections where the fluctuations in signal voltage are not present, and 'B' section is the section where a drop in signal voltage occurs. Firstly, while a row enable signal (R_en) is disabled, a reset sampling operation signal (SR) is applied to a switch b (32b) of a CDS (36) during the reset sampling section (A) so that the reset voltage is stored in a capacitor b (33b).

[17] After that, upon the application of the row enable (R_en) signal among the signals of Fig. 6 to each unit pixel in a row so that an image data signal is applied to a common junction (31) of a column, then the switch a (32a) of CDS (36) processes data sampling (SD) during C section by the data sampling operation signal applied from outside, stores the resulted value in a capacitor a (33a) and applies a data signal voltage to MUX (35) via a comparator a (34a).

[18] Completing the data sampling (SD), reset (RST) signal is applied. Then, upon the completion of row enabling, a switch b (32b) of CDS (36) for processing the next image process data processes reset sampling (SR) during A section by a reset sampling operation signal applied from outside so as to store the reset voltage to a capacitor b (33b) and to apply a signal to MUX (35) via a comparator b (34b).

[19] Upon running of such series of signals (R_en, SD, RST, SR) for one cycle, image data stored in the unit pixel are obtained, and then the obtained image data are outputted through a sample and hold amplifier (SHA) (37), a programmable gain amplifier (PGA) (38), an analogue-digital converter (ADC) (39) or the like.

[20] It means that the image processing data values corresponding to each level are determined by the level of differences in potential of the image stored in each capacitor during the reset sampling section 'A' and the data sampling section 'C. Therefore, in the case of high illumination, the image processing data value is relatively large, while in the case of low illumination, the image processing data value is relatively small.

[21] However, the image displayed through the image data signals outputted from the processing procedure disclosed in Figs. 5 to 7 has significant differences from the real image which is directly seen by the human eye. For instance, when strong source of light such as the sun is inputted, errors or differences in the image occur such as false representation where the part around the sun on the screen display is blackened. Most of such distortions or false representations of an image are generally occurred by excessively large data values in the case of high illumination.

[22] Such conventional technique repeats a sampling procedure twice, which makes a delay in signal processing. Accordingly, there has been a problem of fabricating an image sensor with high speed frames. [23]

Disclosure of Invention

Technical Solution

[24] Accordingly, the present invention is to solve the problems and setbacks of the conventional techniques as above. The object of the present invention is to provide an image sensor which can eliminate analog CDS blocks so that a sampling process can be done at once, and can store the image data values in each column so that it is possible to process data signals at high speed even in low illumination condition.

[25] The object of the present invention is achieved by an image sensor with high speed frame, which comprises a sample and hold amplifier (SHA), PGA and ADC, and is characterized by comprising: a picture element part; a switch which is operated by a data sampling signal for sampling data voltage after completion of a voltage drop of image data signals applied from the picture element part; a capacitor for storing the data voltage applied from the switch; and a comparator for comparing the data voltage stored in said capacitor with a reference voltage of a lamp voltage applied from outside.

[26] It is to be understood that the terms and words used in the specification and claims of the present invention should not be construed to have a limitative meaning provided by conventional definitions or dictionary, but should be understood to have a meaning and a concept corresponding to the technical spirit of the present invention, based on the principle that an inventor may appropriately define the concept and meaning of terms in order to explain the invention to its best.

[27] Accordingly, it is to be understood that both the following embodiments disclosed in the present specification and the constructions disclosed in the attached drawings are merely one of preferred examples of the present invention, and are not be construed to comprehensively represent the technical spirit of the present invention. Therefore, it should be further understood that the various alternatives and modifications which can substitute the present invention at the time of filing the present application may be possible.

[28]

Brief Description of the Drawings

[29] Fig. 1 is a view illustrating a conventional 3-transistor CMOS active pixel.

[30] Fig. 2 is an equivalent circuit diagram illustrating a conventional 3-transistor

CMOS active pixel.

[31] Fig. 3 is a view illustrating a conventional 4-transistor CMOS active pixel.

[32] Fig. 4 is an equivalent circuit diagram illustrating a conventional 4-transistor CMOS active pixel.

[33] Fig. 5 is a circuit diagram connected with the unit pixels represented in Figs. 1 and

3.

[34] Figs. 8 and 9 are views illustrating an image sensor with high speed frame according to the present invention.

[35] Fig. 10 is a view representing the current changes in PMOS according to changes in light intensity, in CMOS unit pixel of the present invention.

[36] Fig. 11 represents a voltage drop in data signals, depending on each level of illumination according to the present invention.

[37] <Numerals used in main parts of drawings>

[38] 400 : PMOS 405 : NMOS

[39] 410 : junction 415 : capacitor

[40] 420 : comparator 425 : MUX

[41] 430 : SHA 435 : PGA

[42] 440 : ADC 445 : switch

[43]

Mode for the Invention

[44] Hereinafter, the preferred examples of the present invention are described in detail, with referring to the drawings attached hereto.

[45] Figs. 8 and 9 are views illustrating an image sensor with high speed frame according to the present invention. Referring to Figs. 8 and 9, the unit pixel is formed by using only MOS process which is used in general semiconductor fabrication processes. The unit pixel structure is a 2-transistor structure comprised of 1 PMOS (400) and 1 NMOS (405) wherein the PMOS (400) utilizing a photoelectric conversion mode upon entrance of light, forms a light receiving area, and the NMOS (405) plays a role of a switch by being connected to the PMOS.

[46] By embodying a unit pixel structure comprising 2 transistors (400,405) unlike the conventional unit pixel structure comprised of one photodiode and 3 transistors, or one photodiode and 4 transistors, the pitch size of the unit pixel can be reduced. Further, since there is no control signal such as conventional reset signals, a metal line in the layout of a pixel can also be reduced. Therefore, the unit pixel structure in the present invention can be simplified.

[47] The principle of an operation process of the present invention is explained as follows.

[48] Upon the application of voltage to the source of the PMOS formed on the same substrate where the NMOS is formed, the N- well of the PMOS forms a depletion region which is in electrically neutral state. Later, when photons enter into the N- well that is a depletion region, upon receiving light from the PMOS that is a light receiving part, EHP (electron hole pair) is formed, which derives the formation of a P channel on the lower surface of the gate in the PMOS element. To the select gate formed on the NMOS which is connected to the PMOS, voltage is applied, and then N channel is formed between the source and drain formed on the NMOS so that it can receive the signal charges formed on the PMOS and send out an output signal.

[49] In a conventional photodiode, an electric current starts to flow when the intensity of light is over a certain critical point, and the current linearly increases with increase in the intensity of light. However, the pixel of an image sensor comprised of PMOS according to the present invention is a structure where an electric current starts to flow right after the entrance of light, thereby having no dark current. As represented in A region, it can be seen that the slope of the changes in electric current relative to small changes in light is very rapid and, while the slope of the changes in electric current relative to the changes in light is relatively easy in B region. (See Fig. 10 which illustrates the current changes in PMOS according to changes in light intensity, in CMOS unit pixel of the present invention)

[50] Since the present invention does not have a control signal such as a conventional reset signal, a metal line in the layout of a pixel can become reduced, and conventional CDS (Correlated Double sampling) can be eliminated which allows only single time of sampling. Therefore, it makes possible to further reduce a pitch size as compared to that of a conventional unit picture element. The PMOS light receiving element of the present invention in which one photon generates an amplified photocurrent, unlike a conventional CMOS image sensor wherein one photon generates one electron-hole pair. Therefore, the current gain of a photocurrent reaches to 100-1000, and then it is possible to embody an image under low illumination condition where a small amount of light is entered. Further, the present invention makes possible to reduce the charge storage time 100-1000 times relative to the conventional image sensors such that several tens of clocks of delay become enough for the charge storage time, unlike in conventional image sensors which require 1 frame or 1 line of delay, therefore it makes possible to eliminate integration time and thus to achieve a high speed moving picture.

[51] Additionally, since the unit pixel of a CMOS image sensor according to the present invention is formed by a general MOS process, it eliminates the conventional use of an exclusive process for a CMOS image sensor. According to the present invention, it is possible to receive light from PMOS, with almost no integration time, and to output signals through NMOS, therefore a dark current in the sensor due to long integration, except a dark current caused by a leakage current of MOS for a switch, can be minimized.

[52] Accordingly, the present invention does not require a process for growing an epitaxial layer on the surface of a light receiving area for preventing a dark current in conventional CMOS image sensor fabricating process. Further, the present invention does not require a conventional process for forming a micro-lens on the upper part of a unit picture element for collecting light to the light receiving area of a unit picture element, since the PMOS light receiving element of the present invention generates amplified photocurrent per one photon. By eliminating said conventional processes, the present invention can have a cost-saving effect.

[53] The processing illustrated in Figs. 8 and 12 are explained as follows. When a select signal is applied to a row consisting of pluralities of unit pixels, a captured image data signal during the row enable section (R_en) in the pluralities of unit pixels is applied from the common junction (410) of a column. Image data signals include data signals corresponding to various levels of illumination depending on the surrounding environment, from a high illumination signal which is the data signal of bright light to a low illumination signal which is the data signal of dimmed light.

[54] These data signals according to various levels of illumination drop the voltage of the image data applied according to each level. It means that the low illumination data signal drops the image data voltage relatively little, but the high illumination data signal drops the image data voltage relatively large. Therefore, the present invention makes possible to carry out a sampling procedure just at once, owing to the absence of CDS, unlike in the prior arts. As being illustrated in Fig. 9, the data values in each column are connected in parallel so as to store the data values.

[55] Fig. 12 represents the voltage drop of a data signal according to the illumination level of the present invention. Three levels are disclosed in Fig. 12, for the sake of convenience; however data signals at more various levels may be present in practical.

[56] In Fig. 12, the A and C sections are the stable sections where the fluctuations in signal are not present, and B section is the section where a drop in signal voltage occurs. As represented in Fig. 10, upon the application of a row enable signal (R_en) to each unit pixel of each row so that an image data signal is applied to a common junction (410) of a column, the applied signals are stored to a capacitor (415) without reset sampling, and then are applied to MUX (425) via a comparator (420). The data sampling signal is enabled during one row enable signal section applied to the picture element part. Upon running of such series of signals (R_en, SD) for one cycle, image data stored in the unit pixel are obtained, and a certain voltage corresponding to a reset sampling is internally generated. The internally generated voltage, which corresponds to a reset sampling is applied to one side of a sample and hold amplifier (SHA) (430) and data is applied to the other side of the SHA so as to carry out signal processing. Later, image data are outputted through a programmable gain amplifier (PGA) (435), an analog-digital converter (ADC) (440) or the like. [57] It utilizes a simultaneous analog-digital conversion mode in each column, and thus signals can be stored in each column. For example, in case of 8 bit, which needs 128 elk , merely 135 elk can achieve IH, which means the holding time between rows, wherein signal is sent out during the time taken for moving to the next row. Therefore, it is possible to process image more rapidly, comparing to the conventional standard 858 elk. When it is 27MHz, the frame rate can be improved from about 30 frames to about 180 frames. (256 elk can be reduced to 128 elk by operating the counter of column parallel ADC at 27MHz)

[58] The image data signal applied from the picture element part which comprises unit pixels is operated by the data sampling signal which is for sampling data voltage, through a switch (445). Then the data voltage applied from the switch (445) is stored in a capacitor (415), and the data voltage is compared at a comparator (410) with a reference voltage applied from a lamp signal so as to output image data through a sample and hold amplifier (SHA) (430), PGA (435), ADC (440) and the like.

[59] The present invention has been illustrated with referring to preferred examples thereof, however it is not limited to the said examples. It will be obvious for persons skilled in the art to which the present invention belongs that various modifications or variations can be made to the present invention without departing from the scope of the present invention. Industrial Applicability

[60] According to the image sensor having high speed frame of the present invention, it is possible to eliminate analog CDS blocks so that a sampling process can be conducted only one time. It is possible to reduce the pitch size of a pixel itself and the area for embodying the same by storing image data values at each column. Further, since it does not require integration time, it is possible to embody a high speed moving picture at low illumination.

[61]

[62]

Claims

[1] An image sensor with high speed frame, which comprises a sample and hold amplifier (SHA), PGA and ADC, and is characterized by comprising: a picture element part; a switch which is operated by a data sampling signal for sampling data voltage after completion of a voltage drop of image data signals applied from the picture element part; a capacitor for storing the data voltage applied from the switch; and a comparator for comparing the data voltage stored in said capacitor with a reference voltage of a lamp voltage applied from outside.

[2] The image sensor with high speed frame according to claim 1, wherein the picture element is comprised of a combination of unit pixels comprising one NMOS and one PMOS light receiving element.

[3] The image sensor with high speed frame according to claim 1, wherein the data sampling signal is enabled during one row enable signal section applied from the picture element part.