WO2007019493A3 - Process for making single crystalline flakes using deep etching - Google Patents

Process for making single crystalline flakes using deep etching Download PDF

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Publication number
WO2007019493A3
WO2007019493A3 PCT/US2006/030870 US2006030870W WO2007019493A3 WO 2007019493 A3 WO2007019493 A3 WO 2007019493A3 US 2006030870 W US2006030870 W US 2006030870W WO 2007019493 A3 WO2007019493 A3 WO 2007019493A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor material
single crystalline
thin strips
deep etching
making single
Prior art date
Application number
PCT/US2006/030870
Other languages
French (fr)
Other versions
WO2007019493A2 (en
Inventor
Sadeg M Faris
Original Assignee
Reveo Inc
Sadeg M Faris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Reveo Inc, Sadeg M Faris filed Critical Reveo Inc
Publication of WO2007019493A2 publication Critical patent/WO2007019493A2/en
Publication of WO2007019493A3 publication Critical patent/WO2007019493A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/0019—Flexible or deformable structures not provided for in groups B81C1/00142 - B81C1/00182
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02027—Setting crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02035—Shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
    • B81B2207/015—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS the micromechanical device and the control or processing electronics being integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A method of forming a plurality of thin strips of semiconductor material includes cutting a wafer having a thickness K from a semiconductor boule. The wafer is masked to form a plurality mask lines of a thickness associated with the desired thickness of the thin strips of semiconductor material. The wafer is etched to form plateaus of semiconductor material beneath the mask line having heights associated with the desired width of the thin strips of semiconductor material. The plateaus are removed thereby providing thin strips of semiconductor material.
PCT/US2006/030870 2005-08-05 2006-08-07 Process for making single crystalline flakes using deep etching WO2007019493A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70592505P 2005-08-05 2005-08-05
US60/705,925 2005-08-05

Publications (2)

Publication Number Publication Date
WO2007019493A2 WO2007019493A2 (en) 2007-02-15
WO2007019493A3 true WO2007019493A3 (en) 2008-12-31

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PCT/US2006/030849 WO2007019487A2 (en) 2005-08-05 2006-08-07 Method and system for fabricating thin devices
PCT/US2006/030870 WO2007019493A2 (en) 2005-08-05 2006-08-07 Process for making single crystalline flakes using deep etching

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PCT/US2006/030849 WO2007019487A2 (en) 2005-08-05 2006-08-07 Method and system for fabricating thin devices

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7605054B2 (en) 2007-04-18 2009-10-20 S.O.I.Tec Silicon On Insulator Technologies Method of forming a device wafer with recyclable support
US8258624B2 (en) 2007-08-10 2012-09-04 Intel Mobile Communications GmbH Method for fabricating a semiconductor and semiconductor package
WO2010062659A1 (en) * 2008-10-28 2010-06-03 Athenaeum, Llc Epitaxial film assembly system & method
US8598016B2 (en) * 2011-06-15 2013-12-03 Applied Materials, Inc. In-situ deposited mask layer for device singulation by laser scribing and plasma etch
FR2977075A1 (en) * 2011-06-23 2012-12-28 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR SUBSTRATE
US9452495B1 (en) * 2011-07-08 2016-09-27 Sixpoint Materials, Inc. Laser slicer of crystal ingots and a method of slicing gallium nitride ingots using a laser slicer
US9799792B2 (en) 2015-01-14 2017-10-24 International Business Machines Corporation Substrate-free thin-film flexible photovoltaic device and fabrication method
US9496165B1 (en) 2015-07-09 2016-11-15 International Business Machines Corporation Method of forming a flexible semiconductor layer and devices on a flexible carrier
KR101723789B1 (en) * 2016-06-03 2017-04-06 서울시립대학교 산학협력단 Method for analyzing line edge roughness for three-dimentional semiconductor device
CN109273607A (en) * 2018-11-05 2019-01-25 武汉理工大学 A method of flexible large area perovskite solar cell module is prepared using femtosecond laser
CN109273608B (en) * 2018-11-05 2021-01-19 武汉理工大学 Semitransparent perovskite solar cell and preparation method thereof
CN111736259A (en) * 2020-07-24 2020-10-02 歌尔股份有限公司 Waveguide lens module, manufacturing method thereof and AR equipment
CN117253791A (en) * 2023-11-20 2023-12-19 物元半导体技术(青岛)有限公司 IGBT device manufacturing method and IGBT device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214703B1 (en) * 1999-04-15 2001-04-10 Taiwan Semiconductor Manufacturing Company Method to increase wafer utility by implementing deep trench in scribe line
US6387773B1 (en) * 1999-06-30 2002-05-14 Infineon Technologies Ag Method for fabricating trenches having hallows along the trenches side wall for storage capacitors of DRAM semiconductor memories
US20030152756A1 (en) * 2001-12-18 2003-08-14 Yasufumi Yamada Method and apparatus for processing three-dimensional structure, method for producing three-dimensional shape product and three-dimensional structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4848931A (en) * 1985-11-20 1989-07-18 Toyo Aluminium Kabushiki Kaisha Packaging sheet and containers and pouches using the sheet
JPS63155731A (en) * 1986-12-19 1988-06-28 Agency Of Ind Science & Technol Semiconductor device
US4900372A (en) * 1987-11-13 1990-02-13 Kopin Corporation III-V on Si heterostructure using a thermal strain layer
US5248621A (en) * 1990-10-23 1993-09-28 Canon Kabushiki Kaisha Method for producing solar cell devices of crystalline material
JP2001085715A (en) * 1999-09-09 2001-03-30 Canon Inc Isolation method of semiconductor layer and manufacturing method of solar battery
JP4708577B2 (en) * 2001-01-31 2011-06-22 キヤノン株式会社 Method for manufacturing thin film semiconductor device
FR2821697B1 (en) * 2001-03-02 2004-06-25 Commissariat Energie Atomique METHOD OF MANUFACTURING THIN LAYERS ON A SPECIFIC CARRIER AND AN APPLICATION
US7220656B2 (en) * 2003-04-29 2007-05-22 Micron Technology, Inc. Strained semiconductor by wafer bonding with misorientation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214703B1 (en) * 1999-04-15 2001-04-10 Taiwan Semiconductor Manufacturing Company Method to increase wafer utility by implementing deep trench in scribe line
US6387773B1 (en) * 1999-06-30 2002-05-14 Infineon Technologies Ag Method for fabricating trenches having hallows along the trenches side wall for storage capacitors of DRAM semiconductor memories
US20030152756A1 (en) * 2001-12-18 2003-08-14 Yasufumi Yamada Method and apparatus for processing three-dimensional structure, method for producing three-dimensional shape product and three-dimensional structure

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Publication number Publication date
WO2007019487A2 (en) 2007-02-15
WO2007019493A2 (en) 2007-02-15
WO2007019487A3 (en) 2007-12-21

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