WO2007013736A1 - Multimedia platform - Google Patents

Multimedia platform Download PDF

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Publication number
WO2007013736A1
WO2007013736A1 PCT/KR2006/002277 KR2006002277W WO2007013736A1 WO 2007013736 A1 WO2007013736 A1 WO 2007013736A1 KR 2006002277 W KR2006002277 W KR 2006002277W WO 2007013736 A1 WO2007013736 A1 WO 2007013736A1
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WO
WIPO (PCT)
Prior art keywords
multimedia
processor
route
memory
main processor
Prior art date
Application number
PCT/KR2006/002277
Other languages
French (fr)
Inventor
You-Hoan Jung
Original Assignee
Mtekvision Co., Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mtekvision Co., Ltd filed Critical Mtekvision Co., Ltd
Publication of WO2007013736A1 publication Critical patent/WO2007013736A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Definitions

  • the present invention is related to sharing of a memory (storage device),
  • processors in an electrical/electronic device digital processing device
  • portable terminals refer to any portable terminals.
  • Portable terminals include
  • PDA personal digital assistants
  • PMP multimedia players
  • the mobile communication terminal is essentially
  • communication terminals have functions, such as camera and multimedia data playback,
  • Portable terminals comprise a plurality of processors to perform multiple
  • a portable terminal has an application processor for performing
  • portable terminals further comprise one or more memories to be
  • the memories linked to the main processor include a NAND flash memory and a
  • buffer memory The NAND flash memory and buffer memory are integrated to one chip
  • connection structure
  • FIG. 1 is a diagram showing the connection structure between processors of the
  • FIG. 1 the number of application processors can vary as
  • a portable terminal 100 of the prior art comprises a main
  • processor 110 a memory chip 115, a multimedia platform 120, a sound output unit 125,
  • the main processor 110 memory chip 115
  • the main processor 110 comprises a boot sequencer 140, a NAND interface 142,
  • a cache memory 146 a cache memory 146, a processor core 148, an SD interface 150 and a host interface 152.
  • the boot sequencer 140 accesses a NAND flash memory 162 through the
  • NAND interface 142 and delivers the read boot data to the processor core 148 to have the
  • processor core 148 perform the booting.
  • the processor core 148 performs a logic and/or operation pre-designated in the
  • the process core 148 can comprise the cache memory 146 as a
  • main processor core 148 included in the main processor 110 will be called the "main processor core.”
  • the NAND interface 142 interfaces with the NAND flash memory 162 included
  • the SD interface 150 interfaces with a buffer memory 164
  • the host interface 152 interfaces with the multimedia
  • the memory chip 115 comprises the NAND flash memory 162 and the buffer
  • the multimedia platform 120 comprises a multimedia processor 170 and a
  • buffer memory 178 in one chip.
  • the multimedia processor 170 comprises a host interface 172 interfacing with
  • main processor 110 a processor core 174 performing a logic and/or operation
  • processor 170 will be called the "multimedia processor core.”
  • connection structure between processors shown in FIG. 1 is based on the
  • FIG. 1 the booting sequence of the main processor 110 and the multimedia processor 120
  • the booting sequence of the main processor 110 is as follows:
  • the boot sequencer 140 accesses
  • the NAND flash memory 162 in the memory chip 115 through the NAND interface 142 is the NAND flash memory 162 in the memory chip 115 through the NAND interface 142.
  • the boot sequencer 140 reads boot data stored in an area of the NAND flash
  • the boot sequencer 140 then delivers the boot data, stored in the cache memory
  • the main processor core After booting through the use of the delivered boot data, the main processor core
  • flash memory 162 through the NAND interface 142 and stores the data in the buffer memory 164 in the memory chip 115 accessed through the SD interface 150.
  • operating data stored in the NAND flash memory 162 is stored in the buffer memory 164
  • the booting sequence of the multimedia processor 170 is as follows:
  • the main processor core 148 reads the boot data stored in the NAND flash
  • the boot data can be what the main processor core 148 stored in the
  • the main processor core 148 delivers the read boot data to the multimedia
  • the boot data can be delivered
  • the multimedia processor core 174 performs the booting by use of the
  • main processor 110 reads the needed data from the NAND flash memory 162 (or from the
  • multimedia processor core 174 through the host interface 152 and 172.
  • NAND flash memory 162 that needs to be delivered to the multimedia platform 120 for display through the display unit 135. This causes a drop in process efficiency of the main
  • processor 110 while the main processor 110 is delivering the data to the multimedia
  • main processor 110 main processor 110
  • memory 110 main memory
  • the portable terminal 100 requires the portable terminal 100 to be at least a
  • the portable terminal 100 comprises more multimedia
  • the present invention aims to provide a
  • nonvolatile memory and a device having a one-chip multimedia platform including a
  • a nonvolatile memory and a device having a one-chip multimedia platform including a
  • nonvolatile memory and a device having a one-chip multimedia platform including a
  • multimedia platform to include a plurality of memories in one chip and lower the
  • an aspect of the present invention features
  • a one-chip multimedia platform having at least one memory device and/or a digital
  • processing apparatus having a multimedia platform.
  • nonvolatile memory a multimedia processor setting or blocking a route in accordance
  • control command which is a boot command or a
  • a first volatile memory which is a
  • the nonvolatile memory the nonvolatile memory
  • the first volatile memory and the second volatile memory can be
  • the multimedia processor can comprise: a processor core controlling a route in
  • a host interface interfacing with the main processor and delivering the
  • processor core or the first NAND interface in accordance with a route control of the
  • the route setting unit can set a route such that the second NAND interface and
  • the first NAND interface are connected before the route control is performed.
  • the main processor can deliver an output signal, which is outputted by any one
  • the main processor can renew a pre-designated register value, which is present
  • the multimedia processor can verify the reception of the
  • the present invention can comprise a first stacking unit, on which a first substrate and a multimedia processor are mounted, a second stacking unit, on which a second substrate
  • One of the first stacking unit and the second stacking unit can be any one of the first stacking unit and the second stacking unit.
  • One of the first stacking unit and the second stacking unit can be any one of the first stacking unit and the second stacking unit.
  • the plurality of memory devices can comprise at least one nonvolatile memory
  • the plurality of memory devices are stacked in the order of size.
  • a multimedia processor setting a route in accordance with
  • the multimedia platform can be formed in one chip.
  • the multimedia processor can comprise: a processor core controlling a route in
  • a host interface interfacing with the main processor and delivering the
  • first NAND interface being coupled to the main processor for accessing the nonvolatile
  • a second NAND interface being coupled to the nonvolatile memory; and a route
  • the route setting unit can set a route such that the second NAND interface and
  • the first NAND interface are connected before the route control is performed.
  • the multimedia platform can further comprise at least one from a group
  • the first volatile memory consisting of a first volatile memory and a second volatile memory.
  • the first volatile memory consisting of a first volatile memory and a second volatile memory.
  • memory is a temporary memory device of the main processor, and the second volatile
  • memory is a temporary memory device of the multimedia processor.
  • the multimedia processor can further comprise an SD interface coupling the
  • processor core and the second volatile memory.
  • the main processor can deliver an output signal, which is outputted by any one
  • GPIO general purpose I/O
  • the main processor can renews a pre-designated register value by sending the
  • multimedia platform shared by a main processor and/or a recorded medium recording a
  • processor reads boot data, stored in a nonvolatile memory included in the multimedia
  • the main processor delivers a boot
  • processor access the nonvolatile memory by a route control in accordance with the boot
  • the multimedia processor can control the route in accordance with a route
  • FIG. 1 shows a diagram of the connection structure between processors in
  • FIG. 2 shows a diagram of the connection structure between a plurality of
  • processors in accordance with a preferred embodiment of the present invention.
  • FIG. 3 shows the structure of a route setting unit in accordance with a preferred
  • FIG. 4 shows the stacking structure of a multimedia platform in accordance with
  • the first element can be
  • PDA portable multimedia player
  • MP3 player digital music player
  • the portable memory in which a particular memory needs to be shared by a plurality of processors, the portable
  • terminal or a memory having two ports but is applicable equivalently to any terminal having a plurality of processors and a shared memory.
  • FIG. 2 is a diagram showing the connection structure between a plurality of
  • FIG. 1 A block diagram illustrating an exemplary computing environment in accordance with a preferred embodiment of the present invention.
  • FIG. 3 is a diagram showing the structure of a route setting unit in accordance with a preferred
  • a portable terminal 200 of the present invention comprises
  • the main processor 110 the multimedia platform 120, the sound output unit 125, the
  • the main processor 110 comprises the boot sequencer 140, the NAND interface
  • the boot sequencer 140 accesses a NAND flash memory 215 through the
  • NAND interface 142 and delivers the boot data, read by accessing a first NAND interface
  • the main processor core 148 performs a logic and/or operation pre-designated in
  • the main processor core 148 can comprise the cache memory 146 as a memory for performing the pre-designated logic or operation.
  • the cache memory 146 can be any type of memory for performing the pre-designated logic or operation.
  • memory 146 can be, for example, an SDRAM.
  • the NAND interface 142 interfaces with the first NAND interface 230, included
  • interface 150 interfaces with a first buffer memory 220, included in the multimedia
  • the host interface 152 interfaces with the multimedia platform 120 for the
  • the multimedia platform 120 comprises the multimedia processor 210, the
  • the multimedia platform 120 is stacked through the POP (package on
  • memories 220 and 225 are only an example of a volatile memory, such as an SDRAM,
  • NAND flash memory 215 is only an example of a nonvolatile memory. In other words,
  • NAND flash memory are described as an example of a volatile memory and a nonvolatile
  • the multimedia platform can be any type of multimedia platform.
  • the multimedia platform can be any type of multimedia platform.
  • the first buffer memory 220 can also be included in the main
  • the multimedia platform 120 can also comprise a plurality of nonvolatile
  • the multimedia processor 210 comprises the host interface 172, the SD interface
  • the host interface 172 interfaces with the main processor 100 for the
  • a route control signal for setting a route can be communicated by the route setting unit
  • the SD interface 176 interfaces with the second buffer memory, which is for
  • memories 220 and 225 can be, for example, an SDRAM.
  • One end of the first NAND flash memory is coupled to the NAND interface of
  • the main processor 110 and the other, the route setting unit 235.
  • the route setting unit 235 sets a route corresponding to the route control signal
  • the route setting unit 235 makes the second NAND interface 240 couple to the multimedia processor core 245 or makes the second NAND interface
  • the second NAND interface 240 interfaces the NAND flash memory 215 and
  • the NAND flash memory 215 is coupled to the main
  • processor 110 or the multimedia processor core 245 according to the setting of route by
  • the multimedia platform 120 of the present invention is a multimedia platform 120 of the present invention.
  • the brief booting sequence of the main processor 110 is as follows:
  • the boot sequencer 140 accesses
  • the boot sequencer 140 For the booting of the main processor core 148, the boot sequencer 140 writes
  • the boot data read from the NAND flash memory 215, in the cache memory 146 and then
  • the main processor core After booting through the use of the delivered boot data, the main processor core
  • operating data stored in the NAND flash memory 215 is stored in the first buffer memory
  • the booting sequence of the multimedia processor 210 is as follows:
  • the main processor core 148 sends a boot command to the multimedia processor
  • the boot command may include a booting instruction and the route
  • the multimedia processor core 245 controls the route setting unit 235 in
  • the route setting unit 235 sets the route to have
  • the multimedia processor core 245 connect to the second NAND interface 240.
  • the multimedia processor core 245 access the NAND flash memory 215
  • the multimedia processor core 245 then stores the read boot data in the second
  • the multimedia processor 210 can access the
  • NAND flash memory and read and process the necessary data in accordance with the
  • the process command may comprise a process instruction and storage
  • the multimedia processor core 245 can directly access the multimedia processor core 245
  • NAND flash memory 215 and read the needed boot data without having to receive the
  • connection structure in which a plurality of processors are connected linearly through the
  • processor 110 has to read the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g. boot data or multimedia data) from the needed data (e.g.
  • NAND flash memory 162 and deliver the data to the multimedia processor 170 (refer to FIG. 1 ) when the multimedia processor 170 is booted or the multimedia data is processed.
  • processor 110 or the multimedia processor core 245 can access the NAND flash memory
  • processor core 245 by the hardware structure is as follows:
  • the route control value corresponding to the route setting unit 235 is set to have
  • a first value e.g. "0"
  • the route setting unit 235 sets the route such
  • first NAND interface 230 and the second NAND interface 240 are coupled.
  • processor core 245 such that the multimedia processor core 245 and the second NAND
  • first NAND interface 230 and the second NAND interface 240 are set to be coupled, and
  • boot sequencer 140 accesses the NAND flash memory 215 through the NAND
  • NAND interface 240 and enables the booting by the main processor core 148. Then, once the main processor core 148 finishes booting, the main processor 110
  • a route control pin e.g. any one of the GPIO (general-purpose I/O) pins and/or
  • the multimedia processor core 245 controls the route setting unit 235 to set a
  • the route setting unit 235 set a route in accordance with the control of the
  • multimedia processor core 245 such that the second NAND interface 240 and the
  • multimedia processor core 245 are connected, and the multimedia processor core 245
  • NAND interface 240 to read the boot data.
  • processor core 245 by the software structure is as follows:
  • the route control value of the route setting unit 235 is set to have a first value
  • the route setting unit 235 sets the route such that the first
  • NAND interface 230 and the second NAND interface 240 are coupled. However, once a
  • first NAND interface 230 and the second NAND interface 240 are set to be coupled, and
  • boot sequencer 140 accesses the NAND flash memory 215 through the NAND
  • NAND interface 240 and enables the booting by the main processor core 148.
  • the register is in the multimedia processor core 245 or the second buffer
  • memory 225 can be managed by the multimedia processor core 245.
  • the multimedia processor core 245 recognizes that the value written in the
  • the multimedia processor core 245 accesses the NAND flash memory 215
  • the route setting unit 235 sets a route such that the
  • the route setting unit 235 controls the route to be set between the
  • the multimedia processor core 245 accesses the NAND flash memory 215
  • control command e.g. boot command
  • the multimedia processor core 245 can enable the main
  • processor 110 to access the NAND flash memory 215 by renewing the route of the route
  • FIG. 4 is a diagram showing the stacking structure of a multimedia platform in
  • the POP package on package
  • second buffer memories 220 and 225 on a single chip for the generation of the multimedia platform 120 of the present invention.
  • a first solder ball 410 a In the vertical structure of the multimedia platform 120, a first solder ball 410 a
  • first substrate 420 Formed on top of the first solder ball 410a is a first substrate 420, in which a
  • multimedia processor 210 which is connected to the first substrate 420 through a wire
  • An electrical mold compound (EMC) 440 is formed around the multimedia
  • processor 210 in order to prevent electrical conduction.
  • a second solder ball 410b is formed on top of the first substrate 420 to make a
  • the second solder ball 41 Ob may be substituted by a
  • the memory devices are stacked in accordance with their sizes.
  • the memory devices can
  • buffer memory 225 and if necessary, other memory devices can be additionally stacked.
  • the memory devices are stacked in a manner that smaller memory devices are placed
  • second stacking unit 404 in which the second substrate 450 and a plurality of memory
  • the first substrate 420 and the second substrate 450 can be in contact
  • the device having a one-chip multimedia platform in
  • the present invention can minimize the bottleneck problem occurred during the
  • the present invention can also lower the production cost of the portable terminal
  • POP package on package
  • the present invention can improve the integration rate of the
  • the terminal by forming the multimedia platform to include a plurality of memories in one

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Abstract

A method for sharing a memory and a device having a one-chip multimedia platform including a plurality of memories are disclosed. The multimedia platform in accordance with an embodiment of the present invention comprises in one chip: a nonvolatile memory; a multimedia processor, the multimedia processor setting or blocking a route in accordance with a route control signal received from a main processor such that the main processor accesses the nonvolatile memory, the multimedia processor reading data from the nonvolatile memory and processing the data in accordance with a control command, the control command being a boot command or a process command received from the main processor; a first volatile memory, the first volatile memory being a temporary memory device of the main processor; and a second volatile memory, the second volatile memory being a temporary memory of the multimedia processor. With the present invention, the process efficiency can be maximized and the portable terminal can be made smaller by putting a plurality of memory devices and the conventional multimedia platform in a single chip by use of the POP (package on package) technology.

Description

[DESCRIPTION]
[Invention Title]
MULTIMEDIA PLATFORM
[Technical Field]
The present invention is related to sharing of a memory (storage device),
particularly to a method and a device thereof for having a memory shared by a plurality of
processors in an electrical/electronic device (digital processing device).
[Background Art]
As an example of electrical/electronic devices, portable terminals refer to
electronic devices that can be easily carried by making the size compact in order to
perform functions such as game and mobile communication. Portable terminals include
mobile communication terminals, personal digital assistants (PDA) and portable
multimedia players (PMP).
Among the portable terminals, the mobile communication terminal is essentially
a device designed to enable a mobile user to telecommunicate with a receiver who is
remotely located. Thanks to scientific development, however, the latest mobile
communication terminals have functions, such as camera and multimedia data playback,
in addition to the basic functions, such as voice communication, short message service and address book.
Portable terminals comprise a plurality of processors to perform multiple
functions. In other words, a portable terminal has an application processor for performing
additional functions (e.g. camera and multimedia data playback) and a main processor for
controlling the functions of the portable terminal and operations of the application
processor. In addition, portable terminals further comprise one or more memories to be
connected to the main processor.
The memories linked to the main processor include a NAND flash memory and a
buffer memory. The NAND flash memory and buffer memory are integrated to one chip
through the multi-chip package technology.
Below is a brief description with reference to FIG. 1 of connection structure and
operation of processors in accordance with the prior art.
FIG. 1 is a diagram showing the connection structure between processors of the
prior art. Although one application processor (a multimedia processor for processing
multimedia data) is shown in FIG. 1, the number of application processors can vary as
necessary.
Referring to FIG. 1, a portable terminal 100 of the prior art comprises a main
processor 110, a memory chip 115, a multimedia platform 120, a sound output unit 125,
an image sensor 130 and a display unit 135. The main processor 110, memory chip 115
and multimedia platform 120 can be realized in one chip, respectively. The main processor 110 comprises a boot sequencer 140, a NAND interface 142,
a cache memory 146, a processor core 148, an SD interface 150 and a host interface 152.
The boot sequencer 140 accesses a NAND flash memory 162 through the
NAND interface 142 and delivers the read boot data to the processor core 148 to have the
processor core 148 perform the booting.
The processor core 148 performs a logic and/or operation pre-designated in the
main processor 110. The process core 148 can comprise the cache memory 146 as a
memory for performing the pre-designated logic or operation. Hereinafter, the processor
core 148 included in the main processor 110 will be called the "main processor core."
The NAND interface 142 interfaces with the NAND flash memory 162 included
in the memory chip 115, and the SD interface 150 interfaces with a buffer memory 164
included in the memory chip 115. The host interface 152 interfaces with the multimedia
platform 120.
The memory chip 115 comprises the NAND flash memory 162 and the buffer
memory 164 in one chip through the multi-chip package technology.
The multimedia platform 120 comprises a multimedia processor 170 and a
buffer memory 178 in one chip.
The multimedia processor 170 comprises a host interface 172 interfacing with
the main processor 110, a processor core 174 performing a logic and/or operation
pre-designated in the multimedia processor 170 and an SD interface 176 interfacing with the buffer memory 178. Hereinafter, the processor core 174 included in the multimedia
processor 170 will be called the "multimedia processor core."
Coupled to the back of the multimedia platform 120 are the sound output unit
125, the image sensor 130 and the display unit 135.
The connection structure between processors shown in FIG. 1 is based on the
prior art and is familiar with anyone of ordinary skill in the art to which the invention
pertains. Thus, further description will be omitted here.
Hereinafter, with reference to the connection structure of processors shown in
FIG. 1 , the booting sequence of the main processor 110 and the multimedia processor 120
will be briefly described.
The booting sequence of the main processor 110 is as follows:
Once the portable terminal 100 is powered on, the boot sequencer 140 accesses
the NAND flash memory 162 in the memory chip 115 through the NAND interface 142.
The boot sequencer 140 reads boot data stored in an area of the NAND flash
memory 162 and writes the boot data in the cache memory 146.
The boot sequencer 140 then delivers the boot data, stored in the cache memory
146, to the main processor core 148.
After booting through the use of the delivered boot data, the main processor core
148 reads the data for operating the portable terminal 100 that are stored in the NAND
flash memory 162 through the NAND interface 142 and stores the data in the buffer memory 164 in the memory chip 115 accessed through the SD interface 150. The
operating data stored in the NAND flash memory 162 is stored in the buffer memory 164
because the operating speed of the NAND flash memory 162 is slow.
Next, the booting sequence of the multimedia processor 170 is as follows:
The main processor core 148 reads the boot data stored in the NAND flash
memory 162 in the memory chip 115 in order to have the multimedia processor core 174
perform the booting. The boot data can be what the main processor core 148 stored in the
buffer memory 164.
The main processor core 148 delivers the read boot data to the multimedia
processor core 174 through the host interface 152 and 172. The boot data can be delivered
with a boot command.
After storing the received boot data in the buffer memory 178 through the SD
interface 176, the multimedia processor core 174 performs the booting by use of the
stored boot data.
As described above, to control the booting of the multimedia processor 170, the
main processor 110 reads the needed data from the NAND flash memory 162 (or from the
buffer memory 164) in the connected memory chip 115 and delivers the data to the
multimedia processor core 174 through the host interface 152 and 172.
The above sequence is commonly applied to the multimedia data stored in the
NAND flash memory 162 that needs to be delivered to the multimedia platform 120 for display through the display unit 135. This causes a drop in process efficiency of the main
processor 110 while the main processor 110 is delivering the data to the multimedia
platform 120. This can also cause a bottleneck problem while communicating the data
between the host interfaces 152 and 172.
Moreover, the need to include the three chips (i.e. main processor 110, memory
chip 115 and multimedia platform 120) requires the portable terminal 100 to be at least a
certain size.
In other words, as the portable terminal 100 comprises more multimedia
functions, more efficient integration is required. As a result, the multi-chip package
technology, in which the NAND flash memory 162 and the buffer memory 164 are
combined in one chip, has been developed.
However, by preparing the multimedia platform 120 and the memory chip 115
separately, the there becomes less available space in a motherboard of the portable
terminal 100, and as a result, it becomes difficult to include additional functions in a small
size motherboard. This also inhibits the effort to make the portable terminal 100 smaller.
[Disclosure]
[Technical Problem]
In order to solve the above problems, the present invention aims to provide a
method for sharing a nonvolatile memory and a device having a one-chip multimedia platform including a plurality of memories that can easily make a portable terminal
smaller and/or add additional functions by integrating the memory chip and the
multimedia platform in one chip by use of the POP (package on package) technology.
It is another object of the present invention to provide a method for sharing a
nonvolatile memory and a device having a one-chip multimedia platform including a
plurality of memories that can minimize the bottleneck problem occurred during the
communication of data between the main processor and the multimedia processor and
deliver the data quickly by having the memory chip and memories in the multimedia
platform shared or exclusively used by the main processor.
It is also another object of the present invention to provide a method for sharing
a nonvolatile memory and a device having a one-chip multimedia platform including a
plurality of memories that can lower the production cost of the portable terminal by
integrating the memory chip and the multimedia platform in one chip by use of the POP
(package on package) technology.
It is yet another object of the present invention to provide a method for sharing a
nonvolatile memory and a device having a one-chip multimedia platform including a
plurality of memories that can improve the integration rate of the motherboard owing to
the reduction in the number of parts included in the portable terminal by forming the
multimedia platform to include a plurality of memories in one chip and lower the
mounting cost, which is determined by the number of mounted parts. Other objects of the present invention will become apparent through preferred
embodiments described below.
[Technical Solution]
In order to achieve the above objects, an aspect of the present invention features
a one-chip multimedia platform having at least one memory device and/or a digital
processing apparatus having a multimedia platform.
The multimedia platform included in a digital processing apparatus in
accordance with a preferred embodiment of the present invention can comprise: a
nonvolatile memory; a multimedia processor setting or blocking a route in accordance
with a route control signal received from a main processor such that the main processor
accesses the nonvolatile memory, and reading data from the nonvolatile memory and
processing the data in accordance with a control command, which is a boot command or a
process command received from the main processor; a first volatile memory, which is a
temporary memory device of the main processor; and a second volatile memory, which is
a temporary memory of the multimedia processor. The nonvolatile memory, the
multimedia processor, the first volatile memory and the second volatile memory can be
formed in a single chip.
The multimedia processor can comprise: a processor core controlling a route in
accordance with the route control signal and performing a process in accordance with the control command; a host interface interfacing with the main processor and delivering the
control command, which is received from the main processor, to the processor core; an
SD interface coupling the processor core and the second volatile memory; a first NAND
interface, which is for allowing the main processor to access the nonvolatile memory; a
second NAND interface interfacing with the nonvolatile memory; and a route setting unit,
which is connected to the processor core, the first NAND interface and the second NAND
interface, and sets a route such that the second NAND interface is connected to the
processor core or the first NAND interface in accordance with a route control of the
processor core.
The route setting unit can set a route such that the second NAND interface and
the first NAND interface are connected before the route control is performed.
The main processor can deliver an output signal, which is outputted by any one
pin of GPIO (general purpose I/O) pins and address pins, as the route control signal to the
multimedia processor.
The main processor can renew a pre-designated register value, which is present
in the multimedia processor or the second volatile memory, by sending the route control
signal through a Data I/O, and the multimedia processor can verify the reception of the
route control signal based on the renewal status of the register value.
The multimedia platform in accordance with another preferred embodiment of
the present invention can comprise a first stacking unit, on which a first substrate and a multimedia processor are mounted, a second stacking unit, on which a second substrate
and a plurality of memory devices are stacked, and a solder ball allowing the first
substrate and the second substrate to come in contact. In the first stacking unit, a pattern
and a via hole are formed on the first substrate, and the multimedia processor is mounted
on top of the first substrate. In the second stacking unit, a pattern and a vial hole are
formed on the second substrate, and the plurality of memory devices are stacked on top of
the second substrate. One of the first stacking unit and the second stacking unit can be
formed on the bottom and the other of the first stacking unit and the second stacking unit
can be formed on the top.
The plurality of memory devices can comprise at least one nonvolatile memory
and at least one volatile memory.
The plurality of memory devices are stacked in the order of size.
The multimedia platform included in a digital processing apparatus in
accordance with another preferred embodiment of the present invention can comprise: at
least one nonvolatile memory; a multimedia processor setting a route in accordance with
a route control signal received from a main processor such that the main processor
accesses the nonvolatile memory or accessing the nonvolatile memory to perform a
process in accordance with a control command corresponding to a boot command or a
process command received from the main processor. The nonvolatile memory and the
multimedia platform can be formed in one chip. The multimedia processor can comprise: a processor core controlling a route in
accordance with the route control signal and performing a process in accordance with the
control command; a host interface interfacing with the main processor and delivering the
control command, which is received from the main processor, to the processor core; a
first NAND interface being coupled to the main processor for accessing the nonvolatile
memory; a second NAND interface being coupled to the nonvolatile memory; and a route
setting unit being connected to the processor core, the first NAND interface and the
second NAND interface, and setting a route such that the second NAND interface is
connected to the processor core or the first NAND interface in accordance with a route
control of the processor core.
The route setting unit can set a route such that the second NAND interface and
the first NAND interface are connected before the route control is performed.
The multimedia platform can further comprise at least one from a group
consisting of a first volatile memory and a second volatile memory. The first volatile
memory is a temporary memory device of the main processor, and the second volatile
memory is a temporary memory device of the multimedia processor.
The multimedia processor can further comprise an SD interface coupling the
processor core and the second volatile memory.
The main processor can deliver an output signal, which is outputted by any one
pin of GPIO (general purpose I/O) pins and address pins, as the route control signal to the multimedia processor.
The main processor can renews a pre-designated register value by sending the
route control signal through a Data I/O, and the multimedia processor can verify the
reception of the route control signal based on the renewal status of the register value,
which is present in the multimedia processor.
In order to achieve the above objects, another aspect of the present invention
features a method for having a plurality of memory devices included in a one-chip
multimedia platform shared by a main processor and/or a recorded medium recording a
program for performing the method thereof.
According to a preferred embodiment of the present invention, the main
processor reads boot data, stored in a nonvolatile memory included in the multimedia
platform for booting, and performs the booting. The main processor delivers a boot
command to a multimedia processor in the multimedia platform, and the multimedia
processor access the nonvolatile memory by a route control in accordance with the boot
command to read the boot data and perform the booting.
The multimedia processor can control the route in accordance with a route
control signal received from the main processor such that the nonvolatile memory is
accessed by any one of the main processor and the multimedia processor. [Description of Drawings]
FIG. 1 shows a diagram of the connection structure between processors in
accordance with the prior art;
FIG. 2 shows a diagram of the connection structure between a plurality of
processors in accordance with a preferred embodiment of the present invention;
FIG. 3 shows the structure of a route setting unit in accordance with a preferred
embodiment of the present invention; and
FIG. 4 shows the stacking structure of a multimedia platform in accordance with
a preferred embodiment of the present invention.
[Mode for Invention]
The above objects, features and advantages will become more apparent through
the below description with reference to the accompanying drawings.
Since there can be a variety of permutations and embodiments of the present
invention, certain embodiments will be illustrated and described with reference to the
accompanying drawings. This, however, is by no means to restrict the present invention
to certain embodiments, and shall be construed as including all permutations, equivalents
and substitutes covered by the spirit and scope of the present invention. Throughout the
drawings, similar elements are given similar reference numerals. Throughout the
description of the present invention, when describing a certain technology is determined to evade the point of the present invention, the pertinent detailed description will be
omitted.
Terms such as "first" and "second" can be used in describing various elements,
but the above elements shall not be restricted to the above terms. The above terms are
used only to distinguish one element from the other. For instance, the first element can be
named the second element, and vice versa, without departing the scope of claims of the
present invention. The term "and/or" shall include the combination of a plurality of listed
items or any of the plurality of listed items.
When one element is described as being "connected" or "accessed" to another
element, it shall be construed as being connected or accessed to the other element directly
but also as possibly having another element in between. On the other hand, if one element
is described as being "directly connected" or "directly accessed" to another element, it
shall be construed that there is no other element in between.
The terms used in the description are intended to describe certain embodiments
only, and shall by no means restrict the present invention. Unless clearly used otherwise,
expressions in the singular number include a plural meaning. In the present description,
an expression such as "comprising" or "consisting of is intended to designate a
characteristic, a number, a step, an operation, an element, a part or combinations thereof,
and shall not be construed to preclude any presence or possibility of one or more other
characteristics, numbers, steps, operations, elements, parts or combinations thereof. Unless otherwise defined, all terms, including technical terms and scientific
terms, used herein have the same meaning as how they are generally understood by those
of ordinary skill in the art to which the invention pertains. Any term that is defined in a
general dictionary shall be construed to have the same meaning in the context of the
relevant art, and, unless otherwise defined explicitly, shall not be interpreted to have an
idealistic or excessively formalistic meaning.
Hereinafter, preferred embodiments will be described in detail with reference to
the accompanying drawings. Identical or corresponding elements will be given the same
reference numerals, regardless of the figure number, and any redundant description of the
identical or corresponding elements will not be repeated.
Although it is evident that the method for sharing a memory in accordance with
the present invention can be equivalently applied to all types of digital processing devices
or systems (e.g. portable terminals and/or home digital appliances, such as the mobile
communication terminal, PDA, portable multimedia player (PMP), MP3 player, digital
camera, digital television, audio equipment, etc.), which has a plurality of processors and
in which a particular memory needs to be shared by a plurality of processors, the portable
terminal and two processors sharing a memory will be described hereinafter for the
convenience of description and understanding. Moreover, it shall be easily understood
through the below description that the present invention is not limited to a specific type of
terminal or a memory having two ports but is applicable equivalently to any terminal having a plurality of processors and a shared memory.
FIG. 2 is a diagram showing the connection structure between a plurality of
processors in accordance with a preferred embodiment of the present invention, and FIG.
3 is a diagram showing the structure of a route setting unit in accordance with a preferred
embodiment of the present invention.
Referring to FIG. 2, a portable terminal 200 of the present invention comprises
the main processor 110, the multimedia platform 120, the sound output unit 125, the
image sensor 130 and the display 135. The main processor 110 and multimedia platform
120 can be realized in one chip, respectively.
The main processor 110 comprises the boot sequencer 140, the NAND interface
142, the cache memory 146, the processor core 148, the SD interface 150 and the host
interface 152.
The boot sequencer 140 accesses a NAND flash memory 215 through the
NAND interface 142 and delivers the boot data, read by accessing a first NAND interface
230, a route setting unit 235 and a second NAND interface 240 in a multimedia processor
210, to the main processor core 148 to have the main processor core 148 perform the
booting.
The main processor core 148 performs a logic and/or operation pre-designated in
the main processor 110. The main processor core 148 can comprise the cache memory 146 as a memory for performing the pre-designated logic or operation. The cache
memory 146 can be, for example, an SDRAM.
The NAND interface 142 interfaces with the first NAND interface 230, included
in the multimedia processor 210, to access the NAND flash memory 215. The SD
interface 150 interfaces with a first buffer memory 220, included in the multimedia
platform 120. The host interface 152 interfaces with the multimedia platform 120 for the
communication of control commands.
The multimedia platform 120 comprises the multimedia processor 210, the
NAND flash memory 215, the first buffer memory 220 and a second buffer memory 225
in one chip. The multimedia platform 120 is stacked through the POP (package on
package) technology in order to include the multimedia processor 210, the NAND flash
memory 215, the first buffer memory 220 and the second buffer memory 225. The
vertical stacking structure of the multimedia platform in accordance with the present
invention will be described later with reference to FIG. 4. The first and second buffer
memories 220 and 225 are only an example of a volatile memory, such as an SDRAM,
and the NAND flash memory 215 is only an example of a nonvolatile memory. In other
words, it is evident that there can be a variety of memory types that are included in the
multimedia platform 120. However, in this description, the buffer memory and the
NAND flash memory are described as an example of a volatile memory and a nonvolatile
memory, respectively. Moreover, it is evident that the number of volatile memories and/or nonvolatile memories included in the multimedia platform 120 can vary as necessary and
shall not be restricted to the illustrated number. For instance, the multimedia platform can
further comprise one or more memories for use by another processor coupled to the
multimedia platform 120. The first buffer memory 220 can also be included in the main
processor 110. The multimedia platform 120 can also comprise a plurality of nonvolatile
memories.
The multimedia processor 210 comprises the host interface 172, the SD interface
176, the first NAND interface, the route setting unit 235 and the second NAND interface.
The host interface 172 interfaces with the main processor 100 for the
communication of commands for control, such as processing multimedia data, hi addition,
a route control signal for setting a route can be communicated by the route setting unit
235 through the host interface 172.
The SD interface 176 interfaces with the second buffer memory, which is for
processing multimedia data of the multimedia processor 210. The first and second buffer
memories 220 and 225 can be, for example, an SDRAM.
One end of the first NAND flash memory is coupled to the NAND interface of
the main processor 110, and the other, the route setting unit 235.
The route setting unit 235 sets a route corresponding to the route control signal,
received from the main processor 110, in accordance with the control of a multimedia
processor core 245. That is, the route setting unit 235 makes the second NAND interface 240 couple to the multimedia processor core 245 or makes the second NAND interface
240 couple to the first NAND interface 230, by the control of the multimedia processor
core 245 in accordance with the route control signal. The operation sequence of the route
setting unit 235 will be described later in detail with reference to FIG. 3.
The second NAND interface 240 interfaces the NAND flash memory 215 and
the multimedia processor 210. The NAND flash memory 215 is coupled to the main
processor 110 or the multimedia processor core 245 according to the setting of route by
the route setting unit 235.
As described above, the multimedia platform 120 of the present invention is
realized in a chip comprising a plurality of memories, reducing the number of parts
included in the portable terminal 200. Therefore, the integration rate of the motherboard
can be improved, and the mounting cost, which is determined by the number of mounted
parts, can be lowered.
Hereinafter, the booting sequence of each processor of the portable terminal 200
will be briefly described.
The brief booting sequence of the main processor 110 is as follows:
Once the portable terminal 200 is powered on, the boot sequencer 140 accesses
the NAND flash memory 215 through the NAND interface, 142 via the first NAND
interface 230, the route setting unit 235 and the second NAND interface 240 in the
multimedia processor 210. For the booting of the main processor core 148, the boot sequencer 140 writes
the boot data, read from the NAND flash memory 215, in the cache memory 146 and then
delivers the boot data, written in the cache memory 146, to the main processor core 148.
After booting through the use of the delivered boot data, the main processor core
148 reads the data for operating the portable terminal 200 that are stored in the NAND
flash memory 215 through the NAND interface 142, the first NAND interface, the route
setting unit 235 and the second NAND interface 240 and stores the data in the first buffer
memory 220 in the multimedia platform 120 accessed through the SD interface 150. The
operating data stored in the NAND flash memory 215 is stored in the first buffer memory
220 because the operating speed of the NAND flash memory 215 is slow.
Next, the booting sequence of the multimedia processor 210 is as follows:
The main processor core 148 sends a boot command to the multimedia processor
core 245 through the host interface 152 and 172 for the booting of the multimedia
processor core 245. The boot command may include a booting instruction and the route
control signal.
The multimedia processor core 245 controls the route setting unit 235 in
accordance with the boot command, and the route setting unit 235 sets the route to have
the multimedia processor core 245 connect to the second NAND interface 240.
The multimedia processor core 245 access the NAND flash memory 215
through the route setting unit 235 and the second NAND interface 240, and reads the boot data stored in an area of the NAND flash memory 215.
The multimedia processor core 245 then stores the read boot data in the second
buffer memory 225 through the SD interface 176 and then performs the booting by use of
the boot data stored in the second buffer memory 225.
The booting sequence of the multimedia processor core 245 described above can
be commonly applied to any case of reading multimedia data, which needs to be
processed by the multimedia processor core 245, stored the NAND flash memory 215. In
other words, if the main processor 110 sends only the process command and route control
signal to the multimedia processor 210, the multimedia processor 210 can access the
NAND flash memory and read and process the necessary data in accordance with the
process command. The process command may comprise a process instruction and storage
location information of the data to be processed.
In other words, the multimedia processor core 245 can directly access the
NAND flash memory 215 and read the needed boot data without having to receive the
boot data for booting or the multimedia data for processing from the main processor 110
This solves the problem of lowered process efficiency in the conventional
connection structure in which a plurality of processors are connected linearly through the
memory chip 115 - main processor 110 - multimedia platform 120 and thus the main
processor 110 has to read the needed data (e.g. boot data or multimedia data) from the
NAND flash memory 162 and deliver the data to the multimedia processor 170 (refer to FIG. 1 ) when the multimedia processor 170 is booted or the multimedia data is processed.
Hereinafter, the process of the route setting unit 235 in the multimedia processor
210 setting a route in accordance with the route control signal, such that the main
processor 110 or the multimedia processor core 245 can access the NAND flash memory
215, will be briefly described.
First, the sequence of the route control signal being delivered to the multimedia
processor core 245 by the hardware structure is as follows:
The route control value corresponding to the route setting unit 235 is set to have
a first value (e.g. "0"), and in this condition the route setting unit 235 sets the route such
that the first NAND interface 230 and the second NAND interface 240 are coupled.
However, once a second value (e.g. "I) is received from the main processor 110, the route
setting unit 235 renews the route in accordance with the control of the multimedia
processor core 245 such that the multimedia processor core 245 and the second NAND
interface 240 are coupled.
Since the route control value corresponding to the route setting unit 235 is "0"
when the portable terminal 200 is powered on (or when it is in the default condition), the
first NAND interface 230 and the second NAND interface 240 are set to be coupled, and
thus the boot sequencer 140 accesses the NAND flash memory 215 through the NAND
interface 142, the first NAND interface 230, the route setting unit 235 and the second
NAND interface 240 and enables the booting by the main processor core 148. Then, once the main processor core 148 finishes booting, the main processor 110
uses a route control pin (e.g. any one of the GPIO (general-purpose I/O) pins and/or
address pins), pre-assigned for booting, to output the route control value of "1" as a route
control signal, and the route control value of "1" is delivered to the multimedia processor
core 245 through the host interface 152 and 172.
The multimedia processor core 245 controls the route setting unit 235 to set a
route corresponding to the route control signal received through the host interface 172.
The route setting unit 235 set a route in accordance with the control of the
multimedia processor core 245 such that the second NAND interface 240 and the
multimedia processor core 245 are connected, and the multimedia processor core 245
accesses the NAND flash memory 215 through the route setting unit 235 and the second
NAND interface 240 to read the boot data.
Next, the sequence of the route control signal being delivered to the multimedia
processor core 245 by the software structure is as follows:
The route control value of the route setting unit 235 is set to have a first value
(e.g. "0"), and in this condition the route setting unit 235 sets the route such that the first
NAND interface 230 and the second NAND interface 240 are coupled. However, once a
second value (e.g. "I) is received from the main processor 110, the route setting unit 235
renews the route in accordance with the control of the multimedia processor core 245
such that the multimedia processor core 245 and the second NAND interface 240 are coupled.
Since the route control value corresponding to the route setting unit 235 is "0"
when the portable terminal 200 is powered on (or when it is in the default condition), the
first NAND interface 230 and the second NAND interface 240 are set to be coupled, and
thus the boot sequencer 140 accesses the NAND flash memory 215 through the NAND
interface 142, the first NAND interface 230, the route setting unit 235 and the second
NAND interface 240 and enables the booting by the main processor core 148.
Then, once the main processor core 148 finishes booting, the main processor 110
writes the second value (e.g. "1") in a register inside the multimedia platform 120 through
the Data I/O of the host interface 152 and 172 for the booting of the multimedia processor
core 245. The register is in the multimedia processor core 245 or the second buffer
memory 225, and can be managed by the multimedia processor core 245.
The multimedia processor core 245 recognizes that the value written in the
register (i.e. the register value) has been renewed and controls such that the route setting
unit 235 sets a route corresponding to the register value.
Then, the multimedia processor core 245 accesses the NAND flash memory 215
through the route setting unit 235 and the second NAND flash memory 240 and reads the
boot data to perform the booting.
Below is a brief description of the route setting sequence of the above route
setting unit 235 with reference to FIG. 3. Under the default condition, the route setting unit 235 sets a route such that the
second NAND interface 240 and the first NAND interface 230 are connected.
Once the multimedia processor core 245 receives a route control signal, for
renewing the route by the hardware or software structure, from the main processor 110
under this condition, the route setting unit 235 controls the route to be set between the
second NAND interface 240 and the multimedia processor core 245.
The multimedia processor core 245 accesses the NAND flash memory 215
through the second NAND interface 240 and reads the boot data to perform the booting or
reads and processes the multimedia data.
After reading data, corresponding to the control command (e.g. boot command
or process command) of the main processor, from the NAND flash memory 215 or
storing the processed data, the multimedia processor core 245 can enable the main
processor 110 to access the NAND flash memory 215 by renewing the route of the route
setting unit 235 to the default condition.
FIG. 4 is a diagram showing the stacking structure of a multimedia platform in
accordance with a preferred embodiment of the present invention.
As shown in FIG. 4, the POP (package on package) technology is utilized to
stack the multimedia processor 210, the NAND flash memory 215 and the first and
second buffer memories 220 and 225 on a single chip for the generation of the multimedia platform 120 of the present invention.
In the vertical structure of the multimedia platform 120, a first solder ball 410 a
is formed on the bottom of the structure, to mount the multimedia platform on the
motherboard of the portable terminal 200.
Formed on top of the first solder ball 410a is a first substrate 420, in which a
design pattern and via holes are formed. Mounted on top of the first substrate 420 is the
multimedia processor 210, which is connected to the first substrate 420 through a wire
bond 430a. An electrical mold compound (EMC) 440 is formed around the multimedia
processor 210 in order to prevent electrical conduction.
A second solder ball 410b is formed on top of the first substrate 420 to make a
contact with a second substrate 450. The second solder ball 41 Ob may be substituted by a
conductive ball.
Like the first substrate 420, a design pattern and via holes are formed on the
second substrate 450. On the upper side of the second substrate 450, a plurality of
memory devices are stacked in accordance with their sizes. The memory devices can
comprise the NAND flash memory 215, the first buffer memory 220 and the second
buffer memory 225, and if necessary, other memory devices can be additionally stacked.
The memory devices are stacked in a manner that smaller memory devices are placed
over larger memory devices, and are connected to the second substrate 450 by the wire
bond 430b, 430c and 43Od. In the stacking structure of the multimedia platform 120 shown in FIG. 4, a
second stacking unit 404, in which the second substrate 450 and a plurality of memory
devices are stacked, is stacked on top of a first stacking unit 402, in which the first
substrate 420 and the multimedia processor 210 are stacked.
As necessary, however, it should be evident that the second stacking unit 402
can be placed under the first stacking unit 404 in the multimedia platform 120. As
described above, the first substrate 420 and the second substrate 450 can be in contact
with each other by the second solder ball 410b, regardless of their placement.
The drawings and detailed description are only examples of the present
invention, serve only for describing the present invention and by no means limit or
restrict the spirit and scope of the present invention. Thus, any person of ordinary skill in
the art shall understand that a large number of permutations and other equivalent
embodiments are possible. The true scope of the present invention must be defined only
by the spirit of the appended claims.
[Industrial Applicability]
As described above, the device having a one-chip multimedia platform in
accordance with the present invention can easily make a portable terminal smaller and/or
add additional functions by integrating the memory chip and the multimedia platform in one chip by use of the POP (package on package) technology.
The present invention can minimize the bottleneck problem occurred during the
communication of data between the main processor and the multimedia processor and
deliver the data quickly by having the memory chip and memories in the multimedia
platform shared or exclusively used by the main processor.
The present invention can also lower the production cost of the portable terminal
by integrating the memory chip and the multimedia platform in one chip by use of the
POP (package on package) technology.
Moreover, the present invention can improve the integration rate of the
motherboard owing to the reduction in the number of parts included in the portable
terminal by forming the multimedia platform to include a plurality of memories in one
chip and lower the mounting cost, which is determined by the number of mounted parts.

Claims

[CLAIMS]
[Claim 1 ]
A multimedia platform included in a digital processing apparatus, the
multimedia platform comprising:
a nonvolatile memory;
a multimedia processor, the multimedia processor setting or blocking a route in
accordance with a route control signal received from a main processor such that the main
processor accesses the nonvolatile memory, the multimedia processor reading data from
the nonvolatile memory and processing the data in accordance with a control command,
the control command being a boot command or a process command received from the
main processor;
a first volatile memory, the first volatile memory being a temporary memory
device of the main processor; and
a second volatile memory, the second volatile memory being a temporary
memory of the multimedia processor,
wherein the nonvolatile memory, the multimedia processor, the first volatile
memory and the second volatile memory are formed in a single chip.
[Claim 2]
The multimedia platform of Claim 1 , wherein the multimedia processor compnses:
a processor core, the processor core controlling a route in accordance with the
route control signal and performing a process in accordance with the control command;
a host interface, the host interface interfacing with the main processor and
delivering the control command to the processor core, the control command being
received from the main processor;
an SD interface, the SD interface coupling the processor core and the second
volatile memory;
a first NAND interface, the first NAND interface being for allowing the main
processor to access the nonvolatile memory;
a second NAND interface, the second NAND interface interfacing with the
nonvolatile memory; and
a route setting unit, the route setting unit being connected to the processor core,
the first NAND interface and the second NAND interface, the route setting unit setting a
route such that the second NAND interface is connected to the processor core or the first
NAND interface in accordance with a route control of the processor core.
[Claim 3]
The multimedia platform of Claim 2, wherein the route setting unit sets a route
such that the second NAND interface and the first NAND interface are connected before the route control is performed.
[Claim 4]
The multimedia platform of Claim 1 or Claim 2, wherein the main processor
delivers an output signal as the route control signal to the multimedia processor, the
output signal being outputted by any one pin of GPIO (general purpose I/O) pins and
address pins.
[Claim 5]
The multimedia platform of Claim 1 or Claim 2, wherein the main processor
renews a pre-designated register value by sending the route control signal through a Data
I/O, and the multimedia processor verifies the reception of the route control signal based
on the renewal status of the register value, the register value being present in the
multimedia processor or the second volatile memory.
[Claim 6]
A digital processing apparatus having a multimedia platform, the digital
processing apparatus comprising:
a first stacking unit, a first substrate and a multimedia processor being mounted
on the first stacking unit, a pattern and a via hole being formed on the first substrate, the multimedia processor being mounted on top of the first substrate;
a second stacking unit, a second substrate and a plurality of memory devices
being stacked on the second stacking unit, a pattern and a vial hole being formed on the
second substrate, the plurality of memory devices being stacked on top of the second
substrate; and
a solder ball, the solder ball allowing the first substrate and the second substrate
to come in contact,
wherein one of the first stacking unit and the second stacking unit is formed on
the bottom and the other of the first stacking unit and the second stacking unit is formed
on the top.
[Claim 7]
The digital processing apparatus of Claim 6, wherein the plurality of memory
devices comprise at least one nonvolatile memory and at least one volatile memory.
[Claim 8]
The digital processing apparatus of Claim 6, wherein the plurality of memory
devices are stacked in the order of size.
[Claim 9] A multimedia platform included in a digital processing apparatus, the
multimedia platform comprising:
at least one nonvolatile memory; and
a multimedia processor, the multimedia processor setting a route in accordance
with a route control signal received from a main processor such that the main processor
accesses the nonvolatile memory or accessing the nonvolatile memory to perform a
process in accordance with a control command, the control command corresponding to a
boot command or a process command received from the main processor,
wherein the nonvolatile memory and the multimedia platform are formed in one
chip.
[Claim 10]
The multimedia platform of Claim 9, wherein the multimedia processor
comprises:
a processor core, the processor core controlling a route in accordance with the
route control signal and performing a process in accordance with the control command;
a host interface, the host interface interfacing with the main processor and
delivering the control command to the processor core, the control command being
received from the main processor;
a first NAND interface, the first NAND interface being coupled to the main processor for accessing the nonvolatile memory;
a second NAND interface, the second NAND interface being coupled to the
nonvolatile memory; and
a route setting unit, the route setting unit being connected to the processor core,
the first NAND interface and the second NAND interface, the route setting unit setting a
route such that the second NAND interface is connected to the processor core or the first
NAND interface in accordance with a route control of the processor core.
[Claim 11 ]
The multimedia platform of Claim 10, wherein the route setting unit sets a route
such that the second NAND interface and the first NAND interface are connected before
the route control is performed.
[Claim 12]
The multimedia platform of Claim 10, further comprising at least one from a
group consisting of a first volatile memory and a second volatile memory, the first
volatile memory being a temporary memory device of the main processor, the second
volatile memory being a temporary memory device of the multimedia processor.
[Claim 13] The multimedia platform of Claim 12, wherein the multimedia processor further
comprises an SD interface, the SD interface allowing the processor core and the second
volatile memory to be coupled to each other.
[Claim 14]
The multimedia platform of Claim 9, wherein the main processor delivers an
output signal as the route control signal to the multimedia processor, the output signal
being outputted by any one pin of GPIO (general purpose I/O) pins and address pins.
[Claim 15]
The multimedia platform of Claim 9, wherein the main processor renews a
pre-designated register value by sending the route control signal through a Data I/O, and
the multimedia processor verifies the reception of the route control signal based on the
renewal status of the register value, the register value being present in the multimedia
processor.
PCT/KR2006/002277 2005-07-28 2006-06-14 Multimedia platform WO2007013736A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050069067A KR100751094B1 (en) 2005-07-28 2005-07-28 Method for sharing non-volatile memory and apparatus having multimedia platform comprising a plurality of memories in one-chip
KR10-2005-0069067 2005-07-28

Publications (1)

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WO (1) WO2007013736A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016123115A1 (en) * 2015-01-29 2016-08-04 Qualcomm Incorporated Package-on-package (pop) structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100885923B1 (en) 2007-06-19 2009-02-26 삼성전자주식회사 Semiconductor memory device for operating of a plurality of operating characteristics and method for controling the device
KR20090095955A (en) 2008-03-07 2009-09-10 삼성전자주식회사 Multi port semiconductor memory device for providing direct access function in shared structure of non-volatile memory and multi processor system having the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980036812A (en) * 1996-11-19 1998-08-05 김광호 Multilayer semiconductor chip package and its manufacturing method
US6025648A (en) * 1997-04-17 2000-02-15 Nec Corporation Shock resistant semiconductor device and method for producing same
KR20020067752A (en) * 2001-02-19 2002-08-24 (주)씨앤에스 테크놀로지 The one chip asynchronous microprocessor Inter Processor Communication circuit
KR20040090874A (en) * 2003-04-18 2004-10-27 조덕수 Detachable Camera Module, Mobile Phone and Control Method thereof
US20050010712A1 (en) * 2003-07-08 2005-01-13 Young-Jun Kim Devices and methods for converting remote device formats to host device formats for access to host associated resources

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980036812A (en) * 1996-11-19 1998-08-05 김광호 Multilayer semiconductor chip package and its manufacturing method
US6025648A (en) * 1997-04-17 2000-02-15 Nec Corporation Shock resistant semiconductor device and method for producing same
KR20020067752A (en) * 2001-02-19 2002-08-24 (주)씨앤에스 테크놀로지 The one chip asynchronous microprocessor Inter Processor Communication circuit
KR20040090874A (en) * 2003-04-18 2004-10-27 조덕수 Detachable Camera Module, Mobile Phone and Control Method thereof
US20050010712A1 (en) * 2003-07-08 2005-01-13 Young-Jun Kim Devices and methods for converting remote device formats to host device formats for access to host associated resources

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016123115A1 (en) * 2015-01-29 2016-08-04 Qualcomm Incorporated Package-on-package (pop) structure

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