WO2007012187A1

WO2007012187A1 - System and method for assembling packaged integrated circuits using insulated wire bond

Info

Publication number: WO2007012187A1
Application number: PCT/CA2006/001230
Authority: WO
Inventors: Robert Lyn; John Persic; Youn-Kyu Song; Yong-Qiang Guo; Lee Upshall; Juan Florencio Munar; James Snell; Y. C. Koo; Russell Anderson
Original assignee: Microbonds Inc.
Priority date: 2005-07-26
Filing date: 2006-07-26
Publication date: 2007-02-01
Also published as: JP2009503822A

Abstract

Devices and methods are providing for reducing the effect of replacing a bare bonding wire with an insulated bonding wire in the IC packaging process. Specifically, methods and devices are presented for limiting the changes required to the assembly process, thereby allowing faster and cheaper conversion of the current assembly process.

Description

SYSTEM AND METHOD FOR ASSEMBLING PACKAGED INTEGRATED CIRCUITS

USING INSULATED WIRE BOND

[0001] The present invention relates generally to a system and method for assembling integrated circuits and specifically to a system for doing so when wire bond used for the assembly is protected by an insulated coating.

BACKGROUND OF THE INVENTION

[0002] Miniaturization is a feature of modern electronic devices. Most miniaturization occurs in integrated circuits (ICs), which may, for example, be prepared on silicon wafers through various known techniques. ICs, which generally contain densely packed electronic circuits and are at the heart of all intelligent electronics devices, must be connected to the outside world to allow access to their functions.

[0003] However, ICs typically need to be connected to other devices to make a complete electronic-based device. For example, ICs may need to be connected to other ICs or to other electronic components, either directly or through a circuit board. For example, in wire-bonded devices ICs are provided with input and output ports comprising bonding pads. The bonding pads allow wires to be connected or bonded to the ports to facilitate making a functioning device.

[0004] However, the ICs are so small and fragile that it is often too difficult to manipulate them directly during a manufacturing process. Accordingly, the ICs are processed into packaged ICs, which reduce the problems associated with using unpackaged ICs in the manufacturing process.

[0005] A standard packaging process for Organic Plastic Encapsulated Modules is described as follows. A number of ICs are typically produced on a single silicon wafer. Accordingly, the ICs are sawed or diced from the wafer into individual ICs, which are also referred to as 'die'. Each die is attached to a bonding substrate. Generally, multiple dies are attached to a single bonding substrate to improve efficiency in the manufacturing process. The IC/substrate combination is cleaned with a plasma to remove foreign contamination or oxides that may inhibit the next step, which is wire bonding.

[0006] The wire bonding involves taking a fine conductive bare wire and welding it from a connection pad on the IC to a connection pad on the substrate. The substrate to which the IC is attached includes a number of bond pads, which are sometimes referred to as bond fingers or lead fingers. These bond fingers are typically located around the outside edge of the substrate and are electrically isolated from each other to inhibit short circuits. The wire bonding process electrically connects bond fingers on the substrate to corresponding IC bond pads via bare gold bonding wire. The bond fingers are typically routed along the substrate to leads or pads (typically metal or solder ball connections), which may then be electrically connected to other components as needed to complete the electrical device.

[0007] The wire bonded IC/substrate combination is often cleaned again with plasma before the molding stage, or encapsulation. The primary purpose of this cleaning is to remove foreign contamination before the next stage begins.

[0008] During the molding stage, a polymeric material with fillers is injected at high pressure to encase the wires and IC in a protective epoxy dielectric for physically shielding the wire bonded IC/substrate combination from the environment. The previous plasma clean stage enhances the adhesion of the molding epoxy to the substrate, which covers the entire IC, all bonding wires and a corresponding substrate portion. The entire assembly is then cured.

[0009] Once encased, leads or conductors, such as solder balls for example, are attached to the substrate. If the substrate is in multiple device strip form, it is then cut into individual components, which are the desired packaged ICs.

[0010] The process outlined above is described in detail in "From dicing to packing: Examining the packaging process", Patrick McKinney, Advanced Packaging, March 2001. This process is typical for price-performance types of ICs such as application specific integrated circuits

(ASICs), microprocessor units (MPUs), digital signal processors (DSPs) and the like. The package configurations available include ball grid arrays (BGAs), quad flat packs (QFPs), chip scale packages (CSPs) and the like, which define the basic physical geometry, size and style of the packaged IC.

[0011] The wires used in this type of wire bonding are typically bare. Accordingly, the IC packaging and bonding pads allow the inputs and outputs for the IC to be separated by a gap sufficient that the wires can be placed without a short circuit occurring. However, the use of bare wires means relatively large spaces between wires is required, which places constraints upon the bond wire pattern. The requirement for such large gaps frustrates miniaturization and yields unnecessarily long circuit paths, which reduce the speed and efficiency of the assembled device.

[0012] Accordingly it is desired to introduce insulated bonding wire into the standard packaging process. The use of insulated bonding wire has long been sought after in microelectronics. The ability to place bond wires in direct physical contact with each other, without the risk of electrical short circuit opens up new flexibility for IC package designs from increasing input/output connections, to improved performance, size and time-to-market.

[0013] Recently, therefore, it has been proposed that insulated wires be used in lieu of bare wires. For example, U.S. Patent Number 6,177,726, titled "SiO₂ Wire Bond Insulation in Semiconductor Assemblies" issued January 23, 2001 to Manteghi describes a process that involves post-wire bonding insulation of bare wires. However, since the wires are bare during wire bonding, they must be kept apart to inhibit electrical short circuits. Accordingly, this solution limits the potential of using insulated wires.

[0014] Therefore, it is much more desirable to be able to use a "pre-insulated' bonding wire in order to achieve maximum flexibility. U.S. Patent Number 5,396,104, titled "Resin Coated Bonding Wire, Method of Manufacturing the Same, and Semiconductor Device" issued to Kimura and U.S. Patent Number 4,860, 941, titled "Ball Bonding of Aluminum Bonding Wire" issued to Otto describe insulated bonding wires.

[0015] Insulated bonding wires such as those exemplified above allow the highest degree of point-to-point connection flexibility, enabling configurations ranging from high density "on- Chip" interconnects to complex Chip-to-Chip assembly. However, when insulated bonding wires are introduced into the packaged IC assembly process, obstacles are encountered. Since such assembly processes are well established, it is desirable to limit the changes required to the assembly process when using an insulation-coated, or insulated, wire.

[0016] Accordingly, it is an object of the present invention to obviate or mitigate at least some of the above-mentioned disadvantages. SUMMARY OF THE INVENTION

[0017] The present invention attempts to reduce the effect of replacing a bare bonding wire with an insulated bonding wire in the IC packaging process. Accordingly several methods are presented for limiting the changes required to the assembly process, thereby allowing faster and cheaper conversion of the current assembly process.

[0018] In accordance with an aspect of the present invention there is provided a process for assembling an integrated circuit/substrate combination into an integrated circuit package using bonding wire having an insulated coating, the process comprising the steps of: cleaning the IC/substrate combination using a plasma; wire bonding the IC/substrate combination using the insulated bonding wire controlling several aspects of the pattern of bonded wires in three dimensions; cleaning the wired IC/substrate combination using a reduced power plasma cleaning device configured to remove contamination while minimally affecting the coating of the insulated bonding wire; molding the wire bonded IC/substrate combination using a molding tool configured to encase the wire bonded IC/substrate combination in an epoxy at a optimized speed, thereby limiting damage to the insulated bonding wire; and curing the epoxy for providing a packaged IC that protects the wire bonded IC/substrate from direct exposure to the environment.

[0019] In accordance with a further aspect of the present invention, there is provided a method for stitch bonding an integrated circuit (IC) to a substrate using bonding wire, the bonding wire being bonded at one end to the IC, the method comprising the steps of: establishing a Tool Inflection Point no higher than 5 mils; using the established Tool Inflection Point for effectively creating a bond at a bond site on the substrate.

[0020] In accordance with a further aspect of the present invention, there is provided a method for ball-stitch bonding an IC to a substrate using bonding wire having an insulated coating on a ball-stitch bonding machine, the method comprising the steps of: arcing a free end of the insulated bonding wire, wherein the insulated coating splits allowing the bonding wire to create a free air ball; creating a ball bond at a bond pad on the IC; using a capillary for bending the wire and forming a loop profile; and creating a stitch bond at a bond finger on the substrate using a low Tool Inflection Point (TIP) for creating the bond, thereby creating an electrical connection between the IC and the substrate. [0021] In accordance with yet a further aspect of the present invention, there is provided a method for effectively bonding wire to a bond site, the method comprising the steps of: hitting the bond site a first time for creating the bond; retreating to a predetermined height; and hitting the bond site a second time.

[0022] In accordance with yet a further aspect of the present invention, there is provided a packaged integrated circuit (IC) comprising an IC attached to a substrate, the IC being electrically coupled with the substrate via bonding wire, the bonding wire being bonded at one end to the IC and at the other end to the substrate, at least one of the bonds comprising a two hit stitch bond.

[0023] In accordance with yet a further aspect of the present invention, there is provided a method for configuring a cleaning device to remove contamination from an integrated circuit/substrate combination that has been wire bonded using a insulated bonding wire while minimally affecting the coating of the insulated bonding wire, the method comprising the steps of: using predefined settings for testing a test substrate and an insulated bonding wire sample; analysing the test substrate to determine that the cleaning device is set at a sufficiently high power configuration for effectively cleaning the substrate from contamination; analysing the insulated bonding wire sample to determine that cleaning device is set at a sufficiently low power configuration for removing minimal coating from the insulated bonding wire; and iteratively repeating the test using modified settings to determine at least one setting that satisfies both of the previous steps.

[0024] In accordance with yet a further aspect of the present invention, there is provided a method for configuring insulated wires to be compatible with a mold tool, the insulated wires being wirebonded between an IC and a substrate, the wires subsequently to be covered in a polymeric material, the method comprising steps of: limiting a loop height of the wires, thus minimizing drag on the wires due to the flow of the polymeric material, and avoiding crossing points in regions and geometrical configurations that are susceptible to physical damage by the mold process.

[0025] In accordance with yet a further aspect of the present invention, there is provided an integrated circuit (IC)/substrate combination wherein the IC and substrate are electrically connected via insulated bonding wire bonded therebetween, the insulated bonding wire configured to be compatible with a molding tool by having: a limited loop height of the wires; and a geometrical configuration that avoids crossing points in regions susceptible to physical damage during a subsequent molding process.

[0026] In accordance with yet a further aspect of the present invention, there is provided a method for configuring a molding tool to encase, in a molding compound, an IC/substrate combination that has been wire bonded using an insulated bonding wire, while limiting damage to the coating of the insulated bonding wire, the method comprising the steps of: initially inserting the molding compound at a minimal flow rate until a flow wall is established; and increasing the insertion speed of the epoxy to an increased flow rate once the flow wall has been established; wherein the duration of the molding process is sufficient to completely cover the IC/substrate combination without voids but less than the gel time of the molding compound.

[0027] In accordance with yet a further aspect of the present invention, there is provided a test kit including components for building a tester to test a dielectric breakdown point of an insulated bonding wire, the test kit comprising: a base for supporting the tester; a pair of conductive rods, one of the rods to be electrically coupled to an anode of a power supply and the other of the rods to be electrically coupled to a cathode of the power supply, wherein the pair of conductive rods are to positioned a predefined distance apart; a slide for supporting the insulated bonding wire to be tested such that the insulated bonding wire is in contact with each of the conductive rods; a first coupling means for coupling the pair of conducting rods to the base; and a second coupling means for coupling the insulated bonding wire to the slide.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] An embodiment of the present invention will now be described by way of example only with reference to the following drawings in which:

Figure 1 is a flowchart illustrating operation of the wire bonding process;

Figure 2 is a diagram of a wire bonder for creating a ball bond; Figure 3a is a diagram illustrating a standard TIP for a stitch bond (prior art); Figure 3b is a diagram illustrating a capillary for a stitch bond in accordance with the present invention; Figure 4 is a diagram illustrating possible LF2 positions for the second bond;

Figure 5 is a schematic diagram illustrating the improved wire density of an IC using a single row configuration;

Figure 6 is a schematic diagram illustrating the improved wire density of an IC using a multi-row configuration;

Figure 7 is a picture of a free air ball of an insulated wire;

Figure 8a is a perspective view of an assembled test kit for testing the dielectric breakdown voltage;

Figure 8b is a schematic diagram of the electrical connection for the assembled kit illustrated in Figure 8a;

Figure 8c is a perspective view of a test substrate for supporting the insulated wire during testing;

Figure 9 is a block diagram illustrating a molding tool;

Figure 10 is a diagram illustrating sensitive wire regions during the molding process; Figure 1 Ia is a top view of a bonded IC/substrate combination illustrating regions of wire crossing that are sensitive during the molding process; Figure l ib is a side view of a bonded IC/substrate combination illustrating regions of wire crossing that are sensitive during the molding process;

Figure 12 is a block diagram of an alternate sample tester to that shown in Figure 8a; Figure 13a is a diagram illustrating a magazine configured to reduce power of the plasma cleaning process;

Figure 13b is a diagram illustrating an alternate embodiment of Figure 13a; Figure 14a is a diagram illustrating an alternate embodiment of Figures 13a and b; and Figure 14b is a diagram illustrating an alternate embodiment of Figures 13a, b and c;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0029] For convenience, like numerals in the description refer to like structures in the drawings. Referring to Figure 1, a flow chart illustrating a process for providing a packaged IC using insulated bonding wire is illustrated generally by numeral 100.

[0030] At step 102, ICs are sawed or diced from a wafer into individual ICs. At step 104, the ICs are attached to a bonding substrate. At step 106 the IC/substrate combination is cleaned in preparation for wire bonding. Typically the cleaning is achieved using plasma, although a person of ordinary skill in the art will appreciate that other methods for cleaning the IC/substrate combination may be used. Examples of alternate cleaning materials include chemical clean, ultraviolet (UV) ozone and other methods. At step 108 the IC bonding pads are connected to the substrate bonding pads using insulated gold bonding wire. At step 110 the bonded IC/substrate combination is plasma cleaned again. At step 112, during a molding process, an epoxy is injected to encapsulate the wires and the IC and protect them from the environment. The entire assembly is then cured. At step 1 14 leads or conductors, typically in the form of solder balls, are attached to the substrate. At step 116 the substrate is cut into individual packaged ICs. The following detailed description of the process 100 reveals changes made to facilitate the use of insulated wire.

[0031] Steps 102 - 106 can be conducted in accordance with the state of the art, as they occur before the introduction of the insulated wire to the IC assembly process. In step 108, the insulated wire is bonded between the IC and the substrate. Two types of wire bonders are usually used for wire bonding. One is referred to as a ball bonder and the other is referred to as a wedge bonder. The following describes the application of insulated bond wire using a ball bonder. Wire bonding using the ball bonder comprises a ball bonding process, also called a first bond, and stitch bonding process, also called a second bond or wedge bond. The ball bonding is usually performed on the bond pads on the semiconductor die and the stitch bonding is performed on the lead fingers on substrates. In the present embodiment, wire bonding to the IC bonding pad is achieved using an automatic ball-stitch wire bonding method, which is available on industry standard equipment provided by Kulicke & Soffa, ASM, Shinkawa, Kaijo, and ESEC for example.

[0032] The general operation of a ball-stitch wire bonding machine is described as follows. The device/substrate combination is heated on a heater block below the substrate to a defined temperature. A free end of the insulated wire is sparked, creating a free air ball (FAB). The wire bonding machine uses pressure and ultrasonic vibration at elevated temperature to bond the FAB to an I/O pad on the IC, referred to as a first bond, or ball bond. The wire bonding machine then positions itself over a corresponding bonding pad, or finger, on the substrate. The wire bonding machine uses pressure and ultrasonic vibration bond the insulated wire to the substrate, referred to as a second bond or stitch bond, and then sever the insulated wire, thus creating an electrical connection, or loop, between the IC and the substrate. A free air ball is created again from the free end of the wire, which is positioned over the IC and the next loop is created. The process repeats itself until all desired wire bond connections have been completed.

[0033] Referring to Figure 2, an example of ball-stitch bonding machine for creating the first bond is illustrated generally by numeral 200. The insulated bond wire 201 is shown extending from a spool 202 remote from a free end 204. In the present embodiment, the insulated bond wire 201 is X- Wire™ from Microbonds Inc. and has an insulation of approximately 0.1-0.5μm thick. The spool 202 acts as a source of the insulated wire 201. A conductive or metal capillary 206 is also shown having a central bore or tube 207, through which the insulated wire 201 is fed. The capillary 206 acts as a wire holder during the formation of a ball for ball bonding. Although many types of material may be used for the capillary due to an advantageous combination of strength, conductivity, and ease of manufacture, a tungsten carbide capillary is preferred.

[0034] A wire clamp 208 is located above the capillary 206 and a distance from a surface 210 to which the wire 201 is to be bonded. An Electronic Flame-Off (EFO) wand 212 is shown in position adjacent to the free end 204 of the wire 201, and generally below the capillary or wire holder. Also shown is an ultrasonic transducer arm 214 which generates sufficient ultra-sonic and compressive energy to bond a ball formed at the free end of the wire to a surface.

[0035] The operation of the above reference ball-stitch bonding device is briefly described as follows. The insulated wire is allowed to pass through a hole in the centre of the capillary 206 until the free end of the wire extends beyond the end of the capillary. The wand 212 releases a charge or arc of electrical energy at the wire 201. This energy then jumps to the wire 201 and, even though the wire is insulated, the energy exceeds the electrical breakdown potential of the insulation and breaks through the insulation to the ground, which in the present embodiment is the electrically conductive capillary 228. In the process the free end of the wire 201 melts, the insulation splits and a suitable ball is formed. The details of a ball-stitch bonder for use with insulated bonding wire is detailed in pending U.S. Patent Number 6,896,170, titled "Wire Bonder for Ball Bonding Insulated Wire and Method of Using Same", by Lyn et al. [0036] Further, it should be noted that the FAB size for insulated wire would likely differ to the FAB size for bare wire under the same parameters. Typically, the FAB size for the insulated wire is expected to be larger than the FAB size for bare wire. Referring to table 1 below, a comparison between bare wire and X-Wire™ insulated wire, provided by Microbonds Inc, is shown for different FAB size parameters. Accordingly, one skilled will appreciate in the art that the parameters of the bonding machine may need to be set differently when insulated wiring is used in order to provide a desired FAB size.

Table 1

[0037] For the second bond, there are several parameters to consider including Tool Inflection Point (TIP), Constant Velocity Motion (CV), ultrasonic power, time, force, temperature, Loop Factor 2 (LF2), loop profile trajectory and contact angle, stitch option and other related second bond parameters. Referring to Figure 3a, a diagram illustrating the position for creating the second bond in accordance with the prior art is illustrated generally by numeral 300. The IC 302 is attached to the substrate 304, and the free end of the bare wire 306 has already been bonded to the IC 302, as described above. The capillary 206 has its clamps closed and is positioning itself to make the second bond. The TIP 308 represents the distance between the capillary 206 and the substrate 304 when the downward motion for creating the second bond slows to the CV setting. The standard CV is relatively low compared to the high-speed descent from the point where the wire loop formation is concluded, which is the highest point in the wire formation cycle.

[0038] Referring to Figure 3b, an example of creating the second bond in accordance with the present embodiment is illustrated generally by numeral 320. The free end of the insulated wire 322 has been bonded to the IC 302. In order to efficiently create the second bond, it has been determined that a lower TIP and higher CV than is standard in the art should be used. Accordingly, in the present embodiment, the TIP is approximately half that of the standard implementation and the CV is approximately twice the standard CV. It has been determined that a sudden increase in velocity with a low TIP induces a higher impact, which is preferable considering the wire 322 comprises an insulated coating. Specifically, it has been found that a TIP less than 5 mils, or more preferably between 2-3 mils, and a CV between 1.0-2.5 mil/m-sec, depending on the wire size, provide the required impact.

[0039] Accordingly, the second bond strength is improved as compared to the standard method for insulated wire. The process described above has consistently yielded strong second bonds. Specifically, using the insulated wire and the TIP and CV as described above provides an average bond strength of 5-8 gf using mid span pull in accordance with MIL-STD-883 Test Method 2011.7 using insulated 4N Be modified gold wire in compliance with ASTM F72-95 having a wire length of 200 mil.

[0040] Referring to Figure 4, an example of possible LF2 positions is illustrated generally by numeral 400. LF2 defines the horizontal position of the capillary at the TIP with reference to the programmed bond location on the substrate as it marks the last step of the CV descent to substrate bonding finger to form the second bond. If the capillary is directly above the programmed bond location, the LF2 is said to be 0. If the capillary is between the IC and the finger, the LF2 is said to be positive. If the capillary is beyond the bonding finger, from the perspective of the IC, the LF2 is said to be negative. Typical LF2 values in wire bonding are positive in order reduce slack between wires, thus inhibiting a short circuit. However, since the present embodiment implements insulated wire, a short circuit by adjacent wires is less of a concern. Further, as will be described with reference to the molding process 112, a certain degree of slack between adjacent wires may inhibit the creation of short circuits during molding. Therefore, the present embodiment can take advantage of using a negative LF2 for creating the second bond.

[0041] As previously described, the energy provided by the EFO exceeds the electrical breakdown potential of the insulation. Accordingly, it can be seen that the wire bonding process described above has the ability to 'burn off coating on the wire during ball formation (for the IC-side connection), while maintaining as much coating on the rest of the wire as possible. In the present embodiment, the insulated coating is maintained down to the neck of the second bond and on the topside of the ball of the first bond. [0042] The bonding process described above facilitates bonding of insulated wires in a variety of possible configurations. Since the insulated wire can be bonded between the IC and the substrate with a minimal reduction of the insulation, the wire configurations can be significantly more dense and complex than in the prior art.

[0043] For example, referring to Figure 5, a schematic diagram illustrating an improved density of the bonding wires per unit length of the periphery of an IC. Recent experiments have shown that the wires can be as close as 0.4 μm apart. Since the wires are insulated, there is little concern if they come into contact with each other. Such a density improvement increases the number of input/output ports that the IC can make available to other components, which may help further miniaturize electronic components.

[0044] Referring to Figure 6, the number of available input/output ports can be further increased by increasing the number of rows of input/output ports so that they are no longer limited to being placed along the periphery of the IC. Since the wires are insulated, the risk of creating a short using such a layout is greatly reduced.

[0045] Furthermore, for the layouts illustrated in both Figures 5 and 6 more complex connections are possible as the wires are allowed to physically come into contact with each other with little risk of creating a short. This greatly expands the potential circuit layout for a chip designer.

[0046] For the wire bonding described above, it is preferable that the wire comprise a gold base metal or copper base metal bond wire. In the present embodiment, a gold base metal bond wire is used. Further, it is preferable that the bond wire is of diameter 0.005" or less. Yet further, it is more preferable for the diameter of the wire to be less than 0.002", and most preferable to be less than 0.001". However, a person of ordinary skill in the art will appreciate that the diameter of the bond wire may vary in accordance with the requirements of the specific implementation.

[0047] Referring to Figure 7, a picture of a free air ball is shown for an insulated wire as described above. In the present embodiment, the insulated coating and metal surface exhibit sufficient adhesion upon EFO free air ball formation. As will be apparent from the picture, the insulated coating is present on the ball and is represented by the "watermelon stripes". Accordingly, it can be seen that the insulation splits when arced during ball bonding.

[0048] Although the present embodiment describes use of a ball-stitch bond for electrically connecting the IC with the substrate, a person of ordinary skill in the art will appreciate that the invention comprehends other bonding methods including wedge-wedge bonding using a wedge bonder.

[00491 In an alternate embodiment, a double hit stitch technique is implemented to improve the stitch bond. As previously described, in the normal stitch bonding process ultrasonic power and force are applied through the bonding tool, or bonding capillary, at an elevated temperature to create a bond between the bonding wire and the bonding pad on the substrate. Prior to applying ultrasonic power and force, the bonding capillary needs to touch down and be kept in contact with the lead finger on the substrate. The bond strength of the wire should be high enough to meet the industry specification necessary to overcome assembly processes and reliability tests.

[0050] Insulated wire requires the wire bonder to crack the insulated coating during bonding. It is beneficial to have a double hit on the stitch bonding process to aid the cracking of the coating and expose metal for bonding and to improve the tendency of fish tailing or peeling. Using the double hit stitch technique, as described below, the stitch bonding process, excluding the looping process, is repeated twice at the same bond site. After the first hit of the stitch bond is made the bonding capillary is lifted up to a programmed height and another hit, or second hit, is made at the same bond site. In each touchdown, ultrasonic power and force are applied. In the present embodiment, the programmed height is sufficient to sever the insulated wire prior to the second hit. However, it is anticipated that this need not be the case.

[0051] Even though the stitch bonding process is repeated on the same bond site, a bond-offset from the first hit of the stitch bond can be applied. A positive bond offset setting offsets the second hit of the stitch bond towards the ball bond, and negative bond offset setting offsets the second hit of the stitch bond away from the ball bond.

[0052] Once the wire bonding 108 is completed, the process continues with the plasma cleaning in step 1 10. As previously described, the purpose of the plasma cleaning 110 is to remove possible contamination from the IC/substrate combination including absorbed and airborne contaminant species that may affect the adhesion of the molding compound. Accordingly, this step 1 10 may not be required if the molding process 1 12 is performed shortly after the wire bonding 108. However, since the molding process 112 is typically performed separately from the bonding 108, either at a different facility or a different region of the same facility, it is likely that significant time will pass between these steps. Accordingly, the post wire bonding plasma clean 110 is a typical step in the assembly process.

[0053] However, the plasma clean 110 may reduce the effectiveness of the insulated bonding wire by inadvertently removing a portion of the insulation from the insulated wires, thereby exposing bare wire to the potential for short circuits. This is especially true since the insulated wires are often positioned in extremely close configurations, including possible cross- configurations.

[0054] Accordingly, the plasma clean step 110 is modified to limit the damage to the insulation to inhibit conductivity between wires. Specifically, the power of the plasma is reduced so its cleaning properties are still effective while minimizing the effect on the coating of the insulated wire. Further, typical plasma selections for the cleaning process 110 include Argon (Ar) and an Argon Oxygen gas mixture. While the latter is suitable for bare wires, it is preferable to use the former for the present embodiment as the Oxygen may react with the coating compound of the insulated wire, further limiting its effectiveness. For example, the oxygen may affect coating characteristics such as moisture resistance, ductility, dielectric breakdown and the like. Since both are commonly used, the selection of Ar has little impact on the implementation of the plasma cleaning process 110.

[0055] A person of ordinary skill in the art will appreciate, however, that there are a number of different types of plasma cleaners in use for the plasma cleaning step 110. Further, the operation of the same plasma cleaning device in different facilities may differ due to different environmental conditions as well as the physical condition of the plasma cleaning device. Accordingly, the power for each plasma cleaning device is configured independently using an evaluation kit.

[0056] The evaluation kit provides the necessary materials and recommended instructions for evaluation of pre-molding or pre-rework low power plasma process parameters. The following description is intended to provide a guideline for the evaluation process. A person skilled in the art will appreciate that modification of the guideline may be necessary in order to meet a particular users' requirements.

[0057] Referring to Figure 8a, a sample tester built using the evaluation kit is illustrated generally by numeral 800. The sample tester 800 is used for conducting a dielectric breakdown test. The tester 800 comprises a plastic or glass base plate 802 and a pair of stainless steel rods

804 separated by width W. The rods 804 are held in place using spring loaded conductive clips

(not shown). In the present embodiment, W=25mm. A glass slide 806 comprising one or more sample insulated wires 808 to be tested is placed across the rods 804. The glass slide is placed on the rods 804 with the sample wires 808 facing down such that they are in direct contact with with rods 804.

[0058] Referring to Figure 8b, a schematic diagram illustrating the electrical connections for the tester illustrated in Figure 8a is shown generally by numeral 820. One of the rods 804 is electrically connected to a positive output of a power supply 822, while the other of the rods 804 is electrically connected to a negative output of the power supply 822. In the present embodiment, the power supply 822 is capable of delivering 0-200V at lAmp. However, the necessary circuit is provided to limit the current just above the fusing current of the wire. A voltage meter 824 is connected to the rods 804 in parallel with the power supply 822. The voltage meter is capable of measuring up to the maximum value of the power supply, which is 200V in the present embodiment.

[0059] Referring to Figure 8c, the configuration of a test substrate 860 used to prepare the sample wires 808 to be tested is shown. In the present embodiment, the test substrate 860 is greater than 15cm long. Preferably, the test substrate is similar in thickness to the actual substrate used for ensuring the best results. Wire posts 862 are placed across the width of the test substrate 860 at opposite ends. The wire posts 862 are attached using a suitable die attach material. Each wire post 862 includes a pair of grooves (not shown) facing upward for receiving the sample wires 808. The sample wires 808 are suspended approximately lmm above the surface of the test substrate 860 by the wire posts 862. The sample wires 808 are secured to the wire posts 862 using an adhesive 864 such as Kapton tape for example. The sample wires 808 are placed across the wire posts 862 such that they are slightly under tension.

[0060] The operation of using the evaluation kit described above in order to determine the desired parameters for the pre-molding plasma clean 110 is detailed as follows.

[0061] The wire to be tested 808 is loaded onto the test substrate 860 as illustrated in Figure 8c. The test substrate 860 is placed into the plasma chamber in the same manner as the intended process condition. It should be noted that for low power plasma in a multi-layer plasma chamber, a single layer should be used. Experimental results have shown a significant difference in the effect of the plasma clean between different layers. Accordingly, for consistency, a single layer should be used. Further, the optimal placement of the substrates in the plasma chamber is a checkerboard pattern. It will be appreciated, however, that other placement patterns may be used with a nominal difference in the results.

[0062] A low power plasma clean is initiated in accordance with the recommended conditions provided in Table 2. As previously described, the plasma of choice is Argon.

Table 2 [0063] The duration of the plasma clean is initially set near the lower time limit. Once the plasma clean has been completed, the sample wires 808 are removed from the test substrate 860. Contact angle measurements are performed on the test substrate 860 at a number of different locations. The contact angle measurement is preferably performed within 60 minutes of the plasma clean.

[0064] In the present embodiment, at least three locations are analysed. The contact angle measurement is used to determine the "cleanliness" of the test substrate 860. The lower the contact angle, the "cleaner" the test substrate 860. If the contact angle is less than 30 degrees using deionized (DI) water with resistivity greater than 12 MΩ, then the test substrate is considered to be sufficiently clean. Otherwise, the duration of the plasma clean is increased and the test process is repeated until a minimum acceptable plasma clean duration is determined based on the contact angle measurement results.

[0065] In the present embodiment, the duration of the test is capped at 200 seconds. If this duration is reached without yielding a sufficient contact angle measurement, the power is increased and the process begins anew starting at the lower duration limit.

[0066] Once a suitable time limit has been established the sample wire 808 is tested to ensure that the plasma clean has not broken down the insulated coating. Accordingly, the sample wire 808 is removed from the wire post 862 and the portion of wire that was under the Kapton tape 864 is cut off. Since the piece off wire under the Kapton tape 864 was not exposed to the plasma it may distort the results of the dielectric breakdown test.

[0067] Six wire samples 808 are positioned for testing by adhering them to a glass slide 806. In the present embodiment, two sample wires 808 are tested per glass slide 806. Care must be taken to prevent the sample wires from being mechanically damaged during handling. For example, any nick, bend or coating damage by handling may affect the test results. Similarly, six wire samples that did not undergo plasma cleaning are tested as references.

[0068] Each of the glass slides 806 is tested as follows. The glass slide 806 is placed on the rods 804 with wire sample 808 face down. The sample wires 808 on the glass slides 806 are in contact with the rods 804 in four locations. Preferably, the glass slide 806 is centred based on a centreline between the rods 804. If the glass slide 806 is off centre, a different weight may be placed on each of the wire contact, therefore, affecting the accuracy of the test.

[0069] A DC voltage from the power supply 822 is applied and gradually increased while the wire is monitored under sufficient light. As soon as the wire breakdown occurs, current flow is detected in the power supply and the wire typically breaks into two pieces. The voltage increases are stopped and the voltage readout from voltage meter 224 is recorded. It should be noted that a typical dielectric breakdown voltage range for X- Wire™ is 30 to 80 V_DC-

[0070] The voltage is slowly increased again until the second wire break occurs, recalling that there are two wires per slide. The readout from the voltage meter is recorded and the voltage supply 822 is ramped down to zero in order to get ready to test the next wire sample 808.

[0071] The following data regarding the dielectric breakdown both reference and plasma treated samples is collected: an average of the six dielectric breakdown voltages; standard deviation of the data sets (reference and test sample); and a minimum dielectric breakdown voltage within the set.

[0072] What is considered to be an acceptable dielectric breakdown voltage shall be determined per design. The following is a guideline for generally acceptable values for X- Wire™. In order to be considered acceptable, the average dielectric breakdown voltage shall be less than 10% difference between the plasma treated wires and the non-plasma treated wires. Also, the minimum dielectric breakdown voltage readout shall be greater than 25 V_DC-

[0073] Therefore it can be seen that the range for the duration of the plasma clean can be determined using the test kit. The shortest time capable of providing a suitable contact angle measurement forms the lower end of the range and the longest time capable of providing suitable dielectric breakdown results forms the higher end of the range. Thus, the pre-molding plasma clean comprises a low power clean that cleans the IC/substrate combination but does not substantially affect the insulated coating of the bonding wire.

[0074] Referring to Figure 12, an alternate embodiment of a sample tester is illustrated generally by numeral 1200. In the present embodiment, the sample tester is a substrate 1202 comprising a plurality of bonding pads 1204 on one side of the substrate 1202 and a plurality of test points (not shown) on another side of the substrate 1202. The test points are electrically coupled with a corresponding one of the bonding pads 1204.

[0075] Two or more insulated bonding wires 1206 are bonding in a crossing configuration. A sample crossing configuration in illustrated in Figure 12. The crossing configuration ensures that the insulated bonding wires 1206 are in contact with each other.

[0076] In order to test a breakdown voltage of the wires in the present embodiment, a voltage is applied across two contacting wires via the test points. A voltage ramp is used to increase the voltage until a breakdown occurs in the insulation. The breakdown is identified by detecting a current flowing through one of the contacting wires. This is accomplished by monitoring the corresponding test points for the wire. The voltage is noted and can be used to determine whether or not the process is satisfactory, as previously described.

[0077] An advantage of using the sample tester 1200 of the present embodiment, is that the tester can continue through the process and, for example, may be used to determine breakdown voltages after encapsulation. This is accomplished since the user has access to the test points. Further, although not shown in Figure 12, the substrate may also include a dummy IC so that it more closely resembles a real IC/substrate combination.

[0078] As previously described, although plasma is used as the cleaning agent, other cleaning agents may be used. Accordingly, it will be appreciated by a person of ordinary skill in the art that the concept of configuring the cleaning device as described above may also be applied to those cleaning agents and mechanisms.

[0079] In alternate embodiments, standard plasma cleaning units may be used at standard power levels. In the following embodiments, an effective low-power plasma clean can be achieved by electrically isolating a carrier of the IC/substrate combination. Isolating the carrier reduces the direct plasma effect by maintaining the carrier at a floating potential with respect to the plasma field line, therefore reducing plasma damage to the insulated coating. Therefore a large volume plasma clean of insulated wire bonded chip carriers can be performed using either magazine loads or in-line plasma cleaners. These embodiments are described below.

[0080] In one embodiment a vertical magazine is implemented. Referring to Figure 13, a vertical magazine is illustrated generally by numeral 1300. In this embodiment, the vertical magazine 1300 includes a plurality of horizontal racks 1302 for shelving a plurality of the bonded IC/substrate combinations. Further, the vertical magazine 1300 includes four legs 1304 for support the vertical magazine 1300 and maintaining a distance between the vertical magazine XlOO and a surface upon which it is placed. The legs 1304 comprise a material selected for its stability during the plasma process. Such material includes, for example, glass, ceramics and semiconductor wafers. Other material that exhibits the desired characteristic may also be used.

[0081] Therefore, when the vertical magazine 1300 is placed in a plasma cleaner (not shown), it is placed onto one of the electrodes. Accordingly, the legs 1304 electrically isolate the vertical magazine 1300 from the electrodes, thereby reducing the intensity of the plasma clean and inhibiting significant damage to the insulated wires.

[0082] In another embodiment a horizontal magazine is implemented. Referring to Figure 13a, a horizontal magazine is illustrated generally by numeral 1350. The horizontal magazine 1350 is similar to the vertical magazine 1300, except for its orientation. The horizontal magazine 1350 includes vertical racks 1352 rather than horizontal racks 1302.

[0083] In yet another embodiment, an insulating sheet is provided for maintaining the electrical isolation. Referring to Figure 14, a further example of a vertical magazine 1400 is shown. In the present example, an insulating sheet 1402 is placed below the vertical magazine 1400 for isolating it from the electrode. Similarly, referring to Figure 14a, a further example of a horizontal magazine 1450 is shown. In the present example, an insulating sheet 1452 is placed below the horizontal magazine 1450 for isolating it from the electrode.

[0084] As illustrated in both Figure 14 and Figure 14a, the size and shape of insulating sheet matches, or close matches, the magazine footprint on the electrode.

[0085] Further, the insulating sheets are covering, and effectively shielding, an electrode on which they sit. This reduces a surface area of the electrode and a path that plasma can flow from a top electrode (for example, power) to a bottom electrode (for example, ground). If many magazines are placed on the electrode and are packed side-by-side with little or no spacing, the electrode may be covered to the point where plasma cannot flow from the top electrode to the bottom electrode. Therefore, space is left between magazines to maintain a sufficient plasma electrode ground to power ratio.

[0086] In accordance with yet a further embodiment, a gap between two adjacent IC/substrate combinations in a magazine is kept at distance low enough to inhibit creating a localized plasma zone or hot spot. For example, a double gap magazine load, where the gap is 12 mm between two adjacent IC/substrate combinations in a magazine, exhibits random hot spots upon cleaning.

However, a single gap magazine load, where the gap is 6 mm between two adjacent IC/substrate combinations in a magazine, exhibits little or no hot spots. It will be appreciated by a person of ordinary skill in the art that other distances about 6mm may also be acceptable and can be verified by experimentation. Further, it will be appreciated that the distances may vary depending on factors such as plasma flow rate, pressure, time, and the like.

[0087] Therefore, in the present embodiment, all slots in the magazine are filled. If there are an insufficient number of IC/substrate combinations to fill the magazine, dummy strips are used. A dummy substrate, such as an empty or discarded substrate for example, may be the most convenient material to be used as a dummy strip. However, other insulating material such as glass, ceramic, and the like may be used in its stead.

[0088] In accordance with a further embodiment, in order to further inhibit damage to insulated bonding wires on the IC/substrate combination, shielding is provided in the top and bottom of the magazine slots. Both the top and bottom of the magazine slots experience high energy plasma compare to the rest of the magazine. The bottom slot in the magazine is normally close to a plasma sheath zone that experiences high temperature electrons, a large concentration of ionized gas, and the like. The top slot in the magazine normally experiences a self bias relative to the magazine surfaces, commonly made by either metal or anodized metal materials. Accordingly, in order to shield the IC/substrate combination dummy strips are placed at both the top and bottom of the magazine.

[0089] The above described embodiments utilize the isolation of a magazine from an electrode for effectively reducing the plasma energy at an integrated circuit/substrate combination during the plasma cleaning stage. Table 3, below, illustrates sample effective parameters used for plasma cleaning. March Plasma's PX-1000 was used for the plasma cleaning process, although other plasma cleaners may also be used. A perforated ground shelf configuration (vertical side by side ground shelves with a power electrode at the bottom of the chamber) was used. The magazine was isolated using glass slides.

Table 3

[0090] The following performance characteristics were noted from the test. Although a perforated ground shelf configuration enhances gas flow during the plasma clean, other configurations, including a perforated power shelf configuration may also be sufficient. Further, applying the plasma process for longer than 5 minutes may cause excessive damage of the insulation coating. Yet further, non-uniform plasma clean is inherent when using magazine loads due to limited gas access at a center of the magazine load.

[0091] In accordance with yet a further embodiment, the high volume plasma clean of the integrated circuit/substrate combination is achieved using modified in-line plasma cleaning equipment. Similar to the previous embodiments, an integrated circuit/substrate combination is isolated from the electrode.

[0092] Accordingly, an in-line plasma cleaner is configured so that IC/substrate combinations entering the plasma cleaner on a chip carrier are isolated. The in-line plasma isolation can be achieved using two methods. In a first method, the chip carrier is isolated by providing isolation material between the carrier and a plasma cleaner railing used to support and transfer the chip carrier during the plasma cleaning process. In a second method, the plasma cleaner railing is configured to be isolated from the electrodes of the plasma cleaner.

[0093] Examples of high volume in-line plasma cleaning equipment would are suitable for such a modification include March Plasma's TRAK™ series of plasma treatment systems and Panasonic's PSX 303.

[0094] The above described embodiments utilize the isolation of a railing from an electrode or the isolation of a carrier from the railing for effectively reducing the plasma energy at a chip carrier location during the plasma clean stage. Table 4, below, illustrates sample effective parameters used for plasma cleaning. March's Plasma ITRAK In-line plasma cleaner having an electrode distance of two inches was used for the plasma cleaning process, although other in-line plasma equipment may also be used.

Table 4 [0095] The following performance characteristics were noted from the test. A lO second plasma time is sufficient to achieve a contact angle of less than 10 degrees. The sample is uniformly cleaned under in-line plasma conditions.

[0096] Once the plasma clean 1 10 is complete, the molding process 112 is performed by injecting a polymeric material, with or without filler, to encapsulate the wires and the IC and protect them from the environment. Although the present embodiment describes using a polymeric material, other molding compounds may be used as will be appreciated by a person of ordinary skill in the art. An example of a polymeric material is an epoxy based molding compound with silica filler. The entire assembly is then cured. However, the high pressure and temperature as well as motion of the polymeric material as it fills the mold during the molding process may potentially damage the wire coating either mechanically (via physical contact) as a combination of thermal and mechanical effects.

[0097] Accordingly, some of the issues to consider during the molding process include loops heights, sensitive crossing geometries and locations between wires, transfer parameters and compound selection criteria such as filler size and distribution, shrinkage upon curing and thermal expansion coefficient of the molding compounds.

[0098] It has been determined that lower loop heights will reduce the drag effects of the molding process on the bonded wires. Specifically, lower loop heights limit the force exerted on the wire bonds during the molding process, thereby reducing "lifting" of the wire contacts.

[0099] Further, lower loop heights maximize the structural strength of the wire and minimize wire sweep. Wire sweep occurs when bonded wires are moved from their original position in the horizontal plane during molding, as opposed to wire sag, which is in the vertical plane. Although wire sweep is less of a concern for insulated wires, reducing wire sweep limits the force exerted on the insulated coating at wire crossings. This, in turn, limits the likelihood that the pressure from the epoxy during molding will cause two crossing wires to "cut" into each other, thereby exposing bare wire and creating the potential for a short circuit. For example, for a PBGA having a BT substrate and a silicon IC thickness between 250μm and 400μm, and using X-Wire™ as the insulated wire, the preferential loop height is set to be below 266μm, for wire greater than 4 mm long.

[00100] The polymeric material is applied using a transfer molding press and associated mold tooling. Transfer molding involves having a piston and cylinder-like device built into the mold so that the epoxy may be injected into a cavity through a small orifice and runner system. Referring to Figure 9, a block diagram illustrating a molding tool is shown. The IC/substrate combination is place is a housing 902 having a 904 gate through which the epoxy is injected by a transfer press. The transfer press may comprise an electro-mechanical press or hydraulic press. The gate 904 is located in the side or corner of the housing 902, as is standard in the art.

[00101] In order to minimize "jetting", which is a turbulent flow in the epoxy caused when a thin section (flow into the gate) rapidly becomes thicker (flow out of the gate), a low transfer speed is set as the epoxy emerges from the gate until a flow wall is established. Once the flow wall is established, the transfer speed can be increased. Although, it may be preferable to use a lower speed than the recommended maximum transfer speed, the overall transfer speed is dictated by the size of cavity and the gel time of the selected epoxy. That is, the transfer speed should be sufficient for the housing to be filled with epoxy in less time than the gel time, or else the epoxy will begin to set during the transfer process. If the epoxy begins to set during the transfer process, the likelihood of damage to the insulated wires increases. Further, it will be apparent that a larger cavity may require a higher transfer speed than a smaller cavity for an epoxy having the same gel time.

[00102] Accordingly, it is desirable to select an epoxy for use in the molding process that has the following properties. A relatively large spiral flow at mold temperature is desired. Spiral flow is a measure of the viscosity and flow characteristics of a thermosetting plastic molding compound at molding temperature for semiconductor devices, and is measured in units of length. The shorter the spiral flow, which is measured in a specially designed test mold, the more drag force will be exerted on the wire during insertion of the epoxy into cavity, because the material will flow less naturally without transfer pressure. Viscosity and spiral flow are closely related. In the example given above, a spiral flow at molding temperature greater than 140cm is desired. It will be appreciated by a person skilled in the art that this particular spiral flow is specific to the example provided, and may differ for different examples.

[00103] As previously described, a relatively long gel time is desirable to reduce the likelihood of the epoxy gelling, since it causes a substantial increase in viscosity during transfer. Continuing on with the present example, a gel time greater than 30s is desired.

[00104] Further it is preferable that the molding compound, such as epoxy, has a low viscosity to limit interaction with the wires. Similarly, it is preferable that the epoxy filler has a relatively low filler size. In the present example, a viscosity less than 60 poise and an average filler size less than 19μm are desired. Similarly it is preferable that the epoxy comprises a relative low percentage of the filler content.

[00105] Yet further, it is preferable that the percentage of spherical filler particles relative to total filler be relatively high, since flow characteristic and wire damage are increased by ragged particles. In the present example, the percentage of spherical filler particles is greater than 80%.

[00106] However, even if all of the above precautions are heeded during transfer molding, there are still some regions and geometrical configurations that are susceptible to physical damage by the molding process. Accordingly, for these regions, it is preferable to control the positions of wire crossings and reduce the possibility of wires touching.

[00107] For example, referring to Figure 10, a block diagram illustrating a sensitive region near the gate is illustrated generally by numeral 1000. As can be seen, the area closest to the gate and the area along the edges of the housing, indicated by a vertical line pattern, are the most sensitive during the molding process. The region represented by a diagonal line pattern is less sensitive but caution should still be taken. Accordingly it is preferable to limit the number of wire crossings in these areas. It will be apparent that for housings wherein the second bond fingers are closely located to the gate, these regions will be more sensitive than for housings wherein the second bond fingers are located further from the gate.

[00108] Yet further, referring to Figure 11, a block diagram illustrating a sensitive wire configuration is illustrated generally by numeral 1100. As can be seen, the wire crossings closest to the substrate, indicated by a vertical line pattern, are the most sensitive during the molding process. The region represented by a diagonal line pattern is less sensitive but caution should still be taken. The insulated wire typically has less flexibility at this point and, therefore, has little "give" when under pressure during the molding process. Although the insulated wires are allowed to be designed in a cross configuration with little worry regarding a short circuit, as previously described, the pressure from the molding process may possibly cause crossed wires to cut through the insulated coating, thus creating a short. This risk is increased for crossed wires on a descending portion of the loop, and near the second bond, and close to the gate. Accordingly, these parameters should be considered when designing the layout of the IC/substrate combination, the bonding diagram, or when programming the wire bonder for manufacturing.

[00109] Steps 114 and 106, the ball attach and singulation do not need to change as they occur once the insulated wire and IC have been packaged. However, as is standard in the art, packaged ICs should be handled with care to minimize mechanical damage and electro-static discharge (ESD) concerns.

[00110] Accordingly, it will be appreciated that the process described above provides an

IC assembly process that facilitates the use of a bonding wire coated with an insulating material for assembling an IC package, while minimizing changes required to the overall assembly process.

[00111] The assembled IC package comprises a semiconductor device, a substrate upon which said semiconductor device is mounted, a semiconductor device mounted onto said substrate with an adhesive or soldered material, at least one bond terminal on the semiconductor device called the 'die bond pad', at least one bond terminal on the substrate called the 'bond finger', at least one bonded wire connecting the chip bond pad to the bond-finger in the form of a loop, and a bonding wire, wherein the wire is an insulated bonding wire

[00112] Although preferred embodiments of the invention have been described herein, it will be understood by those skilled in the art that variations may be made thereto without departing from the spirit of the invention or the scope of the appended claims.

Claims

What is claimed is:

1. A method for stitch bonding an integrated circuit (IC) to a substrate using bonding wire, the bonding wire being bonded at one end to the IC, the method comprising the steps of: (a) establishing a Tool Inflection Point no higher than 5 mils; (b) using the established Tool Inflection Point for effectively creating a bond at a bond site on the substrate.

2. The method of claim 1 where in the step of effectively creating the bond comprises:

(a) hitting the bond site a first time for creating the bond;

(b) retreating to a predetermined height; and (c) hitting the bond site a second time for strengthening the bond.

3. The method of claim 2, wherein the first and second hits at the bond site are offset.

4. A method for effectively bonding wire to a bond site, the method comprising the steps of:

(a) hitting the bond site a first time for creating the bond;

(b) retreating to a predetermined height; and (c) hitting the bond site a second time.

5. The method of claim 4, wherein the predetermined height is set such that the bonding wire is severed while retreating to the predetermine height.

6. The method of claim 4, wherein the bonding wire is an insulated wire.

7. The method of claim 4, wherein the second hit is offset from the first hit.

8. A packaged integrated circuit (IC) comprising an IC attached to a substrate, the IC being electrically coupled with the substrate via bonding wire, the bonding wire being bonded at one end to the IC and at the other end to the substrate, at least one of the bonds comprising a two hit stitch bond.

9. The packaged IC of claim 8, wherein the two hits of the bond are offset from each other.

10. A method for configuring a cleaning device to remove contamination from an integrated circuit/substrate combination that has been wire bonded using an insulated bonding wire, the method comprising the steps of:

(a) setting the cleaning device to predefined values for parameters of at least one of duration and power;

(b) cleaning a test substrate and an insulated bonding wire sample using the set parameters;

(c) analysing the cleaned test substrate to determine whether or not the parameters are sufficiently high for cleaning the substrate from contamination to yield a contact angle of less than 30°;

(d) analysing the cleaned insulated bonding wire sample to determine whether or not the parameters are sufficiently low to reduce a breakdown voltage of the insulated bonding wire sample by no more than 10%; and

(e) iteratively repeating the test using modified values for at least one of the parameters to determine at least one setting that satisfies both steps (c) and (d).

11. The method of claim 10, wherein the duration that the cleaning device is active does not exceed 200 seconds.

12. The method of claim 10, wherein the cleaning device is a plasma cleaning device.

13. A method for using a cleaning device to remove contamination from an integrated circuit/substrate combination that has been wire bonded using an insulated bonding wire, the method comprising the steps of:

(a) placing the integrated circuit/substrate combination onto a chip carrier;

(b) electrically isolating the chip carrier from the cleaning device; and

(c) cleaning the integrated circuit/substrate combination using standard parameters.

14. The method of claim 13, wherein the cleaning device is a plasma cleaning device.

15. The method of claim 14, wherein the chip carrier is a magazine and a plurality of integrated circuit/substrate combinations are placed in the magazine for being cleaned simultaneously.

16. The method claim 15, wherein the magazine includes legs comprising an isolating material for electrically isolating the magazine.

17. The method of claim 15, wherein the magazine is electrically isolated from the cleaning device by providing an isolating sheet there between.

18. The method of claim 17, wherein the isolating sheet is configured to match a footprint of the magazine.

19. The method of claim 14, where in the isolating material comprises a substrate, glass or ceramic.

20. The method of claim 15, wherein sufficient space is left between magazines so to maintain a sufficient plasma electrode ground to power ratio.

21. The method of claim 15, wherein dummy strips are provided at a top and bottom of the magazine.

22. The method of claim 15, wherein adjacent integrated circuit/substrate combinations are evenly spaced apart.

23. The method of claim 22, wherein the spacing is configured to reduce hot spots.

24. The method of claim 23, wherein the spacing is about 6 mm.

25. The method of claim 15, wherein the plasma cleaning time is limited to less than five minutes to reduce excessive damage to the insulated bonding wire.

26. The method of claim 14, wherein the plasma cleaner is an in-line plasma cleaner and the chip carrier carries the IC/substrate combination along a railing of the in-line plasma cleaner.

27. The method of claim 26, wherein the railing comprises an electrode of the in-line plasma cleaner and the chip carrier is isolated from the railing by an isolating material.

28. The method of claim 26, wherein chip carrier is isolated by isolating the railing from an electrode of the in-line plasma cleaner using an isolating material.

29. The method of claim 26, wherein the plasma cleaning time is limited to less than thirty second to reduce excessive damage to the insulated bonding wire.

30. The method of claim 14, wherein the plasma clean process uses an inert gas to inhibit a change of surface characteristics of the insulation material.

31. A chip carrier for supporting in a cleaning device at least one IC/substrate combination that has been wire bonded using an insulated bonding wire, the chip carrier including an isolating material configured to electrically isolate the chip carrier from the cleaning device to reduce an effect of a cleaning process on the insulated bonding wire.

32. The chip carrier of claim 31, wherein the chip carrier is a magazine and a plurality of IC/substrate combinations are placed in the magazine for being cleaned simultaneously.

33. The chip carrier claim 32, wherein the magazine includes legs comprising the isolating material for electrically isolating the magazine from the cleaning device.

34. The chip carrier of claim 32, wherein the magazine is electrically isolated from the cleaning device by providing an isolating sheet there between.

35. The chip carrier of claim 34, wherein the isolating sheet is configured to match a footprint of the magazine.

36. The chip carrier of claim 31, where in the isolating material comprises a substrate, glass or ceramic.

37. The chip carrier of claim 32, wherein slots for adjacent integrated circuit/substrate combinations are evenly spaced apart.

38. The chip carrier of claim 37, wherein the spacing is configured to reduce hot spots.

39. The chip carrier of claim 38, wherein the spacing is about 6 mm.

40. The chip carrier of claim 31 , configured to support the IC/substrate combination along a railing on an in-line cleaning device.

41. The chip carrier of claim 40, wherein the railing comprises an electrode of the in-line cleaning device and the chip carrier is isolated from the railing by an isolating material.

42. An in line cleaning device configured to electrically isolate a chip carrier from the cleaning device, the chip carrier for supporting at least one IC/substrate combination that has been wire bonded using an insulated bonding wire, the in line cleaning device comprising: a railing for guiding the chip carrier through the in line cleaning device during a cleaning process, the railing being electrically isolated from electrodes of the cleaning device using an isolating material, thereby reducing an effect of the cleaning process on the insulated bonding wire.

43. A test kit including components for building a tester to test a dielectric breakdown point of an insulated bonding wire, the test kit comprising: (a) a base for supporting the tester;

(b) a pair of conductive rods, one of the rods to be electrically coupled to an anode of a power supply and the other of the rods to be electrically coupled to a cathode of the power supply, wherein the pair of conductive rods are to positioned a predefined distance apart; (c) a slide for supporting the insulated bonding wire to be tested such that the insulated bonding wire is in contact with each of the conductive rods;

(d) a first coupling means for coupling the pair of conducting rods to the base; and

(e) a second coupling means for coupling the insulated bonding wire to the slide.

44. A test device for testing the effect of a wire bonding process on insulated bonding wire, the test device comprising a substrate having first and second opposing surfaces, the substrate further comprising:

(a) pairs of bonding pads on the first surface for bonding opposite ends of insulated bonding wires; and (b) pairs of test points on the second surface, the pairs test points being electrically coupled to corresponding pairs of bonding pads for facilitating electrical testing of the insulated bonding wire.

45. The test device of claim 44, wherein the substrate further includes an IC positioned thereon.

46. An integrated circuit (IC)/substrate combination wherein the IC and substrate are electrically connected via insulated bonding wire bonded there between, the insulated bonding wire configured to be compatible with a molding tool by having:

(a) a limited loop height of the wires; and (b) a geometrical configuration that avoids crossing points in regions susceptible to physical damage during a subsequent molding process.

47. A method for encasing an IC/substrate combination comprising insulated bonding wires in a molding compound using a transfer molding press when the IC/substrate combination is placed within a mold, the method comprising the steps of: (a) transferring the molding compound into a cavity within the mold at an initial flow rate;

(b) establishing a flow wall within the cavity; and thereafter

(c) increasing the insertion speed of the molding compound to a final flow rate.

48. The method of claim 47, wherein the molding compound is selected to have a gel time at least equal to the time required to encase the IC/substrate combination.

49. The method of claim 47, wherein the molding compound is selected to have relatively low filler size.

50. The method of claim 47, wherein the molding compound is selected to have relatively high percentage of spherical filler particles

51. The method of claim 50, wherein the percentage is at least 80 percent.

52. The method of claim 47, wherein the insulated bonding wires are configured not to cross in an area close to a gate in the transfer molding press.