WO2007005446A3 - Method and apparatus for determining stuck-at fault locations in cell chains using scan chains - Google Patents

Method and apparatus for determining stuck-at fault locations in cell chains using scan chains Download PDF

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Publication number
WO2007005446A3
WO2007005446A3 PCT/US2006/025122 US2006025122W WO2007005446A3 WO 2007005446 A3 WO2007005446 A3 WO 2007005446A3 US 2006025122 W US2006025122 W US 2006025122W WO 2007005446 A3 WO2007005446 A3 WO 2007005446A3
Authority
WO
WIPO (PCT)
Prior art keywords
chains
cell
scan chain
scan
chain
Prior art date
Application number
PCT/US2006/025122
Other languages
French (fr)
Other versions
WO2007005446A2 (en
Inventor
Alexandre Depoorter
Fabrice Picot
Original Assignee
Atmel Corp
Alexandre Depoorter
Fabrice Picot
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0507050A external-priority patent/FR2888014B1/en
Application filed by Atmel Corp, Alexandre Depoorter, Fabrice Picot filed Critical Atmel Corp
Publication of WO2007005446A2 publication Critical patent/WO2007005446A2/en
Publication of WO2007005446A3 publication Critical patent/WO2007005446A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Methods and apparatus are provided for testing digital circuits. In one implementation, a scan chain test structure is provided that includes a cell chain, a first scan chain, and a second scan chain. The first scan chain is operable to test digital circuitry within a first portion of the cell chain, and the second scan chain is operable to test digital circuitry within a second portion of the cell chain. The first scan chain is further operable to test digital circuitry within the second scan chain, and the second scan chain is further operable to test digital circuitry within the first scan chain.
PCT/US2006/025122 2005-07-01 2006-06-27 Method and apparatus for determining stuck-at fault locations in cell chains using scan chains WO2007005446A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0507050A FR2888014B1 (en) 2005-07-01 2005-07-01 METHOD AND APPARATUS FOR DETERMINING THE LOCATION OF BONDING FAULTS IN CELL CHAINS USING TEST CHAINS
FR05/07050 2005-07-01
US11/207,082 2005-08-17
US11/207,082 US7392448B2 (en) 2005-07-01 2005-08-17 Method and apparatus for determining stuck-at fault locations in cell chains using scan chains

Publications (2)

Publication Number Publication Date
WO2007005446A2 WO2007005446A2 (en) 2007-01-11
WO2007005446A3 true WO2007005446A3 (en) 2007-06-07

Family

ID=37604976

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/025122 WO2007005446A2 (en) 2005-07-01 2006-06-27 Method and apparatus for determining stuck-at fault locations in cell chains using scan chains

Country Status (1)

Country Link
WO (1) WO2007005446A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109444716B (en) * 2018-11-27 2021-08-10 中科曙光信息产业成都有限公司 Scanning test structure with positioning function and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030023941A1 (en) * 2001-03-30 2003-01-30 Wang Laung-Terng (L.-T.) Computer-aided design system to automate scan synthesis at register-transfer level
US20040177294A1 (en) * 2003-02-24 2004-09-09 Mcnall Walter Lee Integrated circuit with test signal routing module

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030023941A1 (en) * 2001-03-30 2003-01-30 Wang Laung-Terng (L.-T.) Computer-aided design system to automate scan synthesis at register-transfer level
US20040177294A1 (en) * 2003-02-24 2004-09-09 Mcnall Walter Lee Integrated circuit with test signal routing module

Also Published As

Publication number Publication date
WO2007005446A2 (en) 2007-01-11

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