WO2006134560A1 - Driving a bi-stable display device - Google Patents

Abstract

A driving system (15, 10, 16) for reset-driving a bi-stable display device (1) which comprises bi-stable material of which an optical state changes when a drive voltage (VD) is applied across it and which substantially keeps its optical state unaltered in the absence of the drive voltage (VD). The driving system (15, 10, 16) generates, during an image update period (IUP), a sequence of phases. The sequence at least comprises a reset phase (RE), an address phase (AD) and an offset phase (OP). During the reset phase (RE) a previous optical state of the bi-stable material is changed into at least one of two limit optical states (B; W). During the address phase (AD) the at least one of the two limit optical states (B; W) is changed into an intermediate optical state (Gl, G2) in-between the two limit optical states (B, W). The two limit optical states (B, W) and the intermediate optical state (G1, G2) are called main optical states. During the offset phase (OP), starting from the intermediate optical state (G1, G2), extra optical states (ILG11, ILG12, ILG21, ILG22) are created which differ from the main optical states.

Description

Driving a bi- stable display device

The invention relates to a driver for reset-driving of a bi-stable display device. The invention further relates to a display unit comprising such a bi-stable display device, a display apparatus comprising the display unit, and a method of reset-driving the bi-stable display device.

WO-A-2005/006296 discloses a reset-driving scheme for a bi-stable display with improved grey scale accuracy. A bi-stable display comprises a bi-stable material and electrodes associated with the bi-stable material. A drive voltage supplied between the electrodes generates an electrical field in the bi-stable material. An amount of change of the optical state of the bi-stable material depends on both the electrical field strength and on the duration this field strength is present. Thus, the change of the optical state depends on the multiplication of the level and duration of the drive voltage. This multiplication is referred to as the energy of the drive voltage. If no electrical field is present in the bi-stable material, its optical state is kept substantially constant for a relatively long period of time with respect to the image hold period during which the image should be presented.

Providing a robust driving method for a bi-stable display is not simple because the change of the optical state depends on factors such as, for example, the image history, dwell time, temperature, humidity, lateral inhomogeneity of the bi-stable material, etc. The optical states can not be accurately reproduced without taking care of these issues. One possibility to improve the accurate reproducibility of the optical states is to use the conventional reset drive scheme wherein an image on the display is updated by driving the pixels of the display from a current optical state to a final optical state via one of two reference optical state. The reference optical states are extreme or limit optical states such as black and white. All optical transitions are performed via at least one of the accurately defined extreme optical states. Thus, if the optical state of a pixel of the bi-stable display has to change in successive input images, this transition is always obtained by first changing the original optical state to one of the limit optical states and than changing the limit optical state to the new optical state. Such a drive scheme which comprises a reset phase and an address phase is further referred to as a reset drive scheme. During the reset phase a drive voltage is applied with a level and duration sufficient to obtain one of the limit optical states independent on the factors mentioned above. During the address phase, which often is referred to as the drive phase, a drive voltage is applied with a level and duration selected to change the optical state from the limit optical state to the desired optical state in-between the limit optical states. The actual level and duration of the drive voltage required during the address phase may be determined experimentally. Usually, the energy of the drive voltage needs to be determined for every possible transition between optical states.

These conventional reset drive schemes provide very accurate intermediate optical states in-between the limit optical states. However, a drawback of the conventional reset drive scheme is that a relatively high number of transitions need to be optimized. For example, 16 transitions have to be optimized for 4 grey levels, white, light grey, dark grey, and black. If 16 grey levels are desired, already 256 different transitions have to be optimized.

It is an object of the invention to increase the number of grey levels which can be displayed with a lower number of optimized transitions.

A first aspect of the invention provides a driving system for reset-driving a bi- stable display device as claimed in claim 1. A second aspect of the invention provides a display unit comprising a bi-stable display device as claimed in claim 9. A third aspect of the invention provides a display apparatus comprising the display unit as claimed in claim 10. A fourth aspect of the invention provides a method of reset-driving as claimed in claim 11. Advantageous embodiments are defined in the dependent claims. In accordance with the first aspect of the invention, the bi-stable display device comprises bi-stable material of which an optical state changes when a drive voltage is applied across it, and which substantially keeps its optical state unaltered in the absence of the drive voltage. The bi-stable material may be electrophoretic material, such as, for example, electronic-ink. The driving system generates, during an image update period, a sequence of at least a reset phase, an address phase, and an offset phase. During the reset phase a previous optical state of the material is reset to one of the two limit optical states, and during the address phase the optical state is changed from the one of the two limit optical states to an intermediate optical state in-between the two limit optical states. This combination of the reset phase and the address phase is also referred to as the main transition phase which may be identical to a prior art reset drive scheme. In such a reset drive scheme, more than one intermediate optical state may be defined between the limit optical states. The limit optical states and the intermediate optical states obtained by the reset drive scheme are collectively referred to as the main optical states. In accordance with the present invention, additionally, during an offset phase succeeding the main transition phase, starting from the intermediate optical state, at least one extra optical state is created which differs from the main optical states.

Thus, the intermediate optical states, which are reproducibly and accurately reached due to the reset drive scheme, are used as "support" levels to generate more finely divided grey scales during the offset phase. For example, during the offset phase, the drive voltage may have 16 different levels at a same duration, or 16 different durations at the same level, or a combination thereof. What counts in this example is that drive voltages which are generated during the offset phase have 16 different energies such that 16 different optical transitions occur starting from the same support level. The drive voltage may comprise a single drive pulse or a series of drive pulses. However, the effect of the series of drive pulses on the optical state may be different than that of a single pulse which has the same level and a duration which is sum of the duration of the pulses. Off course, any another number of extra levels may be created with associated energies of the drive pulses.

During the offset phase, the drive voltage required to obtain, starting from the intermediate optical state, at least one extra grey level has an energy such that the extra grey level occurs in-between two adjacent main optical states. Preferably this energy is (or these energies are, if more than one extra optical state is possible between adjacent main optical states) selected to obtain substantially equally spaced grey levels.

The offset drive scheme in accordance with the invention has the advantage that many more grey levels are possible by just defining a few offset drive voltages. For example, adding an offset phase with 16 well defined offset levels, in a reset drive scheme in which the two limit optical states black and white, and the two intermediate main optical states dark grey and light grey are present, now, in total, 52 grey levels are possible. These 52 grey levels are obtained by defining 16 transitions in the standard reset drive scheme and only 16 transitions in the added offset phase.

It has to be noted that although preferably, several different offset levels are possible during different offset phases, the present invention is already useful if only a single offset level is introduced. For example, in a system with 16 support levels obtained by reset driving, adding a single offset level allows to reach an optical states in-between every pair of adjacent support levels.

In an embodiment as claimed in claim 2, during the offset phase of a particular image update period, the drive voltage has a particular energy. During the de-offset phase, which succeeds this offset phase, the drive voltage has an energy which is selected to compensate for the energy of the drive voltage during the offset phase. In fact, the optical state offset created during the offset phase with respect to the associated main optical state is substantially reversed during the successive de-offset phase. Thus, after the de-offset phase, the main optical state which was present before the offset phase is at least substantially restored. The use of the de-offset phase has the advantage that it is much easier to keep the average voltage across the bi-stable material for every pixel near to zero. A further advantage is that the accuracy of the conventional reset drive scheme is improved, because the optical states at the start of the conventional reset drive scheme are at least near to the main optical states. In a more complicated drive scheme, the de-offset phase of the present image update period may be determined to compensate for the offset phase of the next image update period.

If the de-offset drive pulse compensates for the offset drive pulse, the main transition phase is identical to the prior art reset drive scheme wherein the optical transitions occur between main levels. Otherwise, the levels before the reset phase may be offset with respect to the main levels after the address phase. But, these offsets do not negatively influence the generation of the main levels by the consecutive reset and address phase.

In an embodiment as claimed in claim 3, the drive voltage has a particular level and a particular duration during the offset phase. The drive voltage during the de-offset phase has a de-offset level with a polarity opposite to the offset level, and a de-offset duration. The multiplication of the de-offset level and the de-offset duration is substantially identical to the multiplication of the offset level and the offset duration. Consequently, the energy of the drive voltage during the de-offset phase is substantially the same as the energy of the drive voltage during the offset phase. Further, due to the opposite polarity of the drive voltage, the drive voltage during the de-offset phase substantially compensates the optical transition caused by the drive voltage during the offset phase.

In an embodiment as claimed in claim 4, during the offset phase, the drive voltage has an offset level, and during the de-offset phase, the drive voltage has a level with an opposite polarity and a substantially identical amplitude and duration as the offset level. In an embodiment as claimed in claim 5, during the offset phase, the drive voltage comprises a series of pulses, and during the de-offset phase the drive voltage has an energy for compensating the series of pulses.

In an embodiment as claimed in claim 6, the drive voltage has a limit level during the reset phase and an opposite limit level during the address phase.

In an embodiment as claimed in claim 7, shaking pulses are supplied before the reset phase and/or in-between the reset phase and the address phase. These shaking pulses further improve the accurate reproducibility of the main optical state(s).

In an embodiment as claimed in claim 8, the following phases are successively provided, in the following order, the de-offset phase, first shaking pulses, the reset phase, second shaking pulses, the address phase, and the offset phase.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

In the drawings:

Fig. 1 shows diagrammatically a cross-section of a portion of an electrophoretic display,

Fig. 2 shows diagrammatically a picture display apparatus with an equivalent circuit diagram of a portion of the electrophoretic display,

Figs. 3A to 3D show drive voltages across a pixel in different reset drive schemes,

Fig. 4 shows a drive voltage in accordance with an embodiment of the invention, and Fig. 5 shows for an embodiment in accordance with the invention how the different optical states are obtained.

Fig. 1 shows diagrammatically a cross-section of a small portion of an electronic ink display. Bi-stable displays have a bi-stable material which keeps its optical state during a relatively long hold period when no electrical field is present in the material, and which changes its optical state when an electrical field is present in the material. The hold period is the period during which the image should not change too much and thus during which the optical state of the bi-stable material should be substantially constant. The bi-stable materials may be, for example, an electrophoretic material. A special electrophoretic material is electronic ink. The electronic ink display comprise a base substrate 2, an electronic ink film or layer which is present between two transparent substrates 3 and 4 which, for example, are of polyethylene. One of the substrates 3 is provided with transparent pixel electrodes 5, 5' and the other substrate 4 with a transparent counter electrode 6. The electronic ink comprises multiple microcapsules 7 of about 10 to 50 microns. Each microcapsule 7 comprises positively charged white particles 8 and negatively charged black particles 9 suspended in a fluid 40. The dashed material 41 is a polymer binder. The layer 3 is not necessary, or could be a glue layer. When the pixel voltage VD across the pixel 18 (see Fig. 2) is supplied as a positive drive voltage VD to the pixel electrodes 5, 5' with respect to the counter electrode 6, an electric field is generated which moves the white particles 8 to the side of the microcapsule 7 directed to the counter electrode 6 and the display element will appear white to a viewer. Simultaneously, the black particles 9 move to the opposite side of the microcapsule 7 where they are hidden from the viewer. By applying a negative drive voltage VD between the pixel electrodes 5, 5' and the counter electrode 6, the black particles 9 move to the side of the microcapsule 7 directed to the counter electrode 6, and the display element will appear dark to a viewer (not shown). When the electric field is removed, the particles 8, 9 remain in the acquired state for a relatively long period of time and the display exhibits a bi-stable character and consumes substantially no power. Electrophoretic media are known per se from e.g. US 5,961,804, US 6,1120,839 and US 6,130,774 and may be obtained from E-ink Corporation.

The particles 8 and 9 may have other colors than white and black, and also the fluid and the binder may have particular colors or may be transparent.

Fig. 2 shows diagrammatically a picture display apparatus with an equivalent circuit diagram of a portion of the electrophoretic display. The picture display device 1 comprises an electrophoretic film laminated on the base substrate 2 provided with active switching elements 19, a row driver 16 and a column driver 10. Preferably, the counter electrode 6 is provided on the film comprising the encapsulated electrophoretic ink layer. But, the counter electrode 6 could be alternatively provided on a base substrate if a display operates based on using in-plane electric fields. The counter electrode 6 may be segmented. Usually, the active switching elements 19 are thin-film transistors TFT. The display device 1 comprises a matrix of display elements associated with intersections of row or selection electrodes 17 and column or data electrodes 11. The row driver 16 consecutively selects the row electrodes 17, while the column driver 10 provides data signals in parallel to the column electrodes 11 for the selected row electrode 17. Preferably, a processor 15 firstly processes incoming data DA and synchronization signals SY into the data signals to be supplied by the column electrodes 11. The drive lines 12 carry signals which control the mutual synchronisation between the column driver 10 and the row driver 16. The data DA and the synchronization signals SY are supplied by a signal processor SP which receives an incoming signal IV which represents the images to be display on the display apparatus 100. The display apparatus 100 comprises a driver and a display device 1. The driver comprises the processor 15, the row driver 16 and the column driver 10. The driver is also referred to as the driving system to indicate that it comprises more than only the actual (row and column) drivers. The row driver 16 supplies an appropriate select pulse to the gates of the

TFT' s 19 which are connected to the particular row electrode 17 to obtain a low impedance main current path of the associated TFT's 19. The gates of the TFT's 19 which are connected to the other row electrodes 17 receive voltages such that their main current paths have a high impedance. The low impedance between the source electrodes 21 and the drain electrodes of the TFT's allows the data voltages present at the column electrodes 11 to be supplied to the drain electrodes which are connected to the pixel electrodes 22 of the pixels 18. In this manner, a data signal present at the column electrode 11 is transferred to the pixel electrode 22 of the pixel or display element 18 coupled to the drain electrode of the TFT if the TFT is selected by an appropriate level on its gate. In the embodiment shown, the display device of Fig.1 also comprises an additional capacitor 23 at the location of each display element 18. This additional capacitor 23 is connected between the pixel electrode 22 and one or more storage capacitor lines 24. Instead of TFTs, other switching elements can be used, such as diodes, MIMs, etc.

Figs. 3A to 3D show drive voltages across a pixel in different reset drive schemes. Figs. 3 A to 3D are used to indicate the large variety in reset drive schemes. In Fig. 4 for one of these reset drive schemes, the offset and de-offset drive scheme in accordance with an embodiment of the invention is shown. It has to be noted that this offset and de-offset drive scheme can be applied to all possible reset drive schemes in which a reset phase and an address phase are present. Thus, for example, the shaking pulses present in Figs. 3 A to 3B may also be present around the reset phase in Fig. 4.

By way of example, Figs. 3 A to 3D are based on an electrophoretic display with black and white particles and four optical states: black B, dark grey Gl, light grey G2, white W. Fig. 3A shows an image update period IUP lasting from the instant t0 to the instant t8 for a transition from light grey G2 or white W to dark grey Gl . Fig. 3B shows an image update period lasting from the instant t4 tot the instant t8 for a transition from dark grey Gl or black B to dark grey Gl. The vertical dotted lines represent the frame periods TF (which usually last 20 milliseconds), the line periods TL occurring within the frame periods TF are not shown in Figs. 3 A to 3D. The first frame period TF of the image update period IUP lasts from the instant t0 to the instant tl .

In both Fig. 3 A and Fig. 3B, the pixel voltage VD across a pixel 18 comprises successively first shaking pulses SPl, SPl ', a reset pulse RE, RE', second shaking pulses SP2, SP2' and an address pulse AD. The address pulses AD, which are often also referred to as the drive pulses, occur during the same drive period TAD which lasts from instant t7 to instant t8. The optional shaking pulses SPl, SPl ' which occur during the shaking phases TSl and TS I' respectively, and the optional shaking pulses SP2, SP2' which occur during the shaking phases TS2 and TS2', respectively, improve the reproducibility of grey levels and decrease the response time of the display by providing the particles an initial speed. The reset pulses RE, RE' during the reset phases TRl, TRl', respectively, change the original optical state before the shaking pulses SPl, SPl ' to one of the two limit optical states white W or black B. The address pulse AD occurs during the address phase TAD. The address pulse AD has a polarity which is opposite to the polarity of the reset pulse RE, RE' to change the optical state from the limit optical state to one of the intermediate states dark grey Gl or light grey G2. The duration and level of the address pulse AD has to be carefully selected to obtain the desired change in the optical state.

The second shaking pulses SP2, SP2' immediately precede the driving pulses AD and thus occur during a same second shaking period TS2 lasting from the instant t6 to the instant t7. The reset pulse RE, RE' immediately precede the second shaking pulses SP2, SP2'. However, due to the different duration TRl, TRl' of the reset pulses RE, RE', respectively, the starting instants t3 and t5 of the reset pulses RE, RE' are different. The first shaking pulses SPl, SPl' which immediately precede the reset pulses RE, RE', respectively, thus occur during different first shaking periods in time TSl, TSl', respectively. The first shaking period TSl lasts from the instant t0 to the instant t3, the first shaking period TSl ' lasts from the instant t4 to the instant t5. If the second shaking pulses SP2, SP2' occur for every pixel 18 during a same second shaking period TS2, this enables to select the duration of this second shaking period TS2 much shorter as is shown in Figs. 3 A and 3B. For clarity, each one of levels of the second shaking pulses SP2, SP2' is present during a standard frame period TF. In fact, during the second shaking period TS2, the same voltage levels can be supplied to all the pixels 18. Thus, instead of selecting the pixels 18 line by line, it is now possible to select all the pixels 18 at once, and only a single line select period suffices per level. Thus, in the embodiment in accordance with the invention shown in Figs. 3 A and 3B, the second shaking period TS2 only needs to last four line periods TL instead of four standard frame periods TF. It is still possible to select all the pixels during a longer period than a single line period to decrease the power consumption. It is also possible to select successively groups of rows of pixels to lower the capacitive currents required to charge the pixels.

Alternatively, it is also possible to change the timing of the drive signals such that the first shaking pulses SPl and SPl' are aligned in time, the second shaking pulses SP2 are then no longer aligned in time (not shown). Now the duration of the first shaking period TSl can be much shorter or it is possible to decrease the power consumption.

If the drive method shown in Figs. 3 A and 3B is applied to the electrophoretic display, outside the second shaking period TS2, the pixels 18 have to be selected line by line by activating the switches 19 line by line. The voltages VD across the pixels 18 of the selected line are supplied via the column electrodes 11 in accordance with the optical state the pixel 18 should have. For example, for a pixel 18 in a selected row of which pixel the optical state has to change from white W to dark grey Gl, a positive voltage has to be supplied at the associated column electrode 11 during the frame period TF starting at instant t0. For a pixel 18 in the selected row of which pixel the optical state has to change from black B to dark grey Gl, a zero voltage has to be supplied at the associated column electrode during the frame period TF lasting from the instants t0 to tl .

Fig. 3C shows a waveform which is based on the waveform shown in Fig. 3B. This waveform of Fig. 3 C causes the same optical transition. The difference is that the first shaking pulses SPl ' of Fig. 3B are now shifted in time to coincide with the shaking pulses SPl of Fig. 3A. The shifted shaking pulses SPl ' are indicated by SPl". Thus, now, independent on the duration of the reset pulse RE, also all the shaking pulses SPl, SPl" occur during the same shaking period TSl. This has the advantage that independent of the optical transition, the same shaking pulses SPl, SPl" and SP2, SP2' can be supplied to all pixels 18 simultaneously. Thus both during the first shaking period TSl and the second shaking period TS2, it is not required to select the pixels 18 line by line. Whilst in Fig. 3C the shaking pulses SPl" and SP2' have a predetermined high or low level during a complete frame period, it is possible to use shaking pulses SPl" and SP2' lasting one or more line periods TL (see Fig. 6). In this manner, the image update time may be shortened. Further, due to the selection of all (or groups of) lines at the same time and providing a same voltage to all columns, during the shaking periods TSl and TS2, the parasitic capacitances between neighboring pixels and electrodes will have no effect. This will minimize stray capacitive currents and thus dissipation. Even further, the common shaking pulses SPl, SPl" and SP2, SP2' enable implementing shaking by using structured counter electrodes 6. The dissipation will be lowered if a same shaking pulse is supplied to all pixels 18 of the same column, wherein different columns may receive different shaking pulses.

A disadvantage of this approach is that a small dwell time is introduced between the first shaking pulse period TSl and the reset period TRl '. Dependent on the electrophoretic display used, this dwell time should not become longer than, for example, 0.5 seconds.

Fig. 3D shows a waveform which is based on the waveform shown in Fig. 3C. To this waveform third shaking pulses SP3 are added which occur during a third shaking period TS3. The third shaking period TS3 occurs between the first shaking pulses SPl and the reset pulse RE', if this reset pulse RE' does not have its maximum length. The third shaking pulses SP3 may have a lower energy content than the first shaking pulses SPl to minimize the visibility of the shaking. It is also possible that the third shaking pulses SP3 are a continuation of the first shaking pulses SPl. Preferably, the third shaking pulses SP3 fill up the complete period in time available between the first shaking period TSl ' and the reset period TRl ' to minimize the image retention and to increase the grey scale accuracy. With respect to the embodiment in accordance with the invention shown in Fig. 3 C, the image retention is further reduced and the dwell time is massively reduced.

Alternatively, it is possible that the reset pulse RE' occurs immediately after the first shaking pulses SPl and the third shaking pulses occur between the reset pulse RE' and the second shaking pulses SP2'. The shaking pulses which at least partially overlap the reset pulse in accordance with the invention may be applied to any of the situations shown in one of the Figs. 3 A to 3D. It is even possible to apply the invention to a drive cycle of the electrophoretic display which is not an image update cycle but, for example a reset cycle only. It has to be noted that the reset drive schemes shown in Figs. 3A to 3D are an example only. The first shaking pulses SPl, SPl' and/or the second shaking pulses SP2, SP2' are optional. The reset pulses RE and RE' may have the same length for different optical transmissions. It might be advantageous to use different durations of the reset pulses for different optical transmissions, for example, to prevent sticking of the particles if the reset pulse RE lasts much longer than required to change from the starting optical state to the limit optical state. The address pulse AD may have different levels and/or durations for different optical transitions. The reset pulse RE, RE' and/or address pulse may comprise a series of pulses. Fig. 4 shows a drive voltage in accordance with an embodiment of the invention. The drive voltage VD shows an offset and de-offset drive scheme applied on a reset drive scheme wherein only reset pulses REl, RE2 and address pulses ADl, AD2 are present. Only two update periods IUPl and IUP2 of the drive voltage VD are shown. Although these two update periods IUPl and IUP2 occur directly adjacent, this is not required, for example, a hold period may be present in-between the two update periods. Both update periods IUPl and IUP2 comprise the same sequence of phases. The first update period IUPl comprises sequentially, in the order mentioned, a de-offset phase DOPO, a reset phase REl, an address phase ADl, and an offset phase OPl. The second update period IUP2 comprises sequentially, in the order mentioned, a de-offset phase DOPl, a reset phase RE2, an address phase AD2, and an offset phase OP2.

The de-offset phase DOPO comprises a de-offset drive voltage VD with a level and duration such that its energy, defined as the multiplication of the level and the duration is substantially identical to the energy of the offset drive voltage VD applied during the offset phase (not shown) of the update period (not shown) preceding the update period IUPl. The energy of the de-offset drive voltage VD need not be exactly identical to the energy of the preceding offset drive voltage VD.

During the reset period REl a reset pulse is applied with an energy which is at least sufficient to change the optical state obtained after the de-offset phase DOPO to one of the limit optical states black B or white W. During the address phase ADl, an address pulse is supplied which has a polarity opposite to that of the reset pulse. After the address phase ADl, one of the main grey levels is obtained. The main grey levels are the same grey levels which would be obtained if only a reset drive scheme is used. For example, in a four grey level system, after the address phase, the grey level is black B, dark grey Gl, light grey G2, or white W. These levels are referred to as the main levels or the support levels to make clear that they are the levels which are reached with a conventional reset drive scheme which does not comprise the offset phase OP (OPl and OP2 in Fig. 4) and the optional de-offset phase DOP (DOPO and DOPl in Fig. 4). As discussed hereinabove, many different waveforms VD are required to accurately and reproducible provide optical state transitions between the four main grey levels B, Gl, G2, and W. Often the exact energy of the address pulse has to be determined experimentally for each different optical state transition between these four main grey levels or main optical states. Thus if many more grey levels are desired, the known reset drive scheme requires a lot of accurately determined drive waveforms VD, usually one for every possible optical transition between the main grey levels.

The basic idea of the present invention is to add an offset phase OPl which succeeds the address phase ADl. During this offset phase OPl, an offset pulse is generated which causes a change of the optical state which respect to the main optical state reached after the address phase ADl. The energy of the offset pulse is selected to obtain an optical transition which, starting from the main optical state, provides a new optical state which is in- between the main optical states reacheable with the conventional reset scheme only. By having the possibility to use different energies for different offset pulses, it is possible to created many extra optical states in-between the main optical states reachable with the conventional reset scheme. It appeared that these extra optical states have a high and reproducible accuracy without requiring a reset scheme. Thus now, only once, the energy of the offset pulses has to be selected such that the desired extra levels in-between the main levels occur. This selection can be used for providing the extra optical states starting from each one of the main optical states. This is in contrast to the conventional reset drive wherein all the different transitions between all the optical states have to be carefully selected and stored.

The de-offset phase DOPl comprises a de-offset drive voltage VD with a level and duration such that its energy is substantially identical to the energy of the offset drive voltage VD applied during the offset phase OPl of the update period IUPl preceding the update period IUP2. In a simple embodiment, the de-offset pulse during the de-offset period DOPl has the opposite level and the same duration as the offset pulse during the offset period OPl . During the reset period RE2 a reset pulse is applied with an energy which is at least sufficient to change the optical state obtained after the de-offset phase DOPl to one of the limit optical states B or W. During the address phase AD2, an address pulse is supplied which has a polarity opposite to that of the reset pulse. After the address phase AD2, again one of the main grey levels, which would be obtained if only a reset scheme is used, is obtained. During the offset phase OP2, in the same manner as during the offset phase OPl, the extra optical states are obtained by selecting an offset pulse which has the required energy.

It has to be noted that the reset drive scheme may differ from the one shown in Fig. 4. The offset phase OPl, OP2 and de-offset phase DOPl, DOP2 may also be added to one of reset drive schemes shown in Figs. 3 A to 3D, or to any other reset drive schemes which comprises reset pulses RE and address pulses AD. The de-offset period DOPl, DOP2 is optional. However, the accuracy of the grey levels will become somewhat less without the de-offset periods DOPl, DOP2, and it will become more difficult to maintain a substantially average zero DC voltage across the electrophoretic material. It is possible to use drive pulses during the offset period DOPl, DOP2 which only partly compensate for the effect of the drive pulses during the offset period OPl, OP2.

Fig. 5 shows how the different optical states are obtained in an embodiment in accordance with the invention. The different optical states are presented in the vertical direction and are also referred to as different grey levels. In a black and white display the grey levels are actually grey levels. In a color display, the grey levels may be colored levels. Fig. 5 shows grey level transitions during an update period IUP to elucidate the effect of the addition of the de-offset phase DOP and the offset phase OP to the conventional reset drive scheme. It has to be noted that, in the example shown, the four optical states white W, light grey G2, dark grey Gl, and black B are the main optical states which are present in the conventional reset drive scheme. This conventional reset drive scheme has a transition period TP during which each of the four optical states RLl before the transition period TP can be changed into one of these four optical states RL2 after the transition period TP. The transition period TP comprises at least the reset period RE and the address period AD. It is this transition period TP which was referred to as the main transition period. In the well known reset drive scheme, the optical transition from one of the four levels to the same or another one of the four levels is always performed via at least one of the two extreme optical states black B or white W.

In accordance with the present invention, during the offset phase OP, the offset pulse(s) are supplied and the extra optical states or grey levels are obtained. These extra optical states are optical states in-between adjacent main optical states. In the example shown, the offset pulse may have two different energy levels such that two extra optical states are possible in-between two adjacent main optical states. The extra optical states between the black optical state B and the dark grey optical state Gl are ILBl and ILB2. The extra optical states between the dark grey optical state Gl and the light grey optical state G2 are ILGl 1 and ILGl 2, and the extra optical states between the light grey optical state G2 and the white optical state W are ILG21 and ILG22. The extra optical states ILBl, ILGl 1, ILG21 are obtained by using a same offset pulse which has a first energy, and the extra optical states ILB2, ILGl 2, ILG22 are obtained by using a same offset pulse which has a second energy larger than the first energy. The set of grey levels which can be obtained after the offset phase OP are indicated by EL.

It has to be noted that many alternative offset drive schemes are possible. In Fig. 5, all the extra optical states are generated with an offset pulse which has a polarity such that optical state transitions which start from the associated main optical states are changed towards white. Alternatively, the extra optical states may be generated with an offset pulse which has a polarity such that the optical state transitions are changed towards black. Although in Fig. 5 is shown that the main states are identical to the ones which would be reached with a conventional reset scheme, it is possible to select the main states differently. For example, the dark grey level Gl, the light grey level G2 and the white level W may be selected lower than shown, such that extra levels are possible above the main white level. The main white optical state is now not anymore the limit white optical state. Consequently, the reset drive scheme has to reset all optical states to the black optical state before the transition to the next main optical state occurs. It is not anymore possible to reset a main optical state to the white limit optical state because this white limit optical state is not anymore generated as a main optical state. Alternatively, all levels except the white level may be selected higher than shown in Fig. 5 such that extra levels are possible even below the shifted black level. Now all transitions between optical states have to be reset via the white main optical state which still is the limit white optical state.

Preferably, before the optical transition between the main states is made in accordance with a conventional reset drive scheme, a de-offset phase DOP is inserted. During this de-offset phase DOP, the one of the levels SL reached during a previous image update period is changed back to one of the main levels. This de-offset need not be very accurate, it suffices that the level reached after the de-offset phase is near to the one of the main levels from which the offset pulse caused the extra optical level. The reset drive scheme eliminates the influence of these differences. One way of determining the de-offset pulse applied during the de-offset phase is to generate the de-offset pulse with an energy which is opposite to the energy of the preceding offset pulse. With opposite energy is meant a same energy while the voltage levels used have opposite polarity. A simple way of generating the opposite energy is to apply a de-offset pulse during the de-offset phase DOP which has the same absolute value and the same duration as, but the opposite polarity of, the preceding offset pulse applied during the preceding offset phase OP.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims.

The bi-stable display may be any other display then an electrophoretic display. For example, the bi-stable display may be the rotating ball display of Gyricon. A bi-stable display is any display where the pixels maintain their brightness level after the voltage to the pixel is removed. It has to be noted that a bi-stable display may have more than 2 brightness levels.

Electrophoretic display panels can form the basis of a variety of applications where information may be displayed, for example in the form of information signs, public transport signs, advertising posters, pricing labels, billboards etc. In addition, they may be used where a changing non- information surface is required, such as wallpaper with a changing pattern or color, especially if the surface requires a paper like appearance.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. A driving system (15, 10, 16) for reset-driving a bi-stable display device (1) comprising bi-stable material of which an optical state changes when a drive voltage (VD) is applied across it and which substantially keeps its optical state unaltered in the absence of the drive voltage (VD), the driving system (15, 10, 16) comprising means (10, 16) for generating, during an image update period (IUP), a sequence of phases at least comprising a reset phase (RE) for resetting a previous optical state of the bi-stable material to at least one of two limit optical states (B; W), and an address phase (AD) for changing from the at least one of the two limit optical states (B; W) to an intermediate optical state (Gl, G2) in-between the two limit optical states (B, W), the two limit optical states (B; W) and the intermediate optical state (Gl, G2) being main optical states, and an offset phase (OP) for creating, starting from the intermediate optical state (Gl, G2), extra optical states (ILGl 1, ILGl 2, ILG21, ILG22) being different from the main optical states.

2. A driving system as claimed in claim 1, wherein the means for generating (10, 16) are further constructed for generating, during a de-offset phase (DOP) preceding or succeeding a further image update period (IUP), a drive voltage (VD) having an energy for substantially compensating the energy of a drive voltage (VD) during the offset phase (OP).

3. A driving system as claimed in claim 2, wherein the means for generating (10, 16) are constructed for generating: during the offset phase (OP), a drive voltage (VD) having an offset level and an offset duration, and during the de-offset phase (DOP), a drive voltage (VD) having a de-offset duration and a de-offset level, wherein the de-offset level has a polarity opposite to the offset level, and wherein a multiplication of the de-offset level and the de-offset duration is substantially identical to a multiplication of the offset level and the offset duration.

4. A driving system as claimed in claim 2, wherein the means for generating (10, 16) are constructed for generating: during the offset phase (OP), a drive voltage (VD) having an offset level, and during the de-offset phase (DOP), a drive voltage (VD) having a de-offset level with a opposite polarity and a substantially identical amplitude and duration as the offset level.

5. A driving system as claimed in claim 2, wherein the means for generating (10, 16) are constructed for generating during the offset phase (OP) a drive voltage (VD) comprising a series of pulses, and during the de-offset phase a drive voltage (VD) having an energy for substantially compensating the series of pulses.

6. A driving system as claimed in claim 1, wherein the means for generating (10, 16) are constructed for supplying a drive voltage (VD) with a limit level during the reset phase (RE), and a drive voltage (VD) having an opposite limit level during the address phase (AD).

7. A driving system as claimed in claim 1, wherein the means for generating are constructed for supplying shaking pulses (SPl, SP2) before the reset phase (RE) and/or in- between the reset phase (RE) and the address phase (AD).

8. A driving system as claimed in claim 6, wherein the means for generating (10, 16) are constructed for supplying successively in the following order, the de-offset phase (DOP), first shaking pulses (SPl), the reset phase (RE), second shaking pulses (SP2), the address phase (AD), and the offset phase (OP).

9. A display unit (100) comprising a bi- stable display device (1) and the driving system (15, 10, 16) as claimed in claim 1.

10. A display apparatus comprising the display unit (100) as claimed in claim 9, and a signal processor (SP) for receiving an input signal (IV) representing an image to be displayed on the display device to supply a data signal (DA) and a synchronization signal (SY) to the driving system (15, 10, 16).

11. A method of reset-driving a bi-stable display device (1) comprising material of which an optical state changes when a drive voltage (VD) is applied across it and which substantially keeps its optical state unaltered in the absence of the drive voltage (VD), the method comprising generating (10, 16), during an image update period (IUP), a sequence of phases at least comprising resetting a previous optical state of the bi-stable material to at least one of two limit optical states (B; W) during a reset phase (RE), and changing from the at least one of the two limit optical states (B; W) to an intermediate optical state (Gl, G2) ) in-between the two limit optical states (B, W) during an address phase (AD), the two limit optical states (B, W) and the intermediate optical state (Gl, G2) being main optical states, and an offset phase (OP) for creating, starting from the intermediate optical state (Gl, G2), extra optical states (ILGl 1, ILGl 2, ILG21, ILG22) being different from the main optical states.