WO2006103845A1 - Substrate processing method - Google Patents

Substrate processing method Download PDF

Info

Publication number
WO2006103845A1
WO2006103845A1 PCT/JP2006/303070 JP2006303070W WO2006103845A1 WO 2006103845 A1 WO2006103845 A1 WO 2006103845A1 JP 2006303070 W JP2006303070 W JP 2006303070W WO 2006103845 A1 WO2006103845 A1 WO 2006103845A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide film
cleaning
substrate
silicon
substrate processing
Prior art date
Application number
PCT/JP2006/303070
Other languages
French (fr)
Japanese (ja)
Inventor
Shintaro Aoyama
Kazuyoshi Yamazaki
Naoki Shindo
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Publication of WO2006103845A1 publication Critical patent/WO2006103845A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation

Definitions

  • the present invention relates to a substrate processing method for cleaning a silicon substrate and forming an oxide film after the cleaning.
  • the thickness of the gate insulating film also needs to be set to 1 to 2 nm or less when a conventional thermal oxide film is used.
  • a very thin gate insulating film increases the tunnel current, and as a result, the problem of increased gate leakage current cannot be avoided.
  • the relative permittivity is much larger than that of the thermal oxide film, and therefore, even if the physical film thickness is large, the SiO equivalent film thickness (EOT) is small.
  • EOT SiO equivalent film thickness
  • a high dielectric material such as ZrSiO or Hf SiO is suitable for the gate insulating film.
  • a gate insulating film having a physical thickness of about lOnm can be used even in an ultra-high-speed semiconductor device with a gate length of 0.3 m or less.
  • the gate leakage current due to can be suppressed.
  • the thickness between the high-dielectric gate oxide film and the silicon substrate is very thin with a thickness of 1 nm or less, preferably 0.8 nm or less. It is preferable to interpose a base acid film.
  • the base oxide film needs to be very thin. If the thickness is thick, the effect of using the high dielectric film as the gate insulating film is offset. On the other hand, a very thin base oxide film that is strong must uniformly cover the silicon substrate surface, In addition, it is required not to form defects such as interface states.
  • FIG. 1 shows a schematic configuration of a high-speed semiconductor device 10 having a high dielectric gate insulating film.
  • a semiconductor device 10 is formed on a silicon substrate 11, and a Ta 2 O 3, Al 2 O 3, ZrO 2, HfO 2, and ZrSiO 2 are formed on the silicon substrate 11 via a thin base oxide film 12.
  • HfSiO or other high dielectric gate insulating film 13 is formed, and the high dielectric gate insulating film 13 is further formed.
  • a gate electrode 14 is formed on the edge film 13.
  • a range in which the flatness of the interface between the silicon substrate 11 and the base oxide film 12 is maintained on the surface portion of the base oxide film layer 12 is maintained.
  • nitrogen (N) is doped to form an oxynitride film 12A.
  • the calculated film thickness can be further reduced.
  • the thickness of the base oxide film 12 is preferably as thin as possible. Therefore, it is preferable to form the base oxide film 12 while keeping the surface of the silicon substrate 11 as clean as possible.
  • Various silicon substrate cleaning methods and substrate processing methods for this purpose have been proposed (see, for example, Patent Document 1 to Patent Document 4).
  • Patent Document 1 Japanese Patent Laid-Open No. 6-216098
  • Patent Document 2 JP-A-7-302851
  • Patent Document 3 Japanese Patent Laid-Open No. 5-175182
  • Patent Document 4 JP-A-8-31784
  • the silicon substrate is first treated with an oxidizing agent solution such as hydrogen peroxide (HO).
  • DHF dilute hydrofluoric acid
  • the first specific problem of the present invention is to suppress the formation of a natural oxide film on the surface of the cleaned silicon substrate and to improve the controllability of the base oxide film thickness. .
  • a specific second problem of the present invention is to reduce and control the roughness of the interface between the silicon substrate and the base oxide film.
  • a specific third problem of the present invention is to reduce the thickness of the base oxide film without deteriorating the film quality.
  • the present invention solves the above-described problem by a first cleaning step of cleaning a silicon substrate with a first cleaning liquid containing ammonia and hydrogen peroxide water, and cleaning with a cleaning liquid containing HF after the cleaning, A silicon substrate is cleaned with a second cleaning solution containing hydrochloric acid and hydrogen peroxide solution, and then cleaned with a cleaning solution containing HF after the cleaning, and on the silicon substrate after the second cleaning step. And a silicon oxide film forming step, and the second cleaning step is repeatedly performed a plurality of times.
  • a base oxide film that is preferably used for a high-speed device can be formed on a silicon substrate.
  • FIG. 1 is a diagram showing a configuration of a semiconductor device device having a high dielectric gate insulating film.
  • FIG. 2A is a diagram (part 1) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
  • FIG. 2B is a diagram (part 2) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the formation state of the suboxide.
  • FIG. 2C is a diagram (part 3) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
  • FIG. 2D is a diagram (part 4) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
  • FIG. 2E is a diagram (No. 5) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
  • FIG. 3 is a flowchart showing a substrate processing method according to Embodiment 1.
  • FIG. 4A is a diagram (part 1) showing the result of XPS analysis of a chemical acid film.
  • FIG. 4B is a diagram showing an XPS analysis result of an oxide film formed by the substrate processing method of FIG.
  • FIG. 5A is a diagram (part 1) showing an XPS analysis result of an oxide film formed on a Si (111) surface.
  • FIG. 5B is a diagram (No. 2) showing the XPS analysis result of the oxide film formed on the Si (l l l) surface.
  • FIG. 6A is a view (No. 1) showing the XPS analysis result of an oxide film formed on a Si (100) surface.
  • FIG. 6B is a diagram (part 2) showing the XPS analysis result of the oxide film formed on the Si (100) surface.
  • FIG. 7 is a diagram schematically showing the crystal structure of Si.
  • FIG. 8A is a diagram (part 2) showing the result of XPS analysis of a chemical oxide film.
  • FIG. 8B XPS analysis result of the oxide film formed by the substrate processing method of FIG.
  • FIG. 9A is a diagram (part 3) showing the result of XPS analysis of a chemical oxide film.
  • FIG. 9B is a diagram showing an XPS analysis result of an oxide film formed by the substrate processing method of FIG.
  • FIG. 10A is a diagram (part 1) schematically showing an expected state of a silicon substrate surface during the substrate processing method shown in FIG.
  • FIG. 10B is a cross-sectional view taken along line AA of the silicon substrate of FIG. 10A.
  • FIG. 11A is a diagram (part 1) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
  • FIG. 11B is a diagram (part 2) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
  • FIG. 11C is a diagram (part 3) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
  • FIG. 11D is a diagram (part 4) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
  • FIG. 11E is a diagram (part 5) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
  • FIG. 12A is a diagram (part 1) schematically showing an effect of the substrate processing method of FIG.
  • FIG. 12B is a diagram (part 2) schematically showing the effect of the substrate processing method of FIG.
  • FIG. 13A is an example showing a method of forming a silicon oxide film in the substrate processing method of FIG.
  • FIG. 13B is an example showing a method of nitriding a silicon oxide film in the substrate processing method of FIG. 3.
  • FIG. 14 is a diagram showing a remote plasma source used for nitriding in FIG. 13B.
  • FIG. 15 is an example showing another method of forming a silicon oxide film in the substrate processing method of FIG. 3.
  • FIG. 16 is a diagram showing the relationship between the physical film thickness of the silicon oxide film and the XPS film thickness.
  • a base oxide film that is formed between the gate electrode and the silicon substrate and serves as a base of a high dielectric material is formed.
  • FIG. 2A to FIG. 2E show that UV activation O oxidation (UV—O oxidation) is performed on a silicon substrate.
  • silicon atoms on the surface of the silicon substrate are coordinated by both silicon atoms inside the substrate and oxygen atoms on the substrate surface. It is thought that it forms a xide.
  • a low peak seen in the energy range of 101 to 104 eV corresponds to the suboxide
  • the oxide film thickness exceeds 0.3 nm, the peak appearing in this energy region is attributed to Si 4+, which is considered to represent the formation of an oxide film exceeding one atomic layer!
  • the base oxide film is formed on the upper layer of the base oxide film.
  • a malfunction such as an increase in leakage current or unstable electrical characteristics will occur.
  • the thickness of the base oxide film when forming the semiconductor device is 0.4 nm or more so that a stable oxide film can be formed. Further, since the base oxide film is preferably as thin as possible, the electrical characteristics are good, and the thinnest base oxide film thickness, that is, the preferable base oxide film thickness is as described above. From the spectrum results, it is considered to be 0.4 nm.
  • a natural oxide film formed on the silicon substrate may be a problem. If a natural oxide film is formed on a silicon substrate, it is difficult to control the thickness of the base oxide film, and it may be difficult to form a base oxide film having a desired thickness. . In addition, the film quality of the natural oxide film may not meet the required film quality of the base oxide film. In this case, it may be difficult to obtain desired electrical characteristics. .
  • the present invention by cleaning the silicon substrate by the method described below, the formation of a natural oxide film on the silicon substrate is suppressed, and a cleaner silicon substrate surface is maintained. It is possible to do. For this reason, the controllability of the thickness of the base oxide film when the base oxide film is formed on the silicon substrate is improved, and the controllability of the film quality of the base oxide film is also improved. In addition, the electrical characteristics of the formed semiconductor device can be improved.
  • FIG. 3 is a flowchart showing a silicon substrate cleaning method according to the first embodiment of the present invention.
  • step 1 in the cleaning method according to the present embodiment, in step 1 (indicated as S1 in the figure, the same applies hereinafter), the silicon substrate is first cleaned with the first cleaning liquid.
  • the first cleaning liquid includes concentrated aqueous ammonia (NH OH), aqueous hydrogen peroxide (H 2 O), and
  • the mixing ratio is preferably 1: 2: 50, respectively.
  • the first cleaning liquid may be referred to as SC1 cleaning liquid, and the cleaning according to Step 1 may be referred to as SC1 cleaning.
  • the temperature of the first cleaning liquid is, for example, 60 ° C.
  • step 1 particles (fine particles) and organic contamination on the silicon substrate are mainly removed.
  • step 2 the chemical acid formed in the step 1 is removed. Metal contamination in the capsule is removed.
  • step 3 a so-called rinsing process of cleaning the silicon substrate with pure water is performed to remove the first cleaning liquid or DHF cleaning liquid remaining on the silicon substrate.
  • step 4 the silicon substrate is cleaned with a second cleaning liquid.
  • the second cleaning liquid is concentrated hydrochloric acid (HC1), hydrogen peroxide (H 2 O), and pure water (H 2 O).
  • the second cleaning solution may be referred to as an SC2 cleaning solution, and the cleaning that goes to step 4 may be referred to as an SC2 cleaning.
  • the temperature of the second cleaning liquid is, for example, 70 ° C.
  • step 5 metal contamination on the silicon substrate mainly, and in step 6, the chemical oxide film on the silicon substrate formed in step 5 is removed.
  • step 4 to step 5 is repeated a predetermined number of times to Complete the cleaning of the circuit board.
  • step 6 On the surface of the silicon substrate that has been cleaned and cleaned by removing the chemical oxide film and contaminants, in step 6, for example, a silicon oxide film that becomes a base oxide film of a MOS transistor is formed. A film is formed.
  • a high dielectric film is formed on the base oxide film, and in step 8, the base oxide film is nitrided.
  • the nitriding of the base oxide film may be performed after the base oxide film is formed and before the formation of the high dielectric, as shown in FIG. After the formation, the base oxide film may be nitrided through the high dielectric film. Details of the method for forming such a base oxide film and the method for nitriding the base oxide film will be described later.
  • a semiconductor device such as a MOS transistor can be formed by, for example, forming a gate electrode, implanting an impurity, or forming an electrode by a conventional method of forming a MOS transistor. .
  • FIG. 4A shows an XPS of a typical silicon oxide film (hereinafter referred to as a typical oxide film) formed by removing the natural oxide film on the silicon substrate by DHF cleaning and using thermal acid. (X-ray photoelectron spectroscopic analysis) spectrum and enlarged view of the XPS spectrum are shown.
  • Fig. 4B shows that after removing the natural oxide film and chemical oxide film on the silicon substrate by DHF cleaning, SC2 cleaning is performed.
  • the XPS spectrum of the chemical oxide film formed at this time hereinafter referred to as SC2 oxide film in the text
  • the silicon substrate uses a substrate (hereinafter referred to as (100) substrate) in which the surface on which the silicon oxide film is formed is a (100) plane.
  • the spectrum is far from the baseline around the binding energy of 101 to 102eV, and the peak is caused by Si or SiO.
  • the difference in the XPS spectrum occurs when the binding energy is between 101 eV and 102 eV, due to the difference in the state of Si atoms on the surface of the Si substrate.
  • Si atoms on the silicon substrate surface are coordinated by both silicon atoms inside the substrate and oxygen atoms on the substrate surface to form suboxides. It is known that the peak (detection intensity) of the XPS spectrum due to these suboxides is observed in the vicinity of 101 eV to 102 eV.
  • FIG. 5A shows a typical example of an XPS spectrum of a silicon oxide film formed on a (100) substrate of silicon. Also, in order to make it easier to see FIG. 5A, the spin orbit 1Z2 is removed from the spectrum and replotted is shown in FIG. 5B.
  • the Si suboxide peak is observed between the peak due to Si and the peak due to SiO, as indicated by arrows in the figure.
  • the suboxide peak is mainly caused by Si 2+ due to Si crystal structure, and Si 1+ , or Start with Si 3+ It is thought that the peak due to this is hardly observed.
  • the peak due to Si 1+ is due to Si peak
  • the peak due to Si 3+ is due to Si 2+ due to Si peak.
  • a peak is observed between the peak due to Si 1+ and the peak due to Si 3+ .
  • FIG. 6A shows a typical example of an XPS spectrum of a silicon oxide film formed on a silicon (111) substrate.
  • Fig. 6B shows the result of removing the spin orbit 1Z2 from the spectrum and replotting it.
  • the Si suboxide peak is observed between the peak due to Si and the peak due to SiO, as indicated by arrows in the figure.
  • the peak of suboxide is mainly Si 1+ due to the crystal structure of Si. Also, this is due to Si 3+ , and almost no peaks due to Si 2+ are observed. In this case, in the vicinity of the binding energy where a peak due to Si 2+ is observed, the detected intensity is almost in the vicinity of the base line.
  • FIG. 7 is a diagram schematically showing the crystal structure of Si.
  • the (100) plane and (111) plane are different in the state of the chemical bond as seen from the plane direction.
  • the Si 2+ force in the (100) plane is Si 1+ Or Si 3+ is observed
  • Si 3 2 of the typical oxide film and SC2 oxide film shown in FIGS. 4A and 4B are shown.
  • Figures 8A and 8B show the XPS spectra analyzed in more detail in consideration of the Si crystal structure and the typical state of the spectra.
  • FIGS. 8A and 8B the baseline (background) is linear.
  • Figures 9A and 9B show the baselines in the spectra of Figures 8A and 8B.
  • FIGS. 9A and 9B in both the case of the typical oxide film and the case of the SC2 oxide film, the same results as those shown in FIGS. 8A and 8B are obtained. It has become.
  • the surface of the silicon substrate is as follows!
  • FIG. 10A is a diagram schematically showing an expected state of the silicon substrate surface after step 5 in the substrate processing method according to the present embodiment shown in FIG.
  • FIG. 10A the (100) plane of the silicon substrate is in a state in which a plurality of pyramidal structures composed of (111) plane microfacets are formed after step 5 is completed. Conceivable.
  • FIG. 10B shows a cross section taken along the line AA ′ of FIG. 10A. Referring to FIG. 10B, it is considered that an SC2 oxide film is formed on the microfacet composed of the (111) plane. This is mainly formed on the silicon substrate by H 2 O contained in the SC2 cleaning solution.
  • the XPS spectrum results of the SC2 oxide film shown in FIGS. 4B, 8B, and 9B agree well. That is, the XPS spectrum, generally Si 2+ found when formed on the (100) surface of silicon. Most of the peaks due to Si 1+ or Si 3+ are observed, which means that the silicon oxide film is formed on the (111) face microfacets. It can be explained well by thinking.
  • FIGS. 11A to 11F show changes in the surface state (morphology) of a silicon substrate that are expected when the processes in steps 4 and 5 are repeated in the substrate processing method according to the present embodiment shown in FIG.
  • FIG. Figure 11A shows the state after the initial processing of Step 4 and Step 5
  • Figures 11B to 11E show the expected silicon after repeating Step 4 and Step 5 2-5 times, respectively.
  • FIG. 5 is a diagram schematically showing changes in the state (morphology) of a substrate.
  • the flatness (reduction in roughness) of the surface on the silicon substrate progresses by repeating the processing in step 4 and step 5.
  • the Si bond is terminated with H (hydrogen) while the flatness of the silicon substrate surface is advanced, and the surface state is stable. It is thought that it becomes.
  • Step 4 and Step 5 The above is an example schematically showing the change in the morphology of the silicon substrate surface, and the progress of the flatness depending on the number of times of the processing in Step 4 and Step 5 depends on the temperature of the cleaning liquid or the cleaning liquid. It changes at any time depending on the mixing ratio and the surface condition (particles, contamination, etc.) of the silicon substrate. For this reason, it is preferable that the number of times of repeating the processing of Step 4 and Step 5 is appropriately changed according to these states.
  • FIG. 12A and FIG. 12B schematically show the effects considered to be obtained by using the substrate processing method in this example.
  • the horizontal axis represents the number of times the processing in Step 4 to Step 5 was repeated, and the vertical axis represents silicon.
  • the roughness (Rms) of the substrate surface is taken, and the prediction of the state in which the planarization of the substrate surface proceeds by the substrate processing method according to this example is schematically shown. Referring to FIG. 12A, it is considered that the flatness of the silicon substrate surface is improved by repeating the processing of step 4 to step 5.
  • the surface state of the silicon substrate does not necessarily need to be used in the state of FIG. 11E.
  • FIG. 11C and FIG. thus, it is expected that an effect of suppressing the bonding of Si to oxygen can be obtained.
  • FIG. 12B is a diagram schematically showing a difference in the thickness of the natural oxide film formed when the substrate is left in the atmosphere in the conventional substrate processing method and the substrate processing method according to this example. It is.
  • the elapsed time after the cleaning treatment is taken on the horizontal axis, and the thickness of the natural oxide film formed on the vertical axis, and the expected difference is schematically shown.
  • the substrate processing method according to the present example it can be considered that Si on the substrate surface is suppressed from being bonded to oxygen. Therefore, it is considered that the formation of a natural oxide film after the cleaning process is suppressed as compared with the conventional substrate processing method. Therefore, in the substrate processing method according to the present embodiment, a base oxide film that is preferably used for a high-speed device can be formed on a silicon substrate.
  • FIG. 13A shows a substrate processing apparatus 20 for forming a silicon oxide film in step 6 after cleaning a silicon substrate and a silicon oxide film formed by the substrate processing apparatus 20 in the substrate processing method according to the present embodiment. It is the figure which showed the method to do typically.
  • a substrate processing apparatus 20 includes a processing container 21 that houses a substrate holding table 22 that holds a substrate W to be processed, and that defines a process space 21 B together with the substrate holding table 22. Yes.
  • the substrate processing apparatus 20 has an exhaust port 21A for exhausting the process space 21B.
  • the exhaust port 21A is connected to an exhaust means (not shown) such as a vacuum pump.
  • the process space 21B can be depressurized (exhaust).
  • the processing container 21 is provided with a processing gas supply nozzle 21D for supplying oxygen gas to the side facing the exhaust port 21A across the substrate W to be processed, and the processing gas supply nozzle.
  • the oxygen gas supplied to 21D flows in the process space 21B along the surface of the substrate to be processed W, and is exhausted from the exhaust port 21A.
  • the substrate processing apparatus 20 includes the processing gas supply nozzle 21D and the target gas.
  • An ultraviolet light source 25 having a quartz window 25A is provided corresponding to a region between the processing substrate W and the substrate.
  • the oxygen gas introduced into the process space 21B from the processing gas supply nozzle 21D is activated, and the oxygen radical formed as a result becomes the surface of the substrate W to be processed. Flowing along. As a result, a silicon oxide film (base oxide film) having a thickness of 1 nm or less can be formed on the surface of the substrate W to be processed.
  • the method of activating the oxygen gas using ultraviolet light to form the oxide film is thin because the progress of the oxidation is relatively slow and the control of the film thickness is easy. This is suitable for forming a preferable base oxide film.
  • a remote plasma source 26 is formed in the processing container 21 on the side facing the exhaust port 21A with respect to the substrate W to be processed. Nitrogen radicals can be formed by supplying nitrogen gas to the remote plasma source 26 together with an inert gas such as Ar and activating it with plasma.
  • FIG. 13B is a diagram schematically showing a method for nitriding a base oxide film using the substrate processing apparatus 20.
  • the N gas supplied to the remote plasma source 26 together with a carrier gas such as Ar, for example, is activated by the plasma to form nitrogen radicals.
  • the nitrogen radicals thus formed flow along the surface of the substrate to be processed w, and for example, nitride a base oxide film formed on the substrate.
  • FIG. 14 shows an example of the configuration of the remote plasma source 26 used in the substrate processing apparatus 20.
  • the remote plasma source 26 includes a block 26A, typically made of aluminum, in which a gas circulation passage 26a and a gas inlet 26b and a gas outlet 26c communicating with the gas circulation passage 26a are formed.
  • a ferrite core 26B is formed in a part of the block 26A.
  • Fluorine resin coating 26d is applied to the inner surfaces of the gas circulation passage 26a, the gas inlet 26b, and the gas outlet 26c, and a high frequency of 4 OOkHz is supplied to the coil wound around the ferrite core 26B. As a result, plasma 26C is formed in the gas circulation passage 26a.
  • the structure of the ion filter 26e functions as a diffusion plate, so that charged particles such as nitrogen ions can be sufficiently removed.
  • the nitriding treatment of the oxide film is performed not with nitrogen ions but with nitrogen radical N *. For this reason, it is preferable that the number of excited nitrogen ions is small.
  • the number of excited nitrogen ions is preferably small.
  • the substrate processing apparatus 20 of FIG. 13B is suitable for nitriding a very thin base oxide film having a thickness of 1 nm or less under a high dielectric gate insulating film with a small number of excited nitrogen radicals.
  • the nitriding of the base oxide film may be performed immediately after the formation of the base oxide film, or after the formation of the base oxide film and after the formation of the high dielectric film on the base oxide film. You can go there.
  • a method for forming a high dielectric film for example, a film formation method using a MOCVD method (metal organic chemical vapor deposition method), a film formation using an ALD method (Atomic Layer Deposition method), etc. Can be used.
  • MOCVD method metal organic chemical vapor deposition method
  • ALD method Atomic Layer Deposition method
  • the method for forming the base oxide film is not limited to the above.
  • FIG. 15 shows another example of a substrate processing apparatus for forming a silicon oxide film in step 6 after cleaning the silicon substrate in the substrate processing method shown in FIG.
  • FIG. 6 is a diagram schematically showing the device 50.
  • the substrate processing apparatus 50 includes a substrate to be processed inside a processing container 51.
  • a holding base 53 for holding W is provided, and a heating means 52 for heating the substrate W to be processed is formed so as to face the holding base 53.
  • the heating means 52 may be constituted by a lamp heater, and a heater 53 A for heating the substrate W to be processed may be embedded in the holding base 53.
  • the processing container 5 the heating means 52 may be constituted by a lamp heater, and a heater 53 A for heating the substrate W to be processed may be embedded in the holding base 53.
  • the processing container 5 the processing container 5
  • the substrate processing apparatus for example, oxygen or a gas containing an oxygen element is introduced from a gas inlet 54 provided in the processing container, and the substrate W to be processed is heated by the heating means 52. By heating the substrate, the base oxide film can be formed on the surface of the substrate W to be processed made of silicon.
  • the base oxide film is formed by heating the substrate to be processed in an atmosphere containing oxygen. It is also possible to form
  • the base oxide film can also be formed by heat-treating a chemical oxide film formed by SC2 cleaning. The reason why the above chemical oxide film can be used as the base oxide film will be described below.
  • Figure 16 shows the relationship between the film thickness (physical film thickness) measured by ellipsometer and the film thickness derived from the SiO peak of the XPS spectrum (XPS film thickness) for silicon oxide films formed by multiple methods.
  • FIG. 1 boiled thermal oxide film (indicated as thermal SiO in the figure), ⁇ for UV activation
  • Oxidized film by O-acid (denoted as UV-Ox in the figure), chemical oxide film by 11 O by order (H O
  • the physical film thickness and the XPS film thickness are linearly correlated (universal
  • the above universal line force also shifts. This is due to the influence of suboxide existing at the interface between the silicon substrate and the oxide film and the alteration of the oxide film itself.
  • the film is a low-density film having a film quality greatly different from that of the thermal oxide film.
  • the above HO oxide film and SC2 oxide film are annealed, the above-mentioned super
  • the above-described heat treatment step of the SC2 oxide film can be performed in the substrate processing apparatus 20 described in the first embodiment, for example.
  • the silicon substrate is heat-treated at 400 to 700 ° C. in an inert gas or N gas atmosphere. Heat treatment
  • the chemical oxide film can be used as a base oxide film in forming a semiconductor device.
  • the above heat treatment can also be performed in the substrate processing apparatus 50 described in the second embodiment.
  • the process of Step 6 is composed of the SC2 cleaning process (Step 4) and the heat treatment process described above. do it.
  • the substrate processing apparatus and the substrate processing method for forming the base oxide film can be variously selected.
  • a substrate processing apparatus and a substrate processing method can be variously selected for nitriding the base oxide film and forming a high dielectric film.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

Disclosed is a substrate processing method comprising a first cleaning step wherein a silicon substrate is first cleaned with a first cleaning liquid containing ammonia and a hydrogen peroxide solution, and then cleaned with a cleaning liquid containing HF; a second cleaning step wherein the silicon substrate is first cleaned with a second cleaning liquid containing hydrochloric acid and a hydrogen peroxide solution, and then cleaned with a cleaning liquid containing HF; and an oxide film-forming step wherein a silicon oxide film is formed on the silicon substrate after the second cleaning step. This substrate processing method is characterized by repeating the second cleaning step a plurality of times.

Description

明 細 書  Specification
基板処理方法  Substrate processing method
技術分野  Technical field
[0001] 本発明は、シリコン基板を洗浄し、当該洗浄後に酸化膜を形成する基板処理方法 に関する。  The present invention relates to a substrate processing method for cleaning a silicon substrate and forming an oxide film after the cleaning.
背景技術  Background art
[0002] 今日の超高速高速半導体装置では、微細化プロセスの進歩とともに、 0. 1 m以 下のゲート長が可能になりつつある。一般に微細化とともに半導体装置の動作速度 は向上するが、このように非常に微細化された半導体装置では、ゲート絶縁膜の膜 厚を、微細化によるゲート長の短縮に伴って、スケーリング則に従って減少させる必 要がある。  [0002] With today's ultra-high-speed and high-speed semiconductor devices, gate lengths of 0.1 m or less are becoming possible as the miniaturization process advances. In general, the operating speed of a semiconductor device increases with miniaturization. However, in such a highly miniaturized semiconductor device, the thickness of the gate insulating film is reduced according to the scaling law as the gate length is shortened by miniaturization. It is necessary to make it.
[0003] しかしゲート長が 0. 1 μ m以下になると、ゲート絶縁膜の厚さも、従来の熱酸化膜を 使った場合、 l〜2nm、あるいはそれ以下に設定する必要がある力 このように非常 に薄いゲート絶縁膜ではトンネル電流が増大し、その結果ゲートリーク電流が増大す る問題を回避することができない。  [0003] However, when the gate length becomes 0.1 μm or less, the thickness of the gate insulating film also needs to be set to 1 to 2 nm or less when a conventional thermal oxide film is used. A very thin gate insulating film increases the tunnel current, and as a result, the problem of increased gate leakage current cannot be avoided.
[0004] このような事情で従来より、比誘電率が熱酸ィ匕膜のものよりもはるかに大きぐこのた め物理膜厚が大きくても SiO換算膜厚 (EOT)が小さい Ta Oや Al O , ZrO , HfO  [0004] Under such circumstances, the relative permittivity is much larger than that of the thermal oxide film, and therefore, even if the physical film thickness is large, the SiO equivalent film thickness (EOT) is small. Al O, ZrO, HfO
2 2 5 2 3 2 2 2 5 2 3 2
、さらには ZrSiOあるいは Hf SiOのような高誘電体材料をゲート絶縁膜に対して適In addition, a high dielectric material such as ZrSiO or Hf SiO is suitable for the gate insulating film.
2 4 4 2 4 4
用することが提案されている。このような高誘電体材料を使うことにより、ゲート長が 0 . ： m以下と、非常に短い超高速半導体装置においても lOnm程度の物理的膜厚 のゲート絶縁膜を使うことができ、トンネル効果によるゲートリーク電流を抑制すること ができる。  It has been proposed to use. By using such a high dielectric material, a gate insulating film having a physical thickness of about lOnm can be used even in an ultra-high-speed semiconductor device with a gate length of 0.3 m or less. The gate leakage current due to can be suppressed.
[0005] この場合、チャネル領域中のキャリアモビリティーを向上させる観点からは、高誘電 体ゲート酸ィ匕膜とシリコン基板との間に、 lnm以下、好ましくは 0. 8nm以下の厚さの きわめて薄 、ベース酸ィ匕膜を介在させるのが好まし 、。ベース酸ィ匕膜は非常に薄 ヽ 必要があり、厚さが厚いと高誘電体膜をゲート絶縁膜に使った効果が相殺される。一 方、力かる非常に薄いベース酸ィ匕膜は、シリコン基板表面を一様に覆う必要があり、 また界面準位等の欠陥を形成しな!ヽことが要求される。 [0005] In this case, from the viewpoint of improving carrier mobility in the channel region, the thickness between the high-dielectric gate oxide film and the silicon substrate is very thin with a thickness of 1 nm or less, preferably 0.8 nm or less. It is preferable to interpose a base acid film. The base oxide film needs to be very thin. If the thickness is thick, the effect of using the high dielectric film as the gate insulating film is offset. On the other hand, a very thin base oxide film that is strong must uniformly cover the silicon substrate surface, In addition, it is required not to form defects such as interface states.
[0006] 図 1は高誘電体ゲート絶縁膜を有する高速半導体装置 10の概略的な構成を示す  FIG. 1 shows a schematic configuration of a high-speed semiconductor device 10 having a high dielectric gate insulating film.
[0007] 図 1を参照するに、半導体装置 10はシリコン基板 11上に形成されており、シリコン 基板 11上には薄いベース酸化膜 12を介して、 Ta O , Al O , ZrO , HfO , ZrSiO Referring to FIG. 1, a semiconductor device 10 is formed on a silicon substrate 11, and a Ta 2 O 3, Al 2 O 3, ZrO 2, HfO 2, and ZrSiO 2 are formed on the silicon substrate 11 via a thin base oxide film 12.
2 5 2 3 2 2 ' 2 5 2 3 2 2 '
, HfSiO等の高誘電体ゲート絶縁膜 13が形成され、さらに前記高誘電体ゲート絶 , HfSiO or other high dielectric gate insulating film 13 is formed, and the high dielectric gate insulating film 13 is further formed.
4  Four
縁膜 13上にはゲート電極 14が形成されている。  A gate electrode 14 is formed on the edge film 13.
[0008] 図 1の半導体装置 10では、前記ベース酸ィ匕膜層 12の表面部分に、シリコン基板 1 1とベース酸ィ匕膜 12との間の界面の平坦性が保たれるような範囲で窒素 (N)がドー プされ、酸窒化膜 12Aが形成されている。シリコン酸化膜よりも比誘電率の大きい酸 窒化膜 12Aをベース酸ィ匕膜 12中に形成することにより、ベース酸ィ匕膜 12の SiO換 In the semiconductor device 10 of FIG. 1, a range in which the flatness of the interface between the silicon substrate 11 and the base oxide film 12 is maintained on the surface portion of the base oxide film layer 12 is maintained. Thus, nitrogen (N) is doped to form an oxynitride film 12A. By forming the oxynitride film 12A having a relative dielectric constant larger than that of the silicon oxide film in the base oxide film 12, the SiO conversion of the base oxide film 12 can be achieved.
2 算膜厚をさらに減少させることが可能になる。  2 The calculated film thickness can be further reduced.
[0009] 先にも説明したように、力かる高速半導体装置 10では前記ベース酸ィ匕膜 12の厚さ は可能な限り薄いのが好ましい。このため、前記シリコン基板 11の表面は、できるだ け清浄に保持された状態で前記ベース酸ィ匕膜 12を形成することが好ましい。このた めのシリコン基板の洗浄方法、基板処理方法は様々に提案されていた (例えば特許 文献 1〜特許文献 4参照)。 As described above, in the high-speed semiconductor device 10 that is powerful, the thickness of the base oxide film 12 is preferably as thin as possible. Therefore, it is preferable to form the base oxide film 12 while keeping the surface of the silicon substrate 11 as clean as possible. Various silicon substrate cleaning methods and substrate processing methods for this purpose have been proposed (see, for example, Patent Document 1 to Patent Document 4).
特許文献 1：特開平 6 - 216098号公報  Patent Document 1: Japanese Patent Laid-Open No. 6-216098
特許文献 2 :特開平 7— 302851号公報  Patent Document 2: JP-A-7-302851
特許文献 3：特開平 5 - 175182号公報  Patent Document 3: Japanese Patent Laid-Open No. 5-175182
特許文献 4：特開平 8 - 31784号公報  Patent Document 4: JP-A-8-31784
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0010] しかし、ベース酸ィ匕膜 12を lnm以下の厚さで一様に、かつ安定に形成するのは非 常に困難であった。 However, it has been very difficult to form the base oxide film 12 uniformly and stably with a thickness of 1 nm or less.
[0011] 例えば、シリコン基板を洗浄することで、シリコン基板表面を清浄な状態にしても、 当該シリコン基板を大気中に放置した場合には、当該シリコン基板表面の酸化が進 行してしまい、いわゆる自然酸化膜が形成されてしまう。シリコン基板を放置すること で形成される化学酸化膜は、その膜厚を制御することが困難であり、当該化学酸ィ匕 膜と、後の工程において意図的に形成されるシリコン酸ィ匕膜の膜厚を加えた、実質 的なベース酸ィ匕膜の膜厚の制御が困難となる問題があり、所望の厚さでベース酸ィ匕 膜を形成することが困難となる場合があった。 [0011] For example, even if the silicon substrate surface is cleaned by cleaning the silicon substrate, if the silicon substrate is left in the air, the oxidation of the silicon substrate surface proceeds. A so-called natural oxide film is formed. Leave the silicon substrate It is difficult to control the film thickness of the chemical oxide film formed in (1), and the film thickness of the chemical oxide film and the silicon oxide film intentionally formed in the subsequent process are added. However, there is a problem that it is difficult to control the film thickness of the base oxide film substantially, and it may be difficult to form the base oxide film with a desired thickness.
[0012] また、希フッ酸 (DHF)洗浄により、シリコン基板表面の自然酸ィ匕膜を除去した後に 、過酸化水素水 (H O )などの酸化剤薬液処理により、最初に当該シリコン基板上に [0012] In addition, after removing the natural acid film on the surface of the silicon substrate by dilute hydrofluoric acid (DHF) cleaning, the silicon substrate is first treated with an oxidizing agent solution such as hydrogen peroxide (HO).
2 2  twenty two
化学酸化膜を形成し、大気放置による自然酸化膜の形成を抑制する方法もあるが、 化学酸ィ匕膜はその膜質が従来用いられている熱酸ィ匕膜などに比べて低密度で、ベ 一ス酸ィ匕膜として用いるには好ましくな 、。  There is also a method to suppress the formation of a natural oxide film by leaving it in the atmosphere by forming a chemical oxide film, but the chemical oxide film has a lower density than the conventional thermal acid film, etc. Preferred for use as a base acid film.
[0013] また、シリコン基板の洗浄工程やその後のベース酸ィ匕膜形成工程で界面のラフネ スが増加すると、形成された半導体デバイスのチャネル領域のキャリアモビリティに影 響し、半導体デバイスの高速動作が困難になる。これは近年の高速半導体装置にお いては深刻な問題となる。 [0013] In addition, if the interface roughness increases in the silicon substrate cleaning process and the subsequent base oxide film forming process, the carrier mobility in the channel region of the formed semiconductor device is affected, and the semiconductor device operates at high speed. Becomes difficult. This is a serious problem in recent high-speed semiconductor devices.
[0014] そこで、本発明では上記の問題を解決した、新規で有用な基板処理方法を提供す ることを統括的課題として 、る。 [0014] Therefore, in the present invention, it is a general object to provide a new and useful substrate processing method that solves the above-described problems.
[0015] 本発明の具体的な第 1の課題は、洗浄後のシリコン基板表面に自然酸化膜が形成 されることを抑制し、ベース酸ィ匕膜厚の制御性を良好にすることである。 [0015] The first specific problem of the present invention is to suppress the formation of a natural oxide film on the surface of the cleaned silicon substrate and to improve the controllability of the base oxide film thickness. .
[0016] 本発明の具体的な第 2の課題は、シリコン基板とベース酸ィ匕膜界面のラフネスを低 減 Z制御することである。 [0016] A specific second problem of the present invention is to reduce and control the roughness of the interface between the silicon substrate and the base oxide film.
[0017] 本発明の具体的な第 3の課題は、ベース酸化膜を膜質劣化させずに薄膜化するこ とである。 A specific third problem of the present invention is to reduce the thickness of the base oxide film without deteriorating the film quality.
課題を解決するための手段  Means for solving the problem
[0018] 本発明は、上記の課題を、シリコン基板を、アンモニア、過酸化水素水を含む第 1 の洗浄液で洗浄し、当該洗浄後に HFを含む洗浄液で洗浄する第 1の洗浄工程と、 前記シリコン基板を、塩酸、過酸化水素水を含む第 2の洗浄液で洗浄し、当該洗浄 後に HFを含む洗浄液で洗浄する第 2の洗浄工程と、前記第 2の洗浄工程後の前記 シリコン基板上に、シリコン酸化膜を形成する酸化膜形成工程と、を有し、前記第 2の 洗浄工程は複数回繰り返し実施されることを特徴とする基板処理方法により、解決す る。 [0018] The present invention solves the above-described problem by a first cleaning step of cleaning a silicon substrate with a first cleaning liquid containing ammonia and hydrogen peroxide water, and cleaning with a cleaning liquid containing HF after the cleaning, A silicon substrate is cleaned with a second cleaning solution containing hydrochloric acid and hydrogen peroxide solution, and then cleaned with a cleaning solution containing HF after the cleaning, and on the silicon substrate after the second cleaning step. And a silicon oxide film forming step, and the second cleaning step is repeatedly performed a plurality of times. The
発明の効果  The invention's effect
[0019] 本発明によれば、シリコン基板上に、高速度デバイスに用いることが好ましいベース 酸化膜を形成することが可能となる。  According to the present invention, a base oxide film that is preferably used for a high-speed device can be formed on a silicon substrate.
図面の簡単な説明  Brief Description of Drawings
[0020] [図 1]高誘電体ゲート絶縁膜を有する半導体装置装置の構成を示す図である。 FIG. 1 is a diagram showing a configuration of a semiconductor device device having a high dielectric gate insulating film.
[図 2A]シリコン酸ィ匕膜の膜厚とサブオキサイドの形成状態の関係を示す XPSによる 分析結果を示す図 (その 1)である。  FIG. 2A is a diagram (part 1) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
[図 2B]シリコン酸ィ匕膜の膜厚とサブオキサイドの形成状態の関係を示す XPSによる 分析結果を示す図 (その 2)である。  FIG. 2B is a diagram (part 2) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the formation state of the suboxide.
[図 2C]シリコン酸ィ匕膜の膜厚とサブオキサイドの形成状態の関係を示す XPSによる 分析結果を示す図（その 3)である。  FIG. 2C is a diagram (part 3) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
[図 2D]シリコン酸ィ匕膜の膜厚とサブオキサイドの形成状態の関係を示す XPSによる 分析結果を示す図（その 4)である。  FIG. 2D is a diagram (part 4) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
[図 2E]シリコン酸ィ匕膜の膜厚とサブオキサイドの形成状態の関係を示す XPSによる 分析結果を示す図（その 5)である。  FIG. 2E is a diagram (No. 5) showing the XPS analysis result showing the relationship between the thickness of the silicon oxide film and the suboxide formation state.
[図 3]実施例 1による基板処理方法を示すフローチャートである。  FIG. 3 is a flowchart showing a substrate processing method according to Embodiment 1.
[図 4A]化学酸ィ匕膜の XPSによる分析結果を示す図（その 1)である。  FIG. 4A is a diagram (part 1) showing the result of XPS analysis of a chemical acid film.
[図 4B]図 3の基板処理方法により形成される酸化膜の XPSによる分析結果を示す図 FIG. 4B is a diagram showing an XPS analysis result of an oxide film formed by the substrate processing method of FIG.
(その 1)である。 (Part 1).
[図 5A]Si (111)面上に形成される酸化膜の XPS分析結果を示す図（その 1)である。  FIG. 5A is a diagram (part 1) showing an XPS analysis result of an oxide film formed on a Si (111) surface.
[図 5B]Si (l l l)面上に形成される酸ィ匕膜の XPS分析結果を示す図（その 2)である。  FIG. 5B is a diagram (No. 2) showing the XPS analysis result of the oxide film formed on the Si (l l l) surface.
[図 6A]Si (100)面上に形成される酸ィ匕膜の XPS分析結果を示す図（その 1)である。  FIG. 6A is a view (No. 1) showing the XPS analysis result of an oxide film formed on a Si (100) surface.
[図 6B]Si (100)面上に形成される酸ィ匕膜の XPS分析結果を示す図（その 2)である。  FIG. 6B is a diagram (part 2) showing the XPS analysis result of the oxide film formed on the Si (100) surface.
[図 7]Siの結晶構造を模式的に示した図である。  FIG. 7 is a diagram schematically showing the crystal structure of Si.
[図 8A]化学酸ィ匕膜の XPSによる分析結果を示す図（その 2)である。  FIG. 8A is a diagram (part 2) showing the result of XPS analysis of a chemical oxide film.
[図 8B]図 3の基板処理方法により形成される酸化膜の XPSによる分析結果を示す図 [FIG. 8B] XPS analysis result of the oxide film formed by the substrate processing method of FIG.
(その 2)である。 [図 9A]化学酸ィ匕膜の XPSによる分析結果を示す図（その 3)である。 (Part 2). FIG. 9A is a diagram (part 3) showing the result of XPS analysis of a chemical oxide film.
[図 9B]図 3の基板処理方法により形成される酸化膜の XPSによる分析結果を示す図 FIG. 9B is a diagram showing an XPS analysis result of an oxide film formed by the substrate processing method of FIG.
(その 3)である。 (Part 3).
[図 10A]図 3に示した基板処理方法中の、予想されるシリコン基板表面の状態を模式 的に示した図（その 1)である。  FIG. 10A is a diagram (part 1) schematically showing an expected state of a silicon substrate surface during the substrate processing method shown in FIG.
[図 10B]図 10Aのシリコン基板の A— A，断面図である。  FIG. 10B is a cross-sectional view taken along line AA of the silicon substrate of FIG. 10A.
[図 11 A]図 3に示した基板処理中に予想されるシリコン基板表面のモホロジ一の変化 を模式的に示した図（その 1)である。  FIG. 11A is a diagram (part 1) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
[図 11B]図 3に示した基板処理中に予想されるシリコン基板表面のモホロジ一の変化 を模式的に示した図（その 2)である。  FIG. 11B is a diagram (part 2) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
[図 11C]図 3に示した基板処理中に予想されるシリコン基板表面のモホロジ一の変化 を模式的に示した図（その 3)である。  FIG. 11C is a diagram (part 3) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
[図 11D]図 3に示した基板処理中に予想されるシリコン基板表面のモホロジ一の変化 を模式的に示した図（その 4)である。  FIG. 11D is a diagram (part 4) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
[図 11E]図 3に示した基板処理中に予想されるシリコン基板表面のモホロジ一の変化 を模式的に示した図（その 5)である。  FIG. 11E is a diagram (part 5) schematically showing a change in the morphology of the silicon substrate surface expected during the substrate processing shown in FIG.
[図 12A]図 3の基板処理方法の効果を模式的に示した図（その 1)である。  FIG. 12A is a diagram (part 1) schematically showing an effect of the substrate processing method of FIG.
[図 12B]図 3の基板処理方法の効果を模式的に示した図（その 2)である。  FIG. 12B is a diagram (part 2) schematically showing the effect of the substrate processing method of FIG.
[図 13A]図 3の基板処理方法においてシリコン酸化膜を形成する方法を示す一例で ある。  FIG. 13A is an example showing a method of forming a silicon oxide film in the substrate processing method of FIG.
[図 13B]図 3の基板処理方法においてシリコン酸ィ匕膜を窒化する方法を示す一例で ある。  FIG. 13B is an example showing a method of nitriding a silicon oxide film in the substrate processing method of FIG. 3.
[図 14]図 13Bの窒化に用いるリモートプラズマ源を示す図である。  FIG. 14 is a diagram showing a remote plasma source used for nitriding in FIG. 13B.
[図 15]図 3の基板処理方法においてシリコン酸ィ匕膜を形成する別の方法を示す一例 である。  FIG. 15 is an example showing another method of forming a silicon oxide film in the substrate processing method of FIG. 3.
[図 16]シリコン酸ィ匕膜の物理膜厚と XPS膜厚との関係を示した図である。  FIG. 16 is a diagram showing the relationship between the physical film thickness of the silicon oxide film and the XPS film thickness.
符号の説明 Explanation of symbols
20, 50 基板処理装置 21, 51 処理容器 20, 50 Substrate processing equipment 21, 51 Processing container
21A, 55 排気口  21A, 55 Exhaust port
2 ID, 54 ガスノズル  2 ID, 54 Gas nozzle
22, 53 保持台  22, 53 Holding stand
25 紫外光源  25 UV light source
25A 光学窓  25A optical window
26 リモートプラズマ源  26 Remote plasma source
26A ブロック  26A block
26B フェライトコア  26B ferrite core
26C プラズマ  26C plasma
26aガス循環通路  26a Gas circulation passage
26b ガス入り口  26b Gas inlet
26c ガス出口  26c Gas outlet
26d コーティング  26d coating
26e ィ才ンフイノレタ  26e
52, 53A 加熱手段  52, 53A Heating means
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0022] まず本発明の概要について以下に説明する。 [0022] First, the outline of the present invention will be described below.
[0023] シリコン基板を用いて、例えば図 1に示すような半導体装置を形成する場合であつ て、ゲート電極とシリコン基板の間に形成される、高誘電体材料の下地となるベース 酸化膜を形成する場合、できるだけ薄く形成することが望まし 、。  For example, when a semiconductor device as shown in FIG. 1 is formed using a silicon substrate, a base oxide film that is formed between the gate electrode and the silicon substrate and serves as a base of a high dielectric material is formed. When forming, it is desirable to make it as thin as possible.
[0024] 図 2A〜図 2Eは、シリコン基板上に、紫外線活性化 O酸化 (UV— O酸化）により、  [0024] FIG. 2A to FIG. 2E show that UV activation O oxidation (UV—O oxidation) is performed on a silicon substrate.
2 2  twenty two
極薄のシリコン酸ィ匕膜 (ベース酸ィ匕膜)を形成し、そのシリコン酸ィ匕膜の XPS (X線光 電子分光分析)スペクトルを示したものである。また、当該スペクトルは、ベース酸ィ匕 膜の膜厚力 S、 0. lnm, 0. 2nm、 0. 3nm、 0. 4nm、および 0. 8mnの場合にお!ヽて 、それぞれ、図 2A〜図 2Eに結果を示してある。  An ultra-thin silicon oxide film (base oxide film) is formed, and the XPS (X-ray photoelectron spectroscopy) spectrum of the silicon oxide film is shown. In addition, the spectrum is obtained when the film thickness force S of the base oxide film is 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, and 0.8 mn, respectively. Figure 2E shows the results.
[0025] シリコン基板上にベース酸ィ匕膜を形成する場合、シリコン基板表面のシリコン原子 は、基板内部のシリコン原子と、基板表面の酸素原子の双方により配位され、サブォ キサイドを形成していると考ええられる。例えば、図 2A〜図 2Bにおいて、すなわちべ ース酸化膜を 0. lnm〜0. 2nmとした場合には、 101〜104eVのエネルギ範囲に おいて見られる低いピークが前記サブオキサイドに対応し、酸化膜厚が 0. 3nmを超 えた場合にこのエネルギ領域に表れるピークが Si4+に起因するもので、 1原子層を超 える酸化膜の形成を表して!/、るものと考えられる。 [0025] When forming a base oxide film on a silicon substrate, silicon atoms on the surface of the silicon substrate are coordinated by both silicon atoms inside the substrate and oxygen atoms on the substrate surface. It is thought that it forms a xide. For example, in FIG. 2A to FIG. 2B, that is, when the base oxide film is 0.1 nm to 0.2 nm, a low peak seen in the energy range of 101 to 104 eV corresponds to the suboxide, When the oxide film thickness exceeds 0.3 nm, the peak appearing in this energy region is attributed to Si 4+, which is considered to represent the formation of an oxide film exceeding one atomic layer!
[0026] 例えば、ベース酸化膜の厚さが 0. lnm〜0. 2nmである場合のように、ベース酸化 膜としてサブオキサイドが形成されている場合には、当該ベース酸ィ匕膜の上層にデ バイスを形成した場合、例えばリーク電流が増大する、または電気特性が安定しない などの不具合が生じる可能性が高くなることが懸念される。  [0026] For example, when a suboxide is formed as the base oxide film as in the case where the thickness of the base oxide film is 0.1 nm to 0.2 nm, the base oxide film is formed on the upper layer of the base oxide film. When a device is formed, there is a concern that there is a high possibility that a malfunction such as an increase in leakage current or unstable electrical characteristics will occur.
[0027] このため、半導体装置を形成する場合のベース酸化膜となる膜厚は、安定な酸ィ匕 膜が形成することができる 0. 4nm以上とすることが好ましい。また、当該ベース酸ィ匕 膜は、できるだけ薄いことが好ましいため、電気的な特性が良好であって、最も薄い ベース酸化膜の膜厚、すなわち好ましいベース酸ィ匕膜の膜厚は、上記のスペクトル の結果より 0. 4nmであると考えられる。  For this reason, it is preferable that the thickness of the base oxide film when forming the semiconductor device is 0.4 nm or more so that a stable oxide film can be formed. Further, since the base oxide film is preferably as thin as possible, the electrical characteristics are good, and the thinnest base oxide film thickness, that is, the preferable base oxide film thickness is as described above. From the spectrum results, it is considered to be 0.4 nm.
[0028] しかし、この厚さのベース酸ィ匕膜を形成する場合には、シリコン基板上に形成される 自然酸ィ匕膜が問題になる場合がある。シリコン基板上に自然酸化膜が形成されると、 ベース酸ィ匕膜の厚さの制御が困難となり、所望の厚さのベース酸ィ匕膜を形成すること が困難となってしまう場合がある。また、自然酸ィ匕膜の膜質は、必要とされるベース酸 化膜の膜質の要求を満たさない場合があり、この場合には所望の電気特性を得るこ とが困難となる場合があった。  However, when a base oxide film having this thickness is formed, a natural oxide film formed on the silicon substrate may be a problem. If a natural oxide film is formed on a silicon substrate, it is difficult to control the thickness of the base oxide film, and it may be difficult to form a base oxide film having a desired thickness. . In addition, the film quality of the natural oxide film may not meet the required film quality of the base oxide film. In this case, it may be difficult to obtain desired electrical characteristics. .
[0029] そこで、本発明では、以下に示す方法でシリコン基板を洗浄することにより、当該シ リコン基板上に自然酸ィ匕膜が形成されることを抑制し、より清浄なシリコン基板表面を 保持することが可能となっている。このため、当該シリコン基板上にベース酸ィ匕膜を 形成する場合のベース酸ィ匕膜の厚さの制御性が良好となり、またベース酸ィ匕膜の膜 質の制御性も良好となり、そのために、形成される半導体装置の電気特性を良好と することができる。  [0029] Therefore, in the present invention, by cleaning the silicon substrate by the method described below, the formation of a natural oxide film on the silicon substrate is suppressed, and a cleaner silicon substrate surface is maintained. It is possible to do. For this reason, the controllability of the thickness of the base oxide film when the base oxide film is formed on the silicon substrate is improved, and the controllability of the film quality of the base oxide film is also improved. In addition, the electrical characteristics of the formed semiconductor device can be improved.
実施例 1  Example 1
[0030] 図 3は、本発明の実施例 1によるシリコン基板の洗浄方法を示すフローチャートであ る。 FIG. 3 is a flowchart showing a silicon substrate cleaning method according to the first embodiment of the present invention. The
[0031] 図 3を参照するに、本実施例による洗浄方法では、ステップ 1 (図中 S1と表示、以下 同様）において、まず、シリコン基板を、第 1の洗浄液で洗浄する。  Referring to FIG. 3, in the cleaning method according to the present embodiment, in step 1 (indicated as S1 in the figure, the same applies hereinafter), the silicon substrate is first cleaned with the first cleaning liquid.
[0032] 当該第 1の洗浄液は、濃アンモニア水 (NH OH)、過酸化水素水 (H O )、および [0032] The first cleaning liquid includes concentrated aqueous ammonia (NH OH), aqueous hydrogen peroxide (H 2 O), and
4 2 2 純水 (H O)の混合溶液よりなる。例えば、濃アンモニア水、過酸化水素水、純水の 4 2 2 Consists of a mixed solution of pure water (H 2 O). For example, concentrated ammonia water, hydrogen peroxide water, pure water
2 2
混合する割合は、例えばそれぞれ、 1 : 2 : 50とすることが好ましい。この場合、当該第 1の洗浄液は、 SC1洗浄液と呼ばれる場合があり、ステップ 1にかかる洗浄は SC1洗 浄と呼ばれる場合がある。また、本実施例においては、当該第 1の洗浄液の温度は、 例えば 60°Cとする。  For example, the mixing ratio is preferably 1: 2: 50, respectively. In this case, the first cleaning liquid may be referred to as SC1 cleaning liquid, and the cleaning according to Step 1 may be referred to as SC1 cleaning. In this embodiment, the temperature of the first cleaning liquid is, for example, 60 ° C.
[0033] 次に、ステップ 2において、当該シリコン基板を、室温の DHF (濃フッ酸を純水で希 釈したもの、濃フッ酸:純水 = 1 : 200)洗浄液により、洗浄する。  [0033] Next, in step 2, the silicon substrate is cleaned with a DHF (concentrated hydrofluoric acid diluted with pure water, concentrated hydrofluoric acid: pure water = 1: 200) cleaning solution at room temperature.
[0034] 上記ステップ 1の工程においては、おもにシリコン基板上のパーティクル (微粒子状 のごみ）や有機物汚染が除去され、ステップ 2の工程においては、ステップ 1の工程 において形成されたィ匕学酸ィ匕膜中の金属汚染などが除去される。  [0034] In the step 1 above, particles (fine particles) and organic contamination on the silicon substrate are mainly removed. In the step 2, the chemical acid formed in the step 1 is removed. Metal contamination in the capsule is removed.
[0035] 次に、必要に応じて、ステップ 3において、シリコン基板を純水により洗浄する、いわ ゆるリンス工程を実施し、シリコン基板に残留した第 1の洗浄液または DHF洗浄液な どを除去する。  [0035] Next, if necessary, in step 3, a so-called rinsing process of cleaning the silicon substrate with pure water is performed to remove the first cleaning liquid or DHF cleaning liquid remaining on the silicon substrate.
[0036] 次に、ステップ 4において、シリコン基板を、第 2の洗浄液で洗浄する。  [0036] Next, in step 4, the silicon substrate is cleaned with a second cleaning liquid.
[0037] 当該第 2の洗浄液は、濃塩酸 (HC1)、過酸化水素水 (H O )、および純水 (H O)  [0037] The second cleaning liquid is concentrated hydrochloric acid (HC1), hydrogen peroxide (H 2 O), and pure water (H 2 O).
2 2 2 の混合溶液よりなる。例えば、濃塩酸、過酸化水素水、純水の混合する割合は、例え ばそれぞれ、 1 : 2 :40とすること力好ましい。この場合、当該第 2の洗浄液は、 SC2洗 浄液と呼ばれる場合があり、ステップ 4にカゝかる洗浄は SC2洗浄と呼ばれる場合があ る。また、本実施例においては、当該第 2の洗浄液の温度は、例えば 70°Cとする。  It consists of a mixed solution of 2 2 2. For example, the mixing ratio of concentrated hydrochloric acid, hydrogen peroxide solution, and pure water is preferably set to 1: 2: 40, for example. In this case, the second cleaning solution may be referred to as an SC2 cleaning solution, and the cleaning that goes to step 4 may be referred to as an SC2 cleaning. In this embodiment, the temperature of the second cleaning liquid is, for example, 70 ° C.
[0038] 次に、ステップ 5において、当該シリコン基板を、室温の DHF (濃フッ酸を純水で希 釈したもの、濃フッ酸:純水 = 1 : 200)洗浄液により、洗浄する。  [0038] Next, in step 5, the silicon substrate is cleaned with a DHF cleaning solution at room temperature (concentrated hydrofluoric acid diluted with pure water, concentrated hydrofluoric acid: pure water = 1: 200).
[0039] 上記ステップ 5において、おもにシリコン基板上の金属汚染力 さらにステップ 6で はステップ 5の工程において形成されたシリコン基板上の化学酸ィ匕膜が除去される。  [0039] In step 5 above, metal contamination on the silicon substrate mainly, and in step 6, the chemical oxide film on the silicon substrate formed in step 5 is removed.
[0040] さらに、必要に応じて、ステップ 4〜ステップ 5の処理を所定の回数繰り返して、シリ コン基板の洗浄を完了する。 [0040] Further, if necessary, the processing of step 4 to step 5 is repeated a predetermined number of times to Complete the cleaning of the circuit board.
[0041] 基板の洗浄後は、必要に応じて IPA (イソプロピルアルコール)の蒸気による乾燥を 行うと、洗浄液の後（ウォーターマーク）の発生を抑制することができ、好適である。  [0041] After the substrate is cleaned, if necessary, drying with IPA (isopropyl alcohol) vapor is performed, which is preferable because generation of the cleaning liquid (watermark) can be suppressed.
[0042] 次に、洗浄が完了し、化学酸化膜や汚染物が除去されて清浄となったシリコン基板 表面に、ステップ 6で、例えば MOSトランジスタのベース酸ィ匕膜となる、シリコン酸ィ匕 膜を形成する。  [0042] Next, on the surface of the silicon substrate that has been cleaned and cleaned by removing the chemical oxide film and contaminants, in step 6, for example, a silicon oxide film that becomes a base oxide film of a MOS transistor is formed. A film is formed.
[0043] さらに、ステップ 7で、当該ベース酸ィ匕膜上に、高誘電体膜を形成し、ステップ 8で、 当該ベース酸ィ匕膜の窒化を行う。ベース酸ィ匕膜の窒化は、ベース酸ィ匕膜形成後であ つて高誘電体形成前に行ってもよぐ本図に記載したようにベース酸ィ匕膜上に高誘 電体膜を形成した後、高誘電体膜を介してベース酸化膜を窒化してもよい。このよう なベース酸化膜の形成方法や、当該ベース酸ィ匕膜の窒化の方法の詳細に関しては 後述する。この後の工程においては、定法である、 MOSトランジスタの形成方法によ つて、例えばゲート電極の形成や不純物の打ち込み、また電極の形成などを行って MOSトランジスタなどの半導体デバイスを形成することができる。  [0043] Further, in step 7, a high dielectric film is formed on the base oxide film, and in step 8, the base oxide film is nitrided. The nitriding of the base oxide film may be performed after the base oxide film is formed and before the formation of the high dielectric, as shown in FIG. After the formation, the base oxide film may be nitrided through the high dielectric film. Details of the method for forming such a base oxide film and the method for nitriding the base oxide film will be described later. In subsequent steps, a semiconductor device such as a MOS transistor can be formed by, for example, forming a gate electrode, implanting an impurity, or forming an electrode by a conventional method of forming a MOS transistor. .
[0044] 本実施例による上記の洗浄方法を実施した場合、従来の洗浄方法に比べてシリコ ン基板上に自然酸ィ匕膜が形成されることを抑制することができることを、本発明の発 明者は見出した。これらの概要と、この基板処理方法の原理について以下に説明す る。  [0044] When the above cleaning method according to the present embodiment is performed, it is possible to suppress the formation of a natural oxide film on the silicon substrate as compared with the conventional cleaning method. Akira found. These outlines and the principle of this substrate processing method will be described below.
[0045] 図 4Aは、 DHF洗浄によりシリコン基板上の自然酸化膜を除去し、熱酸ィ匕などによ り形成された典型的なシリコン酸化膜 (以降文中、典型的な酸化膜)の XPS (X線光 電子分光分析)スペクトルと、当該 XPSスペクトルの拡大図を示し、図 4Bは、 DHF洗 浄によりシリコン基板上の自然酸化膜や化学酸化膜を除去した後、 SC2洗浄を実行 し、この際に形成された化学酸化膜 (以降文中 SC2酸化膜と記載する）の XPSスぺク トルと、当該 XPSスペクトルの拡大図を示したものである。なお、シリコン基板は、シリ コン酸化膜が形成される表面が、 (100)面である基板 (以下（100)基板と表記)を用 いている。  [0045] FIG. 4A shows an XPS of a typical silicon oxide film (hereinafter referred to as a typical oxide film) formed by removing the natural oxide film on the silicon substrate by DHF cleaning and using thermal acid. (X-ray photoelectron spectroscopic analysis) spectrum and enlarged view of the XPS spectrum are shown. Fig. 4B shows that after removing the natural oxide film and chemical oxide film on the silicon substrate by DHF cleaning, SC2 cleaning is performed. The XPS spectrum of the chemical oxide film formed at this time (hereinafter referred to as SC2 oxide film in the text) and an enlarged view of the XPS spectrum are shown. The silicon substrate uses a substrate (hereinafter referred to as (100) substrate) in which the surface on which the silicon oxide film is formed is a (100) plane.
[0046] まず、図 4Aを参照すると、シリコン基板上に形成された、典型的な酸化膜のスぺク トルでは、 Siに起因する、結合エネルギーが 99〜100eV程度の領域のピークと、 Si Oに起因する、結合エネルギー 103eV程度の領域のピークが観察されている。[0046] First, referring to FIG. 4A, in a typical oxide film spectrum formed on a silicon substrate, a peak in a region where the binding energy is about 99 to 100 eV due to Si, A peak in the region with a binding energy of about 103 eV due to O is observed.
2 2
[0047] 一方、図 4Bを参照すると、シリコン基板上に形成された、 SC2酸ィ匕膜の場合であつ ても上記の典型的な酸ィ匕膜のスペクトルと同様に、 Siに起因する、結合エネルギー 力 S99〜100eV程度の領域のピークと、 SiOに起因する、結合エネルギー 103eV程  [0047] On the other hand, referring to FIG. 4B, even in the case of the SC2 oxide film formed on the silicon substrate, the spectrum of the typical oxide film is caused by Si. Bond energy force Peak in the region of about S99-100eV and bond energy of about 103eV due to SiO
2  2
度の領域のピークが観察されて 、る。  A peak in the region of degrees is observed.
[0048] し力し、図 4Aのスペクトルと、図 4Bのスペクトルを比較すると、結合エネルギーが 1 01eV〜102eV程度の領域（図中それぞれ A, A，にて表示される領域）においてそ の違いが観察される。  [0048] When comparing the spectrum of Fig. 4A with the spectrum of Fig. 4B, the difference is found in the region where the binding energy is about 101 eV to 102 eV (the regions indicated by A and A in the figure, respectively). Is observed.
[0049] 例えば、図 4Aに示した典型的な酸ィ匕膜のスペクトルでは、結合エネルギー 101〜 102eV付近でスペクトルがベースラインから離れており、 Siや SiOに起因するピーク  [0049] For example, in the spectrum of the typical oxide film shown in Fig. 4A, the spectrum is far from the baseline around the binding energy of 101 to 102eV, and the peak is caused by Si or SiO.
2  2
に比べて小さいものの、明らかにピークが存在することがわかる。  It can be seen that there is a clear peak although it is smaller than.
[0050] 一方、図 4Bに示した SC2酸化膜のスペクトルでは、結合エネルギーが 10 leV〜l 02eVで、スペクトルがベースラインに略一致する部分がある。すなわち、典型的な酸 ィ匕膜の場合には検出されて、 SC2酸ィ匕膜の場合には実質的に検出されないピーク が存在して！/、ることがゎ力ゝる。  On the other hand, in the spectrum of the SC2 oxide film shown in FIG. 4B, there is a portion where the binding energy is 10 leV to 102 eV and the spectrum substantially matches the baseline. That is, there is a peak that is detected in the case of a typical oxide film, but not substantially detected in the case of an SC2 oxide film! / It ’s powerful to do.
[0051] このように、結合エネルギーが 101eV〜102eV付近で、 XPSのスペクトルに差が 生じるのは、その Si基板の表面の Si原子の状態の違いに起因して 、ると考えることが できる。この場合、シリコン基板表面の Si原子は、基板内部のシリコン原子と、基板表 面の酸素原子の双方により配位され、サブオキサイドを形成していると考えられる。こ れらのサブオキサイドに起因する XPSのスペクトルのピーク (検出強度）は、結合エネ ルギ一が 101eV〜102eV付近に観察されることが知られている。  [0051] Thus, it can be considered that the difference in the XPS spectrum occurs when the binding energy is between 101 eV and 102 eV, due to the difference in the state of Si atoms on the surface of the Si substrate. In this case, it is considered that Si atoms on the silicon substrate surface are coordinated by both silicon atoms inside the substrate and oxygen atoms on the substrate surface to form suboxides. It is known that the peak (detection intensity) of the XPS spectrum due to these suboxides is observed in the vicinity of 101 eV to 102 eV.
[0052] 例えば、シリコンの（100)基板上に形成されるシリコン酸化膜の、 XPSスペクトルの 代表的な例を図 5Aに示す。また、図 5Aを見やすくするために、当該スペクトルから スピン軌道 1Z2をリムーブして再プロットしたものを図 5Bに示す。  For example, FIG. 5A shows a typical example of an XPS spectrum of a silicon oxide film formed on a (100) substrate of silicon. Also, in order to make it easier to see FIG. 5A, the spin orbit 1Z2 is removed from the spectrum and replotted is shown in FIG. 5B.
[0053] 図 5Aおよび図 5Bを参照するに、 Siのサブオキサイドのピークは、図中に矢印で示 すように、 Siに起因するピークと SiOに起因するピークの間に観察される。一般的に  [0053] Referring to FIG. 5A and FIG. 5B, the Si suboxide peak is observed between the peak due to Si and the peak due to SiO, as indicated by arrows in the figure. Typically
2  2
、シリコンの（100)基板上にシリコン酸ィ匕膜が形成される場合には、 Siの結晶構造よ り、サブオキサイドのピークはおもに Si2+に起因するものであり、 Si1+、または Si3+に起 因するピークは殆ど観察されないと考えられている。この場合、 Si1+に起因するピーク は、 Siのピーク側に、 Si3+に起因するピークは、 SiOのピーク側に、 Si2+に起因する When a silicon oxide film is formed on a (100) substrate of silicon, the suboxide peak is mainly caused by Si 2+ due to Si crystal structure, and Si 1+ , or Start with Si 3+ It is thought that the peak due to this is hardly observed. In this case, the peak due to Si 1+ is due to Si peak, and the peak due to Si 3+ is due to Si 2+ due to Si peak.
2  2
ピークは、 Si1+に起因するピークと Si3+に起因するピークの間に観察される。 A peak is observed between the peak due to Si 1+ and the peak due to Si 3+ .
[0054] 一方、シリコンの（111)基板上に形成されるシリコン酸化膜の、 XPSスペクトルの代 表的な例を図 6Aに示す。また、図 6Aを見やすくするために、当該スペクトルからスピ ン軌道 1Z2をリムーブして再プロットしたものを図 6Bに示す。 On the other hand, FIG. 6A shows a typical example of an XPS spectrum of a silicon oxide film formed on a silicon (111) substrate. To make it easier to see Fig. 6A, Fig. 6B shows the result of removing the spin orbit 1Z2 from the spectrum and replotting it.
[0055] 図 6Aおよび図 6Bを参照するに、 Siのサブオキサイドのピークは、図中に矢印で示 すように、 Siに起因するピークと SiOに起因するピークの間に観察される。一般的に [0055] Referring to FIGS. 6A and 6B, the Si suboxide peak is observed between the peak due to Si and the peak due to SiO, as indicated by arrows in the figure. Typically
2  2
、シリコンの（111)基板上にシリコン酸ィ匕膜が形成される場合には、（100)基板上に 形成される場合と異なり、 Siの結晶構造より、サブオキサイドのピークはおもに Si1+、ま たは Si3+に起因するものであり、 Si2+に起因するピークは殆ど観察されない。この場合 、 Si2+に起因するピークが観察される結合エネルギー付近では、検出強度は殆どべ ースライン近傍に近 ヽ値となって 、る。 When a silicon oxide film is formed on a (111) substrate of silicon, unlike the case of being formed on a (100) substrate, the peak of suboxide is mainly Si 1+ due to the crystal structure of Si. Also, this is due to Si 3+ , and almost no peaks due to Si 2+ are observed. In this case, in the vicinity of the binding energy where a peak due to Si 2+ is observed, the detected intensity is almost in the vicinity of the base line.
[0056] このように、シリコン基板上にシリコン酸ィ匕膜が形成される場合に、 Si基板の面方位 によって観察される XPSスペクトルが異なるのは、以下に示すように、 Siの結晶構造 によるものである。図 7は、 Siの結晶構造を模式的に示した図である。この場合、 (10 0)面と（111)面では、面方向からみたィ匕学結合手の状態が異なり、例えば（100)面 においては Si2+力 （111)面においては、 Si1+、または Si3+が観察されることがわかる [0056] As described below, when the silicon oxide film is formed on the silicon substrate, the XPS spectrum observed depending on the plane orientation of the Si substrate is different depending on the crystal structure of Si as shown below. Is. FIG. 7 is a diagram schematically showing the crystal structure of Si. In this case, the (100) plane and (111) plane are different in the state of the chemical bond as seen from the plane direction. For example, the Si 2+ force in the (100) plane is Si 1+ Or Si 3+ is observed
[0057] ここで、図 4Aおよび図 4Bに示した、典型的な酸化膜および SC2酸化膜の、 Si 3 2 [0057] Here, Si 3 2 of the typical oxide film and SC2 oxide film shown in FIGS. 4A and 4B are shown.
2p 2p
XPSスペクトルを、上記の Siの結晶構造とスペクトルの代表的な状態を考慮して、さ らに詳細に分析した図を図 8Aおよび図 8Bにそれぞれ示す。 Figures 8A and 8B show the XPS spectra analyzed in more detail in consideration of the Si crystal structure and the typical state of the spectra.
[0058] 図 8Aを参照するに、本図に示す典型的な酸化膜のスペクトルでは、 Siの（100)基 板上にシリコン酸ィ匕膜を形成した場合に一般的に観察される Si2+に起因するピーク が観察され、矢印で示すように、 lOleV付近で明らかにベースライン力 検出強度 の立ち上がりが観察されていることがわかる。 [0058] Referring to FIG. 8A, in the spectrum of a typical oxide film shown in the figure, Si 2 commonly observed in the case of forming a silicon Sani匕膜(100) board on the Si A peak due to + is observed, and as shown by the arrow, it is clear that the rise of the baseline force detection intensity is clearly observed near lOleV.
[0059] 一方、図 8Bを参照すると、本図に示す SC2酸ィ匕膜のスペクトルでは、上記の典型 的な酸ィ匕膜の場合に観察された Si2+に起因するピークが殆どみられない特徴がある 。例えば、 lOleV付近では、ベースライン力もの検出強度の立ち上がりが典型的な 酸ィ匕膜の場合に比べて小さぐピークは殆ど観察されていない。一方、 Si1+、または S i3+に起因するピークが観察されて 、ると考えられる。 [0059] On the other hand, referring to FIG. 8B, in the spectrum of the SC2 oxide film shown in this figure, most of the peaks attributed to Si 2+ observed in the case of the above typical oxide film are observed. There are no features . For example, in the vicinity of lOleV, almost no peaks are observed where the rise of the detection intensity of the baseline force is smaller than that of a typical oxide film. On the other hand, it is considered that peaks due to Si 1+ or Si 3+ are observed.
[0060] また、上記の図 8A、図 8Bのスペクトルでは、ベースライン（バックグランド）をリニア にとつている。図 9A,図 9Bには、図 8A、図 8Bのスペクトルにおいて、ベースラインを[0060] Further, in the spectra shown in FIGS. 8A and 8B, the baseline (background) is linear. Figures 9A and 9B show the baselines in the spectra of Figures 8A and 8B.
、いわゆるシヤーリー法により算出した結果をそれぞれ示す。 The results calculated by the so-called Shirley method are respectively shown.
[0061] 図 9A、および図 9Bを参照するに、典型的な酸化膜の場合、および SC2酸ィ匕膜の 場合のいずれにおいても、図 8A、および図 8Bに示した場合と同様の結果となってい る。 [0061] Referring to FIGS. 9A and 9B, in both the case of the typical oxide film and the case of the SC2 oxide film, the same results as those shown in FIGS. 8A and 8B are obtained. It has become.
[0062] すなわち、典型的な酸化膜のスペクトルでは、 Siの（100)基板上にシリコン酸ィ匕膜 を形成した場合に一般的に観察される Si2+に起因するピークが観察される一方で、 S C2酸ィ匕膜のスペクトルでは、上記の典型的な酸ィ匕膜の場合に観察された Si2+に起 因するピークが殆どみられない。また、化学酸ィ匕膜のスペクトルでは Si1+、または Si3+ に起因するピークが小さぐ SC2酸ィ匕膜のスペクトルでは Si1+、または Si3+に起因する ピークは相対的に大きいと考えられる。 [0062] That is, in a typical oxide film spectrum, a peak due to Si 2+ generally observed when a silicon oxide film is formed on a Si (100) substrate is observed. On the other hand, in the spectrum of the SC2 oxide film, there is almost no peak due to Si 2+ observed in the case of the above typical oxide film. In addition, the peak due to Si 1+ or Si 3+ is small in the spectrum of chemical oxide film. The peak due to Si 1+ or Si 3+ is relatively large in the spectrum of SC2 oxide film. it is conceivable that.
[0063] 以上のことを考慮すると、本実施例による洗浄工程では、シリコン基板表面は以下 のようになって!/、ると考えられる。  [0063] In consideration of the above, in the cleaning process according to the present example, it is considered that the surface of the silicon substrate is as follows!
[0064] 図 10Aは、図 3に示した本実施例による基板処理方法において、ステップ 5終了後 の、予想されるシリコン基板表面の状態を模式的に示した図である。  [0064] FIG. 10A is a diagram schematically showing an expected state of the silicon substrate surface after step 5 in the substrate processing method according to the present embodiment shown in FIG.
[0065] 図 10Aを参照するに、シリコン基板の（100)面は、ステップ 5終了後には、（111) 面のマイクロファセットよりなるピラミッド状の構造体が複数形成された状態となってい ると考えられる。また、図 10Aの A—A'断面を図 10Bに示す。図 10Bを参照するに、 (111)面よりなる当該マイクロファセット上には、 SC2酸化膜が形成されていると考え られる。これは、おもに SC2洗浄液中に含まれる H Oにより、シリコン基板上に形成  [0065] Referring to FIG. 10A, the (100) plane of the silicon substrate is in a state in which a plurality of pyramidal structures composed of (111) plane microfacets are formed after step 5 is completed. Conceivable. Further, FIG. 10B shows a cross section taken along the line AA ′ of FIG. 10A. Referring to FIG. 10B, it is considered that an SC2 oxide film is formed on the microfacet composed of the (111) plane. This is mainly formed on the silicon substrate by H 2 O contained in the SC2 cleaning solution.
2 2  twenty two
されるちのである。  It will be done.
[0066] シリコン基板上が上記のような状態になっていると考えた場合、図 4B、図 8B、およ び図 9Bに示した SC2酸化膜の XPSスペクトルの結果とよく一致する。すなわち、 XP Sスペクトル〖こ、一般的にシリコンの（100)面上に形成された場合にみられる Si2+に 起因するピークが殆どみられず、 Si1+、または Si3+に起因するピークが観察されること は、（111)面よりなるマイクロファセット上にシリコン酸ィ匕膜が形成されて 、ると考える ことでよく説明できる。 [0066] When it is considered that the silicon substrate is in the above-described state, the XPS spectrum results of the SC2 oxide film shown in FIGS. 4B, 8B, and 9B agree well. That is, the XPS spectrum, generally Si 2+ found when formed on the (100) surface of silicon. Most of the peaks due to Si 1+ or Si 3+ are observed, which means that the silicon oxide film is formed on the (111) face microfacets. It can be explained well by thinking.
[0067] また、図 3に示した基板処理方法の場合、ステップ 4とステップ 5の処理を繰り返すこ とで、シリコン基板表面の状態は、以下のように変化していくと考えられる。  [0067] Further, in the case of the substrate processing method shown in FIG. 3, it is considered that the state of the silicon substrate surface changes as follows by repeating the processing of step 4 and step 5.
[0068] 図 11A〜図 11Fは、図 3に示した本実施例による基板処理方法において、ステップ 4とステップ 5の処理を繰り返した場合に予想されるシリコン基板の表面状態 (モホロ ジー）の変化を模式的に示した図である。図 11Aは、ステップ 4とステップ 5の処理を 最初に行った後の状態を、以下図 11B〜図 11Eは、それぞれステップ 4とステップ 5 の処理を 2〜5回繰り返した後に、予想されるシリコン基板の状態 (モホロジー）の変 化を模式的に示した図である。  [0068] FIGS. 11A to 11F show changes in the surface state (morphology) of a silicon substrate that are expected when the processes in steps 4 and 5 are repeated in the substrate processing method according to the present embodiment shown in FIG. FIG. Figure 11A shows the state after the initial processing of Step 4 and Step 5, and Figures 11B to 11E show the expected silicon after repeating Step 4 and Step 5 2-5 times, respectively. FIG. 5 is a diagram schematically showing changes in the state (morphology) of a substrate.
[0069] 図 11A〜図 11Eを参照するに、ステップ 4とステップ 5の処理を繰り返すことで、上 記のピラミッド構造が小さくなるようにして、（111)面のマイクロファセットが徐々に消 失し、（100)面の割合が増大していくと予想される。  [0069] Referring to FIG. 11A to FIG. 11E, by repeating the processes of Step 4 and Step 5, the above-mentioned pyramid structure is reduced, and the microfacets on the (111) plane gradually disappear. The percentage of the (100) plane is expected to increase.
[0070] すなわち、ステップ 4とステップ 5の処理を繰り返すことで、シリコン基板上の表面の 平坦ィ匕 (ラフネスの低減）が進行していくと考えられる。このように、本実施例による基 板処理方法では、シリコン基板表面の平坦ィ匕が進行した状態で、 Siの結合手が H ( 水素)で終端された状態となると考えられ、表面状態が安定になると考えられる。  That is, it is considered that the flatness (reduction in roughness) of the surface on the silicon substrate progresses by repeating the processing in step 4 and step 5. Thus, in the substrate processing method according to the present example, it is considered that the Si bond is terminated with H (hydrogen) while the flatness of the silicon substrate surface is advanced, and the surface state is stable. It is thought that it becomes.
[0071] このようにシリコン基板の表面が安定な状態となると、 Siが酸素と結合することが抑 制され、安定で清浄な表面状態を保持することが可能となると考えられる。  As described above, when the surface of the silicon substrate is in a stable state, it is considered that the bonding of Si to oxygen is suppressed, and a stable and clean surface state can be maintained.
[0072] また、上記はシリコン基板表面のモホロジ一の変化を模式的に示した一例であり、 ステップ 4とステップ 5の処理の回数による平坦ィ匕の進行の状態は、洗浄液の温度や または洗浄液の混合比、またシリコン基板の表面の状態 (パーティクル、汚染など）に よって随時変化するものである。そのため、ステップ 4とステップ 5の処理を繰り返す回 数は、これらの状態に応じて適宜変化させて用いることが好ま 、。  [0072] The above is an example schematically showing the change in the morphology of the silicon substrate surface, and the progress of the flatness depending on the number of times of the processing in Step 4 and Step 5 depends on the temperature of the cleaning liquid or the cleaning liquid. It changes at any time depending on the mixing ratio and the surface condition (particles, contamination, etc.) of the silicon substrate. For this reason, it is preferable that the number of times of repeating the processing of Step 4 and Step 5 is appropriately changed according to these states.
[0073] 図 12A、図 12Bは、本実施例に基板処理方法を用いることで得られると考えられる 効果を、模式的に示したものである。  FIG. 12A and FIG. 12B schematically show the effects considered to be obtained by using the substrate processing method in this example.
[0074] 図 12Aは、横軸にステップ 4〜ステップ 5の処理を繰り返した回数、縦軸にシリコン 基板表面のラフネス (Rms)をとり、本実施例による基板処理方法により、基板表面の 平坦化が進行する状態の予想を、模式的に示したものである。図 12Aを参照するに 、ステップ 4〜ステップ 5の処理を繰り返すことで、シリコン基板表面の平坦度は向上 していくと考えられる。 [0074] In FIG. 12A, the horizontal axis represents the number of times the processing in Step 4 to Step 5 was repeated, and the vertical axis represents silicon. The roughness (Rms) of the substrate surface is taken, and the prediction of the state in which the planarization of the substrate surface proceeds by the substrate processing method according to this example is schematically shown. Referring to FIG. 12A, it is considered that the flatness of the silicon substrate surface is improved by repeating the processing of step 4 to step 5.
[0075] また、例えばシリコン基板表面状態を、必ずしも図 11Eの状態で用いる必要は無く 、例えば図 11Cや図 11Dなど、平坦化が有る程度進行した状態であれば、平坦化の 進行状態に対応して、 Siが酸素と結合することが抑制される効果は得られるものと予 想される。  [0075] Further, for example, the surface state of the silicon substrate does not necessarily need to be used in the state of FIG. 11E. For example, as shown in FIG. 11C and FIG. Thus, it is expected that an effect of suppressing the bonding of Si to oxygen can be obtained.
[0076] また、図 12Bは、従来の基板処理方法と、本実施例による基板処理方法において 大気放置の際に形成される自然酸化膜の厚さの違いを予想し、模式的に表した図で ある。図 12Bでは、横軸に洗浄処理後の経過時間をとり、縦軸に形成される自然酸 化膜の厚さをとり、その予想される差を模式的に示している。  [0076] FIG. 12B is a diagram schematically showing a difference in the thickness of the natural oxide film formed when the substrate is left in the atmosphere in the conventional substrate processing method and the substrate processing method according to this example. It is. In FIG. 12B, the elapsed time after the cleaning treatment is taken on the horizontal axis, and the thickness of the natural oxide film formed on the vertical axis, and the expected difference is schematically shown.
[0077] 本実施例による基板処理方法の場合には、基板表面の Siが酸素と結合することが 抑制されると考えら得る。そのため、従来の基板処理方法に比べて、洗浄処理後の 自然酸化膜の形成が抑制されると考えられる。そのため、本実施例による基板処理 方法では、シリコン基板上に、高速度デバイスに用いることが好ましいベース酸ィ匕膜 を形成することが可能となる。  [0077] In the case of the substrate processing method according to the present example, it can be considered that Si on the substrate surface is suppressed from being bonded to oxygen. Therefore, it is considered that the formation of a natural oxide film after the cleaning process is suppressed as compared with the conventional substrate processing method. Therefore, in the substrate processing method according to the present embodiment, a base oxide film that is preferably used for a high-speed device can be formed on a silicon substrate.
[0078] 例えば、シリコン基板上に形成される MOSトランジスタなどのデバイスを高速度で 動作させようとした場合、ゲート電極とシリコン基板の間には、 HfO、 ZrO、 Al Oな  [0078] For example, when a device such as a MOS transistor formed on a silicon substrate is to be operated at a high speed, there are HfO, ZrO, AlO, etc. between the gate electrode and the silicon substrate.
2 2 2 3 どのいわゆる高誘電体膜が形成される。この場合、当該高誘電体とシリコン基板の間 には、ベース酸ィ匕膜を形成することが好ましぐまた、ベース酸化膜は非常に薄い必 要があり、厚さが厚いと高誘電体膜をゲート絶縁膜に使った効果が相殺される。  2 2 2 3 Which so-called high dielectric film is formed. In this case, it is preferable to form a base oxide film between the high dielectric material and the silicon substrate, and the base oxide film needs to be very thin. The effect of using the film as a gate insulating film is offset.
[0079] このため、シリコン基板上に自然酸化膜が形成されると、ベース酸ィ匕膜を薄くするこ とが困難になってしまう場合があった。本実施例による基板処理方法では、シリコン 基板表面に、自然酸化膜が形成されることが抑制されるため、シリコン基板上に形成 する実質的なベース酸ィ匕膜を薄くすることができる。  For this reason, when a natural oxide film is formed on a silicon substrate, it may be difficult to make the base oxide film thin. In the substrate processing method according to the present embodiment, since a natural oxide film is suppressed from being formed on the surface of the silicon substrate, the substantial base oxide film formed on the silicon substrate can be thinned.
[0080] また、膜厚の制御が困難であった自然酸化膜の形成が抑制されるため、後の工程 で形成されるベース酸ィ匕膜の膜厚の制御性を良好にすることが可能となっている。 [0081] 次に、本実施例による基板処理方法において、ステップ 6〜ステップ 8において、シ リコン基板上にシリコン酸化膜 (ベース酸化膜)を形成する方法、高誘電体膜を形成 する方法、および酸ィ匕膜を窒化する方法の例について、以下に説明する。 [0080] Further, since the formation of a natural oxide film, which is difficult to control the film thickness, is suppressed, it is possible to improve the controllability of the film thickness of the base oxide film formed in the subsequent process. It has become. [0081] Next, in the substrate processing method according to the present embodiment, in steps 6 to 8, a method of forming a silicon oxide film (base oxide film) on the silicon substrate, a method of forming a high dielectric film, and An example of a method for nitriding the oxide film will be described below.
[0082] 図 13Aは、本実施例による基板処理方法において、シリコン基板の洗浄後にステツ プ 6においてシリコン酸化膜を形成する基板処理装置 20と、当該基板処理装置 20 によってシリコン酸ィ匕膜を形成する方法を模式的に示した図である。  FIG. 13A shows a substrate processing apparatus 20 for forming a silicon oxide film in step 6 after cleaning a silicon substrate and a silicon oxide film formed by the substrate processing apparatus 20 in the substrate processing method according to the present embodiment. It is the figure which showed the method to do typically.
[0083] 図 13Aを参照するに、基板処理装置 20は、被処理基板 Wを保持する基板保持台 22を収納し、前記基板保持台 22と共にプロセス空間 21Bを画成する処理容器 21を 備えている。  Referring to FIG. 13A, a substrate processing apparatus 20 includes a processing container 21 that houses a substrate holding table 22 that holds a substrate W to be processed, and that defines a process space 21 B together with the substrate holding table 22. Yes.
[0084] 前記基板処理装置 20には、前記プロセス空間 21Bを排気する排気口 21Aが形成 されており、前記排気口 21Aには、図示を省略する、例えば真空ポンプなどの排気 手段が接続され、前記プロセス空間 21Bを減圧 (排気)することが可能になっている。  [0084] The substrate processing apparatus 20 has an exhaust port 21A for exhausting the process space 21B. The exhaust port 21A is connected to an exhaust means (not shown) such as a vacuum pump. The process space 21B can be depressurized (exhaust).
[0085] 前記処理容器 21には、被処理基板 Wを隔てて前記排気口 21Aと対向する側に酸 素ガスが供給される処理ガス供給ノズル 21Dが設けられており、前記処理ガス供給ノ ズル 21Dに供給された酸素ガスは、前記プロセス空間 21B中を前記被処理基板 W の表面に沿って流れ、前記排気口 21Aから排気される。  [0085] The processing container 21 is provided with a processing gas supply nozzle 21D for supplying oxygen gas to the side facing the exhaust port 21A across the substrate W to be processed, and the processing gas supply nozzle. The oxygen gas supplied to 21D flows in the process space 21B along the surface of the substrate to be processed W, and is exhausted from the exhaust port 21A.
[0086] このように前記処理ガス供給ノズル 21Dカゝら供給された処理ガスを活性ィ匕し酸素ラ ジカルを生成させるため、前記基板処理装置 20には、前記処理ガス供給ノズル 21 D と被処理基板 Wとの間の領域に対応して石英窓 25Aを有する紫外光源 25が設けら れる。  In this way, in order to activate the processing gas supplied from the processing gas supply nozzle 21D and generate oxygen radicals, the substrate processing apparatus 20 includes the processing gas supply nozzle 21D and the target gas. An ultraviolet light source 25 having a quartz window 25A is provided corresponding to a region between the processing substrate W and the substrate.
[0087] すなわち前記紫外光源 25を駆動することにより前記処理ガス供給ノズル 21Dから プロセス空間 21Bに導入された酸素ガスが活性化され、その結果形成された酸素ラ ジカルが前記被処理基板 Wの表面に沿って流れる。これにより、前記被処理基板 W の表面に、 lnm以下の膜厚のシリコン酸ィ匕膜 (ベース酸ィ匕膜)を形成することが可能 になる。  That is, by driving the ultraviolet light source 25, the oxygen gas introduced into the process space 21B from the processing gas supply nozzle 21D is activated, and the oxygen radical formed as a result becomes the surface of the substrate W to be processed. Flowing along. As a result, a silicon oxide film (base oxide film) having a thickness of 1 nm or less can be formed on the surface of the substrate W to be processed.
[0088] このように、紫外光を用いて酸素ガスを活性ィ匕し、酸化膜を形成する方法は、その 酸化の進行が比較的遅ぐ膜厚の制御が容易であるため、薄いことが好ましいベー ス酸化膜を形成する場合に好適である。 [0089] また前記処理容器 21には前記被処理基板 Wに対して排気口 21Aと対向する側に リモートプラズマ源 26が形成されている。前記リモートプラズマ源 26に Arなどの不活 性ガスと共に窒素ガスを供給し、これをプラズマにより活性ィ匕することにより、窒素ラジ カルを形成することが可能である。 [0088] As described above, the method of activating the oxygen gas using ultraviolet light to form the oxide film is thin because the progress of the oxidation is relatively slow and the control of the film thickness is easy. This is suitable for forming a preferable base oxide film. Further, a remote plasma source 26 is formed in the processing container 21 on the side facing the exhaust port 21A with respect to the substrate W to be processed. Nitrogen radicals can be formed by supplying nitrogen gas to the remote plasma source 26 together with an inert gas such as Ar and activating it with plasma.
[0090] 図 13Bは、前記基板処理装置 20を用いて、ベース酸化膜を窒化する方法を模式 的に示した図である。ただし図中、先に説明した部分には同一の参照符号を付し、 説明を省略する。前記リモートプラズマ源 26に、例えば Arなどのキャリアガスと共に 供給された Nガスは、プラズマにより活性ィ匕され、窒素ラジカルが形成される。このよ  FIG. 13B is a diagram schematically showing a method for nitriding a base oxide film using the substrate processing apparatus 20. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. The N gas supplied to the remote plasma source 26 together with a carrier gas such as Ar, for example, is activated by the plasma to form nitrogen radicals. This
2  2
うにして形成された窒素ラジカルは前記被処理基板 wの表面に沿って流れ、例えば 基板上に形成されたベース酸化膜を窒化する。  The nitrogen radicals thus formed flow along the surface of the substrate to be processed w, and for example, nitride a base oxide film formed on the substrate.
[0091] 図 14は、前記基板処理装置 20において使われるリモートプラズマ源 26の構成の 一例を示したものである。  FIG. 14 shows an example of the configuration of the remote plasma source 26 used in the substrate processing apparatus 20.
[0092] 図 14を参照するに、リモートプラズマ源 26は、内部にガス循環通路 26aとこれに連 通したガス入り口 26bおよびガス出口 26cを形成された、典型的にはアルミニウムより なるブロック 26Aを含み、前記ブロック 26Aの一部にはフェライトコア 26Bが形成され ている。 [0092] Referring to FIG. 14, the remote plasma source 26 includes a block 26A, typically made of aluminum, in which a gas circulation passage 26a and a gas inlet 26b and a gas outlet 26c communicating with the gas circulation passage 26a are formed. In addition, a ferrite core 26B is formed in a part of the block 26A.
[0093] 前記ガス循環通路 26aおよびガス入り口 26b、ガス出口 26cの内面にはフッ素榭脂 コーティング 26dが施され、前記フェライトコア 26Bに卷回されたコイルに周波数が 4 OOkHzの高周波を供給することにより、前記ガス循環通路 26a内にプラズマ 26Cが 形成される。  [0093] Fluorine resin coating 26d is applied to the inner surfaces of the gas circulation passage 26a, the gas inlet 26b, and the gas outlet 26c, and a high frequency of 4 OOkHz is supplied to the coil wound around the ferrite core 26B. As a result, plasma 26C is formed in the gas circulation passage 26a.
[0094] プラズマ 26Cの励起に伴って、前記ガス循環通路 26a中には窒素ラジカルおよび 窒素イオンが形成されるが、窒素イオンは前記循環通路 26aを循環する際に消滅し 、前記ガス出口 26cからは主に窒素ラジカル N *が放出される。さらに図 12の構成で  [0094] With the excitation of the plasma 26C, nitrogen radicals and nitrogen ions are formed in the gas circulation passage 26a, but the nitrogen ions disappear when circulating through the circulation passage 26a, and from the gas outlet 26c. Mainly releases nitrogen radicals N *. Furthermore, with the configuration of Figure 12
2  2
は前記ガス出口 26cに接地されたイオンフィルタ 26eを設けることにより、窒素イオン をはじめとする荷電粒子が除去され、前記処理空間 21Bには窒素ラジカルのみが供 給される。また、前記イオンフィルタ 26eを接地させない場合においても、前記イオン フィルタ 26eの構造は拡散板として作用するため、十分に窒素イオンをはじめとする 荷電粒子を除去することができる。 [0095] 図 13Bの基板処理装置 20では、酸ィ匕膜の窒化処理を窒素イオンではなく窒素ラジ カル N *で行っており、このため励起される窒素イオンの数は少ない方が好ましい。まBy providing a grounded ion filter 26e at the gas outlet 26c, charged particles such as nitrogen ions are removed, and only nitrogen radicals are supplied to the processing space 21B. Even when the ion filter 26e is not grounded, the structure of the ion filter 26e functions as a diffusion plate, so that charged particles such as nitrogen ions can be sufficiently removed. In the substrate processing apparatus 20 of FIG. 13B, the nitriding treatment of the oxide film is performed not with nitrogen ions but with nitrogen radical N *. For this reason, it is preferable that the number of excited nitrogen ions is small. Ma
2 2
た被処理基板に加えられるダメージを最小化する観点からも、励起される窒素イオン の数は少ないのが好ましい。図 13Bの基板処理装置 20では、励起される窒素ラジカ ルの数も少なぐ高誘電体ゲート絶縁膜下の非常に薄い、 lnm以下の厚さのベース 酸化膜を窒化するのに好適である。  From the viewpoint of minimizing damage to the substrate to be processed, the number of excited nitrogen ions is preferably small. The substrate processing apparatus 20 of FIG. 13B is suitable for nitriding a very thin base oxide film having a thickness of 1 nm or less under a high dielectric gate insulating film with a small number of excited nitrogen radicals.
[0096] また、ベース酸ィ匕膜の窒化は、ベース酸ィ匕膜の形成直後に行ってもよぐまたべ一 ス酸化膜の形成後に当該ベース酸化膜上に高誘電体膜を形成した後で行ってもよ い。 Further, the nitriding of the base oxide film may be performed immediately after the formation of the base oxide film, or after the formation of the base oxide film and after the formation of the high dielectric film on the base oxide film. You can go there.
[0097] また、高誘電体膜の形成方法としては、例えば MOCVD法 (有機金属化学気相成 長法）を用いた成膜方法や、 ALD法 (Atomic Layer Deposition法）を用いた成 膜などを用いることが可能である。  [0097] In addition, as a method for forming a high dielectric film, for example, a film formation method using a MOCVD method (metal organic chemical vapor deposition method), a film formation using an ALD method (Atomic Layer Deposition method), etc. Can be used.
実施例 2  Example 2
[0098] また、ベース酸ィ匕膜を形成する方法は上記に限定されるものではない。  [0098] The method for forming the base oxide film is not limited to the above.
[0099] 例えば、図 15は、図 3に示した基板処理方法において、シリコン基板の洗浄後にス テツプ 6にお 、てシリコン酸化膜を形成する基板処理装置の別の例である、基板処 理装置 50を模式的に示した図である。  [0099] For example, FIG. 15 shows another example of a substrate processing apparatus for forming a silicon oxide film in step 6 after cleaning the silicon substrate in the substrate processing method shown in FIG. FIG. 6 is a diagram schematically showing the device 50.
[0100] 図 15を参照するに、前記基板処理装置 50は、処理容器 51の内部に、被処理基板Referring to FIG. 15, the substrate processing apparatus 50 includes a substrate to be processed inside a processing container 51.
Wを保持する保持台 53を備え、さらに当該被処理基板 Wを加熱するための加熱手 段 52が、前記保持台 53に対向するように形成されて!ヽる。 A holding base 53 for holding W is provided, and a heating means 52 for heating the substrate W to be processed is formed so as to face the holding base 53.
[0101] 例えば、前記加熱手段 52は、ランプヒータよりなり、さらに被処理基板 Wを加熱する ためのヒータ 53Aが、保持台 53に埋設されるように構成してもよい。また、処理容器 5For example, the heating means 52 may be constituted by a lamp heater, and a heater 53 A for heating the substrate W to be processed may be embedded in the holding base 53. In addition, the processing container 5
1内部は、排気口 55によって 気される構造になって 、る。 1 The inside is structured to be noticed by the exhaust port 55.
[0102] 上記の基板処理装置にお!ヽて、処理容器に設けられたガス導入口 54から、例えば 酸素や、または酸素元素を含むガスなどが導入され、前記加熱手段 52により被処理 基板 Wを加熱することで、シリコンよりなる被処理基板 Wの表面に、ベース酸化膜を 形成することが可能に構成されて ヽる。 [0102] In the above substrate processing apparatus, for example, oxygen or a gas containing an oxygen element is introduced from a gas inlet 54 provided in the processing container, and the substrate W to be processed is heated by the heating means 52. By heating the substrate, the base oxide film can be formed on the surface of the substrate W to be processed made of silicon.
[0103] このように、酸素を含む雰囲気中で被処理基板を加熱することによりベース酸化膜 を形成することも可能である。 Thus, the base oxide film is formed by heating the substrate to be processed in an atmosphere containing oxygen. It is also possible to form
実施例 3  Example 3
[0104] また、ベース酸化膜は、 SC2洗浄で形成される化学酸化膜を、熱処理して形成す ることも可能である。上記の化学酸ィ匕膜をベース酸ィ匕膜として用いることが可能な理 由について、以下に説明する。  [0104] The base oxide film can also be formed by heat-treating a chemical oxide film formed by SC2 cleaning. The reason why the above chemical oxide film can be used as the base oxide film will be described below.
[0105] 図 16は、複数の方法で形成したシリコン酸化膜の、エリプソメータにより測定した膜 厚 (物理膜厚）と、 XPSスペクトルの SiOピークから導いた膜厚 (XPS膜厚）との関係  [0105] Figure 16 shows the relationship between the film thickness (physical film thickness) measured by ellipsometer and the film thickness derived from the SiO peak of the XPS spectrum (XPS film thickness) for silicon oxide films formed by multiple methods.
2  2
を示した図である。図中には、參で熱酸化膜 (図中熱 SiOと表記 )、〇で紫外線活性  FIG. In the figure, boiled thermal oxide film (indicated as thermal SiO in the figure), ○ for UV activation
2  2
化 O酸ィ匕による酸ィ匕膜 (図中 UV— Oxと表記）、令で11 Oによる化学酸化膜 (H O Oxidized film by O-acid (denoted as UV-Ox in the figure), chemical oxide film by 11 O by order (H O
2 2 2 2 2 酸化膜)、◊で DHF洗浄後に塩酸 +過酸化水素水による洗浄処理 (SC2洗浄）によ り形成した化学酸化膜 (SC2酸化膜）についての測定結果を、それぞれ示す。また、 上記 H O酸化膜と SC2酸化膜については、酸化膜の形成後に熱処理した結果に2 2 2 2 2 Oxide film) and boiled DHF cleaning, and the measurement results for chemical oxide film (SC2 oxide film) formed by cleaning with hydrochloric acid + hydrogen peroxide (SC2 cleaning) are shown respectively. In addition, the H 2 O oxide film and the SC2 oxide film were subjected to heat treatment after the oxide film was formed.
2 2 twenty two
ついても併記している。  This is also shown.
[0106] 図 16を参照するに、例えば熱酸ィ匕膜の場合を例にとってみると、酸化膜の膜厚が 厚い領域では、物理膜厚と XPS膜厚とは直線的な相関関係 (ユニバーサルライン)と なるが、薄膜ィ匕するに従って上記のユニバーサルライン力もずれが生じている。これ は、シリコン基板と酸ィ匕膜の界面に存在するサブオキサイドの影響や、酸化膜自体の 変質に起因するものである。  Referring to FIG. 16, for example, in the case of a thermal oxide film, in the region where the oxide film is thick, the physical film thickness and the XPS film thickness are linearly correlated (universal However, as the film is thinned, the above universal line force also shifts. This is due to the influence of suboxide existing at the interface between the silicon substrate and the oxide film and the alteration of the oxide film itself.
[0107] また、熱処理前の H O酸ィ匕膜と SC2酸ィ匕膜は、上記のユニバーサルラインカも大  [0107] The HO oxide film and SC2 oxide film before heat treatment are also large in the above universal line mask.
2 2  twenty two
きくずれており、熱酸ィ匕膜とは膜質が大きく異なった低密度の膜であることがわかる。 しかし、上記の H O酸ィ匕膜と SC2酸ィ匕膜を熱処理 (ァニール)すると、上記のュ-バ  It can be seen that the film is a low-density film having a film quality greatly different from that of the thermal oxide film. However, when the above HO oxide film and SC2 oxide film are annealed, the above-mentioned super
2 2  twenty two
ーサルラインに近接し、熱酸ィ匕膜の膜質に近づくことがわ力る。  -Close to the monkey line and approaching the film quality of the hot acid film.
[0108] 特に、 SC2酸ィ匕膜の場合、熱処理後に略ユニバーサルラインに乗っており、 SC2 酸ィ匕膜の膜質が改善されるとともに、サブオキサイドの形成が抑制されていることが 推測できる。このように、シリコン基板を SC2洗浄して SC2酸ィ匕膜を形成し、さらに当 該 SC2酸ィ匕膜の熱処理によって、シリコン基板上にベース酸ィ匕膜形成することが可 能である。この場合、例えばリーク電流増大の原因となりうるサブオキサイドの形成を 抑制し、良質のベース酸ィ匕膜の更なる薄膜ィ匕 (薄膜ィ匕の限界を下げること)が可能と なる。 [0108] In particular, in the case of the SC2 oxide film, it is almost on the universal line after the heat treatment, and it can be assumed that the film quality of the SC2 oxide film is improved and the formation of suboxide is suppressed. In this way, it is possible to form a base oxide film on a silicon substrate by SC2 cleaning the SC2 oxide film to form an SC2 oxide film and then heat-treating the SC2 oxide film. In this case, for example, it is possible to suppress the formation of suboxide, which can cause an increase in leakage current, and to further reduce the thickness of the high-quality base oxide film (lower the limit of the thin film thickness). Become.
[0109] また、上記の SC2酸ィ匕膜の熱処理工程は、例えば、実施例 1に記載した前記基板 処理装置 20において実施することができる。この場合、シリコン基板を、不活性ガス、 または Nガス雰囲気中で、基板温度を 400〜700°Cとして熱処理を行う。当該熱処 [0109] Further, the above-described heat treatment step of the SC2 oxide film can be performed in the substrate processing apparatus 20 described in the first embodiment, for example. In this case, the silicon substrate is heat-treated at 400 to 700 ° C. in an inert gas or N gas atmosphere. Heat treatment
2 2
理によって、 SC2酸化膜の膜質を改善して緻密な化学酸化膜を形成することが可能 であり、当該化学酸化膜は半導体装置を形成する場合のベース酸化膜として用いる ことができる。また、上記の熱処理は、実施例 2に記載した基板処理装置 50において も実施することが可能である。  Thus, it is possible to improve the film quality of the SC2 oxide film to form a dense chemical oxide film, and the chemical oxide film can be used as a base oxide film in forming a semiconductor device. The above heat treatment can also be performed in the substrate processing apparatus 50 described in the second embodiment.
[0110] すなわち、本実施例による基板処理方法では、実施例 1に記載の基板処理方法に おいて、ステップ 6の工程を、 SC2洗浄工程 (ステップ 4)と、上記の熱処理工程から なるようにすればよい。 [0110] That is, in the substrate processing method according to the present embodiment, in the substrate processing method described in Embodiment 1, the process of Step 6 is composed of the SC2 cleaning process (Step 4) and the heat treatment process described above. do it.
[0111] このように、ベース酸化膜を形成する基板処理装置や基板処理方法は様々に選択 することが可能である。同様に、ベース酸化膜を窒化する方法や高誘電体膜を形成 する場合についても、基板処理装置や基板処理方法は様々に選択することが可能 である。しかし、このような選択をする場合、薄いベース酸ィ匕膜を精度よく形成する方 法、また薄い酸ィ匕膜を精度良く窒化する方法をとることが好ましい。  [0111] As described above, the substrate processing apparatus and the substrate processing method for forming the base oxide film can be variously selected. Similarly, a substrate processing apparatus and a substrate processing method can be variously selected for nitriding the base oxide film and forming a high dielectric film. However, when making such a selection, it is preferable to adopt a method of forming a thin base oxide film with high accuracy and a method of nitriding a thin oxide film with high accuracy.
[0112] 以上、本発明を好ましい実施例について説明したが、本発明は上記の特定の実施 例に限定されるものではなく、特許請求の範囲に記載した要旨内にお 、て様々な変 形 ·変更が可能である。  [0112] Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications may be made within the spirit and scope of the claims. · Change is possible.
産業上の利用可能性  Industrial applicability
[0113] 本発明によれば、シリコン基板上に、高速度デバイスに用いることが好ましいベース 酸化膜を形成することが可能となる。 [0113] According to the present invention, it is possible to form a base oxide film preferably used for a high-speed device on a silicon substrate.
[0114] 本国際出願は、 2005年 3月 29日に出願した日本国特許出願 2005— 95124号に 基づく優先権を主張するものであり、 2005— 95124号の全内容を本国際出願に援 用する。 [0114] This international application claims priority based on Japanese Patent Application No. 2005-95124 filed on March 29, 2005. The entire contents of 2005-95124 are incorporated herein by reference. To do.

Claims

請求の範囲 The scope of the claims
[1] シリコン基板を、アンモニア、過酸化水素水を含む第 1の洗浄液で洗浄し、当該洗 浄後に HFを含む洗浄液で洗浄する第 1の洗浄工程と、  [1] A first cleaning step of cleaning the silicon substrate with a first cleaning solution containing ammonia and hydrogen peroxide water, and cleaning with a cleaning solution containing HF after the cleaning,
前記シリコン基板を、塩酸、過酸化水素水を含む第 2の洗浄液で洗浄し、当該洗浄 後に HFを含む洗浄液で洗浄する第 2の洗浄工程と、  A second cleaning step of cleaning the silicon substrate with a second cleaning liquid containing hydrochloric acid and hydrogen peroxide water, and cleaning with a cleaning liquid containing HF after the cleaning;
前記第 2の洗浄工程後の前記シリコン基板上に、シリコン酸化膜を形成する酸化膜 形成工程と、を有し、  An oxide film forming step of forming a silicon oxide film on the silicon substrate after the second cleaning step;
前記第 2の洗浄工程は複数回繰り返し実施されることを特徴とする基板処理方法。  The substrate processing method, wherein the second cleaning step is repeatedly performed a plurality of times.
[2] 前記シリコン酸ィ匕膜は、紫外線照射により活性化された酸素ガスにより、形成される ことを特徴とする請求項 1記載の基板処理方法。 2. The substrate processing method according to claim 1, wherein the silicon oxide film is formed by oxygen gas activated by ultraviolet irradiation.
[3] 前記シリコン酸化膜は、前記シリコン基板が酸素を含む雰囲気中で加熱されること により、形成されることを特徴とする請求項 1記載の基板処理方法。 3. The substrate processing method according to claim 1, wherein the silicon oxide film is formed by heating the silicon substrate in an atmosphere containing oxygen.
[4] 前記酸化膜形成工程は、 [4] The oxide film forming step includes:
前記シリコン基板を前記第 2の洗浄液で洗浄し、前記シリコン基板上に化学酸化膜 を形成する工程と、  Cleaning the silicon substrate with the second cleaning liquid and forming a chemical oxide film on the silicon substrate;
前記化学酸化膜を窒素または不活性ガス雰囲気中で熱処理する工程とからなるこ とを特徴とする請求項 1記載の基板処理方法。  2. The substrate processing method according to claim 1, further comprising a step of heat-treating the chemical oxide film in a nitrogen or inert gas atmosphere.
[5] 前記シリコン酸ィ匕膜上に、 Hfまたは Zrを含む高誘電体膜が形成される工程をさら に含むことを特徴とする請求項 1記載の基板処理方法。 5. The substrate processing method according to claim 1, further comprising a step of forming a high dielectric film containing Hf or Zr on the silicon oxide film.
[6] 前記酸化膜を窒化する窒化工程をさらに含むことを特徴とする請求項 5記載の基 板処理方法。 6. The substrate processing method according to claim 5, further comprising a nitriding step of nitriding the oxide film.
[7] 前記窒化工程では、前記高誘電体膜との界面近傍の前記シリコン酸ィ匕膜が窒化さ れることを特徴とする請求項 6記載の基板処理方法。  7. The substrate processing method according to claim 6, wherein, in the nitriding step, the silicon oxide film in the vicinity of the interface with the high dielectric film is nitrided.
[8] 前記窒化工程は、高周波プラズマを用いたラジカル発生源を用いて生成される窒 素ラジカルにより、行われることを特徴とする請求項 6記載の基板処理方法。 8. The substrate processing method according to claim 6, wherein the nitriding step is performed by a nitrogen radical generated using a radical generation source using high-frequency plasma.
[9] 前記シリコン酸ィ匕膜の膜厚は、 0. 4nmであることを特徴とする請求項 5記載の基板 処理方法。 9. The substrate processing method according to claim 5, wherein the thickness of the silicon oxide film is 0.4 nm.
[10] 前記第 2の洗浄工程を繰り返すことで、前記シリコン基板と前記シリコン酸ィヒ膜の界 面のラフネスを制御することを特徴とする請求項 1記載の基板処理方法。 [10] By repeating the second cleaning step, a boundary between the silicon substrate and the silicon oxide film is obtained. 2. The substrate processing method according to claim 1, wherein the roughness of the surface is controlled.
PCT/JP2006/303070 2005-03-29 2006-02-21 Substrate processing method WO2006103845A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005-095124 2005-03-29
JP2005095124A JP4509839B2 (en) 2005-03-29 2005-03-29 Substrate processing method

Publications (1)

Publication Number Publication Date
WO2006103845A1 true WO2006103845A1 (en) 2006-10-05

Family

ID=37053114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/303070 WO2006103845A1 (en) 2005-03-29 2006-02-21 Substrate processing method

Country Status (2)

Country Link
JP (1) JP4509839B2 (en)
WO (1) WO2006103845A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014165494A (en) * 2013-02-22 2014-09-08 Imec Oxygen monolayer on semiconductor

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5039396B2 (en) * 2007-02-19 2012-10-03 ローム株式会社 Manufacturing method of semiconductor device
JP5223771B2 (en) * 2009-05-08 2013-06-26 東京エレクトロン株式会社 Film forming method, gate electrode structure forming method and processing apparatus
JP7131513B2 (en) * 2019-09-05 2022-09-06 株式会社Sumco Silicon sample pretreatment method, silicon sample metal contamination evaluation method, single crystal silicon ingot growth process evaluation method, single crystal silicon ingot manufacturing method, and silicon wafer manufacturing method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291112A (en) * 1993-04-01 1994-10-18 Nec Corp Fabrication of semiconductor device
JPH06333917A (en) * 1993-05-20 1994-12-02 Fujitsu Ltd Preprocessing method for semiconductor wafer before oxidization
JP2003297822A (en) * 2002-03-29 2003-10-17 Tokyo Electron Ltd Method of forming insulation film
WO2003088341A1 (en) * 2002-03-29 2003-10-23 Tokyo Electron Limited Method for forming underlying insulation film
JP2005079215A (en) * 2003-08-29 2005-03-24 Fujitsu Ltd Method for manufacturing semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3265333B2 (en) * 1993-11-18 2002-03-11 株式会社ピュアレックス Silicon wafer cleaning liquid and method for cleaning silicon wafer using the cleaning liquid
JPH08181094A (en) * 1994-12-26 1996-07-12 Nippondenso Co Ltd Surface flattening method of semiconductor substrate
JP3528534B2 (en) * 1997-09-08 2004-05-17 信越半導体株式会社 Cleaning method of silicon wafer
JP2002329691A (en) * 2001-04-27 2002-11-15 Shin Etsu Handotai Co Ltd Method of cleaning silicon wafer
JP3778432B2 (en) * 2002-01-23 2006-05-24 東京エレクトロン株式会社 Substrate processing method and apparatus, and semiconductor device manufacturing apparatus
EP1605500A4 (en) * 2003-03-17 2007-03-21 Fujitsu Ltd Semiconductor device and method for manufacturing semiconductor device
JP2003347265A (en) * 2003-04-18 2003-12-05 Hitachi Ltd Method for manufacturing semiconductor integrated circuit device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06291112A (en) * 1993-04-01 1994-10-18 Nec Corp Fabrication of semiconductor device
JPH06333917A (en) * 1993-05-20 1994-12-02 Fujitsu Ltd Preprocessing method for semiconductor wafer before oxidization
JP2003297822A (en) * 2002-03-29 2003-10-17 Tokyo Electron Ltd Method of forming insulation film
WO2003088341A1 (en) * 2002-03-29 2003-10-23 Tokyo Electron Limited Method for forming underlying insulation film
JP2005079215A (en) * 2003-08-29 2005-03-24 Fujitsu Ltd Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014165494A (en) * 2013-02-22 2014-09-08 Imec Oxygen monolayer on semiconductor

Also Published As

Publication number Publication date
JP4509839B2 (en) 2010-07-21
JP2006278678A (en) 2006-10-12

Similar Documents

Publication Publication Date Title
JP4708426B2 (en) Method for processing a semiconductor substrate
JP4334225B2 (en) Manufacturing method of electronic device material
TWI292172B (en) Method for forming insulating film on substrate, mehtod for manufacturing semiconductor device, and substrate-processing apparatus
JP4429300B2 (en) Manufacturing method of electronic device material
TWI284940B (en) Free radical nitriding process for sub-nanometer insulation layer
US7235495B2 (en) Controlled growth of highly uniform, oxide layers, especially ultrathin layers
US7115530B2 (en) Top surface roughness reduction of high-k dielectric materials using plasma based processes
TW200805497A (en) Method for forming silicon oxynitride materials
JP4162601B2 (en) Formation method of insulating film
JPWO2009099252A1 (en) Method for plasma modification treatment of insulating film
JP2009545895A (en) Improvement of CMOSSiON gate dielectric performance by formation of double plasma nitride containing rare gas
TW201017753A (en) Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer
TW201403712A (en) Plasma nitriding method, method for manufacturing semiconductor device and plasma processing apparatus
WO2015093389A1 (en) Method and apparatus for forming oxide thin film
WO2006103845A1 (en) Substrate processing method
TWI485771B (en) Semiconductor processing methods
US6740941B2 (en) Semiconductor device including a gate insulating film made of high-dielectric-constant material
TW200301311A (en) Method for processing substrates
JPH06333917A (en) Preprocessing method for semiconductor wafer before oxidization
JP3770870B2 (en) Substrate processing method
JP2006121106A (en) Substrate processing equipment
JP4088275B2 (en) Insulating film formation method
TW202145372A (en) Hydrogenation and nitridization processes for modifying effective oxide thickness of a film

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 06714210

Country of ref document: EP

Kind code of ref document: A1