WO2006060495A1 - Bga to lga interposer - Google Patents
Bga to lga interposer Download PDFInfo
- Publication number
- WO2006060495A1 WO2006060495A1 PCT/US2005/043345 US2005043345W WO2006060495A1 WO 2006060495 A1 WO2006060495 A1 WO 2006060495A1 US 2005043345 W US2005043345 W US 2005043345W WO 2006060495 A1 WO2006060495 A1 WO 2006060495A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interposer
- conductive pad
- grid array
- substrate
- array device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10719—Land grid array [LGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
Definitions
- the present invention relates to an interposer for connecting a land grid array (LGA) socket to a ball grid array (BGA) chip.
- LGA land grid array
- BGA ball grid array
- the present invention overcomes these problems with the prior art by providing an interposer that allows the IC chip manufacture to have the same BGA interface for its IC chips, regardless of whether the IC chip will be directly mounted to the circuit board or to the circuit board through an LGA socket connector.
- the present invention allows an LGA connector to be mounted to a circuit board without the added expense of having to put gold conductive pads directly on the circuit board.
- the use of the interposer of the present invention allows customers desiring a BGA type attachment to the circuit board thorugh a socket connector (as compared to directly mounting the IC chip directly to the circuit board) to use the finer, LGA interface to interface with the IC chip BGA interface.
- the present invention provides an interposer, the interposer having an insulative substrate, at least one via provided through the substrate, the via having a first end and a second end for providing an electrical path through the substrate.
- a conductive pad is located on each end of the via.
- the conductive pads on each end of the via are formed of different materials.
- One conductive pad is formed of solder material and the other conductive pad is formed of gold.
- the interposer includes at least one standoff on the side of the interposer have a conductive pad formed of solder material.
- FIG. 1 is a side elevational view of an assembly which includes an interposer connecting a land grid array socket to a ball grid array chip;
- FIG. 2 is an enlarged side elevational view of a portion of the assembly shown in FIG. i;
- FIG. 3 is a perspective view of the land grid array socket which can be used in the assembly
- FIG. 4 is an enlarged perspective view of a portion of the land grid array socket of FIG. 3;
- FIG. 5 is a perspective view of the ball grid array socket which can be used in the assembly
- FIG. 6 is an enlarged perspective view of a portion of the ball grid array socket of FIG. 5;
- FIG. 7 is a perspective view of the interposer used in the assembly;
- FIG. 8 is an enlarged perspective view of a portion of the interposer
- FIG. 9 is an enlarged perspective view of a portion of the interposer from a second side thereof;
- FIG. 10 is a cross-sectional view of the interposer. Detailed Description of the Illustrated Embodiment:
- An interposer 20 is used to connect a land grid array (LGA) socket 22 to a ball grid array (BGA) chip 24 to form an assembly 26.
- the LGA socket 22 is known in the art.
- the LGA socket 22 provides an array of conductive terminals 28 which extend through apertures in an insulative substrate 30, such as a film or a plastic.
- the substrate 30 is mounted in a stiffening frame 32.
- the frame 32 is generally rectangular-shaped, and may be formed from plastic.
- the terminals 28 extend through the substrate 30 and extend outwardly therefrom on both sides thereof such that a first arm 34 is provided on a first side of the substrate 30 and a second arm 36 is provided on a second side of the substrate 30.
- the second arm 36 is connected to a conductive pad on a printed wiring board 38 by suitable known means, such as a solder ball 40.
- the BGA chip 24 is known in the art.
- the BGA chip 24 includes an insulative substrate 42 in which conductive wiring (not shown) is provided. An end of each wire is terminated to a solder ball 44 on one side of the substrate 42. The solder balls 44 form an array. The other end of the wiring is suitably connected to other known electronic components. Because the BGA chip 24 has solder balls 44, and the LGA socket 22 has conductive terminals 28, it will not be able to mate the BGA chip 24 directly to the LGA socket 22. As such, an interposer 20 is used to make the connection between the BGA chip 24 and the LGA socket 22.
- the interposer 20 is formed of an insulative substrate 46 having a first side 48 and a second side 50.
- the substrate 46 is preferably formed from FR4 laminate (flame retardant woven glass reinforced epoxy resin), polycarbonate or other plastic which can be plated with a conductive material. As shown, the substrate 46 is planar and is generally rectangular.
- a plurality of vias 52 are provided through the substrate 46 such that each via 52 extends from the first side 48 to the second side 50 of the substrate 46.
- Each via 52 is plated by known means with a conductive material, preferably copper.
- a first conductive pad is formed on the first side 48 of the substrate 46 proximate the end of the via 52 and a second conductive pad is formed on the second side 50 of the substrate 46 proximate the end of the via 52.
- a conductive post (not shown) can be provided within each via 52 and extend outwardly therefrom.
- a solder pad 54 is provided on the first side 48 of the substrate 46 and covers the first conductive pad.
- the solder pad 54 is applied to the respective first conductive pad by known means.
- Each resulting solder pad 54 is flat.
- the solder pads 54 may sit against the first side 48 of the substrate 46 or be recessed into the first side 48 of the substrate 46. As a result, an array of solder pads 54 are provided on the first side 48 of the substrate 46.
- a conductive pad 56 preferably formed from gold, is provided on the second side 50 of the substrate 46.
- the conductive pad 56 is applied to the respective second conductive pad by known means.
- Each resulting conductive pad 56 is flat.
- the conductive pads 56 may sit against the second side 50 of the substrate 46 or be recessed into the second side 50 of the substrate 46.
- an array of conductive pads 56 are provided on the second side 50 of the substrate 46 and respective conductive pads 56 align with respective solder pads 54.
- a standoff 58 is provided at each corner of the insulative substrate 46 and extends outwardly from the first side 48 of the substrate 46.
- the standoffs 58 extend outwardly from the substrate a greater distance than the conductive pads 54 extends therefrom.
- the standoffs 58 are formed of an insulative material, such as plastic.
- the standoffs 58 may be integrally formed with the substrate 46 or may be formed as separate members that are suitable attached to the substrate 46, for example by a drilled hole in the substrate 46.
- each solder pad 54 on the interposer 20 is soldered to a respective solder ball 44 on the BGA chip 24 and each conductive pad 56 on the interposer 20 engages against the second end 34 of the respective terminal 28 in the LGA socket 22.
- an electrical path is provide by the solder ball 44 on the BGA chip 24, the solder pad 54, the conductive means in the via 52, the conductive pad 56 and the terminal 28 in the LGA socket 22.
- the standoff 58 controls the solder ball 44 collapse during the soldering process to prevent solder bridging between the solder pads 54 on the interposer 20.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US63209204P | 2004-12-01 | 2004-12-01 | |
US60/632,092 | 2004-12-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006060495A1 true WO2006060495A1 (en) | 2006-06-08 |
Family
ID=36000638
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/043345 WO2006060495A1 (en) | 2004-12-01 | 2005-12-01 | Bga to lga interposer |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2006060495A1 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030146017A1 (en) * | 2000-08-24 | 2003-08-07 | Zhineng Fan | A Method of Forming A HiGH RELIABILITY INTERPOSER FOR LOW COST HIGH RELIABILITY APPLICATIONS |
-
2005
- 2005-12-01 WO PCT/US2005/043345 patent/WO2006060495A1/en active Application Filing
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030146017A1 (en) * | 2000-08-24 | 2003-08-07 | Zhineng Fan | A Method of Forming A HiGH RELIABILITY INTERPOSER FOR LOW COST HIGH RELIABILITY APPLICATIONS |
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