WO2006054189A1

WO2006054189A1 - Active matrix display devices

Info

Publication number: WO2006054189A1
Application number: PCT/IB2005/053571
Authority: WO
Inventors: Ramon P. Van Gorkom; Martin Hiddink; Fransiscus J. Vossen
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-11-16
Filing date: 2005-11-02
Publication date: 2006-05-26
Also published as: GB0425188D0; TW200638328A

Abstract

An active matrix device comprising an array of display pixels, each comprising a current driven light emitting display element (2), a drive transistor (TD) for driving a current through the display element and first and second capacitors (C1, C2) connected in series between the gate and source or drain of the drive transistor. A data input to the pixel is provided to the junction (30) between the first and second capacitors (C1, C2) thereby to charge one of the first and second capacitors to a voltage derived from the pixel data voltage, to and a voltage derived from the drive transistor threshold voltage is stored on the other of the first and second capacitors. A unidirectional charge flow device (50;60) is provided between the gate and source of the drive transistor to allow current flow from the gate to the source for resetting a drive transistor gate voltage. This is used as a reset device which avoids the need to drive is current through the display element when performing a threshold sampling operation.

Description

DESCRIPTION

ACTIVE MATRIX DISPLAY DEVICES

This invention relates to active matrix display devices, particularly but not exclusively active matrix electroluminescent display devices having thin film switching transistors associated with each pixel.

Matrix display devices employing electroluminescent, light-emitting, display elements are well known. The display elements may comprise organic thin film electroluminescent elements, for example using polymer materials, or else light emitting diodes (LEDs) using traditional Hl-V semiconductor compounds. Recent developments in organic electroluminescent materials, particularly polymer materials, have demonstrated their ability to be used practically for video display devices. These materials typically comprise one or more layers of a semiconducting conjugated polymer sandwiched between a pair of electrodes, one of which is transparent and the other of which is of a material suitable for injecting holes or electrons into the polymer layer.

Display devices of this type have current-driven display elements, so that a conventional, analogue drive scheme involves supplying a controllable current to the display element. It is known to provide a current source transistor as part of the pixel configuration, with the gate voltage supplied to the current source transistor determining the current through the display element. A storage capacitor holds the gate voltage after the addressing phase. Figure 1 shows a known active matrix addressed electroluminescent display device. The display device comprises a panel having a row and column matrix array of regularly-spaced pixels, denoted by the blocks 1 and comprising electroluminescent display elements 2 together with associated switching means, located at the intersections between crossing sets of row (selection) and column (data) address conductors 4 and 6. Only a few pixels are shown in the Figure for simplicity. In practice there may be several hundred rows and columns of pixels. The pixels 1 are addressed via the sets of row and column address conductors by a peripheral drive circuit comprising a row, scanning, driver circuit 8 and a column, data, driver circuit 9 connected to the ends of the respective sets of conductors.

The electroluminescent display element 2 comprises an organic light emitting diode, represented here as a diode element (LED) and comprising a pair of electrodes between which one or more active layers of organic electroluminescent material is sandwiched. The display elements of the array are carried together with the associated active matrix circuitry on one side of an insulating support. Either the cathodes or the anodes of the display elements are formed of transparent conductive material. The support is of transparent material such as glass and the electrodes of the display elements 2 closest to the substrate may consist of a transparent conductive material such as ITO so that light generated by the electroluminescent layer is transmitted through these electrodes and the support so as to be visible to a viewer at the other side of the support.

Figure 2 shows in simplified schematic form a known pixel and drive circuitry arrangement for providing voltage-programmed operation. Each pixel 1 comprises the EL display element 2 and associated driver circuitry. The driver circuitry has an address transistor 16 which is turned on by a row address pulse on the row conductor 4. When the address transistor 16 is turned on, a voltage on the column conductor 6 can pass to the remainder of the pixel. In particular, the address transistor 16 supplies the column conductor voltage to a current source 20, which comprises a drive transistor 22 and a storage capacitor 24. The column voltage is provided to the gate of the drive transistor 22, and the gate is held at this voltage by the storage capacitor 24 even after the row address pulse has ended. The drive transistor 22 draws a current from the power supply line 26.

To date, the majority of active matrix circuits for LED displays have used low temperature polysilicon (LTPS) TFTs. The threshold voltage of these devices is stable in time, but varies from pixel to pixel in a random manner. This leads to unacceptable static noise in the image. Many circuits have been proposed to overcome this problem. In one example, each time the pixel is addressed the pixel circuit measures the threshold voltage of the current- providing TFT to overcome the pixel-to-pixel variations.

The use of a-Si:H has also been considered. The variation in threshold voltage is small in amorphous silicon transistors, at least over short ranges over the substrate, but the threshold voltage is very sensitive to voltage stress.

Application of the high voltages above threshold needed for the drive transistor causes large changes in threshold voltage, which changes are dependent on the information content of the displayed image. There will therefore be a large difference in the threshold voltage of an amorphous silicon transistor that is always on compared with one that is not. This differential ageing is a serious problem in LED displays driven with amorphous silicon transistors.

Figure 3 shows a pixel circuit which enables sampling of the threshold voltage of the drive transistor, and which is suitable for implementation using p-type or n-type transistors. Each pixel again has an electroluminescent (EL) display element 2 and an amorphous silicon drive transistor T₀ in series between the power supply line 26 and the cathode line 28. The drive transistor TD is for driving a current through the display element 2.

First and second capacitors Ci and C2 are connected in series between the gate and source of the drive transistor Tp. A data input to the pixel is provided to the junction 30 between the first and second capacitors and charges the second capacitor C₂ to a pixel data voltage as will be explained below. The first capacitor Ci is for storing a drive transistor threshold voltage (or a voltage having a component dependent on this).

In the following description, a transistor is denoted by a subscript (for example transistor Ai) whereas the respective gate control line is denoted by normal text (for example gate control line A1).

An input transistor Ai is connected between the input data line 6 and the junction 30 between the first and second capacitors. This transistor times the application of a data voltage to the pixel, for storage on the second capacitor C₂.

A second "shorting" transistor A₂ is connected between the gate and drain of the drive transistor T_D. This is used to control the supply of current from the power supply line 26 to the capacitor Ci through the drive transistor during a threshold sampling operation Thus, by turning on the second transistor A₂, the first capacitor C₁ can be charged until the threshold voltage is present between the gate and source. A third "switch" transistor A₃ is connected between the drive transistor

T_D and the cathode line 28.

The display is addressed using the phases shown in Figure 4.

During an initial "overdrive" phase 40, the address lines A1 to A3 are each high such that the transistors connected to these lines are conducting. This will cause a current to flow from the power line 26 through the drive transistor T_D and through the switch transistor A₃. The voltage on the data line

6 is kept at a reference voltage, for example Vdata = Vref = 7 V. The power line is always high at for example 12 V. The gate voltage of the drive transistor will go to the anode voltage of the LED, for example 3 V. This in effect removes all excess charge from the normally floating gate of the drive transistor TD and puts it in a well defined state.

During a "Vt correction" phase 41, the switch transistor A3 is switched off by making A3 low. The drive transistor continues to conduct because the gate-source voltage is stored on the capacitors. The drive transistor current discharges the capacitor Ci until the gate voltage of the drive transistor has increased to the voltage on the power line 26 less the threshold voltage.

Thus, Vgs = Vgate - Vpower = Vt, with Vt « -2 V.

Hence Vgate = Vt + Vpower «10 V.

During this stage, a constant voltage is applied to the node 30, and the effect is that a voltage across the capacitor Ci is dependent on the drive transistor threshold voltage.

In a "pre-address" phase 42, the shorting transistor A₂ is switched off by making A2 low.

During the "address" phase 43, the data voltage Vdata is adjusted in order to generate the correct information on the screen. This causes the gate voltage to shift by an amount equivalent to the change in Vdata, so that

Vgate = Vt + Vpower + (Vdata - Vref). During this phase, the data voltage is stored across the capacitor C₂. In the "post address" phase 44, the address transistor Ai is switched off (A1 is made low). After this post address phase, the next row can be addressed starting with the overdrive phase. Light can be generated from the addressed row by switching A₃ of that row high for the desired time (duty cycle). This can be done at the start of the address phase or at a later time. During the hatched area, it does not matter what the data voltage is, and this enables other rows to be addressed during this time. As shown in Figure 4, the operation defines a row address period 46, and the full frame time is shown as 47. The length of the row address period 46 compared to the full frame period 47 is exaggerated for clarity. Light is output during period 48.

This pixel circuit provides compensation of the drive transistor threshold voltage. Only the drive transistor T_D is used in constant current and analogue mode. All other TFTs A₁ to A3 in the circuit are used as digital switches and can be driven with high over-threshold voltages. Therefore, any threshold voltage drift in these devices does not affect the circuit performance. This is of course important particularly for amorphous silicon implementations. One of the disadvantages of this pixel circuit and addressing scheme is that it requires three row lines (A1 , A2, and A3 are implemented as row lines) and hence many drivers and connections to the display. Furthermore, during the initial overdrive phase, light is generated, which can degrade the contrast.

A number of variations to this circuit are shown in the applicant's co- pending WO 2004/066249. In some examples, the generation of light is avoided, but this requires additional transistors and address lines or else requires the use of a power supply line with a switchable voltage. Each of these measures complicates the pixel circuitry and control scheme.

According to a first aspect of the invention, there is provided an active matrix device comprising an array of display pixels, each pixel comprising: a current driven light emitting display element; a drive transistor for driving a current through the display element; and first and second capacitors connected in series between the gate and source or drain of the drive transistor, a data input to the pixel being provided to the junction between the first and second capacitors thereby to charge one of the first and second capacitors to a voltage derived from the pixel data voltage, and a voltage derived from the drive transistor threshold voltage being stored on the other of the first and second capacitors, wherein a unidirectional charge flow device is provided between the gate and source of the drive transistor to allow current flow from the gate to the source for resetting a drive transistor gate voltage.

In this arrangement, a unidirectional charge flow device enables the voltage on the gate of the drive transistor to be brought to a fixed voltage with reference to the source (this fixed voltage depending on the voltage drop across the device). This can be used to enable the drive transistor to be turned on without needing to drive current through the display element. No additional control lines are needed for the device.

The unidirectional charge flow device can comprise a diode or a transistor, which may be diode-connected or have a gate control line for an external control signal. These have relatively fixed voltage drops across them so that the drive transistor gate voltage can be known sufficiently accurately.

Each pixel preferably further comprises an input first transistor connected between an input data line and the junction between the first and second capacitors.

A second (shorting) transistor is preferably connected between the gate and drain of the drive transistor This enables the drive transistor current to be fed back from the drain to the gate during a threshold sampling operation.

This current flows as long as the gate-source voltage difference is larger than the threshold voltage.

Each pixel preferably further comprises a third transistor connected between the drive transistor and the display element, and this is used to isolate the drive transistor from the display element during the pixel addressing phase, thereby to avoid light emission during pixel addressing. The second and third transistors can be of opposite type and can then be controlled by a shared control line. Alternatively, the first and third transistors can be of opposite type can then be controlled by a shared control line. These measures enable simplification of the pixel layout and drive circuitry.

According to a second aspect of the invention, there is provided an active matrix device comprising an array of display pixels, each pixel comprising: a current driven light emitting display element; a drive transistor for driving a current through the display element; first and second capacitors connected in series between the gate and source or drain of the drive transistor, a data input to the pixel being provided to the junction between the first and second capacitors thereby to charge one of the first and second capacitors to a voltage derived from the display data voltage, and a voltage derived from the drive transistor threshold voltage being stored on the other of the first and second capacitors; an input first transistor connected between an input data line and the junction between the first and second capacitors; a second transistor connected between the gate and drain of the drive transistor; and a third transistor connected between the drive transistor and the display element, wherein the first and third transistors are of opposite type and are controlled by a shared control line. This arrangement enables a threshold compensation pixel to be implemented with only three controlling transistors, and only two control lines.

The first aspect of the invention also provides a method of driving an active matrix display device comprising an array of current driven light emitting display pixels, each pixel comprising an display element and a drive transistor for driving a current through the display element, the method comprising, for each pixel, the steps of: (i) driving the gate of the drive transistor to a reset voltage, by driving current through a unidirectional charge flow device connected between the gate and source of the drive transistor;

(ii) coupling a change in voltage to the gate of the drive transistor thereby to switch on the drive transistor and switch off the charge flow device;

(iii) using the drive transistor current to discharge or charge a capacitor arrangement until the drive transistor turns off and the capacitor arrangement stores a voltage dependent on the drive transistor threshold voltage;

(iv) applying a data input voltage to the capacitor arrangement; and (v) using the drive transistor to drive a current through the display element using a gate voltage that is derived from the data input voltage and the drive transistor threshold voltage.

This method uses a unidirectional charge flow device to provide a reset function which avoids the need to drive current through the display element during pixel addressing.

Preferably, during step (i), a first voltage is coupled from a data line to the pixel through an address transistor, during step (ii) a second voltage is coupled from the data line to the pixel through the address transistor, and during step (iv) a third voltage is coupled from the data line to the pixel through the address transistor. In step (iii), a shorting transistor between the gate and drain of the drive transistor is turned on (and may also have been on during steps (i) and (ii)).

A switch transistor for isolating the display element from the drive transistor and the address transistor can be of opposite type and controlled by a shared control line, or the switch transistor and the shorting transistor can be of opposite type and controlled by a shared control line.

The second aspect of the invention also provides a method of driving an active matrix display device comprising an array of current driven light emitting display pixels, each pixel comprising a display element and a drive transistor for driving a current through the display element, the method comprising, for each pixel, the steps of: (i) driving a current through the drive transistor and the display element, and charging a capacitor arrangement to the resulting gate-source voltage;

(ii) isolating the display element from the drive transistor using a switching transistor; (iii) using the drive transistor current to discharge or charge the capacitor arrangement until the drive transistor turns off and the capacitor arrangement stores a voltage dependent on the drive transistor threshold voltage;

(iv) applying a data input voltage to the capacitor arrangement from a data line through an address transistor; and

(v) using the drive transistor to drive a current through the display element using a gate voltage that is derived from the data input voltage and the drive transistor threshold voltage, wherein the switch transistor and the address transistor are of opposite type and are controlled by a shared control line.

This method can provide threshold voltage compensation using only the data line, a control line for the shorting transistor and the shared control line for the switch transistor and the address transistor.

The invention will now be described by way of example with reference to the accompanying drawings, in which:

Figure 1 shows a known EL display device;

Figure 2 is a schematic diagram of a known pixel circuit for current- addressing the EL display pixel using an input drive voltage; Figure 3 shows a schematic diagram of a first known pixel layout for a display device;

Figure 4 is a timing diagram for the pixel layout of Figure 3; Figure 5 shows a first example of pixel layout in accordance with the invention; Figure 6 shows a second example of pixel layout in accordance with the invention; Figure 7 is a timing diagram for a method of operation of the pixel layout of Figures 5 or 6;

Figure 8 shows a third example of pixel layout in accordance with the invention; Figure 9 is a timing diagram for a method of operation of the pixel layout of Figure 8;

Figure 10 shows a fourth example of pixel layout in accordance with the invention;

Figure .11 is a timing diagram for a first method of operation of the pixel layout of Figure 10;

Figure 12 is a timing diagram for a second method of operation of the pixel layout of Figure 10;

Figure 13 shows a fifth example of pixel layout in accordance with the invention; Figure 14 is a timing diagram for a first method of operation of the pixel layout of Figure 13; and

Figure 15 is a timing diagram for a second method of operation of the pixel layout of Figure 13.

The same reference numerals are used in different figures for the same components, and description of these components will not be repeated.

Figure 5 shows a first pixel arrangement in accordance with the invention. The pixel circuit corresponds to Figure 3, but with the addition of a diode 50 between the gate and source of the drive transistor T₀. This diode functions as a unidirectional charge flow device to allow current flow from the gate to the source. Figure 6 shows an alternative configuration in which this device is implemented as a diode-connected transistor 60. The transistor may instead be turned on and off by an additional control line connected to the gate, and this control line could be shared between rows of pixels.

This extra diode or transistor enables the addressing scheme to be changed so that the overdrive phase (step 40 in Figure 4) can be removed, and so that no current flows through the LED material during the addressing phase. The additional diode or transistor 50,60 does not require any additional control lines.

Figure 7 shows the addressing scheme. The first phase 70 is termed a "de-charge" phase, during which the control lines A1 and A2 are high. The column 6 is put at a high voltage. This causes the gate voltage to rise and will cause the diode 50 or 60 to start conducting, limiting the gate voltage to Vpower - Vφiode). Vφbde) is the voltage drop over the diode (or the threshold voltage of a transistor used as diode), In the "Vt correction" phase 72, the column data is lowered at least as much as |

I ⁺ | V_f | . i-e. the absolute value of the threshold of the diode and drive transistor (in this example they are negative).

This causes the drive transistor to conduct and the diode to be reverse biased (or the diode-connected transistor to be turned off) and charges the capacitor Ci causing the gate voltage to rise. The gate voltage continues to rise until the gate-source voltage difference is less than the threshold, namely the transistor conducts until Vgs = Vgate - Vpower = Vt.

The rest of the addressing scheme is unchanged compared to Figure 4.

In the pre-address phase 74, the shorting transistor is switched by making A2 low. Then, during the address phase 75, Vdata is adjusted in order to generate the correct information on the screen. This causes the Vgate to shift equivalent to the change in Vdata, i.e., Vgate = Vf + Vpower + (Vdata - Vref).

In the post address phase 76, the address transistor Ai is switched off

(A1 is made low). After the post address phase, the next row can be addressed starting with the de-charge phase.

Light can be generated from the addressed row by switching on transistor A₃ of that row high for the desired time (duty cycle), and the illumination period is shown as 77, with the row address period shown as 78 and the frame period shown as 79. Illumination can again start immediately after the address phase 78 or even the pre-address phase 74, or it can start at a later time during the frame. In the example of Figure 4, the drive transistor is turned on by driving a current through the LED briefly, to ensure that a gate-source voltage is present which corresponds to an ON condition. This gate-source voltage is then used to continue to drive the transistor during a threshold sampling phase. In the circuit of Figures 5 and 6 and the drive scheme shown in Figure 7, the diode or transistor 50,60 is used to provide a known voltage on the gate. A change in the voltage on the column 6 can then be guaranteed to place the drive transistor into a conducting condition (by providing a suitable gate-source voltage) to enable the subsequent sampling of the threshold voltage. The circuit thus avoids the need for additional control lines, as the diode or diode-connected transistor requires no external control inputs, and also avoids the need for current to be driven through the LED during the row addressing period. The need to provide a voltage waveform on the power line is also avoided, and the number of addressing lines is kept low. There are still three addressing lines in the examples of Figure 5 and 6.

A possible disadvantage of this circuit and addressing scheme is that the voltage swing on the data line is larger than for the previous scheme. In particular, an extra voltage level is needed for the column 6. However, it is possible to add this additional voltage level using a multiplexer. Hence, the data IC does not need to have a larger voltage swing. Indeed, such a technique is already employed for the Vref voltage in the circuit of Figure 3.

An improvement to the circuits of Figures 5 and 6 is to combine the functionality of either address lines A1 and A3 or address lines A2 and A3, as explained further below. In the circuits below, the diode function is shown implemented in each case by a transistor, but as explained above, a diode or other unidirectional device may be used.

An example is shown in Figure 8, in which the address lines A2 and A3 have been combined. To enable this, the switch transistor A₃ and the shorting transistor A₂ must be of opposite type, and in the example shown, the shorting transistor A₂ is n-type and the switch transistor A₃ is p-type. The addressing diagram for this circuit is shown in Figure 9, and is very similar to the addressing diagram shown in Fig. 7. The phases are exactly the same, and the same references are used.

As the address lines A2 and A3 cannot be controlled independently, the start of the period 77 when the light is generated cannot be chosen freely, but is fixed. Light is generated from the beginning of the address phase, until the shared control line A2/A3 is switched high again.

In this example, the switch transistor A₃ opens before the shorting transistor A₂ has been given time to close. This does not give rise to any problems because both transistors will be non-conducting.

The alternative of combining address lines A1 and A3 is also possible as shown in Figure 10. In this case, the address transistor Ai and the switch transistor A₃ need to be of opposite type. A possible addressing diagram for this circuit is shown in Figure 11. Again, the timing is very similar to the timing shown in Figures 7 and 9, and the same operation phases are identified. However this circuit either requires a duty cycle of 100% or an addressing scheme which actively turns the LED off at an intermediate point in time within the frame.

In this circuit, light generation continues as long as the shared control line A1/A3 is low. The control line A3 cannot be independently controlled to switch off the switch transistor A₃, and it is not possible simply to switch A1/A3 high for the remainder of the frame time. This would of course couple the address line 6 to the pixel, which would then see an increased load.

A 100% duty cycle scheme is shown in Figure 11 (by continuous illumination period 77), and Figure 12 shows an alternative drive scheme which enables a duty cycle control to be implemented.

In Figure 12, the phases 70,72,74,75,76 are identical to those shown in

Figure 11. When it is desired to end illumination, namely at the end of the duty cycle 77, the pixel is reprogrammed to a black state. This does not require as many phases as the original programming, because the pixel is placed into a state where the drive transistor is simply closed for sure. The total row address time now has two components, the period 78 and the additional second period 80.

In this second period 80, the high column voltage used in the initial "de- charge" phase is applied to the pixel in order to switch the drive transistor off. This second addressing operation does not require any threshold compensation operations.

The examples above make use of an additional diode - type element to prevent light output during the addressing phase. In some cases, it may be more important to reduce the complexity of the drive scheme and pixel circuit to a maximum.

Figure 13 shows a simplified pixel circuit for providing threshold voltage compensation. This circuit combines the address line A1 and A3, in the same way as explained with reference to Figure 10, but does not use the extra diode/transistor. In this case, the overdrive phase explained with reference to Figure 3 is required again, which generates light. The consequent possible reduction in contrast may be tolerated if the reduction in the amount of surface area occupied by the pixel circuit is more important.

The combination of the address lines A1 and A3 does not require any additional components, whereas the combining address lines A2 and A3 does require an extra component (diode, transistor or resistor), because of the need to switch the shorting transistor A2 independently from the switch transistor A3 to generate the initial overdrive phase.

In all examples above, combining the address lines A1 and A2 is not possible because the threshold voltage sampling requires independent switching of the address and shorting transistors Ai and A₂.

In the same way as for the circuit of Figure 10, the circuit of Figure 13 can either be operated with 100% duty cycle or with double addressing.

Figure 14 shows the 100% duty cycle drive scheme. The end of the row address period is the same as the prior art example of Figure 4, and the same control signals are applied to the three control transistors Ai to A₃ in the

"Vt correction", "pre-address", "address" and "post-address" phases 140,142,144,146. It will be understood that the switch transistor A₃ in Figure 13 is turned on by a low pulse on the A1/A3 shared control line, and for this reason the A1/A3 control line in Figure 14 is performing the same function as the A3 control line in Figure 4 for the phases listed above. The shared control line means the switch transistor A3 cannot be switched off independently as it is in Figure 4, and Figure 14 instead shows a 100% duty cycle control scheme, with illumination during the period shown as 148.

The control scheme differs at the beginning of the row address phase 150.

A reset phase 152 (and post-reset phase 153) is provided at the beginning, such that when entering the overdrive phase 154, the voltage on the intermediate node 30 is not too low. This reset phase involves turning on only the address transistor Ai to charge the intermediate node 30. However, depending on the voltages that are programmed into the circuit during the address phase, the reset (and subsequent post-reset) phase can be omitted.

The overdrive phase 154 requires the switch transistor A₃ to be on

(because this embodiment does not provide the additional diode) and the shared control line means that the address transistor Ai is off during this time. Timing delay phases 156,158 follow the overdrive phase, and these are inserted because the shorting transistor A₂ should be closed in the transition period when switching A1/A3 from low to high. In this transition period, both the switch transistor A₃ and the address transistor Ai are closed for a short period of time. If the threshold voltage sampling operation already starts, then this could put too much charge on the gate of the drive transistor, preventing the subsequent threshold voltage sampling from working correctly.

However, if the transition period is short enough then these timing delay phases can be omitted.

If a duty cycle of less than 100% is desired, then a double addressing scheme can be used, as already explained with reference to Figure 12.

Such as addressing scheme for the circuit of Figure 13 is shown in Figure 15, in which the same reference numerals are used as in Figure 14 to denote phases with the same effect. The addressing has two phases

150,160, and the second phase is a reset phase as explained with reference to Figure 12.

To aid comparison between the embodiments above, they all use a p- type drive transistor. Of course, all the types of transistors can in principle be reversed (n-type with p-type and vice versa) with the voltages adjusted accordingly. Also some individual transistors or pairs of transistors can be changed in type, for example the shorting transistor A₂.

It may be desirable to implement the circuit with only n-type or p-type transistors, as this can reduce manufacturing cost, and this is also possible.

Furthermore, some transistors may be implemented as two or more transistors in series.

In some embodiments, it may be possible to pipeline the addressing sequence so that more than one row of pixels can be programmed at any one time. Thus, the addressing signals on lines Ai to A3 can overlap with the same signals for different rows. This can be achieved providing it is still possible to ensure that only one row of address transistors Ai are on at a time.

The circuits can be used for currently available LED devices. However, the electroluminescent (EL) display element may comprise an electrophosphorescent organic electroluminescent display element. The invention is suitable for a-Si:H or polysilicon transistors for active matrix OLED displays.

In the examples above, the two capacitors are in series between the gate and source of the drive transistor, for storing the gate-source drive voltage. The capacitors may, however, be provided between the gate and drain, and an example of implementation of twin capacitor threshold compensation circuit using this approach can be found in WO2004/066249.

Indeed, this invention may be applied to many of the additional embodiments in WO2004/066249. Various other modifications will be apparent to those skilled in the art.

Claims

1. An active matrix device comprising an array of display pixels, each pixel comprising: a current driven light emitting display element (2); a drive transistor (TD) for driving a current through the display element; and first and second capacitors (Ci, C₂) connected in series between the gate and source or drain of the drive transistor, a data input to the pixel being provided to the junction (30) between the first and second capacitors (Ci, C₂) thereby to charge one of the first and second capacitors to a voltage derived from the pixel data voltage, and a voltage derived from the drive transistor threshold voltage being stored on the other of the first and second capacitors, wherein a unidirectional charge flow device (50;60) is provided between the gate and source of the drive transistor to allow current flow from the gate to the source for resetting a drive transistor gate voltage.

2. A device as claimed in claim 1 , wherein the unidirectional charge flow device comprises a diode (50).

3. A device as claimed in claim 1 , wherein the unidirectional charge flow device comprises a diode-connected transistor (60).

4. A device as claimed in any preceding claim, wherein each pixel further comprises an input first transistor (Ai) connected between an input data line

(6) and the junction between the first and second capacitors (Ci, C₂).

5. A device as claimed in any preceding claim, wherein the source of the drive transistor (T₀) is connected to a power supply line (26).

6. A device as claimed in any preceding claim, wherein each pixel further comprises a second transistor (A₂) connected between the gate and drain of the drive transistor.

7. A device as claimed in claim 6, wherein the second transistor (A₂) is controlled by a first gate control line which is shared between a row of pixels.

8. A device as claimed in any preceding claim, wherein the first and second capacitors (Ci, C₂) are connected in series between the gate and source of the drive transistor (T₀).

9. A device as claimed in claim 8, wherein each pixel further comprises a third transistor (A₃) connected between the drive transistor (T_D) and the display element (2).

10. A device as claimed in claim 9, wherein the third transistor (A₃) is controlled by a third gate control line which is shared between a row of pixels.

11. A device as claimed in any claim 4, 6 and 9, wherein the second and third transistors are of opposite type and are controlled by a shared control line.

12. A device as claimed in any claim 4, 6 and 9, wherein the first and third transistors are of opposite type and are controlled by a shared control line.

13. An active matrix device comprising an array of display pixels, each pixel comprising: a current driven light emitting display element (2); a drive transistor (T₀) for driving a current through the display element; first and second capacitors (C-i, C₂) connected in series between the gate and source or drain of the drive transistor, a data input to the pixel being provided to the junction between the first and second capacitors (Ci, C₂) thereby to charge one of the first and second capacitors to a voltage derived from the display data voltage, and a voltage derived from the drive transistor threshold voltage being stored on the other of the first and second capacitors; an input first transistor (A-i) connected between an input data line (6) and the junction between the first and second capacitors (Ci, C₂); a second transistor (A₂) connected between the gate and drain of the drive transistor; and a third transistor (A₃) connected between the drive transistor (T₀) and the display element (2), wherein the first and third transistors are of opposite type and are controlled by a shared control line.

14. A device as claimed in claim 13, wherein the first and second capacitors (Ci, C₂) are connected in series between the gate and source of the drive transistor (T_D).

15. A method of driving an active matrix display device comprising an array of current driven light emitting display pixels, each pixel comprising an display element (2) and a drive transistor (T_D) for driving a current through the display element, the method comprising, for each pixel, the steps of:

(i) driving the gate of the drive transistor (T_D) to a reset voltage, by driving current through a unidirectional charge flow device (50;60) connected between the gate and source of the drive transistor;

(ii) coupling a change in voltage to the gate of the drive transistor thereby to switch on the drive transistor (T₀) and switch off the charge flow device (50;60);

(iii) using the drive transistor current to discharge or charge a capacitor arrangement (Ci, C₂) until the drive transistor turns off and the capacitor arrangement stores a voltage dependent on the drive transistor threshold voltage;

(iv) applying a data input voltage to the capacitor arrangement; and (v) using the drive transistor (T_D) to drive a current through the display element using a gate voltage that is derived from the data input voltage and the drive transistor threshold voltage.

16. A method as claimed in claim 15, wherein during step (i), a first voltage is coupled from a data line (6) to the pixel through an address transistor (A-i), during step (ii) a second voltage is coupled from the data line to the pixel through the address transistor, and during step (iv) a third voltage is coupled from the data line to the pixel through the address transistor.

17. A method as claimed in claim 15 or 16, wherein in step (iii) a shorting transistor (A₂) between the gate and drain of the drive transistor (T₀) is turned on.

18. A method as claimed in claim 15, 16 or 17, wherein during steps (i) - (iv), the display element is isolated from the drive transistor by a switch transistor (A₃).

19. A method as claimed in claim 16 and claim 18, wherein the switch transistor (A₃) and the address transistor (A-i) are of opposite type and are controlled by a shared control line.

20. A method as claimed in claim 19, further comprising a second addressing step to turn off the pixel during the display frame period.

21. A method as claimed in claim 17, wherein during steps (i) - (iii), the display element is isolated from the drive transistor by a switch transistor (A₃).

22. A method as claimed in claim 21 , wherein the switch transistor (A3) and the shorting transistor (A₂) are of opposite type and are controlled by a shared control line.

23. A method of driving an active matrix display device comprising an array of current driven light emitting display pixels, each pixel comprising an display element (2) and a drive transistor (T₀) for driving a current through the display element, the method comprising, for each pixel, the steps of: (i) driving a current through the drive transistor (T₀) and the display element, and charging a capacitor arrangement (Ci, C2) to the resulting gate- source voltage;

(ii) isolating the display element from the drive transistor using a switching transistor (A₃); (iii) using the drive transistor current to discharge or charge the capacitor arrangement (Ci, C₂) until the drive transistor turns off and the capacitor arrangement stores a voltage dependent on the drive transistor threshold voltage;

(iv) applying a data input voltage to the capacitor arrangement from a data line (6) through an address transistor (A-O; and

(v) using the drive transistor (T₀) to drive a current through the display element using a gate voltage that is derived from the data input voltage and the drive transistor threshold voltage, wherein the switch transistor (A₃) and the address transistor (A-i) are of opposite type and are controlled by a shared control line.

24. A method as claimed in claim 23, wherein in step (ii) a shorting transistor (A₂) between the gate and drain of the drive transistor (T_D) is turned on.

25. A method as claimed in claim 24 wherein the method of controlling each pixel uses only the data line (6), a control line (A2) for the shorting transistor (A₂) and the shared control line (A1/A3) for the switch transistor (A₃) and the address transistor (Ai).

26. A method as claimed in claim 23 or 24, further comprising a second addressing step to turn off the pixel during the display frame period.