WO2006022520A1 - Carrier and also test board for semiconductor device test - Google Patents

Carrier and also test board for semiconductor device test Download PDF

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Publication number
WO2006022520A1
WO2006022520A1 PCT/KR2005/002803 KR2005002803W WO2006022520A1 WO 2006022520 A1 WO2006022520 A1 WO 2006022520A1 KR 2005002803 W KR2005002803 W KR 2005002803W WO 2006022520 A1 WO2006022520 A1 WO 2006022520A1
Authority
WO
WIPO (PCT)
Prior art keywords
lower substrate
semiconductor devices
substrate
test board
test
Prior art date
Application number
PCT/KR2005/002803
Other languages
French (fr)
Inventor
Jong-Cheon Shin
Original Assignee
Isc Technology Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Isc Technology Co., Ltd. filed Critical Isc Technology Co., Ltd.
Publication of WO2006022520A1 publication Critical patent/WO2006022520A1/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2893—Handling, conveying or loading, e.g. belts, boats, vacuum fingers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices
    • G01R31/2867—Handlers or transport devices, e.g. loaders, carriers, trays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333—Trays for chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • the present invention relates to a carrier and test board used in semiconductor testing equipment (test jig, etc.), and more particularly, to a test board which includes an upper substrate a lower substrate, and securely fixes a semiconductor device with it interposed between the upper and lower substrates so that the semiconductor device finished in an FAB process can be transferred to semiconductor testing equipment without using a separate carrier, thereby immediately performing the test process.
  • FIG. 1 is a schematic block diagram illustrating a state where a carrier and a test board are used in a semiconductor device testing process according to prior art.
  • a semiconductor device package 100 finished in a fabrication process of semiconductor devices is transferred to semiconductor testing equipment 14 through a conveyor belt 12 while being carried on a carrier 10 placed on the conveyor belt.
  • the semiconductor device package 100 loaded on the carrier 10 has been delivered to the semiconductor test equipment 14, it is separated from the carrier by a robot and is moved onto a test board 16 of the semiconductor testing equipment 14, followed by undergoing an electric test. Thereafter, depending on the test result, a semiconductor device judged good or poor is collected in a good or poor product container and selectively transferred to a packaging process.
  • the semiconductor device is delivered to a test process after a package process, it is required that the device is loaded onto the carrier, the carrier loaded with the device is transferred to the semiconductor testing equipment, and the device is then removed from the carrier to be loaded onto the test board.
  • the present applicant has invented the idea that if a test board is combined with a conventional carrier for dual purposes after eliminating the carrier, a series of processes involved in the carrier may be omitted, and has completed this invention.
  • the present invention has been made to address and overcome the above-mentioned problems occurring in the conventional prior arts, and it is an object of the present invention to provide a test board which includes an upper substrate a lower substrate, and securely fixes a semiconductor device with it sandwiched between the upper and lower substrates so that the semiconductor device finished in an FAB process can be transferred to semiconductor testing equipment without using a separate carrier, thereby immediately performing the test process.
  • a combined carrier and test board for semiconductor devices being connected to a test circuit of semiconductor testing equipment (not shown) for testing the semiconductor devices, and comprising: a lower substrate formed therein with a plurality of seating portions in which corresponding semiconductor devices are seated, respectively; and an upper substrate coupled to the lower substrate for securely fixing the semiconductor devices seated on the seating portions of the lower substrate.
  • the lower substrate or the upper substrate is formed thereon with pads and connection patterns which are in close contact with terminals of each of the semiconductor devices.
  • the seating portions may be penetratingly formed in the lower substrate to define openings, and each of the opened seating portions may be formed at the periphery thereof with a plurality of pads with which a plurality of leads of the each semiconductor device are in close contact correspondingly.
  • the seating portions may be formed in the lower substrate in the form of recesses for receiving the semiconductor devices therein, and the upper substrate is formed with a plurality of pads at positions thereof corresponding to the positions of terminals of each semiconductor device received in the seating recess.
  • a conventional carrier and a test board are combined with each other for dual purposes so that a semiconductor device testing process is simplified and the manufacturing cost is reduced.
  • FIG. 1 is a schematic block diagram illustrating a state where a carrier and a test board are used in a semiconductor device testing process according to prior art
  • FIG. 2 is a perspective view illustrating the entire construction of a combined carrier and test board which is in a disassembled state according to a preferred embodiment of the present invention
  • FIG. 3 is an enlarged detailed view of a seating portion formed in a lower substrate according to a preferred embodiment of the present invention.
  • FIG. 4 is an enlarged detailed view illustrating a state where a semiconductor device is seated in the seating portion;
  • FIG. 5 is a cross-sectional view illustrating a state where an upper substrate is securely coupled to the lower substrate in the state of FIG. 4;
  • FIG. 6 is a cross-sectional view illustrating a seating portion formed on the lower substrate according to another embodiment of the present invention.
  • FIG. 7 is a cross-sectional view illustrating a combined carrier and test board, which is in an assembled state and is applied to a BGA type semiconductor device according to another preferred embodiment of the present invention.
  • FIG. 2 is a perspective view illustrating the entire construction of a combined carrier and test board, which is in a disassembled state according to a preferred embodiment of the present invention.
  • the combined carrier and test board includes a lower substrate 20 and an upper substrate 30.
  • the lower substrate 20 has to serve as a test board, and thus it is preferably a printed circuit board which is formed thereon with pads, connection patterns and various patterns associated with other components (resistor, condenser, etc) which are in close contact with terminals of each of the semiconductor devices.
  • the upper substrate 30 requires wirings, it preferably employs a printed circuit board. But in the case where the upper substrate 30 functions merely to secure the semiconductor devices by being engagingly covered on the lower substrate 20, it is necessarily not a print circuit board.
  • the lower substrate 20 is formed thereon with a plurality of seating portions 22 in which corresponding semiconductor devices 100 are seated, respectively.
  • FIG. 3 shows an enlarged detailed view of a seating portion 22.
  • the seating portion 22 is penetratingly formed in the lower substrate 20 to define an opening. The shape of the opening depends on the shape of a semiconductor device package to be seated in the seating portion 22(see FIGs. 4 and 5).
  • a plurality of pads 24 with which leads of the semiconductor device are in close contact correspondingly. Since the pads 24 are frequently in close contact with the leads of the semiconductor device, they are preferably plated with gold.
  • Connection patterns 26 are electrically connected to the pads 24 to form a test circuit.
  • FIG. 4 is an enlarged detailed view illustrating a state where a semiconductor device 100 is seated in the seating portion 22.
  • a semiconductor device 100 is fit into the opening constituting the seating portion 22, and terminals 28 of semiconductor device comes into close contact with the pads 24 formed at the periphery of the seating portion 22 while being seated on the pads 24.
  • the lower substrate 20 and the upper substrate 30 are provide with alignment portions 32a and 32b, respectively, for aligning the positions of the lower and upper substrates upon the coupling of the lower and upper substrates so as to securely couple the lower substrate 20 and the upper substrate 30 to each other.
  • the alignment portions may be composed of alignment pins 32a formed protrudingly on the lower substrate 20 and alignment holes 32b formed penetratingly in the upper substrate 30 to correspond to the positions of the alignment pins 32a, but is not limited thereto.
  • the engagement state of the alignment pins 32a and the alignment holes 32b is shown in FIG. 5.
  • the upper substrate 30 may be formed with a plurality of recesses 34 at positions thereof corresponding to the package positions of the semiconductor devices 100 seated in the lower substrate 20 so as to securely fix the semiconductor devices upon the coupling of the lower and upper substrates 20 and 30.
  • the recesses 34 formed on the upper substrate 30 is necessarily required if the package of the semiconductor device 100 is formed in a shape protruding upwardly from the top surface of the lower substrate 20. Unless otherwise, the recesses 34 may not be formed on the upper substrate 30.
  • FIG. 5 is a cross-sectional view illustrating a state where the upper substrate is securely coupled to the lower substrate in the state of FIG. 4.
  • the semiconductor device 100 since the semiconductor device 100 does not protrude from the top surface of the lower substrate 20, the recesses are not formed on the bottom surface of the upper substrate 20.
  • connection portions 40 to be connected to a test circuit of semiconductor testing equipment (not shown).
  • the connection portions 40 may be formed in a pad arranging type that enables the connection portions to be in close contact with test pins of the semiconductor testing equipment, but may be used in a connector type. Since the connection between the test circuit and the test board is well known in the art, the detailed description thereof will omitted. Under the state of FIG. 5, the lower and upper substrates 20 and 30 function as a carrier immediately, so that the semiconductor devices 100 can be transferred to a test process from the FAB process through a conveyor.
  • connection portions 40 of the lower substrate 20 are electrically connected with test pins of the semiconductor testing equipment in a state where the semiconductor devices 100 are interposed between the lower and upper substrates 20 and 30 securely coupled to each other, followed by being subjected to an electric test.
  • the seating portions 22 includes, but is not limited to, an example in which they are penetratingly formed in the lower substrate 20.
  • the lower substrate 20" is sufficiently thick, it is enough that recesses are formed on the top surface of the lower substrate 20 at an extent that the semiconductor devices 100" can be accommodated therein.
  • test board of the type which can be applied to TSOP type package as a semiconductor device 100
  • those skilled in the art can easily modify the test board even in case of package type such as MLF, RCC, QFN, etc.
  • the present invention can be applied like in FIG. 7.
  • the recesses are formed in the lower substrate 20 and then BGA type packages 100" are fit into the recesses in such a fashion that the terminals 102 of the packages 100" are arranged to be oriented upwardly.
  • the upper substrate 30 is coupled to the top surface the lower substrate 20.
  • pads 36 and connection patterns (not shown) have to be formed on the bottom surface the upper substrate 30".
  • "Integrated silicone contactor Kelean Patent Application No. 10-2001-75606)
  • various well-known methods for example, separate interposer or spring pin connector, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

Disclosed herein is a test board which includes an upper substrate a lower substrate, and securely fixes a semiconductor device with it interposed between the upper and lower substrates so that the semiconductor device finished in an FAB process can be transferred to semiconductor testing equipment without using a separate carrier, thereby immediately performing the test process. The inventive combined carrier and test board for semiconductor devices, comprises: a lower substrate formed therein with a plurality of seating portions in which corresponding semiconductor devices are seated, respectively; and an upper substrate coupled to the lower substrate for securely fixing the semiconductor devices seated on the seating portions of the lower substrate. The lower substrate or the upper substrate is formed thereon with pads and connection patterns which are in close contact with terminals of each of the semiconductor devices.

Description

A combined test board with cariier for semiconductor device test
Technical Field The present invention relates to a carrier and test board used in semiconductor testing equipment (test jig, etc.), and more particularly, to a test board which includes an upper substrate a lower substrate, and securely fixes a semiconductor device with it interposed between the upper and lower substrates so that the semiconductor device finished in an FAB process can be transferred to semiconductor testing equipment without using a separate carrier, thereby immediately performing the test process.
Background Art
In order to test electrical properties of a semiconductor device for which a package is formed after the assembling of a die, when a number of semiconductor devices packed on a carrier are delivered to semiconductor testing equipment through a conveyor, the semiconductor devices placed on the carrier are then moved to a test board disposed on the semiconductor testing equipment so as to be loaded on the test board.
FIG. 1 is a schematic block diagram illustrating a state where a carrier and a test board are used in a semiconductor device testing process according to prior art.
Referring to FIG. 1, a semiconductor device package 100 finished in a fabrication process of semiconductor devices (FAB) is transferred to semiconductor testing equipment 14 through a conveyor belt 12 while being carried on a carrier 10 placed on the conveyor belt. After the semiconductor device package 100 loaded on the carrier 10 has been delivered to the semiconductor test equipment 14, it is separated from the carrier by a robot and is moved onto a test board 16 of the semiconductor testing equipment 14, followed by undergoing an electric test. Thereafter, depending on the test result, a semiconductor device judged good or poor is collected in a good or poor product container and selectively transferred to a packaging process.
As described above, conventionally when the semiconductor device is delivered to a test process after a package process, it is required that the device is loaded onto the carrier, the carrier loaded with the device is transferred to the semiconductor testing equipment, and the device is then removed from the carrier to be loaded onto the test board.
Disclosure of Invention
Technical Problem In order to more simplify a series of processes as mentioned above, the present applicant has invented the idea that if a test board is combined with a conventional carrier for dual purposes after eliminating the carrier, a series of processes involved in the carrier may be omitted, and has completed this invention. To this end, there has been a need for modifying the structure of the test board. Therefore, the present invention has been made to address and overcome the above-mentioned problems occurring in the conventional prior arts, and it is an object of the present invention to provide a test board which includes an upper substrate a lower substrate, and securely fixes a semiconductor device with it sandwiched between the upper and lower substrates so that the semiconductor device finished in an FAB process can be transferred to semiconductor testing equipment without using a separate carrier, thereby immediately performing the test process.
Technical Solution To achieve the above objects, according to the present invention, there is provided a combined carrier and test board for semiconductor devices, the combined test board being connected to a test circuit of semiconductor testing equipment (not shown) for testing the semiconductor devices, and comprising: a lower substrate formed therein with a plurality of seating portions in which corresponding semiconductor devices are seated, respectively; and an upper substrate coupled to the lower substrate for securely fixing the semiconductor devices seated on the seating portions of the lower substrate. The lower substrate or the upper substrate is formed thereon with pads and connection patterns which are in close contact with terminals of each of the semiconductor devices. Preferably, the seating portions may be penetratingly formed in the lower substrate to define openings, and each of the opened seating portions may be formed at the periphery thereof with a plurality of pads with which a plurality of leads of the each semiconductor device are in close contact correspondingly.
Preferably, the seating portions may be formed in the lower substrate in the form of recesses for receiving the semiconductor devices therein, and the upper substrate is formed with a plurality of pads at positions thereof corresponding to the positions of terminals of each semiconductor device received in the seating recess.
Advantageous Effects According to the present invention, a conventional carrier and a test board are combined with each other for dual purposes so that a semiconductor device testing process is simplified and the manufacturing cost is reduced.
Description of Drawings
FIG. 1 is a schematic block diagram illustrating a state where a carrier and a test board are used in a semiconductor device testing process according to prior art;
FIG. 2 is a perspective view illustrating the entire construction of a combined carrier and test board which is in a disassembled state according to a preferred embodiment of the present invention;
FIG. 3 is an enlarged detailed view of a seating portion formed in a lower substrate according to a preferred embodiment of the present invention;
FIG. 4 is an enlarged detailed view illustrating a state where a semiconductor device is seated in the seating portion; FIG. 5 is a cross-sectional view illustrating a state where an upper substrate is securely coupled to the lower substrate in the state of FIG. 4;
FIG. 6 is a cross-sectional view illustrating a seating portion formed on the lower substrate according to another embodiment of the present invention; and
FIG. 7 is a cross-sectional view illustrating a combined carrier and test board, which is in an assembled state and is applied to a BGA type semiconductor device according to another preferred embodiment of the present invention.
Best Mode for Invention
Now, an explanation on a test board according to a preferred embodiment of the present invention will be in detail given with reference to attached drawings.
FIG. 2 is a perspective view illustrating the entire construction of a combined carrier and test board, which is in a disassembled state according to a preferred embodiment of the present invention. Referring to FIG. 2, the combined carrier and test board includes a lower substrate 20 and an upper substrate 30. Among the both substrates, the lower substrate 20 has to serve as a test board, and thus it is preferably a printed circuit board which is formed thereon with pads, connection patterns and various patterns associated with other components (resistor, condenser, etc) which are in close contact with terminals of each of the semiconductor devices. Also, in the case where the upper substrate 30 requires wirings, it preferably employs a printed circuit board. But in the case where the upper substrate 30 functions merely to secure the semiconductor devices by being engagingly covered on the lower substrate 20, it is necessarily not a print circuit board.
The lower substrate 20 is formed thereon with a plurality of seating portions 22 in which corresponding semiconductor devices 100 are seated, respectively. FIG. 3 shows an enlarged detailed view of a seating portion 22. The seating portion 22 is penetratingly formed in the lower substrate 20 to define an opening. The shape of the opening depends on the shape of a semiconductor device package to be seated in the seating portion 22(see FIGs. 4 and 5). At the periphery of the opened seating portion 22 is formed a plurality of pads 24 with which leads of the semiconductor device are in close contact correspondingly. Since the pads 24 are frequently in close contact with the leads of the semiconductor device, they are preferably plated with gold. Connection patterns 26 are electrically connected to the pads 24 to form a test circuit.
In the meantime, FIG. 4 is an enlarged detailed view illustrating a state where a semiconductor device 100 is seated in the seating portion 22.
As shown in FIG. 4, a semiconductor device 100 is fit into the opening constituting the seating portion 22, and terminals 28 of semiconductor device comes into close contact with the pads 24 formed at the periphery of the seating portion 22 while being seated on the pads 24.
When the upper substrate 30 is placed on the lower substrate 20 and then is downwardly pressed with an appropriate pressure in a state where the semiconductor device is fit into the seating portion 22, the semiconductor device 100 is not escaped from the lower and upper substrates. This is in detail illustrated in FIG. 5. The lower substrate 20 and the upper substrate 30 are provide with alignment portions 32a and 32b, respectively, for aligning the positions of the lower and upper substrates upon the coupling of the lower and upper substrates so as to securely couple the lower substrate 20 and the upper substrate 30 to each other. The alignment portions may be composed of alignment pins 32a formed protrudingly on the lower substrate 20 and alignment holes 32b formed penetratingly in the upper substrate 30 to correspond to the positions of the alignment pins 32a, but is not limited thereto. The engagement state of the alignment pins 32a and the alignment holes 32b is shown in FIG. 5.
The upper substrate 30 may be formed with a plurality of recesses 34 at positions thereof corresponding to the package positions of the semiconductor devices 100 seated in the lower substrate 20 so as to securely fix the semiconductor devices upon the coupling of the lower and upper substrates 20 and 30. But, the recesses 34 formed on the upper substrate 30 is necessarily required if the package of the semiconductor device 100 is formed in a shape protruding upwardly from the top surface of the lower substrate 20. Unless otherwise, the recesses 34 may not be formed on the upper substrate 30.
FIG. 5 is a cross-sectional view illustrating a state where the upper substrate is securely coupled to the lower substrate in the state of FIG. 4. In FIG. 5, since the semiconductor device 100 does not protrude from the top surface of the lower substrate 20, the recesses are not formed on the bottom surface of the upper substrate 20.
Also, the lower substrate 20 is partially formed with connection portions 40 to be connected to a test circuit of semiconductor testing equipment (not shown). The connection portions 40, as shown in FIG. 2, may be formed in a pad arranging type that enables the connection portions to be in close contact with test pins of the semiconductor testing equipment, but may be used in a connector type. Since the connection between the test circuit and the test board is well known in the art, the detailed description thereof will omitted. Under the state of FIG. 5, the lower and upper substrates 20 and 30 function as a carrier immediately, so that the semiconductor devices 100 can be transferred to a test process from the FAB process through a conveyor. Then, after the semiconductor devices 100 have been moved to the test process, the connection portions 40 of the lower substrate 20 are electrically connected with test pins of the semiconductor testing equipment in a state where the semiconductor devices 100 are interposed between the lower and upper substrates 20 and 30 securely coupled to each other, followed by being subjected to an electric test.
In the above embodiment, the seating portions 22 includes, but is not limited to, an example in which they are penetratingly formed in the lower substrate 20. For example, like in FIG. 6, in the case where the lower substrate 20" is sufficiently thick, it is enough that recesses are formed on the top surface of the lower substrate 20 at an extent that the semiconductor devices 100" can be accommodated therein.
In addition, although the aforementioned embodiment suggests a test board of the type, which can be applied to TSOP type package as a semiconductor device 100, those skilled in the art can easily modify the test board even in case of package type such as MLF, RCC, QFN, etc.
If the terminals of the semiconductor device are formed of the type (for example, BGA type package), which is exposed only to the bottom surface of the package, the present invention can be applied like in FIG. 7.
That is, the recesses are formed in the lower substrate 20 and then BGA type packages 100" are fit into the recesses in such a fashion that the terminals 102 of the packages 100" are arranged to be oriented upwardly. Thereafter, the upper substrate 30 is coupled to the top surface the lower substrate 20. Of course, in this case, pads 36 and connection patterns (not shown) have to be formed on the bottom surface the upper substrate 30". In order to secure stability in the contact between the BGA type package 100" and the pads 36 of the upper substrate 30", "Integrated silicone contactor (Korean Patent Application No. 10-2001-75606)" as previously filed by the same applicant as the present invention may be interposed between the BGA type package 100" and the upper substrate 30", and various well-known methods (for example, separate interposer or spring pin connector, etc.) may be applied.
While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by the embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or

Claims

modify the embodiments without departing from the scope and spirit of the present invention.
Claims L A combined carrier and test board for semiconductor devices, the combined test board being connected to a test circuit of semiconductor testing equipment (not shown) for testing the semiconductor devices, and comprising: a lower substrate formed therein with a plurality of seating portions in which corresponding semiconductor devices are seated, respectively; and an upper substrate coupled to the lower substrate for securely fixing the semiconductor devices seated on the seating portions of the lower substrate, wherein the lower substrate or the upper substrate is formed thereon with pads and connection patterns which are in close contact with terminals of each of the semiconductor devices.
2. The combined carrier and test board according to claim 1, wherein either the lower substrate or the upper substrate is a printed circuit board.
3. The combined carrier and test board according to claim 1, wherein the seating portions are penetratingly formed in the lower substrate to define openings, and each of the opened seating portions is formed at the periphery thereof with a plurality of pads with which a plurality of leads of the each semiconductor device are in close contact correspondingly.
4. The combined carrier and test board according to claim 1, wherein the seating portions are formed in the lower substrate 20" in the form of recesses for receiving the semiconductor devices therein, and the upper substrate 30" is formed with a plurality of pads 36 at positions thereof corresponding to the positions of terminals of each semiconductor device received in the seating recess.
5. The combined carrier and test board according to any one claims 1 to 4, wherein the lower substrate 20 and the upper substrate 30 are provide with alignment portions 32a and 32b, respectively, for aligning the positions of the lower and upper substrates upon the coupling of the lower and upper substrates so as to securely couple the lower substrate and the upper substrate to each other.
6. The combined carrier and test board according to any one claims 1 to 4, wherein the upper substrate is formed with a plurality of recesses 34 at positions thereof corresponding to the package positions of the semiconductor devices 100 seated in the lower substrate 20.
PCT/KR2005/002803 2004-08-27 2005-08-25 Carrier and also test board for semiconductor device test WO2006022520A1 (en)

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Application Number Priority Date Filing Date Title
KR20-2004-0024556 2004-08-27
KR20-2004-0024556U KR200368618Y1 (en) 2004-08-27 2004-08-27 Carrier and also test board for semiconductor device test

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007130790A2 (en) * 2006-05-01 2007-11-15 Sensarray Corporation Process condition measuring device with shielding
US7540188B2 (en) 2006-05-01 2009-06-02 Lynn Karl Wiese Process condition measuring device with shielding

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230019687A (en) 2021-08-02 2023-02-09 황영상 Boat carrier for manufacturing semiconductor package
KR102672234B1 (en) * 2023-02-16 2024-06-04 한화엔엑스엠디 주식회사 Substrate carrier apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899107A (en) * 1988-09-30 1990-02-06 Micron Technology, Inc. Discrete die burn-in for nonpackaged die
US5302891A (en) * 1991-06-04 1994-04-12 Micron Technology, Inc. Discrete die burn-in for non-packaged die
KR19990009287A (en) * 1997-07-09 1999-02-05 문정환 Semiconductor Package Test Tray

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899107A (en) * 1988-09-30 1990-02-06 Micron Technology, Inc. Discrete die burn-in for nonpackaged die
US5302891A (en) * 1991-06-04 1994-04-12 Micron Technology, Inc. Discrete die burn-in for non-packaged die
KR19990009287A (en) * 1997-07-09 1999-02-05 문정환 Semiconductor Package Test Tray

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007130790A2 (en) * 2006-05-01 2007-11-15 Sensarray Corporation Process condition measuring device with shielding
WO2007130790A3 (en) * 2006-05-01 2008-05-22 Sensarray Corp Process condition measuring device with shielding
US7540188B2 (en) 2006-05-01 2009-06-02 Lynn Karl Wiese Process condition measuring device with shielding
US7555948B2 (en) 2006-05-01 2009-07-07 Lynn Karl Wiese Process condition measuring device with shielding

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