WO2006019336A2

WO2006019336A2 - Impedance controlled interconnect substrate and package for high-frequency electronic device

Info

Publication number: WO2006019336A2
Application number: PCT/RU2005/000422
Authority: WO
Inventors: Andrey Petrovich Zemlianov; Alexey Nikolaevich Bogachev; Alexander Roger Deas
Original assignee: Andrey Petrovich Zemlianov; Alexey Nikolaevich Bogachev
Priority date: 2004-08-11
Filing date: 2005-08-11
Publication date: 2006-02-23

Abstract

The present invention relates to a ball grad array (BGA) semiconductor package for high frequency semiconductor device and its fabrication method. The BGA package comprises a multi-layer printed circuit board interconnect substrate with a plurality of solder bumps of predefined size for mounting a Ball Grid Array Packaging type semiconductor component and provides a controlled impedance environment for transmitting high frequency differential signals.

Description

IMPEDANCE CONTROLLED INTERCONNECT SUBSTRATE AND PACKAGE FOR HIGH-FREQUENCY ELECTRONIC DEVICE

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a multi-layer printed circuit board interconnect substrate, and more particularly, to a multi-layer printed circuit board having a plurality of bump connection pads for mounting a Ball Grid Array Packaging type semiconductor component, and its fabrication method. The present invention also relates to a multi-layer printed circuit board interconnect substrate providing a controlled impedance environment for transmitting high frequency differential signals.

Description of the Background Art

Several types of electronic devices utilizing a circuit, which is integrated in a chip of semiconductor material, are possible. The chip is typically mounted on a chip carrier, so as to protect the chip from mechanical stresses, and is then encapsulated to produce an electronic package. The chip carrier includes an insulating substrate with conductive tracks, each track bonded to a corresponding terminal of the chip. Each track terminates at a contact pad (typically for connection to a printed circuit board). A typical chip carrier layout is shown in Fig.1 , where two high frequency differential pairs of contacts are designated as HF1 and HF2, while one of the low frequency contacts is shown as LF1.

A conventional integrated circuit typically includes a plastic or ceramic package that encapsulates an electronic circuit formed on a semiconductor substrate ("semiconductor die"). Typically, terminals, or so called "bump pads" are provided on the package for external connections. In one type of package, known as a "ball grid array" (BGA) package, the external terminals further provide solder bumps, or balls, which can be bonded onto conductive pads on a printed circuit board for connection to other circuit elements provided on the printed circuit board, as shown in Figs.2 and 3. In Fig.2, a lower pair 63, 64 of high frequency differential signal solder balls for connecting to a load board is marked by a different color.

Fig. 3 shows a pair of upper high frequency differential solder bumps 61 , 62 attached to the upper bump pads of connection elements of the flip-chip BGA package and intended for connection to a semiconductor device.

In a high-speed integrated circuit, such as one operating at the 10 gigahertz (10 GHz) range, the complex impedance (e.g., inductance) introduced by solder balls and other conductive elements can significantly affect signal quality by distorting signal waveforms and introducing noise. It is believed that a conventional wire- bonded BGA package cannot support a 1 GHz integrated circuit.

The transmission of a signal in a corresponding conductive track generates an electromagnetic wave; the wave propagates along a transmission line defined by the conductive track and an underlying ground plane. When the chip operates at a high frequency (for example more than about 1 Gigahertz), the propagation of the wave (microwave) can severely affect the performance of the electronic package. The electromagnetic field produced by a high frequency differential pair of contacts can be clearly seen in Fig. 4.

Particularly, any discontinuity (or transition) in the transmission line that the signal encounters as it travels along a conductive track, such as any change in structure, material properties and/or design features, generates a reflected wave. Moreover, the package includes stray structures (capacitors, inductors and resistors), which act as low pass filters for the transmitted signal. As a consequence, the integrity of the electromagnetic wave propagated along the transmission line degrades, especially at high frequencies. The transmitted signal, switching between a low voltage (logic value 0) and a high voltage (logic value 1) generates a square-shaped . wave. Because of discontinuities in the transmission line, this wave is generally received as a pseudo-sinusoidal wave. The quality of the transmitted wave can be visualized by a so-called "eye diagram", which plots the value of the received signal as a function of the phase of a clock signal controlling the electronic device. The above described discontinuities in the transmission line reduce the central opening of the eye diagram. This problem has been discussed in detail in previous publications by the same inventors, see, for example, US 2003 0014683 (EP 1 ,386,441). Therefore, it is quite difficult to understand if a switching transition has actually taken place or if the shift of a signal baseline is due to background noise. These drawbacks are particular acute in modern electronic devices working with a reduced level of power supply voltage (down to 1.2 V). In this case, there is a very low margin to discriminate between the logic value 0 (1V) and the logic value 1 (1.2V).

Moreover, the continuous trend towards miniaturization of electronic devices requires a reduction in the dimensions of chip carrier conductive tracks on which such devices are packaged. However, the impedance of the transmission line must be maintained at a desired value which optimizes the performance of the electronic device (typically 50 Ohm). Therefore, it is necessary to use a thin dielectric layer between the conductive tracks and the ground plane of the electronic package (since the impedance is inversely proportional to the track width and directly proportional to the dielectric layer thickness). A shortened distance between conductive tracks and the ground plane increases the value of a corresponding stray capacitance. As a consequence, the bandwidth of the transmission line is strongly reduced.

Therefore, as the quality of the transmission in the package is degraded it can cause the electronic device to operate at a frequency far lower than the working frequency which is afforded by the chip.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a printed circuit board and an integrated circuit package that can support a high-speed integrated circuit operating at 10 GHz or higher switching speeds.

Another object of the present invention is to provide a controlled impedance environment for a high frequency differential signal pair of contacts of the packaged electronic device.

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a multi-layer printed circuit board, including: The present invention is directed to a ball grid array ("BGA") package with controlled impedance high frequency ball differential pair.

According to an embodiment of the invention, a ball grid array package comprises a number of signal balls and ground balls. At least one pair of the signal balls is a controlled impedance signal ball pair, i.e. a pair of signal balls whose impedance is adjusted and/or reduced according to the present invention. The ball grid array package also includes a number of ground planes and signal planes.

In one embodiment of the invention, a controlled impedance pair of signal balls is coupled to one of the signal planes by means of a signal blind via. A number of ground balls surround the controlled impedance pair of signal balls. Each of the ground balls is connected to at least one of the ground planes through respective ground blind vias. By varying the arrangement, number, and size while maintaining a standard separation distance between the ground balls and the ground balls and the controlled impedance pair of signal balls, the impedance of the pair of signal balls is adjusted and/or reduced.

In one embodiment of the invention, a standard 100 Ohm differential impedance is achieved for the controlled impedance pair of signal balls.

Depending on the particular circuit or logic function assigned to a signal ball or a differential pair of signal balls, a different degree of impedance control and/or reduction can be achieved by the present invention. Various other features and advantages of the present invention are described in the detailed description section below.

According to the invention, a BGA semiconductor package comprises:

- an interconnect substrate having at least one high frequency differential input/output signal track for conducting a high frequency signal to/from a high speed semiconductor device/a load board;

- wherein the said high frequency differential signal track is formed by at least one pair of upper contacts arranged on one surface of the substrate, for connecting to the said semiconductor device, the upper contacts being connected to an interconnection element, which is arranged within the substrate and is connected in turn to the lower pair of contacts arranged on the other surface of the substrate, for connecting to the said load board; wherein either a plurality of the upper contacts or a plurality of the lower contacts, or both, are sized so as to provide a controlled impedance environment for the said at least one high frequency differential input/output signal track.

Preferably, the BGA package comprises the interconnection element which is formed by penetrating the insulation layer to achieve point-to-point adhering of the two plated layers so as to form an electronic component bump pad on one side of the connection element and a blind via hole for securing the load board solder bumps, on the other side of the connection element.

To achieve the above objects, a method is provided for fabricating an impedance controlled BGA semiconductor package, the method comprising the steps of:

- defining a package area in which impedance is to be controlled;

- creating a 3D model of the area using the above geometry design layout parameters of the package/PCB and package/PCB manufacturing data;

- importing the obtained 3D model into a 3D solver;

- assigning material properties obtained from package/PCB manufacturing data to the model components;

- running simulation to obtain the impedance data in the defined area; - comparing the obtained impedance data with the required data parameter, and, if desirable,

- modifying the shape and location of the bumps and connection elements in the model to bring the impedance to the desired value;

- providing the calculated parameters to the manufacturer. Preferably, the package area in which impedance is controlled, covers the area where a differential pair of high frequency signal contacts are located. Preferably, the controlled BGA semiconductor package manufactured by the method comprises:

- an interior layer with a plurality of connection elements therein forming a number N of upper bump pads on a device mounting surface and a number M of lower bump pads on a load board mounting surface;

- a number N1 of upper solder bumps of diameter D1 attached to the upper bump pads, upon which a semiconductor device is mounted;

- a number M1 of lower solder bumps of diameter D2 attached to the lower bump pads, upon which a load board is mounted - wherein at least one pair of connection elements with respectively attached upper and lower solder bumps forms a high frequency differential pair of signal elements.

Optionally, the material properties of the model components are varied as well. In this case, the simulation with changed geometry is run again until acceptable results are obtained. Geometry variations have to be consistent with values allowed by the package/PCB manufacturer.

Any suitable software tools can be used to create 3D model and calculate the impedance. Thus, the 3D model can be created using 3D CAD software such as Autocad 2000, while the 3D Solver can be ANSOFT HFSS v.9.0. Preferably, the impedance mismatch is calculated between the said high frequency differential pair of connection elements.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a top plan view of a printed circuit board substrate in accordance with the present invention;

FIG. 2 is a schematic perspective view from below showing the larger solder bumps attached to the lower bump pads of a BGA package in accordance with the present invention;

FIG. 3 is a schematic perspective view from above showing the smaller solder bumps attached to the upper bump pads of a BGA package in accordance with the present invention; FIG. 4 illustrates electromagnetic filed distribution in the vicinity of a high frequency differential signal pair solder bumps;

FIG. 5 is a sectional view of a BGA package in accordance with the present invention;

FIG. 6 is a schematic perspective view from above showing the area taken into account for impedance mismatch calculations;

FIGS. 7a and 7b show sectional views of a BGA package illustrating how the size of the solder bumps can be varied for the purposes of impedance control in accordance with the invention;

FIG. 8 shows how the arrangement of the BGA package can be varied for the purposes of impedance calculations in accordance with the invention;

FIG. 9 is a graph showing impedance calculation results for a high speed differential pair: (A) - upper solder bumps, and (B) - lower solder bumps.

FIGS. 10 - 12 show graphs of S-parameter calculations for a high speed differential pair: (A) - upper solder bumps, and (B) -lower solder bumps. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. A multi-layer BGA package in accordance with the present invention will now be described with reference to FIG. 5. FIG. 5 is a sectional view of a multi-layer BGA package in accordance with the present invention.

As shown in the drawing, pcb substrate comprises an interior layer 55. Upper circuit pattern 50 and lower circuit pattern 56 made of metal thin layer are formed on the interior layer 55. According to the example, there is one interior layer, however, the number of layers is not limited by this particular example.

A plurality of connection elements 52 penetrate the resin layer and electrically connect the upper circuit pattern 50 and the lower circuit pattern 56. These connection elements are formed as having an upper attachment elements 54 for attaching a silicon device and lower attachment elements 57 for attaching power pcb. The upper attachment elements are shaped in the form of bump pads 54 for attaching upper solder bumps 51 thereon, while the lower attachment elements are shaped in the form of blind via holes 57 for accommodating the lower solder bumps 53 therein. The blind via hole 58 is formed having a reversed conical shape wherein the diameter of the entrance is greater than that of the bottom. Preferably, the diameter of the entrance of the via hole 58 is such so as to accommodate only one lower solder bump 53.

An upper solder bump 51 for electrical connection with a semiconductor chip component (schematically shown as "silicon") is attached at the upper bump pad 54 which forms a part of the upper plated circuit layer 50 on the upper surface of the substrate 55.

As shown in the drawing, the upper solder bump 51 is to be connected with a chip component, and the lower solder bump 53 is to be connected with the main PCB (that is, the main PCB of an electronic appliance).

In other words, an upper solder bump 51 is formed at the upper surface of the upper bump pad 54 of the connection element 52 formed in the substrate and a ball grid array (BGA) semiconductor chip is attached on the upper surface of the upper solder bump 51. Respectively, the lower solder bump 53 is attached at the lower surface of the lower solder bump pad 57 formed as the blind via hole 58 of the printed circuit board. Typically, the lower solder bumping pad 57 is bigger than the upper solder bumping pad 54, and the lower solder bump 53 is formed larger than the upper solder bump 51. The reason for this is that, as the chip component connected with the upper bump 51 , that is, the semiconductor device, is being integrated with a higher density, the size of the lower bump remains the same or is rather reduced. But, in this respect, since the external terminals of the semiconductor chip components rather increases in number, the space between the terminals becomes narrow. Thus, the upper bumping pad 54 of the printed circuit board needs to become small, whereas the main PCB, relatively speaking, is not varied in its size.

Reference is now made to FIG. 6 which shows a plan view of a bump configuration in the area Z defined in the circuit layout in FIG. 1.

FIG. 6 shows the spatial arrangement of high frequency signal bumps 61 , 62, 63, 64 corresponding to signal bumps HF1 and HF2 in FIG. 1 , relative to ground bumps 65, 66, 67, 68, 69, 70 surrounding signal bumps.

With reference to FIGS. 1 , 2 and 3, it is noted that the impedance of a high frequency signal bump, such as signal bumps 61 , 62 is determined in part by a "return path" which is typically determined by the number, arrangement, and distance of any ground bumps, or in general any reference bumps with a constant DC voltage (and no AC component), around signal bumps 61 , 62. It is known that in response to a current flow through a conductor, such as a signal conductor, an "imaginary current" flows through an "imaginary conductor" situated at an opposite side of a ground bump, or in general a reference bump with a constant DC voltage (and no AC component), next to signal bump 61. The imaginary current loop that results from the existence of the "imaginary current" in the "imaginary conductor" and the existence of the "real current" in signal bump 61 , affects the impedance of signal bump 61. As such, the impedance of signal bump 61 is determined, in part, by the arrangement, number, and the distance of any ground bumps or reference pins around signal bump 61. As an example, suppose that a particular signal bump is to operate at a different frequency relative to another signal bump. The frequencies of operation of the two signal bumps might be very different; for example, signal bump LF1 in Fig.1 could be operating at approximately 32 MHz while signal bump HF1 could be operating at approximately 620 MHz. In that case, it may be desirable to reduce the impedance of signal bump HF1 more than that of signal bump LF1. Conventionally, this will be achieved by mounting an additional ground bump or reference bump in close proximity of signal bump HF1 to ensure that its impedance is significantly reduced.

According to the invention, if there is a particular signal bump which requires impedance control, this control can be achieved by simply adjusting the size or shape of the signal bump itself, thus avoiding the necessity of making additional changes to ground bumps, or introducing additional bumps, such as ground bumps or reference bumps, that should be otherwise located adjacent to this signal bump making the package less compact.

According to an embodiment of the present invention, with reference to Fig.6, the impedance of signal solder bumps 61 , 62 and 63, 64 is controlled and/or reduced by the size, shape and arrangement of these bumps themselves.

It shall be also noted that the distance between the bumps in a semiconductor package, such as a BGA package, is also referred to as a "pitch." Generally, the pitch in a semiconductor package, such as a BGA package, remains uniform. In other words, any two given bumps in a BGA package would have a distance from one another which is equal to the distance between any other two bumps in the BGA package. The present invention is applicable to a BGA package in a way to avoid making changes to the distance thus allowing for the BGA package manufacturers to preserve a uniform pitch and keep this distance undisturbed.

A method for controlling impedance of the high frequency differential pair of signal contacts will now be described.

To fabricate a controlled impedance BGA semiconductor package, the following method is provided.

First of all, an area is defined, which is taken into account when calculating impedance mismatch. Typically, this is the area embracing a high frequency differential pair of signal bumps surrounded by respective ground bumps, such as the area defined as Z in Fig.1 and shown in the plan view of Fig.6. FIG. 6 shows a computer-generated model of a portion of integrated circuit package.

According to the geometry obtained from package/PCB design layout and package/PCB manufacturing data a 3D model of the zone is created with the help of a 3D CAD software (e.g. Autocad 2000).

The 3D model is imported into a 3D solver (e.g. ANSOFT HFSS v.9.0). Using 3D solver material library, the material properties (obtained from package/PCB manufacturing data) are assigned to the model components. After creating the simulation setup the simulation is run. After the simulation is complete, the impedance data is available for analysis.

The shape and diameter of the balls and traces in the model can be modified in order to change the impedance to desired value. If necessary, material properties of the model components can be tuned as well. The simulation with changed geometry is run again until acceptable results are obtained. Geometry variations have to be consistent with values allowed by the package/PCB manufacturer.

Examples of impedance calculations are shown in Tables 1 ,2, 3 below.

Table 1

Impedance of high frequency ball differential pair vs. size of balls on silicon side

As seen from Table 1 , by varying the size of the upper small bumps, the impedance of the differential pair can be reduced. Still, the industry standard requires the impedance do not exceeding 100 Ohm, and thus, the next step was to vary the size of the lower signal bumps. The results are shown in Table 2. Table 2

Impedance of high frequency ball differential pair vs. size of balls on power PCB side

As seen from Table 2, it has become possible to reach the desired impedance value of 102 Ohm when the size of the lower bumps was increased by 20%. This provides a simple instrument to adjust the characteristics of the chip package.

Graphs in Fig.9 show lowering the impedance with frequency for the two high frequency ports, including upper port (graph A) and lower port (graph B), based on data presented in Table 2.

Table 3

Dependence of high frequency ball differential pair impedance on presence of ground balls and underfill material (simulation made for the original ball sizes: small balls diameter 0,11 mm, large balls diameter 0,4 mm)

FIG. 8 and Table 3 show influence of different package arrangements on the signal attenuation in the signal path and the conductive traces under the conditions of FIG. 5, further including variations in underfill material and ground balls. That is, Table 3 shows the electrical characteristics of a BGA package having (a) both the ground balls and the underfill material, (b) without ground balls, with underfill material; (c) with ground balls and with no underfill material; and (d) without both ground balls and underfill material.

As seen from the data of Table 3, removing underfill material increases impedance mismatch, nearly doubling it, while removing ground balls while keeping the underfill material makes insignificant changes to the impedance value. This confirms that the impedance can be adjusted by only varying the size and shape of the signal bumps themselves, in the absence of changes to the surrounding ground balls. FIGS. 10-12 are S-matrix simulations illustrating the results achieved in the present invention.

Specifically, FIG. 10 is a S-matrix plot that shows signal return loss S11 in the solder bumps and connection elements (due to reflection), and transmission loss S21 in the solder bumps and connection elements, under the arrangement of FIG. 5, when calculated for the upper port at the center of the upper solder bumps using the optimal solder balls diameter.

In other words, FIG. 10 shows the electrical characteristics of a BGA package for the original size of the solder bumps. Signal return loss in the signal path bond wire represents signal reflection due to impedance mismatch in the high frequency differential pair formed by the solder balls and connection elements in the package. As shown in FIG.10, transmission loss (S22) in the differential pair becomes hectic and instable as operating frequency increases. For the purpose of comparison, at 10 GHz operating frequency, signal loss in data path from the tip of the upper solder ball to the tip of lower solder ball is - 20 dB, and isolation signal loss is about - 4 dB.

FIG. 11 is the S-matrix plot that shows signal attenuation in the bond wire and the conductive traces due to transmission and reflection under the conditions of FIGs. 6 and 7, with the size of upper and lower signal balls varied. As seen in FIG. 11 , optimal size of signal balls makes the signal return loss remaining within the acceptable interval and reaching -25 dB at 10 GHz (curve S11) (though increasing gradually with frequency), and improves transmission loss to practically -0.1 dB (curve S21). This improvement is believed due to cancellation of impedance mismatch between the differential pair solder balls.

In the manner described above, impedance control and/or impedance reduction of a signal ball can allow to handle high frequency applications. As previously mentioned, high frequency applications usually require higher bump counts which in turn lead to larger and larger packages. The increase in package size intensifies problems such as impedance mismatches between two interconnect structures. Moreover, the high impedance of the relatively big bumps used in high-speed BGA applications has adverse effects on the performance of the PGA package. The lack of control over impedance of BGA bumps can be considerably reduced or eliminated by making the BGA signal bumps "controlled impedance structures" in the manner described above. The improvement resulting from the present invention can allow for the use of the BGA technology in high speed applications, without the performance limitations of conventional BGA packages. From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. As such, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalence of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims

CLAIMS:

1. A ball grad array (BGA) package comprising:

2. A BGA package of claim 1 , wherein the contact elements are implemented as solder bumps.

3. A BGA package of claim 1 , wherein the lower solder bumps are surrounded by a plurality of ground solder bumps contacting a ground plane.

4. A BGA package of claim 1 , wherein said impedance of said controlled impedance high frequency differential input/output signal track is practically invariable on the presence of the ground solder bumps.

5. A BGA package of claim 1 , wherein said impedance of said controlled impedance high frequency differential input/output signal track is reduced by the said ground solder bumps.

6. The BGA package of claim 1 wherein said impedance of said controlled impedance differential signal track is approximately 100 Ohms.

7. The BGA package of claim 1 wherein said impedance of said controlled impedance signal track is controlled by adjusting the size of the lower solder bumps.

8. The BGA package of claim 1 wherein said impedance of said controlled impedance signal track is reduced by increasing the size of the lower solder bumps.

9. The BGA package of claim 1 wherein said impedance of said controlled impedance signal track is controlled by adjusting the size of the upper solder bumps.

10. The BGA package of claim 1 wherein said impedance of said controlled impedance signal track is controlled by adjusting the separation distance between solder bumps.

11. A method of fabricating an impedance controlled BGA semiconductor package having a plurality of solder bumps for connecting to a semiconductor device and a plurality of solder bumps for connecting to a load board, the method comprising the steps of:

- defining a package area in which impedance is to be controlled; - creating a 3D model of the area using the above geometry design layout parameters of the package/PCB and package/PCB manufacturing data;

- importing the obtained 3D model into a 3D solver;

- running simulation to obtain the impedance data in the defined area;

- comparing the obtained impedance data with the required data parameter, and, if desirable,

- modifying the size and shape of the bumps and connection elements in the model to bring the impedance to the desired value;

- providing the calculated parameters to the manufacturer.

12. The method of claim 11 , wherein the material properties of underfill material are varied.

13. The method of claim 11, wherein the package area in which impedance is to be controlled covers a high frequency differential input/output signal track for conducting a high frequency signal to/from a high speed semiconductor device/a load board.

14. The method of claim 11 , wherein the package comprises:

- an interior layer with a plurality of connection elements therein forming a number N of upper bump pads on a device mounting surface and a number M of lower bump pads on a load board mounting surface; - a number N1 of upper solder bumps of diameter D1 attached to the upper bump pads, upon which a semiconductor device is mounted;

- a number M1 of lower solder bumps of diameter D2 attached to the lower bump pads, upon which a load board is mounted

- wherein at least one pair of connection elements with respectively attached upper and lower solder bumps forms a high frequency differential pair of signal elements.

15. The method of claim 11 , wherein the package comprises: an interconnect substrate having at least one high frequency differential input/output signal track for conducting a high frequency signal to/from a high speed semiconductor device/a load board; wherein the said high frequency differential signal track is formed by at least one pair of upper contacts arranged on one surface of the substrate, for connecting to the said semiconductor device, the upper contacts being connected to an interconnection element, which is arranged within the substrate and is connected in turn to the lower pair of contacts arranged on the other surface of the substrate, for connecting to the said load board;

16. The method of claim 11 , wherein the parameters modified include the size of the solder bumps on semiconductor side.

17. The method of claim 11 , wherein the parameters modified include the size of the solder bumps on the load board side.