WO2006019156A1 - 三次元積層構造を持つ半導体装置の製造方法 - Google Patents
三次元積層構造を持つ半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2006019156A1 WO2006019156A1 PCT/JP2005/015133 JP2005015133W WO2006019156A1 WO 2006019156 A1 WO2006019156 A1 WO 2006019156A1 JP 2005015133 W JP2005015133 W JP 2005015133W WO 2006019156 A1 WO2006019156 A1 WO 2006019156A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor
- insulating film
- substrate
- semiconductor substrate
- manufacturing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 892
- 238000000034 method Methods 0.000 title claims abstract description 271
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 530
- 239000004020 conductor Substances 0.000 claims abstract description 108
- 230000008569 process Effects 0.000 claims description 27
- 230000000149 penetrating effect Effects 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 abstract description 382
- 239000011229 interlayer Substances 0.000 abstract description 45
- 235000012431 wafers Nutrition 0.000 description 84
- 229910052751 metal Inorganic materials 0.000 description 48
- 239000002184 metal Substances 0.000 description 48
- 239000000853 adhesive Substances 0.000 description 40
- 230000001070 adhesive effect Effects 0.000 description 40
- 238000005530 etching Methods 0.000 description 37
- 238000005498 polishing Methods 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 25
- 238000005229 chemical vapour deposition Methods 0.000 description 21
- 239000000463 material Substances 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 239000011810 insulating material Substances 0.000 description 12
- 230000008901 benefit Effects 0.000 description 11
- 238000012545 processing Methods 0.000 description 11
- 238000003466 welding Methods 0.000 description 10
- 238000007747 plating Methods 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 239000010949 copper Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000010292 electrical insulation Methods 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- -1 etc. Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012966 insertion method Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the present invention relates to a method for manufacturing a semiconductor device (three-dimensional stacked semiconductor device) having a three-dimensional stacked structure formed by stacking a plurality of semiconductor circuit layers having various functions.
- the present invention relates to a method for manufacturing a three-dimensional stacked semiconductor device, including formation of embedded wiring for performing electrical connection in the vertical direction (stacking direction) between the semiconductor circuit layers.
- embedded interconnections refer to wirings for electrical connection in the stacking direction embedded in each of the semiconductor circuit layers.
- This image sensor chip has a four-layer structure, a processor array and an output circuit are arranged in the first semiconductor circuit layer, a data latch and a masking circuit are arranged in the second semiconductor circuit layer, An amplifier and an analog / digital converter are arranged in the third semiconductor circuit layer, and an image sensor array is arranged in the fourth semiconductor circuit layer.
- the uppermost surface of the image sensor array is covered with a quartz glass layer including the microlens array, and the microlens array is formed on the surface of the quartz glass layer.
- Image sensor A photodiode is formed as a semiconductor light receiving element in each image sensor in the array.
- the semiconductor circuit layers that constitute the four-layer structure are mechanically connected using an adhesive, and embedded wiring using conductive plugs and the micro-contacts that are in contact with the embedded wiring. It is electrically connected using bump electrodes.
- the image sensor chip does not use bonding wires for electrical connection between the semiconductor circuit layers. Therefore, a plurality of semiconductor chips are stacked on a support substrate and integrated, and bonding wires are arranged around the semiconductor chips. This is different from a semiconductor device having a three-dimensional structure in which electrical connection between the semiconductor chips is realized by bonding wires (this is conventionally known as disclosed in Patent Document 1).
- Non-patent Document 2 An image processing chip including an image sensor similar to the solid-state image sensor has been proposed (Non-patent Document 2).
- Each of the conventional image sensor chip and the image processing chip having the three-dimensional laminated structure described above is formed by laminating a plurality of semiconductor wafers (hereinafter also simply referred to as one wafer) incorporating desired semiconductor circuits. After the wafers are fixed to each other, the resulting wafer stack is cut (diced) and divided into a plurality of chip groups.
- a three-dimensional laminated structure is formed by laminating and integrating a semiconductor wafer having a semiconductor circuit formed therein at the wafer level, and an image sensor chip or an image processing chip is obtained by dividing it. .
- each of a plurality of stacked semiconductor circuits inside the chip constitutes a “semiconductor circuit layer”.
- Patent Document 2 has a convex structure in which a small-diameter portion and a large-diameter portion are connected to a semiconductor substrate, and an end portion of the small-diameter portion is a first main portion of the semiconductor substrate. A through-hole that is exposed to the surface and the end of the large-diameter portion is exposed to the second main surface of the semiconductor substrate is formed.
- a semiconductor chip manufacturing method is disclosed in which a conductor plug is formed by embedding a body, and then a multilayer wiring layer is formed on the first main surface. According to this manufacturing method, it is said that high reliability against thermal stress stress with high adhesion strength with bumps with high integration of devices can be obtained.
- Non-Patent Document 1 Kurino et al., “Intelligent 'Image Sensor' Chip with Three-dimensional Structure”, 1999 I'D. 1 D. 1-Tech. 'Digest' p. 36. 4.1 1-3 4 4 (H. Kunno et al., Intelligent Image Sensor Cnip with Three Dimensional Structure , 1999 IEDM Technical Digest, pp. 36.4.1-36.4.4, 1999)
- Non-Patent Document 2 Li et al., “Development of three-dimensional integration technology for highly parallel image processing chips”, “The Journal of Japan Society of Applied Physics”, Vol. 39, p. 2473-2477, Part 1 4B, 2000 4 (K. Lee et al "Development of fhree— Dimensional Integration Technology ror Highly Paralle 1 Image-Processing Chip", Jpn. J. Appl. Phys. Vol. 39, pp. 2474-2477, April 2000)
- Patent Document 1 Japanese Patent Laid-Open No. 2002-110902 (Figs. 1 and 4)
- Patent Document 2 Japanese Unexamined Patent Application Publication No. 2004-14657 (Figs. 1-9)
- the wafer stack (this is configured by stacking and integrating a plurality of semiconductor wafers)
- the electrical connection between the semiconductor circuit layers (here, the semiconductor wafers) in the vertical direction (stacking direction) is made up of fine embedded wiring (or conductive plugs) formed through each semiconductor circuit layer in the stacking direction.
- the microbump electrode is fixed to the end of the embedded wiring.
- the specific method of forming the buried wiring and the microbump electrode is not specified. Since both the embedded wiring and the micro bump electrode are about several meters in size and are very fine, they are arranged close to each other, so it is not easy to realize them. For this reason, there is a demand for a method for realizing highly reliable electrical connection in the stacking direction using such embedded wiring and micro bump electrodes.
- a semiconductor circuit layer (semiconductor wafer) inside the wafer stack generally includes a plurality of semiconductor elements formed on the surface of a semiconductor substrate on which the semiconductor circuit layer is formed, and an interlayer insulating film. And a wiring structure formed on these semiconductor elements.
- the embedded wiring (or conductive plug) must be formed by an optimum method according to the layout of the semiconductor elements on the semiconductor substrate, the layout of the wiring in the wiring structure, and the manufacturing process. For example, depending on the layout of the wiring in the wiring structure, it may not be possible to form embedded wiring (or conductive plugs) that penetrate the wiring structure. It may be difficult or impossible to form trenches for buried wiring with the surface side force of the substrate. Therefore, it is desirable to be able to cope with such restrictions.
- Patent Document 2 Since the semiconductor chip manufacturing method disclosed in Patent Document 2 described above needs to form a through-hole having a convex structure in which a small diameter portion and a large diameter portion are connected to each other in a semiconductor substrate, In order to form the through-hole, there are drawbacks that a mask formation process and an etching process are required twice.
- the present invention has been made in consideration of these points, and an object of the present invention is to use embedded wiring for electrical connection in the stacking direction between stacked semiconductor circuit layers.
- An object of the present invention is to provide a method of manufacturing a semiconductor device having a three-dimensional stacked structure that can be easily realized.
- Another object of the present invention is to lay out the elements and circuits of each of the stacked semiconductor circuit layers.
- An object of the present invention is to provide a method for manufacturing a semiconductor device having a three-dimensional stacked structure, which can form a buried wiring.
- the semiconductor substrate is bonded to the support substrate or the plurality of semiconductor circuit layers by bonding the second insulating film directly or indirectly via a wiring structure to the other one of the semiconductor circuit layers. Fixing to another one of the semiconductor circuit layers;
- the semiconductor substrate fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers is selectively removed from the back surface side force, so that the first insulating film is exposed to the back surface side of the semiconductor substrate.
- the semiconductor substrate constituting one of a plurality of semiconductor circuit layers is provided inside the semiconductor substrate.
- a trench whose inner wall surface is covered with a first insulating film is formed from the surface side, and a conductive plug is formed by filling the inside of the trench with a surface side force conductive material of the semiconductor substrate.
- a desired element or circuit is formed from the surface side inside or on the surface of the semiconductor substrate on which the conductive plug is formed, and the surface of the semiconductor substrate on which the element or circuit is formed is formed on the second insulating film. Cover with.
- the semiconductor substrate is bonded to the supporting substrate or the plurality of semiconductor circuit layers by bonding the second insulating film directly or indirectly via a wiring structure.
- the first insulating film is removed from the back surface side of the semiconductor substrate by selectively removing the semiconductor substrate fixed to the support substrate or the other one of the plurality of semiconductor circuit layers from the back surface side thereof. Expose to the side. Subsequently, the first insulating film exposed on the back side of the semiconductor substrate is selectively removed. Thus, the conductive plug is exposed on the back side of the semiconductor substrate.
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.).
- a known process for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.
- an electrical connection between the support substrate or the other one of the plurality of semiconductor circuit layers and the conductive plug exposed on the back side of the semiconductor substrate is formed on the surface of the semiconductor substrate. It can be easily realized by using wiring (in the case where the semiconductor substrate has a wiring structure, wiring inside the wiring structure and wiring formed on the surface of the semiconductor substrate). Further, wiring formed on the surface of the semiconductor substrate (in the case where a wiring structure exists, wiring in the wiring structure and wiring formed on the surface of the semiconductor substrate), and the conductive inside the trench.
- the conductive plug is an “embedded wiring” that penetrates the semiconductor circuit layer in the stacking direction. Therefore, by using this embedded wiring, electrical connection in
- the formation of the trench and the filling of the conductive material are performed from the surface side of the semiconductor substrate, and the trench is the second It does not penetrate through the insulating film (when the wiring structure exists, the second insulating film and the wiring structure). Therefore, the formation of the trench and the filling of the conductive material cannot be performed from the back side of the semiconductor substrate! /, Or the second insulating film (if there is a wiring structure, the second insulating film).
- This manufacturing method can be suitably applied when it is impossible or difficult to form a trench penetrating the film and the wiring structure.
- the first electrode may be used in the step of fixing the semiconductor substrate to the supporting substrate or one of the plurality of semiconductor circuit layers.
- the first electrode is disposed on at least one of the second insulating film or the wiring structure and the other one of the support substrate or the plurality of semiconductor circuit layers.
- the semiconductor substrate is fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers using the first electrode.
- the “support substrate” may be any material as long as it has sufficient rigidity to support a plurality of semiconductor circuit layers. Is optional. It may be a semiconductor, glass, or other material. It may be a semiconductor substrate with a circuit formed inside, that is, a so-called LSI wafer.
- “Semiconductor circuit layer” means a layer of a semiconductor circuit, in other words, a semiconductor circuit formed in a layer shape. Therefore, the “semiconductor circuit layer” may have any other configuration as long as it includes a “semiconductor substrate” and an “element” or a “circuit” formed inside or on the surface of the semiconductor substrate. is there.
- circuit for example, an amplifier circuit, a signal processing circuit, or an integrated circuit providing a predetermined function
- circuit for example, an amplifier circuit, a signal processing circuit, or an integrated circuit providing a predetermined function
- element for example, a light receiving element
- only a large number of “light receiving elements” arranged in an array may be formed inside or on the surface of the “semiconductor substrate”.
- elements include active elements such as transistors and passive elements such as resistors.
- Active elements typically include MOS field-effect transistors (Metal Oxide-Semiconductor Field-Effect Transistors, MOSFETs) that take into account the small footprint, etc. However, a diode or the like may be used.
- Passive element for example, a resistor or a capacitive element is used.
- the "semiconductor substrate” may be formed of a single semiconductor member (for example, a semiconductor wafer or a semiconductor chip), or may be formed of a plurality of semiconductor members (for example, a semiconductor wafer or a semiconductor chip). It may be.
- the physical size of the “semiconductor substrate” may be a semiconductor wafer size (wafer size) that is not limited, or may be a chip size (chip size) obtained by dividing a semiconductor wafer. It may be an intermediate size between the chip size and the chip size, or may be larger than the wafer size.
- the material of the “semiconductor substrate” is arbitrary, and may be silicon, a compound semiconductor, or other semiconductors as long as a desired semiconductor element or circuit can be formed.
- the structure of the “semiconductor substrate” is also arbitrary, and may be a simple board made of semiconductor, A so-called SOI (Silicon On Insulator) substrate may be used.
- the "trench” has any desired configuration as long as it has a desired depth and accommodates a conductive material to be an embedded wiring.
- the depth, opening shape, opening size, cross-sectional shape, etc. of the “trench” can be arbitrarily set as required.
- the “trench” can be formed by any method as long as it can be formed by selectively removing the semiconductor substrate from the surface side. An anisotropic etching method using a mask can be preferably used.
- the "first insulating film” covering the inner wall surface of the trench can electrically insulate the "semiconductor substrate" of the semiconductor circuit layer from the "conductive material” filled in the trench. Any insulating film can be used. Silicon dioxide (SiO 2), silicon nitride (SiN), etc. are suitable.
- any material can be used as long as it can be used as a conductive plug (buried wiring).
- a semiconductor such as polysilicon, or a metal such as tungsten (W), copper (Cu), or aluminum (A1) can be suitably used.
- the filling method of the “conductive material” any method can be used as long as it can fill the inside of the trench with the conductive material from the surface side of the semiconductor substrate.
- the "second insulating film” covers the surface of the "semiconductor substrate" of the semiconductor circuit layer on which the element or circuit is formed, and the surface can be electrically insulated from its adjacent partial force. Any insulating film can be used. Silicon dioxide (SiO 2), silicon nitride (SiN), etc. are suitable.
- the "first electrode” has only to be disposed on at least one of the second insulating film or the wiring structure and the other one of the support substrate or the plurality of semiconductor circuit layers. Can be chosen arbitrarily.
- the “first electrode” is preferably formed on the second insulating film directly or indirectly via a wiring structure, and the configuration and shape thereof can be arbitrarily selected.
- the “first electrode” is usually formed so as to protrude from the surface of the second insulating film (if the semiconductor circuit layer has a wiring structure, the surface of the wiring structure), but it does not necessarily have to protrude. It is sufficient if it can be electrically connected to the support substrate or another one of the plurality of semiconductor circuit layers.
- the “first electrode” is a conductive material piece that is separately formed, the surface of the second insulating film or the surface of the wiring structure (there is! Is the support substrate or other semiconductor circuit layers).
- One surface of the second insulating film or the surface of the wiring structure (or the other surface of the support substrate or the plurality of semiconductor circuit layers). ) May be formed by directly depositing a conductive material by a plating method or the like.
- the material, configuration, function, etc. of the “wiring structure” are arbitrary. It may be a single layer structure or a multilayer structure. Usually, it is composed of one or a plurality of patterned metal wiring films and one or a plurality of insulating films, but the specific configuration is arbitrarily selected as necessary.
- the “wiring structure” is an electrode for electrical connection between the support substrate or another one of the semiconductor circuit layers. Including, ok.
- the method for executing the “step of fixing the semiconductor substrate to the supporting substrate or the other one of the plurality of semiconductor circuit layers using the first electrode is bonded to the support substrate or the other one of the semiconductor circuit layers by welding, heating, or pressurization at room temperature, and an adhesive is used in combination.
- the method may be used. If welding or direct pressure bonding is not possible, an appropriate bonding metal (for example, In, Au, Ag, Sn, Cu, Al, W, etc., or an alloy composed of two or more of them or two of them) Bonding is performed with two or more laminated films) interposed therebetween.
- the semiconductor substrate fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers is selectively removed from the back surface side force thereof, so that the first insulating film is formed on the semiconductor substrate.
- the method of performing the “step of exposing to the back side” is not particularly limited. Typically An isotropic etching method using a mask, an anisotropic etching method, or a CMP method is used. A mechanical polishing method may be used in combination.
- a method of executing "a step of selectively removing the first insulating film exposed on the back side of the semiconductor substrate and exposing the conductive plug on the back side of the semiconductor substrate” There is no particular limitation. Typically, an isotropic etching method using a mask, an anisotropic etching method, or a CMP method is used.
- the semiconductor circuit layer is formed on the second insulating film in addition to the element or circuit.
- the first electrode is indirectly formed on the second insulating film via the wiring structure.
- an embedded wiring for optimal electrical connection is formed in response to restrictions caused not only by the layout of the elements or circuits of the semiconductor circuit layer but also by the wiring layout in the wiring structure.
- the step of exposing the first insulating film on the back side of the semiconductor substrate, and the back side of the semiconductor substrate A step of forming a third insulating film covering a back surface of the semiconductor substrate between the step of exposing the conductive plug, and the step of exposing the conductive plug in the step of exposing the first plug.
- the third insulating film is selectively removed together with the film.
- the back surface of the semiconductor substrate is covered with the remaining third insulating film, so that the electrical insulation of the back surface of the semiconductor substrate can be ensured. is there.
- the step of exposing the first insulating film on the back side of the semiconductor substrate, and the back side of the semiconductor substrate A step of forming a third insulating film covering a back surface of the semiconductor substrate between the step of exposing the conductive plug, a step of forming a flat film on the third insulating film, and the flat A step of selectively removing the insulating film, and in the step of exposing the conductive plug, the third insulating film and the remaining flattening film are selected together with the first insulating film. Removed.
- This second electrode is used as a bump electrode.
- a separately formed piece of conductive material may be fixed to the end of the conductive plug, or the conductive material is directly deposited on the end of the conductive plug by a plating method or the like. You may let them.
- the semiconductor substrate is formed of a single semiconductor member or a plurality of semiconductor members.
- a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the second aspect of the present invention is different from the method for manufacturing a semiconductor device according to the first aspect described above.
- Conductive plug embedded wiring that penetrates the first insulating film (if the semiconductor substrate has a wiring structure, the first insulating film and its wiring structure) that covers the surface of the semiconductor substrate that constitutes one of the above Is formed.
- the method for manufacturing a semiconductor device according to the second aspect of the present invention includes:
- the semiconductor substrate is used as the support substrate or another one of the semiconductor circuit layers. Fixing, and
- the semiconductor substrate fixed to the support substrate or the other one of the plurality of semiconductor circuit layers is selectively removed from the back surface side force, so that the second insulating film is exposed to the back surface side of the semiconductor substrate.
- a semiconductor substrate constituting one of the plurality of semiconductor circuit layers. After a desired element or circuit is formed inside or on the surface of the plate, the surface of the semiconductor substrate is covered with a first insulating film. Next, a trench that penetrates the first insulating film and reaches the inside of the semiconductor substrate and whose inner wall surface is covered with the second insulating film is formed from the surface side of the semiconductor substrate, and A conductive plug is formed in the trench from the surface side of the semiconductor substrate, and then a first electrode disposed at a position corresponding to an end of the surface side of the semiconductor substrate of the conductive plug is used.
- the semiconductor substrate is fixed to the supporting substrate or another one of the plurality of semiconductor circuit layers.
- the second insulating film is removed from the back surface of the semiconductor substrate by selectively removing the semiconductor substrate fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers from the back surface side. Expose to the side. Subsequently, the conductive plug is exposed on the back side of the semiconductor substrate by selectively removing the second insulating film exposed on the back side of the semiconductor substrate.
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.). Further, the trench penetrates the first insulating film and reaches the inside of the semiconductor substrate. The conductive plug of the portion becomes “buried wiring” that penetrates the semiconductor circuit layer in the stacking direction. Therefore, by using this embedded wiring and the first electrode, electrical connection in the stacking direction between the stacked semiconductor circuit layers can be easily realized.
- a known process for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.
- the formation of the trench and the filling of the conductive material are performed from the surface side of the semiconductor substrate, and the trench is the first. It penetrates the insulating film and reaches the inside of the semiconductor substrate. Therefore, this manufacturing method can be suitably applied when a trench that penetrates the first insulating film and reaches the inside of the semiconductor substrate can be formed. That is, the layout of the element or circuit of the semiconductor circuit layer (when the semiconductor circuit layer has a wiring structure, the layout of the wiring in the wiring structure is included in addition to the layout of the element and circuit) Corresponding to the constraints caused by the above, it is possible to form an optimal embedded wiring for electrical connection.
- the “support substrate”, “semiconductor circuit layer”, “semiconductor substrate”, “circuit”, “element”, and the inside of the trench The meaning of the “conductive material” filled in is the same as in the semiconductor device manufacturing method according to the first aspect of the present invention.
- the "first insulating film” covers the surface of the "semiconductor substrate" of the semiconductor circuit layer on which the element or circuit is formed and can electrically insulate the surface by its adjacent partial force
- Any insulating film can be used. Silicon dioxide (SiO 2), silicon nitride (SiN), etc. are suitable
- the "trench” reaches the inside of the semiconductor substrate through the first insulating film (if the semiconductor circuit layer has a wiring structure, the first insulating film and its wiring structure).
- any structure can be used as long as it has a desired depth and accommodates a conductive plug serving as an embedded wiring.
- the depth, opening shape, opening size, cross-sectional shape, etc. of the “trench” can be arbitrarily set as necessary.
- the “trench” is formed by penetrating the first insulating film (if the semiconductor circuit layer has a wiring structure, the first insulating film and its wiring structure) from the surface side of the semiconductor substrate. Any method can be used as long as it can be selectively removed.
- the "second insulating film" covering the inner wall surface of the trench can electrically insulate the "semiconductor substrate" of the semiconductor circuit layer from the "conductive material” filled in the trench. Any insulating film can be used. Silicon dioxide (SiO 2), silicon nitride (SiN), etc. are suitable
- the “first electrode” disposed at a position corresponding to the surface-side end of the conductive plug of the conductive plug can use any configuration and shape.
- the “first electrode” is usually formed so that the surface force of the wiring structure also protrudes, but it does not necessarily have to protrude.
- the “first electrode” may be formed at a position corresponding to the support substrate or another one of the conductive plugs of the plurality of semiconductor circuit layers. In short, it is sufficient if it can be electrically connected to the support substrate or another one of the plurality of semiconductor circuit layers. Any material can be used for the “first electrode” as long as it has electrical conductivity that can be used for electrical connection with the outside using the conductive plug inside the trench.
- the “first electrode” may be formed by fixing a separately formed conductive material piece to the end of the conductive plug, and a conductive material is attached to the end of the conductive plug. Alternatively, it may be formed by direct deposition. In addition, the first electrode may be formed using the conductive plug. Any one of these methods other than the end of the conductive plug may be used to form the support substrate or another one of the plurality of semiconductor circuit layers.
- the semiconductor substrate is placed on the support substrate or a plurality of the semiconductor circuit layers.
- the method of performing the “step of fixing to one” is not particularly limited. Typically under welding or heating !, the first electrode is bonded to the supporting substrate or the other one of the semiconductor circuit layers by pressurization at room temperature, and an adhesive is used in combination. Other methods may be used. If welding or direct pressure bonding cannot be performed, bonding may be performed with a bonding metal as described in the method for manufacturing a semiconductor device according to the first aspect of the present invention interposed therebetween.
- the semiconductor substrate fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers is selectively removed from the back surface side force, and the second insulating film is formed on the semiconductor substrate.
- the method of performing the step of exposing to the back side is the semiconductor device according to the first aspect of the present invention.
- an isotropic etching method using a mask, an anisotropic etching method, or a CMP method is used.
- a mechanical polishing method may be used in combination.
- a method of performing the "step of selectively removing the second insulating film exposed on the back side of the semiconductor substrate and exposing the conductive plug on the back side of the semiconductor substrate" As in the case of the semiconductor device manufacturing method according to the first aspect of the present invention, there is no particular limitation. Typically, an isotropic etching method using a mask, an anisotropic etching method, or a CMP method is used.
- the semiconductor circuit layer is formed on the first insulating film in addition to the element or circuit.
- the trench has a wiring structure, and the trench is formed through the first insulating film and the wiring structure.
- an embedded wiring for optimal electrical connection is formed in response to restrictions caused not only by the layout of the element or circuit in the semiconductor circuit layer but also by the layout of the wiring in the wiring structure.
- the material, configuration, function, etc. of the “wiring structure” are arbitrary. It may be a single layer structure or a multilayer structure. Usually, it is composed of one or a plurality of patterned metal wiring films and one or a plurality of insulating films, but the specific configuration is arbitrarily selected as necessary.
- the “wiring structure” is used for electrical connection between the supporting substrate or the other one of the plurality of semiconductor circuit layers separately from the first electrode used for electrical connection in the stacking direction. Including the electrode.
- the step of exposing the second insulating film on the back side of the semiconductor substrate, and the back side of the semiconductor substrate A step of forming a third insulating film that covers a back surface of the semiconductor substrate between the step of exposing the conductive plug, and the step of exposing the conductive plug;
- the third insulating film is selectively removed together with the second insulating film covering the wall surface of the trench.
- the step of exposing the second insulating film on the back surface side of the semiconductor substrate, and the back surface side of the semiconductor substrate A step of forming a third insulating film covering a back surface of the semiconductor substrate between the step of exposing the conductive plug, a step of forming a flat film on the third insulating film, and the flat A step of selectively removing the conductive film, and in the step of exposing the conductive plug, the third insulating film and the remaining flattening film are selected together with the second insulating film. Removed.
- the back surface of the semiconductor substrate is covered with the remaining third insulating film after the step of exposing the conductive plug is completed, the electrical insulation of the back surface of the semiconductor substrate can be ensured, Since the conductive plug protrudes from the back surface of the semiconductor substrate, there is an advantage that the conductive plug can be used as a bump electrode.
- the step of forming the second electrode on the end of the conductive plug exposed on the back surface side of the semiconductor substrate is used as a bump electrode.
- a separately formed piece of conductive material may be fixed to the end of the conductive plug, or the conductive material is directly deposited on the end of the conductive plug by a plating method or the like. You may let them.
- the end of the conductive plug exposed on the back side of the semiconductor substrate can be used as it is as the second electrode.
- the semiconductor substrate is formed of a single semiconductor member or a plurality of semiconductor members.
- a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the third aspect of the present invention differs from the method for manufacturing a semiconductor device according to the first and second aspects described above, and includes a plurality of semiconductor circuit layers.
- a conductive plug buried wiring
- the method for manufacturing a semiconductor device according to the third aspect of the present invention is as described in claim 23, A method of manufacturing a semiconductor device having a three-dimensional stacked structure configured by stacking a plurality of semiconductor circuit layers on a support substrate,
- the semiconductor substrate is bonded to the supporting substrate or the plurality of semiconductor circuit layers by bonding the first insulating film directly or indirectly through a wiring structure to the supporting substrate or the plurality of semiconductor circuit layers. Fixing to another one of the semiconductor circuit layers;
- the interior of the semiconductor substrate constituting one of the plurality of semiconductor circuit layers Alternatively, a desired element or circuit is formed on the surface, and then the surface of the semiconductor substrate on which the element or circuit is formed is covered with a first insulating film. Next, the semiconductor substrate is bonded to the support substrate or the plurality of semiconductor circuit layers by bonding the first insulating film directly or indirectly through a wiring structure to the other one of the plurality of semiconductor circuit layers. It is fixed to the other one of the semiconductor circuit layers.
- a conductive plug is formed by filling a conductive material into the trench from the back side of the semiconductor substrate.
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.).
- electrical connection between the support substrate or the other one of the semiconductor circuit layers and the conductive plug is as follows: Easily realized by using wiring formed on the surface of the semiconductor substrate (if the semiconductor substrate has a wiring structure, wiring inside the wiring structure and wiring formed on the surface of the semiconductor substrate) be able to. Furthermore, wiring formed on the surface of the semiconductor substrate (in the case where a wiring structure exists, wiring in the wiring structure and wiring formed on the surface of the semiconductor substrate) and the conductive plug inside the trench The “embedded wiring” penetrates the semiconductor circuit layer in the stacking direction. Therefore, by using this embedded wiring, electrical connection in the stacking direction between the stacked semiconductor circuit layers can be easily realized.
- the formation of the trench and the filling of the conductive material are performed by a back side force of the semiconductor substrate. Therefore, the formation of the trench and the filling of the conductive material cannot be performed by the surface side force of the semiconductor substrate, or the first insulating film (if there is a wiring structure, the first insulating film and the wiring This manufacturing method can be suitably applied when it is impossible or difficult to form a trench penetrating the structure.
- the first electrode may be used in the step of fixing the semiconductor substrate to the support substrate or one of the plurality of semiconductor circuit layers.
- the first electrode is disposed on at least one of the first insulating film or the wiring structure and the other one of the support substrate or the plurality of semiconductor circuit layers.
- the semiconductor substrate is fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers using the first electrode.
- the “first insulating film” is a “semiconductor substrate” of the semiconductor circuit layer on which the element or circuit is formed. Any insulating film can be used as long as it covers the surface of the substrate and can electrically insulate the surface with its adjacent partial force. Silicon dioxide (SiO 2), silicon nitride (SiN), etc. are suitable.
- the "trench” may have any desired structure as long as it has a desired depth and accommodates a conductive plug serving as an embedded wiring.
- the opening shape, opening size, cross-sectional shape, etc. of the “trench” can be arbitrarily set as required.
- any method for forming the “trench” any method can be used as long as it can be formed by selectively removing the semiconductor substrate from its back side. An anisotropic etching method using a mask can be suitably used.
- the "second insulating film” covering the inner wall surface of the trench can electrically insulate the "semiconductor substrate" of the semiconductor circuit layer from the "conductive material” filled in the trench. Any insulating film can be used. Silicon dioxide (SiO 2), silicon nitride (SiN), etc. are suitable.
- the “first electrode” has only to be disposed on at least one of the first insulating film or the wiring structure and the other one of the support substrate or the plurality of semiconductor circuit layers. Can be chosen arbitrarily.
- the configuration and shape of the “first electrode” is preferably selected as long as it is formed directly on the first insulating film or indirectly via the wiring structure.
- the “first electrode” is usually formed so as to protrude from the surface of the first insulating film (if the semiconductor circuit layer has a wiring structure, the surface of the wiring structure), but it does not necessarily have to protrude. It is sufficient if it can be electrically connected to the support substrate or another one of the plurality of semiconductor circuit layers.
- the “first electrode” is a conductive material piece that is separately formed, the surface of the first insulating film or the surface of the wiring structure (there is !, the support substrate or a plurality of the semiconductor circuit layers).
- One surface of the first insulating film or the surface of the wiring structure (or the other surface of the support substrate or the plurality of semiconductor circuit layers). ) May be formed by directly depositing a conductive material by a plating method or the like.
- the method of performing the "step of fixing the semiconductor substrate to the supporting substrate or the other one of the plurality of semiconductor circuit layers using the first electrode" is not particularly limited.
- the first electrode is bonded to the support substrate or the other one of the semiconductor circuit layers by welding, heating, or pressurization at room temperature, and an adhesive is used in combination.
- the method may be used.
- bonding may be performed with a bonding metal as described in the method for manufacturing a semiconductor device according to the first aspect of the present invention interposed therebetween.
- the semiconductor circuit layer is a wiring formed on the first insulating film in addition to the element or circuit.
- the first electrode is indirectly formed on the first insulating film via the wiring structure.
- an embedded wiring for optimal electrical connection is formed in response to restrictions caused not only by the layout of the element or circuit of the semiconductor circuit layer but also by the wiring layout in the wiring structure.
- the semiconductor substrate in the step of forming the trench whose inner wall surface is covered with the second insulating film, the semiconductor substrate is placed on the back surface thereof.
- the trench that penetrates the semiconductor substrate is formed by selective removal from the side, and the second insulating film covering the inner wall surface of the trench is electrically connected to the first electrode and the conductive plug. It is formed with an opening that allows connection.
- the first electrode and the conductive plug can be easily electrically connected through the opening only by filling the inside of the trench with the conductive material.
- the opening of the second insulating film is formed in the vicinity of an end of the trench on the surface side of the semiconductor substrate.
- the conductive plug is easily brought into contact with the element, circuit, or wiring formed on the surface or inside of the semiconductor circuit. There is an advantage that the electrical connection between the electrode and the conductive plug is facilitated.
- the step of forming the second electrode at the end of the conductive plug exposed on the back side of the semiconductor substrate is performed.
- This second electrode is used as a bump electrode.
- a separately formed piece of conductive material is fixed to the end of the conductive plug, and the conductive material is directly attached to the end of the conductive plug by a plating method or the like. It may be deposited.
- the end of the conductive plug exposed on the back side of the semiconductor substrate can be used as it is as the second electrode.
- the semiconductor substrate is formed of a single semiconductor member or a plurality of semiconductor members.
- a method of manufacturing a semiconductor device having a three-dimensional stacked structure according to a fourth aspect of the present invention includes a step of forming an element or a circuit and a trench in the method of manufacturing a semiconductor device according to the first aspect described above. This corresponds to a case in which the order of the steps for forming is changed. That is,
- the second insulating film is directly or indirectly via the wiring structure, the support substrate or the composite substrate. Fixing the semiconductor substrate to the supporting substrate or to another one of the plurality of semiconductor circuit layers by bonding to another one of the plurality of semiconductor circuit layers;
- the semiconductor substrate fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers is selectively removed from the back surface side force, so that the first insulating film is exposed to the back surface side of the semiconductor substrate.
- the first electrode may be used in the step of fixing the semiconductor substrate to the support substrate or one of the plurality of semiconductor circuit layers.
- the first electrode is disposed on at least one of the second insulating film or the wiring structure and the other one of the support substrate or the plurality of semiconductor circuit layers.
- the semiconductor substrate is fixed to the supporting substrate or the other one of the plurality of semiconductor circuit layers using the first electrode.
- the semiconductor circuit layer is a wiring formed on the second insulating film in addition to the element or circuit.
- the first electrode is indirectly formed on the second insulating film via the wiring structure.
- an embedded wiring for optimal electrical connection is formed in response to restrictions caused not only by the layout of the element or circuit of the semiconductor circuit layer but also by the wiring layout in the wiring structure.
- the step of exposing the first insulating film on the back side of the semiconductor substrate, and the back side of the semiconductor substrate A step of forming a third insulating film covering a back surface of the semiconductor substrate between the step of exposing the conductive plug, and the step of exposing the conductive plug in the step of exposing the first plug.
- the third insulating film is selectively removed together with the film.
- the back surface of the semiconductor substrate is covered with the remaining third insulating film, so that the electrical insulation of the back surface of the semiconductor substrate can be ensured. is there.
- the step of exposing the first insulating film on the back side of the semiconductor substrate and the back side of the semiconductor substrate A step of forming a third insulating film covering a back surface of the semiconductor substrate between the step of exposing the conductive plug, a step of forming a flat film on the third insulating film, and the flat A step of selectively removing the insulating film, and in the step of exposing the conductive plug, the third insulating film and the remaining flattening film are selected together with the first insulating film. Removed.
- the back surface of the semiconductor substrate is covered with the remaining third insulating film after the step of exposing the conductive plug is completed, the electrical insulation of the back surface of the semiconductor substrate can be ensured, Since the conductive plug protrudes from the back surface of the semiconductor substrate, there is an advantage that the conductive plug can be used as a bump electrode.
- the step of forming the second electrode on the end of the conductive plug exposed on the back side of the semiconductor substrate Further included.
- This second electrode is used as a bump electrode.
- a separately formed piece of conductive material may be fixed to the end of the conductive plug, or the conductive material is directly deposited on the end of the conductive plug by a plating method or the like. You may let them.
- the semiconductor substrate is formed of a single semiconductor member, or a plurality of semiconductor members. Is formed.
- the semiconductor device manufacturing method according to the first to fourth aspects of the present invention described above can be applied to any semiconductor device having a three-dimensional stacked structure, and the size thereof is not limited.
- the three-dimensional stacked semiconductor device may be a wafer size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure becomes a wafer size) or a chip size (in this case, each of the semiconductor circuit layers). May be a chip size), or an intermediate size between the wafer size and the chip size (in this case, each of the semiconductor circuit layers constituting the three-dimensional stacked structure is an intermediate size between the wafer size and the chip size).
- wafer size means almost the same size as a semiconductor wafer (for example, 8 inches in diameter).
- the height of the three-dimensional stacked semiconductor device is also arbitrary.
- Each of the semiconductor circuit layers may be formed from one semiconductor wafer or a plurality of semiconductor wafers arranged two-dimensionally, and may be one semiconductor chip (or a semiconductor member) or two A plurality of semiconductor chip (a semiconductor member) force arranged in a dimension may also be formed.
- the connection in the stacking direction between the stacked semiconductor circuit layers is performed using embedded wiring.
- Layout of each element or circuit in the stacked semiconductor circuit layer if the semiconductor circuit layer has a wiring structure, it can be used for layout of the element and circuit.
- FIG. 1A to FIG. 7A are partial cross-sectional views illustrating a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the first embodiment of the present invention for each step.
- the first embodiment is an example of manufacturing a semiconductor device having a three-dimensional stacked structure by stacking semiconductor wafers.
- a wafer (Si wafer) 11 made of single crystal silicon (Si) is prepared as a semiconductor substrate.
- a silicon dioxide (SiO 2) film 12 (thickness of about 10 nm) is formed on the surface (first main surface) of the wafer (semiconductor substrate) 11, and the entire surface
- Si N film 12a thinness 50
- SiO film 12 The entire surface of the SiO film 12 is covered with the SiN film 12a. Furthermore, Si N film 12
- a photoresist film 17 patterned so as to obtain a desired trench 13 is formed on 2 3 4 3 4 a.
- each trench 13 may be any force, for example, a diameter or a circle or rectangle with a side of about several zm.
- the state at this time is as shown in Fig. 1 (a).
- the photoresist film 17 used as a mask is removed. Note that the photoresist film 17 used as the mask is made of SiO 2 after the etching of the Si N film 12a.
- the film 12 may be removed before etching.
- the Si N film 12a is left on the surface of the Si substrate (wafer) 11, and a thermal oxidation method is used.
- SiO film 14 (thickness of about 500 nm) is selectively applied to the exposed surface (inner wall surface) of these trenches 13. Form.
- the SiO film 14 covers the entire inner wall surface of the trench 13 and covers the surface of the substrate 11.
- the Si N film 12a is removed.
- an appropriate conductive material is selectively embedded from the surface side of the substrate 11 into each trench 13 whose exposed surface is covered with the insulating film 14 by a known method, and the conductive plug 15 is inserted.
- Form For example, after depositing a film of a conductive material over the entire surface of a Si substrate (wafer) 11 by CVD (Chemical Vapor Deposition), it is etched back or by mechanical polishing and CMP (Chemical Mechanical Polishing).
- CVD Chemical Vapor Deposition
- CMP Chemical Mechanical Polishing
- the conductive plug 15 is obtained by leaving the portion inside the hose 13.
- the conductive material used here is not limited to, for example, a semiconductor such as polysilicon or a metal such as tungsten (W), copper (Cu), or aluminum (A1).
- each conductive plug 15 is drawn slightly lower than the surface of the SiO film 12.
- MOSFE T Metal
- MOS transistor Oxide-Semiconductor Field-Effect Transistor
- MOS transistor is formed as a desired circuit.
- Each MOS transistor includes a pair of source / drain regions 16 formed in the substrate 11 at a distance, a gate insulating film 12b formed between the source / drain regions 16, and a gate insulating film 12b.
- the gate insulating film 12b is made of a SiO film formed in a separate process from the SiO film 12.
- the SiO film 12 is selected at the location where the gate insulating film 12b is to be formed.
- a MOS transistor is shown as an example of a semiconductor element formed on the substrate 11.
- the present embodiment is not limited to this, and it is possible to form an arbitrary semiconductor element as necessary. Needless to say. This also applies to other embodiments described later.
- an interlayer insulating film 19 is formed over the entire surface of the Si substrate (wafer) 11 on the insulating film 12 covering the surface of the substrate 11, and this interlayer insulation is formed.
- the film 19 covers the entire MOS transistor and the exposed surface.
- the interlayer insulating film 19 a known organic or inorganic insulating film is arbitrarily used.
- the interlayer insulating film 19 is selectively etched to form through holes reaching the desired source / drain regions 16 and the conductive plugs 15 inside the trenches 13.
- a conductive material 21 is filled in the through holes corresponding to the source / drain regions 16 of the interlayer insulating film 19 by a known method.
- a conductive metal film (not shown) is formed on the interlayer insulating film 19, and the metal film is selectively etched to obtain a patterned metal wiring film 20.
- the metal wiring film 20 is divided into several wiring parts, and these wiring parts are in contact with the corresponding conductive plugs 15 through the through holes of the interlayer insulating film 19, respectively.
- Each wiring part of the wiring film 20 and the corresponding conductive plug 15 are electrically connected to each other.
- one wiring portion of the metal wiring film 20 corresponds to the corresponding source / drain region 16 via the conductive material 21 filled in the corresponding through hole of the interlayer insulating film 19. Is electrically connected to!
- a multilayer wiring structure 30 is formed on the metal wiring film 20 by a known method.
- This multilayer wiring structure 30 is composed of an insulating material 31 and three wiring layers 32, 33, 34 embedded in the insulating material 31, and a conductor mainly used for interlayer connection between the wiring layers 32, 33, 34. 35 and 36.
- the electric conductors 35 and 36 are not normally limited to the force embedded in the via hole formed in the insulating material 31.
- Insulating material 31 is formed from a single electrical insulating material force, but is often formed from a stack of several layers of different electrically insulating materials. Since the materials and forming methods used for the multilayer wiring structure 30 are well known, a detailed description thereof will be omitted.
- each microbump electrode 37 (which correspond to “first electrodes”) are formed on the surface (which is flattened) of the multilayer wiring structure 30 by a known method.
- the shape and size of each microbump electrode 37 is an arbitrary force, for example, a diameter or a circle or rectangle with a side of about several meters. The state at this time is as shown in Fig. 2 (d).
- These micro-bump electrodes 37 are respectively connected to the wiring layers 32, 33 or 3 in the multilayer wiring structure 30. Electrical connection is made to the corresponding conductive plug 15 inside the trench 13 via 4 and the conductor 35 or 36.
- the micro bump electrodes 37 on the surface of the multilayer wiring structure 30 and the conductive plugs 15 below the multilayer wiring structure 30 are electrically interconnected, and through this, the vertical direction (stacking direction) of the Si substrate 11 Can be electrically interconnected.
- the MOS transistor formed on the Si substrate 11 that is, the circuit formed on the substrate 11
- the metal wiring film 20 as necessary. Since they are connected, an electrical signal can be input to and output from the MOS transistor (that is, a circuit formed on the substrate 11) via the micro bump electrode 37 and the conductive plug 15.
- the microbump electrode 37 may be formed by adhering a separately formed conductive material piece to a predetermined location on the surface of the multilayer wiring structure 30, or directly on the surface of the multilayer wiring structure 30. The material may be selectively deposited by a plating method or the like. Further, the micro bump electrode 37 may be formed by using the conductor 36 of the multilayer wiring structure 30 or the like. For example, the upper end of the conductor 36 may be exposed or protruded from the surface of the multilayer wiring structure 30 and used as the micro bump electrode 37! /.
- the Si substrate (Si wafer) 11 having the MOS transistor (circuit) formed as described above and the multilayer wiring structure 30 formed on the substrate 11 constitute the first semiconductor circuit layer 1.
- the first semiconductor circuit layer 1 is fixed to the support substrate 40 by using the micro bump electrodes 37 formed on the surface of the multilayer wiring structure 30.
- the first semiconductor circuit layer 1 and the support substrate 40 are mechanically connected using the micro bump electrodes 37.
- the support substrate 40 for example, a glass, a single crystal Si wafer, or the like can be suitably used.
- a Si wafer (an LSI wafer incorporating a semiconductor circuit) is used!
- the first semiconductor circuit layer 1 is also electrically connected to the semiconductor circuit formed in the support substrate 40 made of a Si wafer by the micro bump electrode 37.
- a semiconductor circuit is built-in.
- the gap 39 is filled with electrically insulating adhesive 39. Fill and cure.
- adhesive 39 polyimide resin, epoxy resin and the like can be suitably used.
- the first semiconductor circuit layer 1 is electrically and mechanically connected to the support substrate 40 by the adhesive 39 and the microbump electrode 37.
- the microbump electrode 37 includes the first semiconductor circuit layer 1 and the support substrate 40. Will be used only for mechanical connection between. In this case, the micro bump electrode 37 may be omitted, and the first semiconductor circuit layer 1 and the support substrate 40 may be directly bonded.
- the back surface (second main surface) side of the Si substrate 11 is placed on each of the trenches 13 inside by mechanical polishing and CMP. Polishing is performed until the distance from the lower end is about 1 m, for example, to reduce the thickness of the entire substrate 11.
- the first semiconductor circuit layer 1 thus polished and thinned is denoted by la hereinafter.
- the state at this time is as shown in Fig. 2 (e).
- the back side of the thinned first semiconductor circuit layer la ie, the Si substrate 11
- isotropic etching such as wet-etching or plasma etching, and FIG.
- the SiO film 14 covering the inner wall surface of the trench 13 is formed on the first semiconductor circuit layer la.
- the etching amount at this time is adjusted so that the lower end of the conductive plug 15 protrudes from the back surface of the substrate 11 by a predetermined distance at the end of etching.
- an SiO film is formed on the back surface of the substrate 11 and the exposed SiO film 14.
- the thickness of the SiO film 41 is, for example, about 0.2; z m
- the lower end of the conductive plug 15 is exposed.
- the remaining SiO film 41 is formed on the conductive film on the back surface of the substrate 11.
- the entire back surface of the first semiconductor circuit layer la is flat.
- microbump electrodes 42 are formed on the exposed lower ends of the respective conductive plugs 15 by a known method. These micro bump electrodes 42 are, for example, led to the entire back surface of the substrate 11 (first semiconductor circuit layer la) in the state shown in FIG. After forming an electric film (not shown), the conductive film can be selectively removed by lithography and etching, or a lift-off method or a plating method can be used. When using the lift-off method, first, a resist film (not shown) having through holes is formed on the entire back surface of the substrate 1a in the state shown in FIG. Next, after forming a conductive layer (not shown) on the resist film, the resist film is peeled off.
- each electrode 42 is fixed to the lower end of the corresponding conductive plug 15. In the case of the plating method, it can be formed in the same manner as in the lift-off method.
- the second semiconductor circuit layer 2 is fixed to the back surface of the first semiconductor circuit layer la as follows.
- the corresponding elements are denoted by the same reference numerals as those of the first semiconductor circuit layer 1 and their corresponding elements. Description is omitted. Needless to say, the second semiconductor circuit layer 2 may be configured differently from the first semiconductor circuit layer 1 if necessary.
- a micro-bump electrode provided on the back surface of the first semiconductor circuit layer la (Si wafer 11) Micro bump electrodes 43 are formed at positions corresponding to (overlapping) 42, respectively. These electrodes 43 are bonded to each other by welding to the corresponding electrodes 42 of the first semiconductor circuit layer la.
- the second semiconductor circuit layer 2 is thus fixed (mechanically connected) to the back surface side of the first semiconductor circuit layer la, and electrical connection between the circuit layers la and 2 is simultaneously performed.
- a gap corresponding to the sum of the thicknesses of the electrodes 42 and 43 is formed between the two semiconductor circuit layers la and 2. The state at this time is as shown in Fig. 5 (j).
- the force of joining the electrode 43 and the electrode 42 by “welding” is not limited to this, and any other method can be used for joining the electrode 43 and the electrode 42.
- the electrode 43 and the electrode 42 may be directly pressed and brought into contact with each other at room temperature or under heating, and the electrodes 43 and 42 may be brought into contact with each other with a bonding metal interposed therebetween. It is also possible to join by heating the metal for joining and melting it.
- the gap between the first and second semiconductor circuit layers la and 2 is Fill and harden the electrically insulating adhesive 44 by insertion method.
- the mechanical connection and electrical connection between the two semiconductor circuit layers la and 2 are completed.
- the adhesive 44 polyimide resin or epoxy resin can be used.
- the first and second semiconductor circuit layers la and 2 face each other before bonding.
- Adhesive 44 is applied to the surface (or one of the opposing surfaces), and the adhesive 44 is filled in the gap between the first and second semiconductor circuit layers la and 2 when bonded. At the same time, excess adhesive 44 may be pushed out from the gap. In this case, after the excess adhesive 44 is removed, the adhesive 44 in the gap is cured.
- the lower part of the substrate (wafer) 11 of the second semiconductor circuit layer 2a is selectively removed by the same method as that for the first semiconductor circuit layer la, and the SiO film 14 inside the trench 13 is removed.
- the SiO film 41 is formed on the back surface of the substrate 11 and the exposed SiO film 14.
- Micro bump electrodes 42 are formed on the lower ends of the conductive plugs 15.
- the configuration of the semiconductor circuit layer 2a is as shown in FIG. 7 (1).
- the second semiconductor circuit layer 2a in FIG. 7 (1) is substantially in the same state as the first semiconductor circuit layer la shown in FIG. 4 (i).
- the semiconductor device is a two-layered three-dimensional stacked semiconductor device composed of the first and second semiconductor circuit layers la and 2a
- the outlet bump electrode 42 is used as a micro bump electrode for connecting an external circuit.
- the back surface of the second semiconductor circuit layer 2a has a portion other than the micro bump electrode 42 formed of SiO.
- the semiconductor device has the third or more semiconductor circuit layers
- the third, fourth, and second layers are stacked on the second semiconductor circuit layer 2a by the same method as described above, if necessary.
- the semiconductor circuit layers (not shown) are sequentially stacked and fixed to manufacture a semiconductor device having a three-dimensional stacked structure of three-layer structure, four-layer structure, and five-layer structure.
- the circuit inside the first semiconductor circuit layer la is on the one hand the wiring in the multilayer wiring structure 30 inside the first semiconductor circuit layer la and the micro It is electrically connected to the circuit in the upper support substrate 40 via the bump electrode 37, and on the other hand, the conductive plug 15 in the first semiconductor circuit layer la, the micro bump electrodes 42 and 43, and the first 2 is electrically connected to the circuit in the second semiconductor circuit layer 2a via the wiring in the multilayer wiring structure 30 in the semiconductor circuit layer 2a.
- the circuit in the second semiconductor circuit layer 2a is connected to the lower external circuit or third semiconductor circuit via the conductive plug 15 and the micro bump electrode 42 (and 43) in the second semiconductor circuit layer 2a. Electrically connected to circuitry in the layer.
- the silicon substrate (Si wafer) 11 constituting the first semiconductor circuit layer 1 is placed at a predetermined position inside.
- a plurality of trenches 13 each having a predetermined depth whose inner wall surface is covered with SiO film 14 are formed from the surface side of
- a conductive plug 15 is formed by filling the trench 13 with a surface side force conductive material of the substrate 11.
- a desired semiconductor element here, a MOS transistor
- a multilayer wiring structure 30 is formed thereon via an interlayer insulating film 19, and then a microbump electrode 37 electrically connected to the conductive plug 15 is formed on the surface of the multilayer wiring structure 30.
- a plurality are formed.
- the Si substrate 11 having the multilayer wiring structure 30 is fixed to one surface of the support substrate 40 by using these microphone opening bump electrodes 37 .
- the Si substrate 11 fixed to the support substrate 40 is selectively removed from the back side of the Si substrate 11 to thin the Si substrate 11 itself, thereby forming the SiO film 14 covering the inner wall surface (exposed surface) of the trench 13 as a substrate. Exposed on the back side of 11. Subsequently, the dew
- the conductive plug 15 is formed on the substrate.
- a micro bump electrode 42 is formed on the exposed end.
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.).
- the electrical connection between the micro-bump electrode 37 on the surface of the multilayer wiring structure 30 and the conductive plug 15 formed inside the trench 13 and having one end exposed on the back surface side of the substrate 11 is connected to the multilayer wiring structure 30.
- the wiring inside the multi-layer wiring structure 30 (wiring layers 32, 33, 34 and conductors) is performed using the metal wiring inside the wiring and the wiring film 20 formed on the interlayer insulating film 19. 35, 36), the wiring film 20, and the conductive plug 15 form an “embedded wiring” that penetrates the first semiconductor circuit layer la in the stacking direction. Therefore, by using the embedded wiring and the micro bump electrode 37 (or the micro bump electrodes 42 and 43), the support substrate 40 and the first semiconductor circuit layer la (or the first semiconductor circuit layer la and the first semiconductor circuit layer la) are used. The electrical connection in the stacking direction between the two semiconductor circuit layers 2a and between the adjacent semiconductor circuit layers after the second semiconductor circuit layer 2a can be easily realized.
- the formation of the trenches 13 and the filling of the conductive materials into the trenches 13 are performed on the surface (first main surface) of the Si substrate (wafer) 11 At the same time, the trench 13 does not penetrate the multilayer wiring structure 30 and the interlayer insulating film 19. For this reason, the formation of the trench 13 and the filling of the conductive material cannot be performed from the back surface (second main surface) side of the substrate 11, or the formation of the trench 13 penetrating the multilayer wiring structure 30 is impossible or difficult.
- this manufacturing method can be suitably applied. In other words, it is possible to deal with restrictions caused by the layout of the semiconductor elements and wirings in the first semiconductor circuit layer la and the wiring layout in the multilayer wiring structure 30. The same applies to the second semiconductor circuit layer 2a and the subsequent semiconductor circuit layers.
- the first semiconductor circuit layer la and the second semiconductor circuit layer 2a are sequentially stacked and fixed below the support substrate 40.
- the support substrate 40 is turned upside down. Then, the first semiconductor circuit layer la and the second semiconductor circuit layer 2a may be stacked and fixed in order on the support substrate 40! Needless to say! /
- the manufacturing method of the present embodiment is not limited to this.
- it may be as follows. That is, first, the first semiconductor circuit layer 1 having the structure shown in FIG. 2 (d) and the second semiconductor circuit layer 2 having the structure shown in FIG. 5 (j) are first manufactured. Thereafter, the first semiconductor circuit layer 1 is fixed to the support substrate 40, and the back surface of the first semiconductor circuit layer 1 is processed to form the first semiconductor circuit layer la having the structure shown in FIG. 4 (i).
- the second semiconductor circuit layer 2 having the structure shown in FIG. 5 (j) is fixed to the first semiconductor circuit layer la and the back surface of the second semiconductor circuit layer 2 is processed to obtain the structure shown in FIG. 7 (1).
- the second semiconductor circuit layer 2a having the following is formed.
- the wafer-size three-dimensional stacked semiconductor device having the above-described configuration is used as it is as a single wafer-size three-dimensional stacked semiconductor device without dividing the wafer stack composed of a plurality of stacked wafers.
- it can be divided into a plurality of parts by appropriately dicing in the direction (stacking direction) perpendicular to the support substrate 40 and used as a plurality of three-dimensional stacked semiconductor devices smaller than the wafer size. Needless to say.
- FIGS. 8 (a) to 13 (i) are partial cross-sectional views illustrating a method for manufacturing a semiconductor device having a three-dimensional laminated structure according to the second embodiment of the present invention.
- the second embodiment is an example of manufacturing a semiconductor device having a three-dimensional stacked structure by stacking semiconductor chips.
- the first and second semiconductor circuit layers la and 2a are both configured using Si wafers. However, in the second embodiment, the first and second semiconductor circuit layers la and 2a are both configured.
- the two semiconductor circuit layers la ′ and 2a ′ are different from each other in that a plurality of Si chip forces are arranged in one plane.
- the first semiconductor circuit layer la ′ is composed of two Si chips 51a and 52a arranged in one plane, In the following description, it is assumed that the two semiconductor circuit layers 2a 'are composed of two Si chips 6la and 62a.
- the first semiconductor circuit layer 1 having the configuration shown in FIG. 2 (d) is formed. Then, the first semiconductor circuit layer 1 is diced by a known method to obtain two Si chips 51 and 52 as shown in FIG.
- the dicing direction is a direction orthogonal to the Si substrate 11 (stacking direction). Si chip 51 and 52 may be manufactured in other ways, not to mention! /.
- the Si chips 51 and 52 are fixed to predetermined positions on one surface of the support substrate 40, respectively.
- the support substrate 40 for example, glass, a single crystal Si wafer, or the like can be suitably used.
- a Si wafer incorporating a semiconductor circuit is used.
- the micro bump electrode 37 the Si chips 51 and 52 are electrically connected to a semiconductor circuit formed in the support substrate 40 made of a Si wafer.
- FIG. 8 (a) only one micro bump electrode 37 for connecting the Si chip 51 is shown, but it goes without saying that a large number of micro bump electrodes 37 are actually connected. This also applies to the Si chip 5.
- the strength of filling the gap with an electrically insulating adhesive 53 and curing it is different from the case of the first embodiment in order to increase the adhesive strength by the adhesive 53.
- the thickness of the adhesive 53 is made sufficiently large. In this way, as shown in FIG. 8B, parts other than the back side of the Si chips 51 and 52 are buried in the adhesive 53.
- the adhesive 53 polyimide resin or epoxy resin can be used.
- the Si chips 51 and 52 are mechanically and electrically connected to the support substrate 40 by the adhesive 53 and the micro bump electrode 37.
- the first semiconductor circuit layer 1 ′ having the Si chips 51 and 52 is formed.
- the microbump electrode 37 includes the Si chips 51 and 52, the support substrate 40, Will be used only for mechanical connection between.
- the back surface (second main surface) side of the Si substrate 11 of each of the chips 51 and 52 is placed inside Polishing is performed until the distance from the lower end of the trench 13 is, for example, about 1 ⁇ m, and the total thickness of the chips 51 and 52 is reduced. Chips 51 and 52 thus polished and thinned are denoted 51a and 52a, respectively.
- the first semiconductor circuit layer 1 'polished and thinned in this way is referred to as la' It shows with.
- the back side of the Si substrate 11 of both chips 51a and 52a is selectively removed by isotropic etching such as wet etching, plasma, etching, or the like, as shown in FIG. 9 (c). Then, the SiO film 14 inside the trench 13 is exposed. The etching amount at this time is
- a SiO film 41 having a thickness of about 0.2 m is formed by a known method such as a CVD method. And this way, a SiO film 41 having a thickness of about 0.2 m is formed by a known method such as a CVD method. And this way, a SiO film 41 having a thickness of about 0.2 m is formed by a known method such as a CVD method. And this way, a SiO film 41 having a thickness of about 0.2 m is formed by a known method such as a CVD method. And this way
- the SiO film 41 and SiO film 14 formed in this way are used until the lower end of the conductive plug 15 is exposed.
- the SiO film 14 is selectively removed together with the SiO film 41, and FIG.
- the lower end of the conductive plug 15 is exposed.
- the remaining SiO film 41 is formed on each chip.
- 51a and 52a covers the portion other than the conductive plug 15 on the back surface of the substrate 11 and the exposed surface of the adhesive 53, which are flat, in other words, the first consisting of the chips 51a and 52a.
- the entire back surface of the semiconductor circuit layer la ′ is flat.
- microbump electrode 42 is formed on each exposed lower end of each conductive plug 15 by a known method.
- These micro bump electrodes 42 can be formed by the same method as described in the first embodiment.
- two Si forming the second semiconductor circuit layer 2 ′ are formed at predetermined positions on the back surfaces of the chips 51a and 52a forming the first semiconductor circuit layer la ′.
- Secure chips 61 and 62 respectively.
- the Si chips 61 and 62 have almost the same configuration as the Si chips 51 and 52, respectively, the corresponding elements are denoted by the same reference numerals as those of the Si chips 51 and 52. Description is omitted.
- the Si chips 61 and 62 may be configured differently from the Si chips 51 and 52! /.
- the gap between the first and second semiconductor circuit layers la ′ and 2 ′ is filled with an electrically insulating adhesive 44 by an injection method or the like. And let it harden. At this time, the thickness of the adhesive 44 is sufficiently increased in order to increase the adhesive strength by the adhesive 44 and to fill the gap between the Si chips 61 and 62. In this way, as shown in FIG. 12 (h), parts other than the back side of the Si chips 61 and 62 are buried in the adhesive 44. This completes the electrical and mechanical connection between the Si chips 5 la and 52a and the Si chips 61 and 62 forming the first and second semiconductor circuit layers la ′ and 2 ′.
- the adhesive 44 polyimide resin, epoxy resin or the like can be used.
- the distance from the lower end of each trench 13 inside the Si substrate 11 is about 1 m, for example, by mechanical polishing and CMP.
- the substrate 11 is thinned until it becomes.
- the Si chips 61 and 62 thus reduced in thickness are hereinafter referred to as Si chips 6 la and 62a, respectively.
- the second semiconductor circuit layer 2 ′ thus polished and thinned is denoted by 2a ′.
- the lower part of the substrate 11 of the Si chips 61a and 62a forming the second semiconductor circuit layer 2a ′ is formed by the same method as that of the Si chips 51a and 52a forming the first semiconductor circuit layer la ′.
- a microbump electrode 42 is formed on the lower end of each conductive plug 15 that is removed and exposed.
- the configuration of the second semiconductor circuit layer 2a ′ is as shown in FIG. 13 (i).
- the second semiconductor circuit layer 2a ′ i.e., Si chips 61a and 62a
- the first semiconductor circuit layer la ′ i.e., Si chips 51a and 52a
- the semiconductor device has a two-layer structure including the first and second semiconductor circuit layers la 'and 2a', the back surface of the second semiconductor circuit layer 2a '(ie, the Si chips 61a and 62a) is formed. Formed The microbump electrode 42 thus used is used as a microbump electrode for connecting an external circuit. If the semiconductor device has a third or more semiconductor circuit layers, the third, fourth, fifth,... Semiconductor circuit layers (not shown) may be formed by the same method as described above, if necessary. ) Are stacked and fixed to produce a semiconductor device having a three-dimensional stacked structure.
- the Si chips 51 and 52 constituting the first semiconductor circuit layer 1 ′ are arranged inside the Si substrate 11.
- a plurality of trenches 13 having a predetermined depth, each of which has an inner wall surface covered with an insulating film 14, are formed at a predetermined position of the substrate 11, and the surface side force conductive material of the substrate 11 is placed inside the trench 13.
- the conductive plug 15 is formed by filling.
- a desired semiconductor element here, a MOS transistor
- the microbump electrode 37 electrically connected to the conductive plug 15 on the surface of the multilayer wiring structure 30 is formed. A plurality of are formed. Then, using these micro-bump electrodes 37, Si chips 51 and 52 having the multilayer wiring structure 30 are fixed to predetermined positions on one surface of the support substrate 40. After that, the Si chips 51a and 52a fixed to the support substrate 40 are selectively removed from the back surface side, and the Si chips 51a and 52a are thinned to cover the inner wall surface (exposed surface) of the trench 13 SiO film 14 Si
- micro bump electrodes 42 are formed on the exposed ends of the tips 51a and 52a. The same applies to the second semiconductor circuit layer 2 and the third, fourth, and fifth semiconductor circuit layers.
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.).
- a known process for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.
- the electrical connection between the electrode 37 on the surface of the multilayer wiring structure 30 and the conductive plug 15 formed inside the trench 13 of the chips 51a and 52a and exposed on the back side of the substrate 11 is the multilayer wiring structure.
- the wiring inside the multilayer wiring structure 30 (conducting with the wiring layers 32, 33, and 34) Body 35, 36) and
- the wiring film 20 and the conductive plug 15 form an “embedded wiring” that penetrates the first semiconductor circuit layer la ′ (that is, the chips 51a and 52a) in the stacking direction.
- the formation of the trenches 13 and the filling of the conductive materials into the trenches 13 are performed on the Si substrate 11 of each chip 51, 52, 61, 62.
- the process is performed from the front surface (first main surface) side, and the trench 13 does not penetrate the multilayer wiring structure 30 and the interlayer insulating film 19.
- the formation of the trench 13 and the filling of the conductive material cannot be performed from the back surface (second main surface) side of the substrate 11, or the formation of the trench 13 penetrating the multilayer wiring structure 30 is impossible or difficult.
- This manufacturing method can be suitably applied. In other words, it is possible to deal with restrictions caused by the layout of the first semiconductor circuit layer la ′ and the layout of the wiring in the multilayer wiring structure 30. The same applies to the second semiconductor circuit layer 2a and the subsequent semiconductor circuit layers.
- the first semiconductor circuit layer la ′ (chips 51a and 52a) and the second semiconductor circuit layer 2a ′ (chips 61a and 62a) are sequentially stacked and fixed under the support substrate 40.
- the support substrate 40 may be turned upside down and the first semiconductor circuit layer la ′ and the second semiconductor circuit layer 2a ′ may be stacked and fixed in order on the support substrate 40. Needless to say, it is good.
- the three-dimensional stacked semiconductor device having the above-described configuration can be used as it is, and is divided into a plurality of parts by dicing in a direction orthogonal to the support substrate 40 (stacking direction). May be used. In this case, each part formed by the division becomes a three-dimensional stacked semiconductor device.
- the first and second semiconductor circuit layers la 'and 2a' may each be composed of a single Si chip (ie, a single chip-like Si substrate or Si member) force!
- FIGS. 14 (a) to 16 (f) show a semiconductor having a three-dimensional laminated structure according to the third embodiment of the present invention. It is a fragmentary sectional view which shows the manufacturing method of a body apparatus.
- the trench and the conductive material filled in the trench have pierced only the Si substrate and not the multilayer wiring structure, but in the third embodiment, This is different from the first and second embodiments in that the trench and the conductive material filled in the trench penetrate not only the Si substrate but also the multilayer wiring structure.
- the description is given here using a Si wafer, it goes without saying that the Si wafer may be replaced with one or more Si chips as in the case of the second embodiment.
- a wafer (Si wafer) 11 made of single crystal SU is prepared as a semiconductor substrate.
- an insulating film 12 is formed on the surface (first main surface) of the wafer 11, and the entire surface is covered with the SiO film 12. The state at this time is as shown in Fig. 14 (a).
- Each MOS transistor includes a pair of source and drain regions 16 formed in the substrate 11 at intervals, and a gate electrode 18 formed on the gate insulating film 12b between the source and drain regions 16. It consists of.
- the gate insulating film 12b is formed of a SiO film formed in a separate process from the SiO film 12.
- the SiO film 12 is selectively removed at the location where the gate insulating film 12b is to be formed, and then modified.
- an interlayer insulating film 19 is formed over the entire surface of the substrate 11 on the insulating film 12, and the MOS transistor and the entire surface exposed from the interlayer insulating film 19 are formed by this interlayer insulating film 19. Cover.
- the interlayer insulating film 19 is formed of a known organic or orientation insulating material cover. Further, the interlayer insulating film 19 is selectively etched to form through holes reaching the desired source / drain regions 16. Next, the conductive material 21 is filled into the through holes corresponding to the source / drain regions 16 of the insulating film 19 by a known method.
- a conductive metal film (not shown) is formed on the insulating film 19 and then the metal film is selectively etched to obtain a patterned metal wiring film 20.
- This metal wiring film 20 In FIG. 15 (c), one wiring portion is electrically connected to the source / drain region 16 via the conductive material 21 filled in the corresponding through hole of the interlayer insulating film 19. Connected with care.
- a multilayer wiring structure 30A is formed on the metal wiring film 20 by a known method.
- This multilayer wiring structure 30A includes an insulating material 31 and three wiring layers 32, 33, 34 embedded in the insulating material 31, and a conductor 35 used mainly for interlayer connection between the wiring layers 32, 33, 34. , 36, and 38.
- the electric conductors 35, 36, and 38 are usually force embedded in via holes formed in the insulating material 31, but are not limited to this.
- the insulating material 31 may also be formed with a single electrically insulating material force, but it is often formed with a laminate force consisting of several layers of different electrically insulating materials. Since the configuration, materials used, and formation method of the multilayer wiring structure 30A are known, a detailed description thereof will be omitted.
- the Si substrate (Si wafer) 11 having a MOS transistor and the multilayer wiring structure 30A formed on the substrate 11 constitute a first semiconductor circuit layer 1A.
- the multilayer wiring structure 30A, the metal wiring film 20, the interlayer insulating film 19, the SiO film 12, and the Si substrate 11 are selectively etched in order from the surface side of the multilayer wiring structure 30A by a known method.
- a plurality of trenches 13 having a predetermined depth are formed at predetermined positions on the Si substrate 11 as shown in FIG.
- These trenches 13 penetrate the multilayer wiring structure 30A in the vertical direction (thickness direction) and deeply reach the inside of the substrate 11 (the trench 13 is usually about 30 to 50 111 from the surface of the substrate 11, Force that penetrates into board 11) It does not penetrate board 11.
- These trenches 13 are respectively arranged at positions where buried wirings (conductor plugs) are to be formed. Thereafter, the exposed surface (inner wall surface) of the trench 13 is covered with the SiO film 14 by a known method (for example, CVD method). This SiO film 14 also covers the surface of the multilayer wiring structure 30A.
- An appropriate conductive material is selectively embedded from the surface side of the structure 30A by a known method.
- the method described in the first embodiment can be used. That is, after depositing a film of a conductive material over the entire surface of the multilayer wiring structure 30A by a CVD method, it is then performed by an etch back method or by a mechanical polishing method and CMP (Chemical Mechanical Polishing) (chemical mechanical polishing). A portion of the conductive material film outside the trenches 13 is selectively removed by a combination of polishing methods. In this way, the conductive plug 15 is obtained inside each trench 13.
- a semiconductor such as silicon or a metal such as tungsten (W) is used. The state at this time is as shown in FIG.
- each conductive plug 15 is exposed on the surface of the multilayer wiring structure 3OA. Thereafter, as shown in FIG. 16 (e), a microbump electrode 37 is formed on each upper end of the conductive plug 15 where the surface force of the multilayer wiring structure 30A is also exposed by a known method.
- the first semiconductor circuit layer 1A is formed on the support substrate 40 made of a Si wafer. Let it stick. In other words, the first semiconductor circuit layer 1A and the support substrate 40 are mechanically connected. The first semiconductor circuit layer 1A is also electrically connected to the semiconductor circuit formed in the support substrate 40 made of a Si wafer by the microbump electrode 37.
- the gap 39 is filled with an electrically insulating adhesive 39 and cured.
- the adhesive 39 polyimide resin or epoxy resin can be used.
- the first semiconductor circuit layer 1A is mechanically and electrically connected to the support substrate 40 by the adhesive 39 and the micro bump electrode 37.
- the state at this time is as shown in Fig. 16 (e).
- the microbump electrode 37 includes the first semiconductor circuit layer 1A and the support substrate. Will be used only for mechanical connection between 40.
- the back surface of the Si substrate 11 (the second substrate) is held by the mechanical polishing method and the CMP method while holding the first semiconductor circuit layer 1A using the support substrate 40.
- the main surface) side is polished until the distance of the lower end force of each inner trench 13 becomes, for example, about 1 ⁇ m, and the thickness of the entire substrate 11 is reduced.
- the first semiconductor circuit layer 1A thus polished and thinned is denoted by lAa hereinafter.
- the back side of the thinned substrate 11 is selectively removed by isotropic etching such as wet etching or plasma etching, and the The SiO film 14 inside the niche 13 is exposed.
- isotropic etching such as wet etching or plasma etching
- the lower end of the conductive plug 15 inside the trench 13 is adjusted so that the back surface force of the substrate 11 protrudes by a predetermined distance.
- a SiO film 41 having a thickness of about 0.2 m is formed by a known method such as a CVD method. Then this
- the SiO film 41 formed in this way is polished by the CMP method.
- the remaining SiO film 41 is formed by the conductive plug 15 on the back surface of the semiconductor substrate 11.
- the entire back surface of the first semiconductor circuit layer lAa is flat.
- a microbump electrode 42 is formed on each exposed lower end of each conductive plug 15 by a known method.
- the method of forming these micro bump electrodes 42 is the same as that described in the first embodiment.
- a second semiconductor circuit layer (not shown) is fixed to the back surface of the first semiconductor circuit layer lAa in the same manner as described in the first embodiment.
- the microbump electrodes 42 formed on the back surface of the second semiconductor circuit layer include: Used as a micro bump electrode for external circuit connection. If the semiconductor device has a third or more semiconductor circuit layers, the third, fourth, fifth,... Semiconductor circuit layers (not shown) can be obtained by the same method as described above. The semiconductor device having a three-dimensional stacked structure is manufactured.
- a predetermined position on the surface of the Si substrate (Si wafer) 11 constituting the first semiconductor circuit layer 1A is set.
- Surface-side force A desired semiconductor element here, a MOS transistor
- a multilayer wiring structure 30A is formed thereon via an interlayer insulating film 19.
- the multilayer wiring structure 30A and the interlayer insulating film 19 were penetrated to reach the inside of the substrate 11, and the inner wall surface was covered with the SiO film 14. Training at a certain depth
- a plurality of punches 13 are formed. These trenches 13 should not overlap with MOS transistors It is formed.
- a conductive material is filled into each trench 13 from the surface side of the multilayer wiring structure 30A to form a conductive plug 15.
- micro bump electrodes 37 are respectively formed on the upper ends of these conductive plugs 15 (that is, the end on the multilayer wiring structure 3 OA side).
- the substrate 11 having the multilayer wiring structure 30A is fixed to the support substrate 40. Thereafter, the substrate 11 fixed to the support substrate 40 is selectively removed from the back surface side and thinned to expose the SiO film 14 to the back surface side of the substrate 11.
- the SiO film 14 exposed on the back side of the substrate 11 is selectively removed.
- the conductive plug 15 is exposed on the back side of the substrate 11.
- a micro bump electrode 42 is formed on the end of the exposed conductive plug 15. The same applies to the second semiconductor circuit layer and the subsequent semiconductor circuit layers (not shown).
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.). Further, since the micro bump electrode 37 on the surface side of the multilayer wiring structure 30A is directly electrically connected to the conductive plug 15 exposed on the same surface side, the conductive plug 15 inside the trench 13 is provided. As such, it becomes an “embedded wiring” that penetrates the first semiconductor circuit layer lAa in the stacking direction.
- the support substrate 40 and the first semiconductor circuit layer lAa (or the first semiconductor circuit layer lAa and The electrical connection in the stacking direction between the second semiconductor circuit layers and between adjacent semiconductor circuit layers after the second semiconductor circuit layer can be easily realized.
- the method for manufacturing a semiconductor device in the method for manufacturing a semiconductor device according to the third embodiment of the present invention, formation of the trench 13 and filling of the conductive material are performed on the surface side of the multilayer wiring structure 30A (ie, the Si substrate 11). At the same time, the trench 13 penetrates the multilayer wiring structure 30A and the interlayer insulating film 19. Therefore, when the formation of the trench 13 and the filling of the conductive material cannot be performed from the back surface (second main surface) side of the substrate 11 or when the trench 13 penetrating the multilayer wiring structure 30A can be formed, This manufacturing method can be suitably applied.
- FIGS. 17 (a) to 20 (h) are partial cross-sectional views showing a method for manufacturing a semiconductor device having a three-dimensional multilayer structure according to the fourth embodiment of the present invention.
- the filling force of the conductive material into the trench and the inside thereof is also the surface side force of the Si substrate 11 (multilayer wiring structure 30, 30A).
- the trench and the inside thereof are filled with the conductive material from the back side of the Si substrate 11.
- Si wafer is used for explanation, but as in the case of the second embodiment, it is needless to say that one Si wafer or two or more Si chips may be replaced! /.
- a Si wafer 11 is prepared as a semiconductor substrate.
- the SiO film 12 is formed on the surface (first main surface) of the wafer 11 and the entire surface is made S.
- Each MOS transistor includes a pair of source and drain regions 16 formed in the substrate 11 at intervals, and a gate electrode 18 formed on the gate insulating film 12b between the source and drain regions 16. It consists of.
- the gate insulating film 12b is formed of a SiO film formed in a separate process from the SiO film 12.
- the SiO film 12 is selectively removed at the location where the gate insulating film 12b is to be formed, and then modified.
- an interlayer insulating film 19 is formed over the entire surface of the substrate 11 on the SiO film 12, and this interlayer
- the insulating film 19 covers the MOS transistor and the entire surface exposed from them. Further, the interlayer insulating film 19 is selectively etched to form through holes that reach the desired source / drain regions 16. Next, a conductive material 21 is filled into the through hole corresponding to the source / drain region 16 of the interlayer insulating film 19 by a known method. Thereafter, a conductive metal film (not shown) is formed on the interlayer insulating film 19 and then the metal film is selectively etched to obtain a patterned metal wiring film 20. The metal wiring film 20 is divided into several wiring parts. In FIG. 17A, one wiring part is interposed through a conductive material 21 filled in the corresponding through hole of the interlayer insulating film 19. Source and drain region 16 electrically It is connected to the.
- a multilayer wiring structure 30B is formed on the metal wiring film 20 by a known method.
- This multilayer wiring structure 30B includes an insulating material 31 and three wiring layers 32, 33, 34 embedded in the insulating material 31, and a conductor 35 used mainly for interlayer connection between the wiring layers 32, 33, 34. 36. Since the configuration, materials used, and formation method of the multilayer wiring structure 30B are the same as those of the multilayer wiring structure 30A of the first embodiment, detailed description thereof will be omitted.
- a plurality of microbump electrodes 37 are formed on the surface of the multilayer wiring structure 30 by a known method. As will be described later, these micro bump electrodes 37 are electrically connected to the conductive plug 15 inside the trench 13 via the wiring inside the multilayer wiring structure 30B and the metal wiring film 20. The state at this time is as shown in FIG.
- the Si substrate (Si wafer) 11 having the MOS transistor and the multilayer wiring structure 30B formed on the substrate 11 constitute the first semiconductor circuit layer 1B.
- the first semiconductor circuit layer 1B is fixed to the support substrate 40 (mechanical). Connect to).
- the support substrate 40 for example, a glass, a single crystal Si wafer or the like can be suitably used, but here, a Si wafer is used.
- the first semiconductor circuit layer 1B is also electrically connected to the semiconductor circuit formed in the support substrate 40 made of a Si wafer by the microbump electrode 37.
- the gap 39 is filled with an electrically insulating adhesive 39 and cured.
- the adhesive 39 polyimide resin or epoxy resin can be used.
- the first semiconductor circuit layer 1B is mechanically and electrically connected to the support substrate 40 by the adhesive 39 and the micro bump electrode 37. The state at this time is as shown in Fig. 17 (b).
- the microbump electrode 37 includes the first semiconductor circuit layer 1B and the support substrate. Will be used only for mechanical connection between 40.
- the mechanical polishing is performed while holding the first semiconductor circuit layer 1B using the support substrate 40.
- the back surface (second main surface) side of the Si substrate 11 is polished by the method and the CMP method, and the entire thickness of the substrate 11 is reduced to a predetermined value.
- the first semiconductor circuit layer 1B thus polished and thinned is denoted by IBa hereinafter.
- the state at this time is as shown in FIG.
- a plurality of trenches 13a are formed from the back side of the substrate 11 by anisotropic etching such as the above. That is, the SiO film 45 on the back surface of the substrate 11 is selectively removed by using a mask (not shown) having a plurality of through holes at a position where an embedded wiring (conductor plug) is to be formed.
- a plurality of openings are formed in the SiO film 45 where the buried wiring (conductor plug) is to be formed.
- the Si substrate 11 is selectively selected through the opening of the SiO film 45.
- the surface of the substrate 11 is formed through the opening of the SiO film 45 and the trench 13a.
- the SiO film 12 on the surface side is selectively removed, and a plurality of openings are formed in the SiO film 12. This way
- the bottom portions (lower ends) of the plurality of trenches 13a on which the rear surface side force of the substrate 11 is also formed are all exposed downward through the corresponding openings of the SiO film 45.
- the top (upper end) is also exposed upward through the corresponding opening of the SiO film 12.
- the lower portion of the metal wiring 20 is exposed below the substrate 11 (inside the trench 13a) through the trench 13a.
- the SiO film 14 is deposited from the back side of the substrate 11 by a known method (for example, CVD method).
- the back side force SiO film 14 of the substrate 11 is selectively removed by anisotropic etching.
- the etching amount is adjusted so that the SiO film 14 on the exposed surface of the metal wiring film 20 and the exposed surface of the interlayer insulating film 19 is completely removed inside each trench 13a.
- the SiO film 14 is formed only on the inner wall side surface of the trench 13a.
- An appropriate conductive material is embedded inside by a known method.
- the SiO film 45 After depositing a conductive material film over the entire back surface of the Si substrate (wafer) 11 by the CVD method, the conductive material film SiO is then etched by the etch back method, mechanical polishing method or CMP method.
- the conductive material By selectively removing a portion on the film 45, the conductive material is left only in the trench 13. By doing so, the conductive material is embedded in each trench 13a.
- the conductive material used here include a semiconductor such as silicon and a metal such as tantasten (W).
- the lower end of each conductive plug 15 is in the same plane as the exposed surface of the SiO film 41, and the substrate 11, that is, the first semiconductor circuit.
- the entire back surface of the layer IBa is flattened, and the lower end of each conductive plug 15 is exposed.
- a SiO film 41 having a thickness of about 0.2 m is formed on the entire back surface of the substrate 11 by a CVD method or the like.
- the entire back surface of the first semiconductor circuit layer IBa is covered with this SiO film 41.
- the SiO film 41 thus formed is selectively etched to form a plurality of through holes.
- each conductive plug 15 inside the trench 13 is connected to the SiO film 41.
- micro bump electrodes 42 are formed at the lower ends of the exposed conductive plugs 15 through the through holes of the SiO film 41, respectively.
- each micro bump electrode 42 Since the height of the bump electrode 42 is larger than the thickness of the SiO film 41, each micro bump electrode 42 is larger than the thickness of the SiO film 41, each micro bump electrode 42
- the second semiconductor circuit layer (not shown) is applied to the micro bump electrode 42 (and the micro bump electrode 43) in the same manner as described in the first embodiment. ) To fix.
- the micro-bump electrode 42 formed on the back surface of the second semiconductor circuit layer includes: Used as a micro bump electrode for external circuit connection. If the semiconductor device has a third or more semiconductor circuit layers, the third, fourth, fifth,... Semiconductor circuit layers (not shown) can be obtained by the same method as described above. The semiconductor device having a three-dimensional stacked structure is manufactured.
- a desired MOS transistor is also formed on the surface (first main surface) to form a desired circuit.
- a multilayer wiring structure 30B is formed through the interlayer insulating film 19.
- the micro bump electrode 37 electrically connected to the wiring in the multilayer wiring structure 30B is formed on the surface of the multilayer wiring structure 30B, and then, using these micro bump electrodes 37, the multilayer wiring is formed.
- the substrate 11 having the structure 30B is fixed to the support substrate 40.
- a plurality of trenches 13a penetrating from the back surface (second main surface) side of the substrate 11 toward the front surface (first main surface) are formed.
- the inside of the trench 13a is filled with a conductive material from the back side of the substrate 11, and the conductive plug 15 electrically connected to the wiring in the multilayer wiring structure 30B is obtained. Yes.
- All of these steps can be performed using a known process (for example, a CVD method, an isotropic etching method, a mechanical polishing method, a CMP method, etc.).
- the trench 13a and the conductive plug 15 penetrate the substrate 11, and are electrically connected to the wiring in the multilayer wiring structure 30B through the metal wiring film 20 on the surface of the substrate 11.
- the wiring in the multilayer wiring structure 30B is electrically connected to the micro bump electrode 37 on the surface of the multilayer wiring structure 30B.
- the conductive plug 15, the metal wiring film 20, and the wiring in the multilayer wiring structure 30B in the trench 13a become buried wiring that penetrates the first semiconductor circuit layer IBa in the stacking direction (thickness direction).
- the support substrate 40 and the first semiconductor circuit layer IBa (or the first semiconductor circuit layer IBa and It is possible to easily realize the electrical connection in the stacking direction between the second semiconductor circuit layers and further between adjacent semiconductor circuit layers after the second semiconductor circuit layer.
- FIGS. 21A to 21C are partial cross-sectional views illustrating a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the fifth embodiment of the present invention.
- the fifth embodiment corresponds to the i-th modification of the first embodiment described above.
- the order of forming the MOS transistor and forming the trench and the conductive plug is the same as in the first embodiment. Is reversed.
- the formation of the trench and the conductive plug is performed first, and then the MOS transistor is also formed.
- the formation of the MOS transistor is performed first.
- Both embodiments differ in that trenches and conductive plugs are formed. Except for this point, both embodiments are the same.
- the SiO film 12 is formed on the surface (first main surface) of the Si wafer 11 as the semiconductor substrate, and the entire surface is covered with the SiO film 12. Next, the surface of the substrate 11
- MOS transistors are formed at a position where the trench 13 is not formed, in other words, at a position not overlapping with the trench 13 on the surface of the substrate 11 to obtain a desired circuit.
- Each MOS transistor includes a pair of source and drain regions 16 formed inside the substrate 11 at an interval, a gate insulating film 12b formed between the source and drain regions 16, and a gate insulating film 12b. And a gate electrode 18 formed thereon.
- Gate insulating film 12b is made of SiO film 12
- the gate insulating film 12b is formed from a SiO film formed in a separate process. That is, the gate insulating film 12b is
- the SiO film 12 is selectively removed at the place to be formed, and then the SiO film is again formed at the same place.
- the Si substrate 11 and the SiO film 1 are formed by a known method.
- the surface 2 of the substrate 11 is selectively etched to form a plurality of trenches 13 having a predetermined depth at predetermined positions on the substrate 11. Then, after covering the inner wall surfaces of the trenches 13 with the SiO film 14 by the thermal oxidation method, the conductive material is introduced into the trenches 13 from the surface side of the substrate 11.
- the semiconductor device manufacturing method according to the fifth embodiment of the present invention is the same as the above-described first embodiment except that the order of forming the MOS transistor and the trench and the conductive plug is reversed. It is clear that the same effect as in the first embodiment can be obtained.
- FIG. 22 is a partial cross-sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the sixth embodiment of the present invention.
- the sixth embodiment corresponds to the second modification of the first embodiment described above.
- the microbump electrode formed at the lower end of the conductive plug 15 inside the trench 13 is used.
- a micro bump electrode 42a is formed directly on the end of the conductive plug 15 by an electroless plating method or a selective CVD method. Other points are the same as in the case of the first embodiment.
- the metal film is made conductive. Only the end face of the plug 15 can be selectively grown. That is, the micro bump electrode 42a made of the metal film is formed on the lower end surface of each conductive plug 15 in a self-aligning manner.
- the conductive material for the conductive plug 15 suitable for the electroless plating method includes Ni, Cu, Sn, Ag, Au, Ti, Pt or Ta, or an alloy composed of two or more thereof or an alloy thereof. Examples include a laminated film composed of two or more.
- the conductive material for the conductive plug 15 suitable for the selective CVD method Cu, Ni, W, Ti, Ta, TiN, TaN, etc., or an alloy with two or more of them, or two of them.
- Examples of such a laminated film include the above.
- FIG. 23 (a) to FIG. 25 (e) are partial cross-sectional views showing a method for manufacturing a semiconductor device having a three-dimensional multilayer structure according to a seventh embodiment of the present invention.
- the seventh embodiment corresponds to the third modification of the first embodiment described above, and the microbump electrodes 42 are formed by a method different from that in the first embodiment. That is, after performing the steps from FIG. 1 (a) to FIG. 3 (g) in the same manner as in the first embodiment, the subsequent steps are the steps shown in FIG. 23 (b) to FIG. 25 (e). Are executed in order.
- an SiO film 41 is formed.
- this state force is immediately applied to the SiO film.
- the lower end of the conductive plug 15 inside the trench 13 is exposed.
- a flat film is further formed on the SiO film 41 thus formed.
- the resist film (flat film) 60 is selectively etched by the etch back method, and the SiO film 41 is resisted at the lower end of each conductive plug 15 as shown in FIG.
- the resist film 60 is formed on the SiO film 41 with a conductive plastic layer.
- the upper SiO film 41 is selectively removed, and the conductive braid in the trench 13 is removed as shown in FIG.
- each conductive plug 15 is connected to the SiO film 41.
- the entire back surface of the substrate 11, that is, the first semiconductor circuit layer la is flat.
- micro bump electrodes 42 are formed on the lower ends of the exposed conductive plugs 15 respectively.
- the method for forming these micro bump electrodes 42 the one used in the first embodiment or the sixth embodiment described above can be used. Remaining The existing SiO film 41 and resist film 60 are electrically connected to the second semiconductor circuit layer (not shown).
- the remaining resist film 60 may be removed in the state shown in FIG. 24 (d). In this case, the remaining SiO film 41 force is electrically connected to the second semiconductor circuit layer (not shown).
- the removal of the resist film 60 creates a gap in the portion, but the gap is filled with an adhesive when fixing the first semiconductor circuit layer la to the second semiconductor circuit layer (not shown). There is no hindrance.
- FIG. 26 is a partial sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the eighth embodiment of the present invention, and corresponds to FIG. 2 (d).
- the eighth embodiment corresponds to the fourth modification of the first embodiment described above, and is different only in that the first semiconductor circuit layer does not have the multilayer wiring structure 30. Other than that, it is the same as the manufacturing method of the first embodiment.
- the first semiconductor circuit layer has a multilayer wiring structure, but the present invention is not limited to such a configuration.
- the eighth embodiment is shown as an example having no multilayer wiring structure.
- the eighth embodiment will be described as a modified example of the first embodiment, but it can be applied as a modified example of any of the second to seventh embodiments.
- the first semiconductor circuit layer 1 ′′ does not have the multilayer wiring structure 30.
- a patterned metal wiring film 20 on an interlayer insulating film 19 (this is a conductive film for electrically connecting a MOS transistor and a conductive plug 15 and is not included in the multilayer wiring structure 30.
- the metal wiring film 20 is covered with another interlayer insulating film 19 a formed on the interlayer insulating film 19.
- the surface of the interlayer insulating film 19a is flat, and a plurality of micro bump electrodes 37 are formed on the surface. Each microbump electrode 37 is connected to a corresponding portion of the metal wiring film 20 via a conductor 35a.
- the surface of the substrate 11 is covered with two interlayer insulating films 19 and 19a.
- FIG. 26 It goes without saying that the configuration of FIG. 26 can also be applied to the second semiconductor circuit layer or a semiconductor circuit layer after that! /.
- the semiconductor circuit layer constituting one of the plurality of semiconductor circuit layers of the three-dimensional stacked semiconductor device is formed on the semiconductor substrate and the surface or inside of the semiconductor substrate. It suffices to have a single element or circuit, and it may or may not have a single-layer or multilayer wiring structure.
- the microbump electrode is omitted if the end of the conductive material filled in the force trench using the microbump electrode can function as the microbump electrode. Can do.
- the force for bonding the microbump electrodes of adjacent semiconductor circuit layers to each other by welding is not limited to this.
- bonding by welding is impossible or difficult.
- the micro bump electrodes may be bonded to each other using a bonding metal (for example, a solder alloy).
- the present invention is not limited to this.
- the present invention when the present invention is applied to the second semiconductor circuit layer, the second semiconductor circuit layer is fixed to the first semiconductor circuit layer adjacent thereto.
- each of the semiconductor circuit layers is formed by a single semiconductor wafer and the case where each of the semiconductor circuit layers is formed by a plurality of semiconductor chips are described. Is not limited to these.
- at least one semiconductor circuit layer may be formed by a single semiconductor wafer, and each of the remaining semiconductor circuit layers may be formed by a plurality of semiconductor chips.
- a semiconductor circuit layer is formed by a plurality of semiconductor chips. In such a case, all of the semiconductor chips do not have to incorporate an electronic circuit. That is, some semiconductor chips contain electronic circuits and may be “dummy chips” (or built-in electronic circuits that are not used).
- the semiconductor wafer contains an electronic circuit.
- V, N, (or built-in electronic circuit, used) may include “dummy area”.
- FIG. 1 is a partial cross-sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to a first embodiment of the present invention for each step.
- FIG. 2 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 3 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 5 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 6 is a partial cross-sectional view showing the method of manufacturing the semiconductor device having a three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 7 is a partial cross-sectional view showing the method of manufacturing the semiconductor device having a three-dimensional stacked structure according to the first embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 8 is a partial cross-sectional view showing a method of manufacturing a semiconductor device having a three-dimensional stacked structure according to a second embodiment of the present invention for each step.
- FIG. 9 is a partial cross-sectional view showing the method of manufacturing a semiconductor device having a three-dimensional stacked structure according to the second embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 10 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the second embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 11 shows a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to a second embodiment of the present invention.
- FIG. 10 is a partial cross-sectional view showing each process, which is continued from FIG.
- FIG. 12 A partial cross-sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the second embodiment of the present invention for each step, which is a continuation of FIG.
- FIG. 13 A partial cross-sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to the second embodiment of the present invention for each step, which is a continuation of FIG.
- FIG. 15 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the third embodiment of the present invention for each process, and is a continuation of FIG.
- FIG. 16 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the third embodiment of the present invention for each step, and is a continuation of FIG.
- FIG. 17 is a partial cross-sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to a fourth embodiment of the present invention for each step.
- FIG. 18 is a partial cross-sectional view showing the method of manufacturing the semiconductor device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each process, and is a continuation of FIG.
- FIG. 19 is a partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each process, and is a continuation of FIG.
- FIG. 19 is a partial cross-sectional view showing the method of manufacturing the semiconductor device having a three-dimensional stacked structure according to the fourth embodiment of the present invention for each process, and is a continuation of FIG.
- FIG. 22 is a partial cross-sectional view showing a method for manufacturing a semiconductor device having a three-dimensional stacked structure according to a sixth embodiment of the present invention for each step.
- FIG. 24 A partial cross-sectional view showing the method for manufacturing the semiconductor device having a three-dimensional stacked structure according to the seventh embodiment of the invention for each step, which is a continuation of FIG.
- FIG. 24 is a partial cross-sectional view showing each process, which is continued from FIG.
- FIG. 26 is a partial cross-sectional view showing the method of manufacturing the semiconductor device having a three-dimensional stacked structure according to the eighth embodiment of the invention.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2005800355633A CN101048868B (zh) | 2004-08-20 | 2005-08-19 | 具有三维层叠结构的半导体器件的制造方法 |
US11/573,976 US7906363B2 (en) | 2004-08-20 | 2005-08-19 | Method of fabricating semiconductor device having three-dimensional stacked structure |
JP2006531871A JP5354765B2 (ja) | 2004-08-20 | 2005-08-19 | 三次元積層構造を持つ半導体装置の製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004240944 | 2004-08-20 | ||
JP2004-240944 | 2004-08-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006019156A1 true WO2006019156A1 (ja) | 2006-02-23 |
Family
ID=35907539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/015133 WO2006019156A1 (ja) | 2004-08-20 | 2005-08-19 | 三次元積層構造を持つ半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7906363B2 (ja) |
JP (2) | JP5354765B2 (ja) |
CN (3) | CN101714512B (ja) |
TW (1) | TWI427700B (ja) |
WO (1) | WO2006019156A1 (ja) |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1739747A2 (en) * | 2005-06-30 | 2007-01-03 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
JP2007311385A (ja) * | 2006-05-16 | 2007-11-29 | Sony Corp | 半導体装置の製造方法および半導体装置 |
JP2008270354A (ja) * | 2007-04-17 | 2008-11-06 | Applied Materials Inc | 三次元半導体デバイスの製造方法、基板生産物の製造方法、基板生産物、及び三次元半導体デバイス |
WO2008157001A1 (en) * | 2007-06-15 | 2008-12-24 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
KR100884986B1 (ko) | 2007-07-26 | 2009-02-23 | 주식회사 동부하이텍 | 반도체 소자와 그의 제조방법 |
WO2009115449A1 (en) * | 2008-03-19 | 2009-09-24 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method for fabricating through-substrate vias |
JP2010510664A (ja) * | 2006-11-21 | 2010-04-02 | フリースケール セミコンダクター インコーポレイテッド | ダイの裏面に接点を形成する方法 |
JP2010123696A (ja) * | 2008-11-18 | 2010-06-03 | Nikon Corp | 積層半導体装置及び積層半導体装置の製造方法 |
US7875552B2 (en) | 2008-06-10 | 2011-01-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby |
JP2011507283A (ja) * | 2007-12-20 | 2011-03-03 | モサイド・テクノロジーズ・インコーポレーテッド | 直列接続された集積回路を積層する方法およびその方法で作られたマルチチップデバイス |
JP2011129902A (ja) * | 2009-12-16 | 2011-06-30 | Samsung Electronics Co Ltd | イメージセンサーモジュール、その製造方法、及びそれを含むイメージ処理システム |
JP2011523203A (ja) * | 2008-05-06 | 2011-08-04 | ガウサム ヴィスワナダム, | 相互接続を伴うウェハレベルインテグレーションモジュール |
KR20110106915A (ko) * | 2009-01-13 | 2011-09-29 | 인터내셔널 비지네스 머신즈 코포레이션 | 쓰루-실리콘 비아들을 노출 및 접촉시키는 고-수율 방법 |
JP2011530812A (ja) * | 2008-08-08 | 2011-12-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | シリコン貫通ビアおよびこれを製作する方法 |
JP2012520568A (ja) * | 2009-03-12 | 2012-09-06 | マイクロン テクノロジー, インク. | マスクを使用せずに導電性ビアに対して裏面位置合わせを行うことによる半導体構成部品の製造方法 |
JP2012175067A (ja) * | 2011-02-24 | 2012-09-10 | Sony Corp | 撮像素子、製造方法、および電子機器 |
JP2012522398A (ja) * | 2009-03-30 | 2012-09-20 | メギカ・コーポレイション | 上部ポストパッシベーション技術および底部構造技術を使用する集積回路チップ |
JP2013175786A (ja) * | 2006-12-29 | 2013-09-05 | Cufer Asset Ltd Llc | スルーチップ接続を有するフロントエンドプロセス済ウェハ |
JP2013197470A (ja) * | 2012-03-22 | 2013-09-30 | Fujitsu Ltd | 貫通電極の形成方法 |
JP2014138037A (ja) * | 2013-01-15 | 2014-07-28 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
US8846445B2 (en) | 2005-06-14 | 2014-09-30 | Cufer Asset Ltd. L.L.C. | Inverse chip connector |
KR20140143169A (ko) * | 2012-03-12 | 2014-12-15 | 마이크론 테크놀로지, 인크 | 복수의 전기 전도성 포스트를 평탄화시키는 반도체 구조물 및 방법 |
JP2016048780A (ja) * | 2010-04-12 | 2016-04-07 | クアルコム,インコーポレイテッド | 積層集積回路のための二面の相互接続されたcmos |
JP2017204510A (ja) * | 2016-05-09 | 2017-11-16 | キヤノン株式会社 | 光電変換装置の製造方法 |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7880278B2 (en) * | 2006-05-16 | 2011-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having stress tuning layer |
US7867878B2 (en) * | 2007-09-21 | 2011-01-11 | Infineon Technologies Ag | Stacked semiconductor chips |
JP4835631B2 (ja) * | 2008-04-21 | 2011-12-14 | ソニー株式会社 | 固体撮像装置及び電子機器の製造方法 |
JP5479703B2 (ja) * | 2008-10-07 | 2014-04-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR20100040455A (ko) * | 2008-10-10 | 2010-04-20 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US8513119B2 (en) | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US20100171197A1 (en) * | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
TW201034150A (en) * | 2009-03-13 | 2010-09-16 | Advanced Semiconductor Eng | Silicon wafer having interconnection metal |
US8531015B2 (en) * | 2009-03-26 | 2013-09-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming a thin wafer without a carrier |
US8503186B2 (en) | 2009-07-30 | 2013-08-06 | Megica Corporation | System-in packages |
US8791549B2 (en) | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
JP2011086709A (ja) * | 2009-10-14 | 2011-04-28 | Toshiba Corp | 固体撮像装置及びその製造方法 |
US8264065B2 (en) * | 2009-10-23 | 2012-09-11 | Synopsys, Inc. | ESD/antenna diodes for through-silicon vias |
IT1398204B1 (it) | 2010-02-16 | 2013-02-14 | St Microelectronics Srl | Sistema e metodo per eseguire il test elettrico di vie passanti nel silicio (tsv - through silicon vias). |
US8466059B2 (en) | 2010-03-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer interconnect structure for stacked dies |
CN102050418B (zh) * | 2010-09-30 | 2013-01-09 | 北京大学 | 一种三维集成结构及其生产方法 |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
US8890047B2 (en) | 2011-09-21 | 2014-11-18 | Aptina Imaging Corporation | Stacked-chip imaging systems |
US9013615B2 (en) | 2011-09-21 | 2015-04-21 | Semiconductor Components Industries, Llc | Image sensor with flexible interconnect capabilities |
US9496255B2 (en) * | 2011-11-16 | 2016-11-15 | Qualcomm Incorporated | Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same |
CN102403270B (zh) * | 2011-12-07 | 2013-09-18 | 南通富士通微电子股份有限公司 | 硅通孔互连结构的形成方法 |
US9185307B2 (en) | 2012-02-21 | 2015-11-10 | Semiconductor Components Industries, Llc | Detecting transient signals using stacked-chip imaging systems |
JP2014053355A (ja) * | 2012-09-05 | 2014-03-20 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
KR20140065282A (ko) * | 2012-11-21 | 2014-05-29 | 삼성전자주식회사 | Tsv를 포함한 반도체 소자, 및 그 반도체 소자를 포함한 반도체 패키지 |
US20140199833A1 (en) * | 2013-01-11 | 2014-07-17 | Applied Materials, Inc. | Methods for performing a via reveal etching process for forming through-silicon vias in a substrate |
US9105701B2 (en) * | 2013-06-10 | 2015-08-11 | Micron Technology, Inc. | Semiconductor devices having compact footprints |
US8860229B1 (en) | 2013-07-16 | 2014-10-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9299640B2 (en) | 2013-07-16 | 2016-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US9087821B2 (en) | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9929050B2 (en) | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
FR3009128A1 (fr) * | 2013-07-25 | 2015-01-30 | Commissariat Energie Atomique | Procede de realisation d'un plot conducteur sur un element conducteur |
KR102209097B1 (ko) * | 2014-02-27 | 2021-01-28 | 삼성전자주식회사 | 이미지 센서 및 이의 제조 방법 |
EP3373329B1 (en) * | 2014-02-28 | 2023-04-05 | LFoundry S.r.l. | Integrated circuit comprising a laterally diffused mos field effect transistor |
JP2016058655A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社ジェイデバイス | 半導体装置の製造方法 |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
JP2016122759A (ja) | 2014-12-25 | 2016-07-07 | キヤノン株式会社 | 貫通配線を有する電子デバイスの作製方法 |
US9917159B2 (en) * | 2015-03-30 | 2018-03-13 | Infineon Technologies Austria Ag | Semiconductor device comprising planar gate and trench field electrode structure |
FR3037720A1 (fr) * | 2015-06-19 | 2016-12-23 | St Microelectronics Crolles 2 Sas | Composant electronique et son procede de fabrication |
US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
CN107851648B (zh) | 2015-07-16 | 2022-08-16 | 索尼半导体解决方案公司 | 固态摄像元件、制造方法和电子装置 |
US9620548B1 (en) | 2015-10-30 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor with wide contact |
JP6478902B2 (ja) * | 2015-12-01 | 2019-03-06 | キヤノン株式会社 | 貫通配線基板の製造方法、及び電子デバイスの製造方法 |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
US9966318B1 (en) * | 2017-01-31 | 2018-05-08 | Stmicroelectronics S.R.L. | System for electrical testing of through silicon vias (TSVs) |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
CN109285825B (zh) * | 2017-07-21 | 2021-02-05 | 联华电子股份有限公司 | 芯片堆叠结构及管芯堆叠结构的制造方法 |
CN107994043A (zh) * | 2017-12-11 | 2018-05-04 | 德淮半导体有限公司 | 晶圆、堆叠式半导体装置及其制造方法 |
KR102467030B1 (ko) * | 2018-01-17 | 2022-11-14 | 삼성전자주식회사 | 반도체 패키지 및 그 패키지를 포함한 반도체 장치 |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
WO2020010265A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US11158606B2 (en) | 2018-07-06 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
EP3841850A4 (en) | 2018-08-22 | 2022-10-26 | Liquid Wire Inc. | STRUCTURES WITH DEFORMABLE LADDERS |
WO2020068042A1 (en) * | 2018-09-24 | 2020-04-02 | Hewlett Packard Enterprise Development Lp | 3d cross-bar array of non-volatile resistive memory devices and an operating method of the same |
US11079282B2 (en) * | 2018-11-28 | 2021-08-03 | Semiconductor Components Industries, Llc | Flexible interconnect sensing devices and related methods |
CN113330557A (zh) | 2019-01-14 | 2021-08-31 | 伊文萨思粘合技术公司 | 键合结构 |
JP7150632B2 (ja) * | 2019-02-13 | 2022-10-11 | キオクシア株式会社 | 半導体装置の製造方法 |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
CN110537259A (zh) * | 2019-06-28 | 2019-12-03 | 长江存储科技有限责任公司 | 三维存储器件中的存储器内计算 |
CN112466350B (zh) | 2019-06-28 | 2023-05-12 | 长江存储科技有限责任公司 | 一种三维3d存储器件以及用于操作三维3d存储器件上的数据处理单元的***及方法 |
JP7391574B2 (ja) | 2019-08-29 | 2023-12-05 | キヤノン株式会社 | 半導体装置の製造方法および半導体装置 |
KR20210071539A (ko) * | 2019-12-06 | 2021-06-16 | 삼성전자주식회사 | 인터포저, 반도체 패키지, 및 인터포저의 제조 방법 |
JP2021197519A (ja) * | 2020-06-17 | 2021-12-27 | 東北マイクロテック株式会社 | 積層型半導体装置及びこれに用いる搭載部品、基体及びバンプ接続体 |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS607149A (ja) * | 1983-06-24 | 1985-01-14 | Nec Corp | 半導体装置の製造方法 |
JPS62272556A (ja) * | 1986-05-20 | 1987-11-26 | Fujitsu Ltd | 三次元半導体集積回路装置及びその製造方法 |
JPH08509842A (ja) * | 1993-05-05 | 1996-10-15 | シーメンス アクチエンゲゼルシヤフト | 縦型チップ接続のための接触構造 |
JPH11238870A (ja) * | 1998-02-20 | 1999-08-31 | Nec Corp | 半導体装置とその製造方法 |
JP2001326325A (ja) * | 2000-05-16 | 2001-11-22 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2001326326A (ja) * | 2000-05-16 | 2001-11-22 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2002289623A (ja) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR900008647B1 (ko) * | 1986-03-20 | 1990-11-26 | 후지쓰 가부시끼가이샤 | 3차원 집적회로와 그의 제조방법 |
US5191405A (en) * | 1988-12-23 | 1993-03-02 | Matsushita Electric Industrial Co., Ltd. | Three-dimensional stacked lsi |
JPH0775270B2 (ja) | 1989-04-20 | 1995-08-09 | 沖電気工業株式会社 | ベアチップの実装構造 |
JP2546407B2 (ja) | 1990-03-27 | 1996-10-23 | 日本電気株式会社 | ハイブリッド素子及びその製造方法 |
JPH04326757A (ja) | 1991-04-26 | 1992-11-16 | Hitachi Ltd | 情報処理装置及びそれを用いた並列計算機システム |
DE4433845A1 (de) * | 1994-09-22 | 1996-03-28 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung |
TW383435B (en) * | 1996-11-01 | 2000-03-01 | Hitachi Chemical Co Ltd | Electronic device |
JP4011695B2 (ja) * | 1996-12-02 | 2007-11-21 | 株式会社東芝 | マルチチップ半導体装置用チップおよびその形成方法 |
JPH10189653A (ja) | 1996-12-26 | 1998-07-21 | Toshiba Corp | 半導体素子およびこの半導体素子を有する回路モジュール |
JPH10294423A (ja) * | 1997-04-17 | 1998-11-04 | Nec Corp | 半導体装置 |
US6265776B1 (en) | 1998-04-27 | 2001-07-24 | Fry's Metals, Inc. | Flip chip with integrated flux and underfill |
JP4042254B2 (ja) | 1999-05-21 | 2008-02-06 | 日産自動車株式会社 | 塗膜付き樹脂部品の再生処理装置 |
JP3339838B2 (ja) | 1999-06-07 | 2002-10-28 | ローム株式会社 | 半導体装置およびその製造方法 |
US6331227B1 (en) * | 1999-12-14 | 2001-12-18 | Epion Corporation | Enhanced etching/smoothing of dielectric surfaces |
JP2001250913A (ja) * | 1999-12-28 | 2001-09-14 | Mitsumasa Koyanagi | 3次元半導体集積回路装置及びその製造方法 |
JP2001274196A (ja) | 2000-03-28 | 2001-10-05 | Rohm Co Ltd | 半導体装置 |
JP2002043252A (ja) * | 2000-07-25 | 2002-02-08 | Toshiba Corp | マルチチップ用半導体チップの製造方法 |
JP2002110902A (ja) | 2000-10-04 | 2002-04-12 | Toshiba Corp | 半導体素子及び半導体装置 |
JP2003124251A (ja) | 2001-10-10 | 2003-04-25 | Matsushita Electric Ind Co Ltd | 半導体装置と実装構造及びその製造方法 |
US6677235B1 (en) * | 2001-12-03 | 2004-01-13 | National Semiconductor Corporation | Silicon die with metal feed through structure |
US6599778B2 (en) * | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
US6642081B1 (en) * | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
JP3835352B2 (ja) * | 2002-06-03 | 2006-10-18 | 株式会社デンソー | バンプの形成方法及びバンプを有する基板と他の基板との接合方法 |
JP2004014657A (ja) | 2002-06-05 | 2004-01-15 | Toshiba Corp | 半導体チップおよびその製造方法、ならびに三次元積層半導体装置 |
JP4439976B2 (ja) * | 2004-03-31 | 2010-03-24 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7273806B2 (en) * | 2004-12-09 | 2007-09-25 | International Business Machines Corporation | Forming of high aspect ratio conductive structure using injection molded solder |
-
2005
- 2005-08-19 TW TW94128547A patent/TWI427700B/zh active
- 2005-08-19 US US11/573,976 patent/US7906363B2/en active Active
- 2005-08-19 CN CN2009102089409A patent/CN101714512B/zh active Active
- 2005-08-19 CN CN201110184865.4A patent/CN102290425B/zh active Active
- 2005-08-19 WO PCT/JP2005/015133 patent/WO2006019156A1/ja active Application Filing
- 2005-08-19 JP JP2006531871A patent/JP5354765B2/ja active Active
- 2005-08-19 CN CN2005800355633A patent/CN101048868B/zh active Active
-
2012
- 2012-03-13 JP JP2012056531A patent/JP2012129551A/ja active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS607149A (ja) * | 1983-06-24 | 1985-01-14 | Nec Corp | 半導体装置の製造方法 |
JPS62272556A (ja) * | 1986-05-20 | 1987-11-26 | Fujitsu Ltd | 三次元半導体集積回路装置及びその製造方法 |
JPH08509842A (ja) * | 1993-05-05 | 1996-10-15 | シーメンス アクチエンゲゼルシヤフト | 縦型チップ接続のための接触構造 |
JPH11238870A (ja) * | 1998-02-20 | 1999-08-31 | Nec Corp | 半導体装置とその製造方法 |
JP2001326325A (ja) * | 2000-05-16 | 2001-11-22 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2001326326A (ja) * | 2000-05-16 | 2001-11-22 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2002289623A (ja) * | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
Cited By (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9754907B2 (en) | 2005-06-14 | 2017-09-05 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
US8846445B2 (en) | 2005-06-14 | 2014-09-30 | Cufer Asset Ltd. L.L.C. | Inverse chip connector |
US9147635B2 (en) | 2005-06-14 | 2015-09-29 | Cufer Asset Ltd. L.L.C. | Contact-based encapsulation |
US9324629B2 (en) | 2005-06-14 | 2016-04-26 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
US10340239B2 (en) | 2005-06-14 | 2019-07-02 | Cufer Asset Ltd. L.L.C | Tooling for coupling multiple electronic chips |
US7843068B2 (en) | 2005-06-30 | 2010-11-30 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
EP1739747A2 (en) * | 2005-06-30 | 2007-01-03 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
US8338289B2 (en) | 2005-06-30 | 2012-12-25 | Shinko Electric Industries Co., Ltd. | Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole |
EP1739747A3 (en) * | 2005-06-30 | 2007-08-01 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
JP2007311385A (ja) * | 2006-05-16 | 2007-11-29 | Sony Corp | 半導体装置の製造方法および半導体装置 |
JP2010510664A (ja) * | 2006-11-21 | 2010-04-02 | フリースケール セミコンダクター インコーポレイテッド | ダイの裏面に接点を形成する方法 |
JP2013175786A (ja) * | 2006-12-29 | 2013-09-05 | Cufer Asset Ltd Llc | スルーチップ接続を有するフロントエンドプロセス済ウェハ |
JP2008270354A (ja) * | 2007-04-17 | 2008-11-06 | Applied Materials Inc | 三次元半導体デバイスの製造方法、基板生産物の製造方法、基板生産物、及び三次元半導体デバイス |
US9209166B2 (en) | 2007-06-15 | 2015-12-08 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
CN101681886B (zh) * | 2007-06-15 | 2014-04-23 | 美光科技公司 | 半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法 |
US8994163B2 (en) | 2007-06-15 | 2015-03-31 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
US8367471B2 (en) | 2007-06-15 | 2013-02-05 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
WO2008157001A1 (en) * | 2007-06-15 | 2008-12-24 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
KR100884986B1 (ko) | 2007-07-26 | 2009-02-23 | 주식회사 동부하이텍 | 반도체 소자와 그의 제조방법 |
JP2011507283A (ja) * | 2007-12-20 | 2011-03-03 | モサイド・テクノロジーズ・インコーポレーテッド | 直列接続された集積回路を積層する方法およびその方法で作られたマルチチップデバイス |
WO2009115449A1 (en) * | 2008-03-19 | 2009-09-24 | Interuniversitair Microelektronica Centrum Vzw (Imec) | Method for fabricating through-substrate vias |
US9646930B2 (en) | 2008-03-19 | 2017-05-09 | Imec | Semiconductor device having through-substrate vias |
US8809188B2 (en) | 2008-03-19 | 2014-08-19 | Imec | Method for fabricating through substrate vias |
JP2011523203A (ja) * | 2008-05-06 | 2011-08-04 | ガウサム ヴィスワナダム, | 相互接続を伴うウェハレベルインテグレーションモジュール |
US8629059B2 (en) | 2008-06-10 | 2014-01-14 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit chips having vertically extended through-substrate vias therein |
US7875552B2 (en) | 2008-06-10 | 2011-01-25 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby |
US9219035B2 (en) | 2008-06-10 | 2015-12-22 | Samsung Electronics Co., Ltd. | Integrated circuit chips having vertically extended through-substrate vias therein |
JP2011530812A (ja) * | 2008-08-08 | 2011-12-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | シリコン貫通ビアおよびこれを製作する方法 |
JP2010123696A (ja) * | 2008-11-18 | 2010-06-03 | Nikon Corp | 積層半導体装置及び積層半導体装置の製造方法 |
KR101589782B1 (ko) * | 2009-01-13 | 2016-02-12 | 인터내셔널 비지네스 머신즈 코포레이션 | 쓰루-실리콘 비아들을 노출 및 접촉시키는 고-수율 방법 |
KR20110106915A (ko) * | 2009-01-13 | 2011-09-29 | 인터내셔널 비지네스 머신즈 코포레이션 | 쓰루-실리콘 비아들을 노출 및 접촉시키는 고-수율 방법 |
JP2012515432A (ja) * | 2009-01-13 | 2012-07-05 | インターナショナル・ビジネス・マシーンズ・コーポレーション | シリコン貫通電極(tsv)を露出させ接触させる高歩留まりの方法 |
US11869809B2 (en) | 2009-03-12 | 2024-01-09 | Micron Technology, Inc. | Semiconductor components having conductive vias with aligned back side conductors |
JP2012520568A (ja) * | 2009-03-12 | 2012-09-06 | マイクロン テクノロジー, インク. | マスクを使用せずに導電性ビアに対して裏面位置合わせを行うことによる半導体構成部品の製造方法 |
JP2012522398A (ja) * | 2009-03-30 | 2012-09-20 | メギカ・コーポレイション | 上部ポストパッシベーション技術および底部構造技術を使用する集積回路チップ |
JP2015073107A (ja) * | 2009-03-30 | 2015-04-16 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | 上部ポストパッシベーション技術および底部構造技術を使用する集積回路チップ |
US9612615B2 (en) | 2009-03-30 | 2017-04-04 | Qualcomm Incorporated | Integrated circuit chip using top post-passivation technology and bottom structure technology |
JP2011129902A (ja) * | 2009-12-16 | 2011-06-30 | Samsung Electronics Co Ltd | イメージセンサーモジュール、その製造方法、及びそれを含むイメージ処理システム |
US9257467B2 (en) | 2009-12-16 | 2016-02-09 | Samsung Electronics Co., Ltd. | Image sensor modules, methods of manufacturing the same, and image processing systems including the image sensor modules |
US10257426B2 (en) | 2009-12-16 | 2019-04-09 | Samsung Electronics Co., Ltd. | Image sensor modules, methods of manufacturing the same, and image processing systems including the image sensor modules |
JP2016048780A (ja) * | 2010-04-12 | 2016-04-07 | クアルコム,インコーポレイテッド | 積層集積回路のための二面の相互接続されたcmos |
JP2012175067A (ja) * | 2011-02-24 | 2012-09-10 | Sony Corp | 撮像素子、製造方法、および電子機器 |
KR101587373B1 (ko) * | 2012-03-12 | 2016-01-20 | 마이크론 테크놀로지, 인크 | 복수의 전기 전도성 포스트를 평탄화시키는 반도체 구조물 및 방법 |
KR20140143169A (ko) * | 2012-03-12 | 2014-12-15 | 마이크론 테크놀로지, 인크 | 복수의 전기 전도성 포스트를 평탄화시키는 반도체 구조물 및 방법 |
JP2013197470A (ja) * | 2012-03-22 | 2013-09-30 | Fujitsu Ltd | 貫通電極の形成方法 |
JP2014138037A (ja) * | 2013-01-15 | 2014-07-28 | Disco Abrasive Syst Ltd | ウエーハの加工方法 |
JP2017204510A (ja) * | 2016-05-09 | 2017-11-16 | キヤノン株式会社 | 光電変換装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI427700B (zh) | 2014-02-21 |
CN101714512B (zh) | 2012-10-10 |
CN102290425A (zh) | 2011-12-21 |
JPWO2006019156A1 (ja) | 2008-05-08 |
CN102290425B (zh) | 2014-04-02 |
US7906363B2 (en) | 2011-03-15 |
US20090149023A1 (en) | 2009-06-11 |
CN101714512A (zh) | 2010-05-26 |
TW200620474A (en) | 2006-06-16 |
JP5354765B2 (ja) | 2013-11-27 |
CN101048868A (zh) | 2007-10-03 |
JP2012129551A (ja) | 2012-07-05 |
CN101048868B (zh) | 2010-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2006019156A1 (ja) | 三次元積層構造を持つ半導体装置の製造方法 | |
US10756056B2 (en) | Methods and structures for wafer-level system in package | |
US7691672B2 (en) | Substrate treating method and method of manufacturing semiconductor apparatus | |
JP5175003B2 (ja) | 三次元積層構造を持つ集積回路装置の製造方法 | |
JP4787559B2 (ja) | 半導体装置およびその製造方法 | |
TWI441285B (zh) | 用於封裝裝置之凹陷的半導體基底及其方法 | |
TWI251314B (en) | Manufacturing method of semiconductor device, semiconductor device, circuit substrate and electronic equipment | |
WO2005119776A1 (ja) | 三次元積層構造を持つ半導体装置及びその製造方法 | |
JP2004327910A (ja) | 半導体装置およびその製造方法 | |
US11107794B2 (en) | Multi-wafer stack structure and forming method thereof | |
JP2007180529A (ja) | 半導体装置およびその製造方法 | |
TW202042329A (zh) | 具有增強性能之射頻元件及其形成方法 | |
TW201906021A (zh) | 半導體封裝結構及其製造方法 | |
JP3356122B2 (ja) | システム半導体装置及びシステム半導体装置の製造方法 | |
TWI434384B (zh) | 電子電路裝置與其製造方法 | |
US20060267190A1 (en) | Semiconductor device, laminated semiconductor device, and method for producing semiconductor device | |
JP5383874B2 (ja) | 三次元積層構造を持つ集積回路装置 | |
US9842827B2 (en) | Wafer level system in package (SiP) using a reconstituted wafer and method of making | |
JP2015053371A (ja) | 半導体装置およびその製造方法 | |
JP2006210802A (ja) | 半導体装置 | |
JP4528018B2 (ja) | 半導体装置及びその製造方法 | |
TWI841894B (zh) | 半導體裝置及其製造方法 | |
JP2003258196A (ja) | 半導体装置及びその製造方法 | |
JP2013191639A (ja) | 積層型半導体装置及びその製造方法 | |
TW202226396A (zh) | 半導體裝置及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2006531871 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 200580035563.3 Country of ref document: CN |
|
122 | Ep: pct application non-entry in european phase | ||
WWE | Wipo information: entry into national phase |
Ref document number: 11573976 Country of ref document: US |