WO2006013835A1 - Electronic circuit - Google Patents

Electronic circuit Download PDF

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Publication number
WO2006013835A1
WO2006013835A1 PCT/JP2005/014063 JP2005014063W WO2006013835A1 WO 2006013835 A1 WO2006013835 A1 WO 2006013835A1 JP 2005014063 W JP2005014063 W JP 2005014063W WO 2006013835 A1 WO2006013835 A1 WO 2006013835A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmission
current
coil
capacitor
circuit
Prior art date
Application number
PCT/JP2005/014063
Other languages
French (fr)
Japanese (ja)
Inventor
Tadahiro Kuroda
Daisuke Mizoguchi
Noriyuki Miura
Original Assignee
Keio University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Keio University filed Critical Keio University
Priority to US11/659,111 priority Critical patent/US20090057039A1/en
Publication of WO2006013835A1 publication Critical patent/WO2006013835A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/20—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission technique; characterised by the transmission medium
    • H04B5/22—Capacitive coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/10—Polarisation diversity; Directional diversity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03248—Arrangements for operating in conjunction with other apparatus
    • H04L25/03254—Operation with other circuitry for removing intersymbol interference
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to an electronic circuit that can suitably perform communication between substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed circuit board).
  • substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed circuit board).
  • the present inventors have implemented a system-in-package in which a plurality of bare chips are encapsulated in one LSI (Large Scale Integration) package by a method in which chips are three-dimensionally mounted and electrically connected by inductive coupling between the chips. Proposed to realize (SiP) (see Patent Document 1).
  • LSI Large Scale Integration
  • FIG. 3 is a diagram showing the configuration of the electronic circuit of the prior invention.
  • This electronic circuit comprises first to third LSI chips 31a to 31c.
  • LSI chips are stacked in three layers to form a bus that spans three chips. In other words, one communication channel that can communicate with each other between three parties (three LSI chips) is configured.
  • the first to third LSI chips 31a to 31c are stacked vertically, and the chips are fixed to each other with an adhesive.
  • first to third transmission coils 33a to 33c used for transmission are formed by wiring, respectively, and first to third reception coils 35a to 35a used for reception are respectively formed.
  • 35c is formed by wiring.
  • the first to third transmission coils 33a to 33c are respectively connected to the first to third transmission circuits 32a to 32c, and the first to third reception coils 35a to 35c are respectively connected to the first to third reception circuits 34a to 34c. 34c is connected.
  • the transmission and reception coils 33 and 35 are mounted as three-dimensional or more coils in a three-dimensional manner within the area allowed for communication using multilayer wiring of process technology.
  • the transmission / reception coils 33 and 35 have an optimal shape for communication, and it is necessary to take an optimal number of windings, openings, and line widths.
  • the transmitter coil 33 is more than the receiver coil 35 / J.
  • FIG. 4 is a diagram illustrating a configuration example of a transmission circuit used in the electronic circuit of the prior invention.
  • the communication circuit includes a delay buffer 41 and transistors T7 to T10.
  • Transistor ⁇ 7 and transistor ⁇ 8, and transistor ⁇ 9 and transistor T10 each form an inverter with a CMOS (Complementary Metal Oxide Semiconductor) structure, function as a buffer, and drive transmission coil 42.
  • CMOS Complementary Metal Oxide Semiconductor
  • a buffer is connected to both ends of the transmission coil 42 in order to cause a pulse current having a triangular wave shape to flow through the transmission coil 42, and these are further shifted in time. Since the delay buffer 41 is provided, the circuit scale is large and the circuit scale is large, so that the power consumed by these circuits also increases.
  • the present invention provides an electronic circuit capable of simplifying a transmission circuit and realizing low voltage driving and low power consumption when inter-board communication is realized by inductive coupling.
  • the purpose is to provide.
  • An electronic circuit of the present invention includes a selection circuit that outputs a first reference potential or a second reference potential according to a transmission signal, and a capacitor and a substrate between the output of the selection circuit and the first potential.
  • the selection circuit is composed of a transistor having a CMOS structure, so that the power consumption can be reduced and the operation speed can be increased.
  • the transmission coil when the transmission coil transmits a signal! / ⁇ , the transmission coil is opened so that the closed transmission coil can change the magnetic flux during reception of another substrate force. Interfering with it can be deterred.
  • the transmission circuit when communication between substrates is realized by inductive coupling, the transmission circuit can be simplified, and low voltage driving and low power consumption can be realized.
  • FIG. 1 is a diagram showing a configuration of a transmission circuit in an electronic circuit according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing the voltage and current of each part.
  • FIG. 3 is a diagram showing a configuration of an electronic circuit according to the invention of the prior application.
  • FIG. 4 is a diagram showing a configuration example of a transmission circuit used in the electronic circuit of the prior invention. Explanation of symbols
  • FIG. 1 is a diagram showing a configuration of a transmission circuit in an electronic circuit according to an embodiment of the present invention.
  • This transmission circuit includes NOTl l, NAND12, NOR13, transistor Tl, ⁇ 2, and capacitor 15, and drives the transmission coil.
  • the transistors Tl and ⁇ 2 are the same as the transistors ⁇ 7 and ⁇ 8 described as the prior art, and detailed description thereof is omitted.
  • the signal ⁇ bar (Rx) is a signal that is high when transmitting and low when receiving, assuming that this chip is receiving when this chip is not transmitting for this communication channel. is there.
  • Capacitor 15 can be easily manufactured by using the capacitance of a MOS transistor. When transmitting, that is, when the TxZ bar (Rx) is high and the input transmission data Txdata goes low, transistor T1 turns off and transistor T2 turns off. The current IT flows through the transmission coil 14 and charges the capacitor 15.
  • the delay buffer 41 can be omitted and the two buffers (T7 to T10) for driving the transmission coil 14 can be made one (T1, ⁇ 2), further power saving can be achieved.
  • the charge / discharge current when charging and discharging the capacitor via the coil is linear, it is possible to transmit a large signal from the transmission coil 14 with a small current. Voltage drive is possible.
  • FIG. 2 is a diagram showing the voltage and current of each part.
  • the transmission coil 22, the reception coil 23, the reception circuit 24, and the ammeter 25 FIG. 2 (a) is for the conventional transmission circuit
  • FIG. 2 (b) is for the present embodiment.
  • the transmission data Txdata which is the input of the transmission circuit 21, the current IT of the transmission coil 22, the voltage VR between the reception coils 23, and the power supply current ISS flowing through the transmission circuit 21 are shown.
  • the transmission data Txdata goes from low to high, the current IT rises slowly and falls gently in the conventional Fig. 2 (a), whereas in Fig. 2 (b) of this example, it rises linearly. Because it falls linearly, only a small current IT is required. Nevertheless, compared to the conventional Fig.
  • the amount of power supply current ISS of the transmitter circuit 21 where the peak value of the voltage VR between the receiving coils 23 is large is very small. You can see that it is over.
  • the transmission data Txdata becomes high and low, it can be seen that the amount of power supply current ISS of the transmission circuit 21 is almost not shown in Fig. 2 (b) of this example compared to the conventional Fig. 2 (a). .
  • NOTl l, NAND12, and NOR13 are intended to prevent the closed transmit coil 14 from interfering with the change in magnetic flux being received from other boards, which is a problem. If not, you can omit it.
  • Transistors Tl and ⁇ 2 are examples of a configuration of a selection circuit that selectively connects one end of the transmission coil 14 to two potentials. Other arbitrary circuits having the function of this selection circuit are shown in FIG. You can!

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Near-Field Transmission Systems (AREA)
  • Logic Circuits (AREA)

Abstract

An electronic circuit capable of realizing low driving voltage and low power consumption while simplifying a transmission circuit when communication between substrates is realized through inductive coupling. When transmission data (Txdata) goes high from low, a transistor (T1) is turned on, a transistor (T2) is turned off and a current (IT) flows through a transmission coil (14) to charge a capacitor (15). When the capacitor (15) is fully charged, the current (IT) stops flowing, and a triangular pulse current flows through the transmission coil (14). When the transmission data (Txdata) goes low from high, the current (IT) flows through the transmission coil (14) reversely to discharge the capacitor (15) and a triangular pulse current of reverse polarity flows through the transmission coil (14). Since discharge of the capacitor (15) is employed for feeding the pulse current of reverse polarity and the power supply current is not employed, power can be saved.

Description

明 細 書  Specification
電子回路  Electronic circuit
技術分野  Technical field
[0001] 本発明は、 IC (Integrated Circuit)ベアチップや PCB (プリント基板）などの基板間 の通信を好適に行うことができる電子回路に関する。  The present invention relates to an electronic circuit that can suitably perform communication between substrates such as an IC (Integrated Circuit) bare chip and a PCB (printed circuit board).
背景技術  Background art
[0002] 本発明者らは、チップを 3次元実装し、チップ間を誘導性結合により電気的に接続 する方法によって、 LSI (Large Scale Integration)の 1パッケージに複数のベアチップ を封入するシステムインパッケージ (SiP)を実現することを提案して ヽる（特許文献 1 参照)。  [0002] The present inventors have implemented a system-in-package in which a plurality of bare chips are encapsulated in one LSI (Large Scale Integration) package by a method in which chips are three-dimensionally mounted and electrically connected by inductive coupling between the chips. Proposed to realize (SiP) (see Patent Document 1).
[0003] 図 3は、先願発明の電子回路の構成を示す図である。この電子回路は、第 1〜第 3 LSIチップ 31a〜31cから成る。 LSIチップが 3層にスタックされ、 3チップにまたがる バスを形成する例である。すなわち、 3者間（3つの LSIチップ間）で互いに通信可能 な 1つの通信チャネルを構成している。第 1〜第 3LSIチップ 31a〜31cが縦に積まれ 、各チップは接着剤で互いに固定されている。第 1〜第 3LSIチップ 31a〜31c上に は、それぞれ、送信に用いる第 1〜第 3送信コイル 33a〜33cが配線により形成され、 また、それぞれ、受信に用いる第 1〜第 3受信コイル 35a〜35cが配線により形成さ れる。これら 3ペアの送受信コイル 33、 35の開口の中心が一致するように、第 1〜第 3LSIチップ 31a〜31c上で配置されている。これにより、 3ペアの送受信コイル 33、 3 5は誘導性結合を形成し、通信が可能となる。第 1〜第 3送信コイル 33a〜33cには それぞれ第 1〜第 3送信回路 32a〜32cが接続され、第 1〜第 3受信コイル 35a〜35 cにはそれぞれ第 1〜第 3受信回路 34a〜34cが接続される。送受信コイル 33、 35は 、プロセス技術の多層配線を利用し、通信に許される面積内で、 3次元的に 1回巻き 以上のコイルとして実装される。送受信コイル 33、 35には、通信に最適な形状が存 在し、最適なまき数、開口、線幅をとる必要がある。一般的に、送信コイル 33が受信 コィノレ 35より/ J、さい。  FIG. 3 is a diagram showing the configuration of the electronic circuit of the prior invention. This electronic circuit comprises first to third LSI chips 31a to 31c. In this example, LSI chips are stacked in three layers to form a bus that spans three chips. In other words, one communication channel that can communicate with each other between three parties (three LSI chips) is configured. The first to third LSI chips 31a to 31c are stacked vertically, and the chips are fixed to each other with an adhesive. On the first to third LSI chips 31a to 31c, first to third transmission coils 33a to 33c used for transmission are formed by wiring, respectively, and first to third reception coils 35a to 35a used for reception are respectively formed. 35c is formed by wiring. These three pairs of transmitting and receiving coils 33 and 35 are arranged on the first to third LSI chips 31a to 31c so that the centers of the openings coincide with each other. As a result, the three pairs of transmitting and receiving coils 33 and 35 form inductive coupling, and communication is possible. The first to third transmission coils 33a to 33c are respectively connected to the first to third transmission circuits 32a to 32c, and the first to third reception coils 35a to 35c are respectively connected to the first to third reception circuits 34a to 34c. 34c is connected. The transmission and reception coils 33 and 35 are mounted as three-dimensional or more coils in a three-dimensional manner within the area allowed for communication using multilayer wiring of process technology. The transmission / reception coils 33 and 35 have an optimal shape for communication, and it is necessary to take an optimal number of windings, openings, and line widths. Generally, the transmitter coil 33 is more than the receiver coil 35 / J.
[0004] 図 4は、先願発明の電子回路に用いる送信回路の構成例を示す図である。この送 信回路は、遅延バッファ 41、及びトランジスタ T7〜T10から成る。トランジスタ Τ7とト ランジスタ Τ8、及び、トランジスタ Τ9とトランジスタ T10がそれぞれ CMOS (Complem entary Metal Oxide Semiconductor)構造のインバータを形成して、バッファとして機 能し、送信コイル 42を駆動する。入力される送信データ Txdataがロー力もハイにな ると、トランジスタ T7、 Τ8で反転して送信コイル 42に電流 ITを流し、遅延バッファ 41 で遅延されて、トランジスタ T9、 T10で反転して送信コイル 42の電流 ITを止める。こ れにより送信コイル 42に三角波形状のパルス電流を流す。送信データ Txdataがハ ィからローになると、送信コイル 42に逆極性の三角波形状のパルス電流を流す。 特許文献 1：特願 2004— 037242 FIG. 4 is a diagram illustrating a configuration example of a transmission circuit used in the electronic circuit of the prior invention. This The communication circuit includes a delay buffer 41 and transistors T7 to T10. Transistor Τ7 and transistor Τ8, and transistor Τ9 and transistor T10 each form an inverter with a CMOS (Complementary Metal Oxide Semiconductor) structure, function as a buffer, and drive transmission coil 42. When the input transmit data Txdata becomes high, the transistor T7 and Τ8 inverts it and inverts it through the transmit coil 42, causes the current IT to flow through it. Stop the current IT of 42. As a result, a triangular wave-shaped pulse current is caused to flow through the transmission coil 42. When transmission data Txdata goes from high to low, a pulse current having a triangular wave shape with a reverse polarity is sent to the transmission coil 42. Patent Document 1: Japanese Patent Application 2004-037242
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] しかし、上記の送信回路の場合には、送信コイル 42に三角波形状のパルス電流を 流すために送信コイル 42の両端にバッファを接続して、更にそれらを時間的にずら して動作させるための遅延バッファ 41を設けているために、回路規模が大きぐ更に 回路規模が大きいためにそれらの回路で消費される電力も大きくなつてしまう。  [0005] However, in the case of the above-described transmission circuit, a buffer is connected to both ends of the transmission coil 42 in order to cause a pulse current having a triangular wave shape to flow through the transmission coil 42, and these are further shifted in time. Since the delay buffer 41 is provided, the circuit scale is large and the circuit scale is large, so that the power consumed by these circuits also increases.
[0006] また、受信コイルにおける起電力を大きくするためには送信コイル 42に流すパルス 電流を直線状にすることが望ましいのである力 送信コイル 42のインダクタンスによる 遅延効果によって流すパルス電流がなだらかになってしまい、結果として送信回路に は高電圧の電源が必要になる。  [0006] In order to increase the electromotive force in the receiving coil, it is desirable to make the pulse current flowing through the transmitting coil 42 linear. The force of the pulse due to the delay effect due to the inductance of the transmitting coil 42 becomes gentle. As a result, a high voltage power supply is required for the transmission circuit.
[0007] 本発明は、上記問題点に鑑み、基板間通信を誘導性結合によって実現する場合 に、送信回路を簡潔にして、なおかつ低電圧駆動及び低消費電力を実現することが できる電子回路を提供することを目的とする。  In view of the above problems, the present invention provides an electronic circuit capable of simplifying a transmission circuit and realizing low voltage driving and low power consumption when inter-board communication is realized by inductive coupling. The purpose is to provide.
課題を解決するための手段  Means for solving the problem
[0008] 本発明の電子回路は、送信信号に応じて第 1基準電位又は第 2基準電位を出力す る選択回路と、該選択回路の出力と前記第 1電位との間にコンデンサと基板上の配 線により形成される送信コイルとを直列に接続して有する第 1基板と、基板上の配線 により前記送信コイルと対応する位置に形成され前記送信コイルと誘導結合する受 信コイルを有する第 2基板とを備える。 [0009] また、前記選択回路は、 CMOS構造のトランジスタから成ることで、消費電力を少 なくし、動作を高速にすることができる。 [0008] An electronic circuit of the present invention includes a selection circuit that outputs a first reference potential or a second reference potential according to a transmission signal, and a capacitor and a substrate between the output of the selection circuit and the first potential. A first substrate having a transmitting coil formed by connecting the wirings in series and a receiving coil formed at a position corresponding to the transmitting coil by wiring on the substrate and inductively coupled to the transmitting coil. 2 substrates. [0009] Further, the selection circuit is composed of a transistor having a CMOS structure, so that the power consumption can be reduced and the operation speed can be increased.
[0010] また、前記選択回路は、前記送信コイルが信号を送信して!/ヽな 、間は送信コイルを 開放することで、閉じた送信コイルが他の基板力 受信中の磁束の変化に対して干 渉することを抑止することができる。 [0010] Further, in the selection circuit, when the transmission coil transmits a signal! / ヽ, the transmission coil is opened so that the closed transmission coil can change the magnetic flux during reception of another substrate force. Interfering with it can be deterred.
発明の効果  The invention's effect
[0011] 本発明によれば、基板間通信を誘導性結合によって実現する場合に、送信回路を 簡潔にして、なおかつ低電圧駆動及び低消費電力を実現することができる。  [0011] According to the present invention, when communication between substrates is realized by inductive coupling, the transmission circuit can be simplified, and low voltage driving and low power consumption can be realized.
[0012] 本明細書は本願の優先権の基礎である特願 2004— 229941の明細書及び Z又は 図面に記載される内容を包含する。 [0012] This specification includes the contents described in the specification and Z or drawings of Japanese Patent Application No. 2004-229941 which is the basis of the priority of the present application.
図面の簡単な説明  Brief Description of Drawings
[0013] [図 1]図 1は本発明の実施例による電子回路における送信回路の構成を示す図であ る。  FIG. 1 is a diagram showing a configuration of a transmission circuit in an electronic circuit according to an embodiment of the present invention.
[図 2]図 2は各部の電圧及び電流を示す図である。  FIG. 2 is a diagram showing the voltage and current of each part.
[図 3]図 3は先願発明の電子回路の構成を示す図である。  FIG. 3 is a diagram showing a configuration of an electronic circuit according to the invention of the prior application.
[図 4]図 4は先願発明の電子回路に用いる送信回路の構成例を示す図である。 符号の説明  FIG. 4 is a diagram showing a configuration example of a transmission circuit used in the electronic circuit of the prior invention. Explanation of symbols
11 NOT  11 NOT
12 NAND  12 NAND
13 NOR  13 NOR
14 送信コイル  14 Transmitting coil
15 コンデンサ  15 capacitor
21 送信回路  21 Transmitter circuit
22 送信コイル  22 Transmitting coil
23 受信コイル  23 Receiver coil
24 受信回路  24 Receiver circuit
25 電流十 31 LSIチップ 25 current 31 LSI chip
32 送信回路  32 Transmitter circuit
33 送信コイル  33 Transmitting coil
34 受信回路  34 Receiver circuit
35 受信コイル  35 Receiver coil
41 遅延バッファ  41 Delay buffer
42 送信コイル  42 Transmitting coil
T1、 T2、 T7〜T10 トランジスタ  T1, T2, T7 to T10 transistors
Txdata 送信データ  Txdata transmission data
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0015] 以下、添付図面を参照しながら本発明を実施するための最良の形態について詳細 に説明する。 Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the accompanying drawings.
[0016] 図 1は、本発明の実施例による電子回路における送信回路の構成を示す図である 。この送信回路は、 NOTl l、 NAND12、 NOR13、トランジスタ Tl、 Τ2、及びコン デンサ 15から成り、送信コイル 14を駆動する。トランジスタ Tl、 Τ2は、従来技術とし て説明したトランジスタ Τ7、 Τ8と同一のものであり詳しい説明は省略する。信号 ΤχΖ バー (Rx)は、この通信チャネルに関してこのチップが送信していない時には受信し ているものであることを想定して、送信している時にはハイ、受信している時にはロー である信号である。これによりこのチップが送信していない時 (この実施例では、すな わち、受信している時）には、信号 TxZバー（Rx)はローであるので、 NOT11の出 力はハイ、 NAND12の出力はハイ、 NOR13の出力はローとなって、トランジスタ T1 、 T2をオフにして、送信コイル 14を開放状態にする。これにより閉じた送信コイル 14 1S 受信中の磁束の変化に対して干渉することを抑止する。コンデンサ 15は MOSト ランジスタの容量性を用いることで、簡易に製造することができる。送信の時、すなわ ち、 TxZバー（Rx)がハイである時に、入力される送信データ Txdataがロー力 ハイ になると、トランジスタ T1はオフ力もオンになると共に、トランジスタ T2はオン力もオフ になり、送信コイル 14には電流 ITが流れコンデンサ 15を充電する。コンデンサ 15が 十分に充電されると電流 ITは止まり、結局、送信コイル 14には三角波形状のノルス 電流が流れることになる。つぎに、送信データ Txdataがハイからローになると、トラン ジスタ T1はオン力もオフになると共に、トランジスタ T2はオフ力もオンになり、送信コ ィル 14には電流 ITが逆に流れコンデンサ 15を放電する。コンデンサ 15が十分に放 電されると電流 ITは止まり、送信コイル 14には逆極性の三角波形状のパルス電流が 流れること〖こなる。この実施例の場合、逆極性のパルス電流を流すのにコンデンサ 1 5の放電を用いていて、電源電流を用いていないので、節電ができる。また、遅延バ ッファ 41を割愛でき、送信コイル 14を駆動する 2つのバッファ（T7〜T10)を 1つ（T1 、 Τ2)にできるので、さらに節電ができる。また、コイルを介してコンデンサを充放電す る場合の充放電電流は線形性がょ 、ので、小さな電流で送信コイル 14から大きな信 号を送信することができ、この点でも節電ができると共に低電圧駆動ができる。 FIG. 1 is a diagram showing a configuration of a transmission circuit in an electronic circuit according to an embodiment of the present invention. This transmission circuit includes NOTl l, NAND12, NOR13, transistor Tl, Τ2, and capacitor 15, and drives the transmission coil. The transistors Tl and Τ2 are the same as the transistors Τ7 and Τ8 described as the prior art, and detailed description thereof is omitted. The signal ΤχΖ bar (Rx) is a signal that is high when transmitting and low when receiving, assuming that this chip is receiving when this chip is not transmitting for this communication channel. is there. As a result, when this chip is not transmitting (in this example, when receiving), the signal TxZ bar (Rx) is low, so the output of NOT11 is high, NAND12 Output is high, NOR13 output is low, transistors T1 and T2 are turned off, and the transmitter coil 14 is opened. As a result, interference with the change in magnetic flux during reception of the closed transmission coil 14 1S is suppressed. Capacitor 15 can be easily manufactured by using the capacitance of a MOS transistor. When transmitting, that is, when the TxZ bar (Rx) is high and the input transmission data Txdata goes low, transistor T1 turns off and transistor T2 turns off. The current IT flows through the transmission coil 14 and charges the capacitor 15. When the capacitor 15 is fully charged, the current IT stops and eventually the transmitter coil 14 has a triangular wave-shaped nors. Current will flow. Next, when the transmission data Txdata goes from high to low, the transistor T1 is turned off and the transistor T2 is turned off, and the current IT flows in the reverse direction to the transmission coil 14, discharging the capacitor 15. To do. When the capacitor 15 is sufficiently discharged, the current IT stops, and a reverse-polarity triangular current flows through the transmitter coil 14. In the case of this embodiment, since the discharge of the capacitor 15 is used to flow the pulse current having the reverse polarity and the power supply current is not used, power can be saved. Further, since the delay buffer 41 can be omitted and the two buffers (T7 to T10) for driving the transmission coil 14 can be made one (T1, Τ2), further power saving can be achieved. In addition, since the charge / discharge current when charging and discharging the capacitor via the coil is linear, it is possible to transmit a large signal from the transmission coil 14 with a small current. Voltage drive is possible.
[0017] 図 2は、各部の電圧及び電流を示す図である。送信回路 21、送信コイル 22、受信 コイル 23、受信回路 24、及び電流計 25において、図 2(a)は従来の送信回路の場合 の、そして、図 2(b)は本実施例の場合の、送信回路 21の入力である送信データ Txd ata、送信コイル 22の電流 IT、受信コイル 23間の電圧 VR、及び送信回路 21に流れ る電源電流 ISSを示す。送信データ Txdataがローからハイになった後、従来の図 2( a)では電流 ITがゆるやかに立ち上がり、ゆるやかに立ち下がるのに対して、本実施 例の図 2(b)では直線的に立ち上がり、直線的に立ち下がるため、小さな電流 ITで済 む。それでも、従来の図 2(a)と比べて本実施例の図 2(b)では、受信コイル 23間の電 圧 VRのピーク値が大きぐ送信回路 21の電源電流 ISSの量は極めて少なくて済む ことが分かる。送信データ Txdataがハイ力もローになった場合には、従来の図 2(a)と 比べて本実施例の図 2(b)では、送信回路 21の電源電流 ISSの量がほとんどないこと が分かる。 FIG. 2 is a diagram showing the voltage and current of each part. In the transmission circuit 21, the transmission coil 22, the reception coil 23, the reception circuit 24, and the ammeter 25, FIG. 2 (a) is for the conventional transmission circuit, and FIG. 2 (b) is for the present embodiment. The transmission data Txdata which is the input of the transmission circuit 21, the current IT of the transmission coil 22, the voltage VR between the reception coils 23, and the power supply current ISS flowing through the transmission circuit 21 are shown. After the transmission data Txdata goes from low to high, the current IT rises slowly and falls gently in the conventional Fig. 2 (a), whereas in Fig. 2 (b) of this example, it rises linearly. Because it falls linearly, only a small current IT is required. Nevertheless, compared to the conventional Fig. 2 (a), in Fig. 2 (b) of the present embodiment, the amount of power supply current ISS of the transmitter circuit 21 where the peak value of the voltage VR between the receiving coils 23 is large is very small. You can see that it is over. When the transmission data Txdata becomes high and low, it can be seen that the amount of power supply current ISS of the transmission circuit 21 is almost not shown in Fig. 2 (b) of this example compared to the conventional Fig. 2 (a). .
[0018] 以上のとおり、本実施例の場合には、（1).送信データ Txdataがハイ力 ローになつ た場合に送信回路 21の電源電流をほとんど流さず、（2).送信コイル 22に流れる電流 の線形性がよぐ（3).回路規模が小さいために更に節電できる。  [0018] As described above, in the case of the present embodiment, (1). When the transmission data Txdata becomes high and low, almost no power supply current flows to the transmission circuit 21, and (2). The linearity of the flowing current is good (3). Since the circuit scale is small, further power saving can be achieved.
[0019] なお、本発明は上記実施例に限定されるものではない。  Note that the present invention is not limited to the above embodiment.
[0020] NOTl l、 NAND12、及び NOR13は、閉じた送信コイル 14が他の基板から受信 中の磁束の変化に対して干渉することを抑止するためのものであるので、これを問題 としなければ割愛することができる。 [0020] NOTl l, NAND12, and NOR13 are intended to prevent the closed transmit coil 14 from interfering with the change in magnetic flux being received from other boards, which is a problem. If not, you can omit it.
[0021] トランジスタ Tl、 Τ2は、送信コイル 14の一端を 2つの電位に選択的に接続する選 択回路の構成の例を示したもので、この選択回路の機能を有する他の任意の回路を 用!/、ることができる。  [0021] Transistors Tl and Τ2 are examples of a configuration of a selection circuit that selectively connects one end of the transmission coil 14 to two potentials. Other arbitrary circuits having the function of this selection circuit are shown in FIG. You can!
[0022] 送信コイル 14とコンデンサ 15とは直列に接続されていれば、その位置を入れ換え ても構わない。  [0022] As long as the transmission coil 14 and the capacitor 15 are connected in series, their positions may be interchanged.
[0023] 本明細書で引用した全ての刊行物、特許及び特許出願をそのまま参考として本明 細書にとり入れるものとする。  [0023] All publications, patents, and patent applications cited in this specification are incorporated herein by reference in their entirety.

Claims

請求の範囲 The scope of the claims
[1] 送信信号に応じて第 1基準電位又は第 2基準電位を出力する選択回路と、該選択 回路の出力と前記第 1電位との間にコンデンサと基板上の配線により形成される送信 コイルとを直列に接続して有する第 1基板と、  [1] A selection circuit that outputs a first reference potential or a second reference potential according to a transmission signal, and a transmission coil formed by a capacitor and a wiring on a substrate between the output of the selection circuit and the first potential A first substrate having a series connection of
基板上の配線により前記送信コイルと対応する位置に形成され前記送信コイルと 誘導結合する受信コイルを有する第 2基板と  A second substrate having a receiving coil formed at a position corresponding to the transmitting coil by wiring on the substrate and inductively coupled to the transmitting coil;
を備えることを特徴とする電子回路。  An electronic circuit comprising:
[2] 前記選択回路は、 CMOS構造のトランジスタ力 成ることを特徴とする請求項 1記 載の電子回路。 2. The electronic circuit according to claim 1, wherein the selection circuit is a transistor having a CMOS structure.
[3] 前記選択回路は、前記送信コイルが信号を送信していない間は送信コイルを開放 することを特徴とする請求項 1又は 2記載の電子回路。  3. The electronic circuit according to claim 1, wherein the selection circuit opens the transmission coil while the transmission coil is not transmitting a signal.
PCT/JP2005/014063 2004-08-05 2005-08-01 Electronic circuit WO2006013835A1 (en)

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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006173986A (en) 2004-12-15 2006-06-29 Keio Gijuku Electronic circuit
WO2007029435A1 (en) 2005-09-02 2007-03-15 Nec Corporation Transmission method, interface circuit, semiconductor device, semiconductor package, semiconductor module and memory module
WO2009035028A1 (en) * 2007-09-12 2009-03-19 Nec Corporation Data transmission device and data transmission method
WO2009069532A1 (en) 2007-11-26 2009-06-04 Keio University Electronic circuit
JP5600237B2 (en) 2008-02-02 2014-10-01 学校法人慶應義塾 Integrated circuit
JP5258343B2 (en) 2008-03-27 2013-08-07 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor integrated circuit
JP5475962B2 (en) 2008-04-28 2014-04-16 学校法人慶應義塾 Electronic circuit
JP5252486B2 (en) 2008-05-14 2013-07-31 学校法人慶應義塾 Inductor element, integrated circuit device, and three-dimensional mounting circuit device
JP5671200B2 (en) 2008-06-03 2015-02-18 学校法人慶應義塾 Electronic circuit
JP4982778B2 (en) 2008-07-04 2012-07-25 学校法人慶應義塾 Electronic circuit equipment
JP5325495B2 (en) 2008-08-12 2013-10-23 学校法人慶應義塾 Semiconductor device and manufacturing method thereof
JP5433199B2 (en) 2008-10-21 2014-03-05 学校法人慶應義塾 Electronic circuit
JP5326088B2 (en) 2008-10-21 2013-10-30 学校法人慶應義塾 Electronic circuit and communication function inspection method
JP5283075B2 (en) 2008-12-26 2013-09-04 学校法人慶應義塾 Electronic circuit
JP5395458B2 (en) 2009-02-25 2014-01-22 学校法人慶應義塾 Inductor element and integrated circuit device
JP5374246B2 (en) 2009-06-12 2013-12-25 学校法人慶應義塾 Sealed semiconductor recording medium and sealed semiconductor recording device
JP5635759B2 (en) 2009-10-15 2014-12-03 学校法人慶應義塾 Multilayer semiconductor integrated circuit device
JP5750031B2 (en) 2010-11-19 2015-07-15 株式会社半導体エネルギー研究所 Electronic circuit and semiconductor device
US9431168B2 (en) * 2012-06-13 2016-08-30 Advanced Micro Devices, Inc. Contactless interconnect
US9509375B2 (en) * 2013-08-01 2016-11-29 SK Hynix Inc. Wireless transceiver circuit with reduced area

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08149054A (en) * 1994-11-25 1996-06-07 Japan Aviation Electron Ind Ltd Non-contact connector, signal transmitting and receiving method using the connector, and device performing the method
JPH09171541A (en) * 1995-12-19 1997-06-30 Tokimec Inc Communication equipment
JP2001045075A (en) * 1999-07-28 2001-02-16 Nippon Soken Inc Transmitter using ask modulation wave

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5701037A (en) * 1994-11-15 1997-12-23 Siemens Aktiengesellschaft Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit
JP3258923B2 (en) * 1997-02-26 2002-02-18 株式会社東芝 Semiconductor integrated circuit device
FR2791493B1 (en) * 1999-03-25 2001-06-08 Inside Technologies TRANSMITTING / RECEIVING CIRCUIT OF DATA BY INDUCTIVE COUPLING
US6807109B2 (en) * 2001-12-05 2004-10-19 Renesas Technology Corp. Semiconductor device suitable for system in package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08149054A (en) * 1994-11-25 1996-06-07 Japan Aviation Electron Ind Ltd Non-contact connector, signal transmitting and receiving method using the connector, and device performing the method
JPH09171541A (en) * 1995-12-19 1997-06-30 Tokimec Inc Communication equipment
JP2001045075A (en) * 1999-07-28 2001-02-16 Nippon Soken Inc Transmitter using ask modulation wave

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